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[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 void *mem_ctx,
41 const struct brw_wm_prog_key *key,
42 struct brw_wm_prog_data *prog_data,
43 struct gl_shader_program *prog,
44 struct gl_fragment_program *fp,
45 bool dual_source_output,
46 bool runtime_check_aads_emit,
47 bool debug_flag)
48
49 : brw(brw), key(key), prog_data(prog_data), prog(prog), fp(fp),
50 dual_source_output(dual_source_output),
51 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(debug_flag),
52 mem_ctx(mem_ctx)
53 {
54 ctx = &brw->ctx;
55
56 p = rzalloc(mem_ctx, struct brw_compile);
57 brw_init_compile(brw, p, mem_ctx);
58 }
59
60 fs_generator::~fs_generator()
61 {
62 }
63
64 bool
65 fs_generator::patch_discard_jumps_to_fb_writes()
66 {
67 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
68 return false;
69
70 /* There is a somewhat strange undocumented requirement of using
71 * HALT, according to the simulator. If some channel has HALTed to
72 * a particular UIP, then by the end of the program, every channel
73 * must have HALTed to that UIP. Furthermore, the tracking is a
74 * stack, so you can't do the final halt of a UIP after starting
75 * halting to a new UIP.
76 *
77 * Symptoms of not emitting this instruction on actual hardware
78 * included GPU hangs and sparkly rendering on the piglit discard
79 * tests.
80 */
81 struct brw_instruction *last_halt = gen6_HALT(p);
82 last_halt->bits3.break_cont.uip = 2;
83 last_halt->bits3.break_cont.jip = 2;
84
85 int ip = p->nr_insn;
86
87 foreach_list(node, &this->discard_halt_patches) {
88 ip_record *patch_ip = (ip_record *)node;
89 struct brw_instruction *patch = &p->store[patch_ip->ip];
90
91 assert(patch->header.opcode == BRW_OPCODE_HALT);
92 /* HALT takes a half-instruction distance from the pre-incremented IP. */
93 patch->bits3.break_cont.uip = (ip - patch_ip->ip) * 2;
94 }
95
96 this->discard_halt_patches.make_empty();
97 return true;
98 }
99
100 void
101 fs_generator::generate_fb_write(fs_inst *inst)
102 {
103 bool eot = inst->eot;
104 struct brw_reg implied_header;
105 uint32_t msg_control;
106
107 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
108 * move, here's g1.
109 */
110 brw_push_insn_state(p);
111 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
112 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
113 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
114
115 if (inst->header_present) {
116 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
117 * present.
118 */
119 if ((fp && fp->UsesKill) || key->alpha_test_func) {
120 struct brw_reg pixel_mask;
121
122 if (brw->gen >= 6)
123 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
124 else
125 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
126
127 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
128 }
129
130 if (brw->gen >= 6) {
131 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
132 brw_MOV(p,
133 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
134 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
135 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
136
137 if (inst->target > 0 && key->replicate_alpha) {
138 /* Set "Source0 Alpha Present to RenderTarget" bit in message
139 * header.
140 */
141 brw_OR(p,
142 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
143 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
144 brw_imm_ud(0x1 << 11));
145 }
146
147 if (inst->target > 0) {
148 /* Set the render target index for choosing BLEND_STATE. */
149 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
150 inst->base_mrf, 2),
151 BRW_REGISTER_TYPE_UD),
152 brw_imm_ud(inst->target));
153 }
154
155 implied_header = brw_null_reg();
156 } else {
157 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
158
159 brw_MOV(p,
160 brw_message_reg(inst->base_mrf + 1),
161 brw_vec8_grf(1, 0));
162 }
163 } else {
164 implied_header = brw_null_reg();
165 }
166
167 if (this->dual_source_output)
168 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
169 else if (dispatch_width == 16)
170 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
171 else
172 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
173
174 brw_pop_insn_state(p);
175
176 uint32_t surf_index =
177 prog_data->binding_table.render_target_start + inst->target;
178 brw_fb_WRITE(p,
179 dispatch_width,
180 inst->base_mrf,
181 implied_header,
182 msg_control,
183 surf_index,
184 inst->mlen,
185 0,
186 eot,
187 inst->header_present);
188
189 brw_mark_surface_used(&prog_data->base, surf_index);
190 }
191
192 void
193 fs_generator::generate_blorp_fb_write(fs_inst *inst)
194 {
195 brw_fb_WRITE(p,
196 16 /* dispatch_width */,
197 inst->base_mrf,
198 brw_reg_from_fs_reg(&inst->src[0]),
199 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
200 inst->target,
201 inst->mlen,
202 0,
203 true,
204 inst->header_present);
205 }
206
207 /* Computes the integer pixel x,y values from the origin.
208 *
209 * This is the basis of gl_FragCoord computation, but is also used
210 * pre-gen6 for computing the deltas from v0 for computing
211 * interpolation.
212 */
213 void
214 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
215 {
216 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
217 struct brw_reg src;
218 struct brw_reg deltas;
219
220 if (is_x) {
221 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
222 deltas = brw_imm_v(0x10101010);
223 } else {
224 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
225 deltas = brw_imm_v(0x11001100);
226 }
227
228 if (dispatch_width == 16) {
229 dst = vec16(dst);
230 }
231
232 /* We do this SIMD8 or SIMD16, but since the destination is UW we
233 * don't do compression in the SIMD16 case.
234 */
235 brw_push_insn_state(p);
236 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
237 brw_ADD(p, dst, src, deltas);
238 brw_pop_insn_state(p);
239 }
240
241 void
242 fs_generator::generate_linterp(fs_inst *inst,
243 struct brw_reg dst, struct brw_reg *src)
244 {
245 struct brw_reg delta_x = src[0];
246 struct brw_reg delta_y = src[1];
247 struct brw_reg interp = src[2];
248
249 if (brw->has_pln &&
250 delta_y.nr == delta_x.nr + 1 &&
251 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
252 brw_PLN(p, dst, interp, delta_x);
253 } else {
254 brw_LINE(p, brw_null_reg(), interp, delta_x);
255 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
256 }
257 }
258
259 void
260 fs_generator::generate_math1_gen7(fs_inst *inst,
261 struct brw_reg dst,
262 struct brw_reg src0)
263 {
264 assert(inst->mlen == 0);
265 brw_math(p, dst,
266 brw_math_function(inst->opcode),
267 0, src0,
268 BRW_MATH_DATA_VECTOR,
269 BRW_MATH_PRECISION_FULL);
270 }
271
272 void
273 fs_generator::generate_math2_gen7(fs_inst *inst,
274 struct brw_reg dst,
275 struct brw_reg src0,
276 struct brw_reg src1)
277 {
278 assert(inst->mlen == 0);
279 brw_math2(p, dst, brw_math_function(inst->opcode), src0, src1);
280 }
281
282 void
283 fs_generator::generate_math1_gen6(fs_inst *inst,
284 struct brw_reg dst,
285 struct brw_reg src0)
286 {
287 int op = brw_math_function(inst->opcode);
288
289 assert(inst->mlen == 0);
290
291 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
292 brw_math(p, dst,
293 op,
294 0, src0,
295 BRW_MATH_DATA_VECTOR,
296 BRW_MATH_PRECISION_FULL);
297
298 if (dispatch_width == 16) {
299 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
300 brw_math(p, sechalf(dst),
301 op,
302 0, sechalf(src0),
303 BRW_MATH_DATA_VECTOR,
304 BRW_MATH_PRECISION_FULL);
305 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
306 }
307 }
308
309 void
310 fs_generator::generate_math2_gen6(fs_inst *inst,
311 struct brw_reg dst,
312 struct brw_reg src0,
313 struct brw_reg src1)
314 {
315 int op = brw_math_function(inst->opcode);
316
317 assert(inst->mlen == 0);
318
319 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
320 brw_math2(p, dst, op, src0, src1);
321
322 if (dispatch_width == 16) {
323 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
324 brw_math2(p, sechalf(dst), op, sechalf(src0), sechalf(src1));
325 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
326 }
327 }
328
329 void
330 fs_generator::generate_math_gen4(fs_inst *inst,
331 struct brw_reg dst,
332 struct brw_reg src)
333 {
334 int op = brw_math_function(inst->opcode);
335
336 assert(inst->mlen >= 1);
337
338 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
339 brw_math(p, dst,
340 op,
341 inst->base_mrf, src,
342 BRW_MATH_DATA_VECTOR,
343 BRW_MATH_PRECISION_FULL);
344
345 if (dispatch_width == 16) {
346 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
347 brw_math(p, sechalf(dst),
348 op,
349 inst->base_mrf + 1, sechalf(src),
350 BRW_MATH_DATA_VECTOR,
351 BRW_MATH_PRECISION_FULL);
352
353 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
354 }
355 }
356
357 void
358 fs_generator::generate_math_g45(fs_inst *inst,
359 struct brw_reg dst,
360 struct brw_reg src)
361 {
362 if (inst->opcode == SHADER_OPCODE_POW ||
363 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
364 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
365 generate_math_gen4(inst, dst, src);
366 return;
367 }
368
369 int op = brw_math_function(inst->opcode);
370
371 assert(inst->mlen >= 1);
372
373 brw_math(p, dst,
374 op,
375 inst->base_mrf, src,
376 BRW_MATH_DATA_VECTOR,
377 BRW_MATH_PRECISION_FULL);
378 }
379
380 void
381 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
382 {
383 int msg_type = -1;
384 int rlen = 4;
385 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
386 uint32_t return_format;
387
388 switch (dst.type) {
389 case BRW_REGISTER_TYPE_D:
390 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
391 break;
392 case BRW_REGISTER_TYPE_UD:
393 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
394 break;
395 default:
396 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
397 break;
398 }
399
400 if (dispatch_width == 16 &&
401 !inst->force_uncompressed && !inst->force_sechalf)
402 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
403
404 if (brw->gen >= 5) {
405 switch (inst->opcode) {
406 case SHADER_OPCODE_TEX:
407 if (inst->shadow_compare) {
408 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
409 } else {
410 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
411 }
412 break;
413 case FS_OPCODE_TXB:
414 if (inst->shadow_compare) {
415 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
416 } else {
417 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
418 }
419 break;
420 case SHADER_OPCODE_TXL:
421 if (inst->shadow_compare) {
422 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
423 } else {
424 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
425 }
426 break;
427 case SHADER_OPCODE_TXS:
428 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
429 break;
430 case SHADER_OPCODE_TXD:
431 if (inst->shadow_compare) {
432 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
433 assert(brw->is_haswell);
434 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
435 } else {
436 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
437 }
438 break;
439 case SHADER_OPCODE_TXF:
440 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
441 break;
442 case SHADER_OPCODE_TXF_CMS:
443 if (brw->gen >= 7)
444 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
445 else
446 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
447 break;
448 case SHADER_OPCODE_TXF_UMS:
449 assert(brw->gen >= 7);
450 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
451 break;
452 case SHADER_OPCODE_TXF_MCS:
453 assert(brw->gen >= 7);
454 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
455 break;
456 case SHADER_OPCODE_LOD:
457 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
458 break;
459 case SHADER_OPCODE_TG4:
460 if (inst->shadow_compare) {
461 assert(brw->gen >= 7);
462 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
463 } else {
464 assert(brw->gen >= 6);
465 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
466 }
467 break;
468 case SHADER_OPCODE_TG4_OFFSET:
469 assert(brw->gen >= 7);
470 if (inst->shadow_compare) {
471 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
472 } else {
473 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
474 }
475 break;
476 default:
477 assert(!"not reached");
478 break;
479 }
480 } else {
481 switch (inst->opcode) {
482 case SHADER_OPCODE_TEX:
483 /* Note that G45 and older determines shadow compare and dispatch width
484 * from message length for most messages.
485 */
486 assert(dispatch_width == 8);
487 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
488 if (inst->shadow_compare) {
489 assert(inst->mlen == 6);
490 } else {
491 assert(inst->mlen <= 4);
492 }
493 break;
494 case FS_OPCODE_TXB:
495 if (inst->shadow_compare) {
496 assert(inst->mlen == 6);
497 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
498 } else {
499 assert(inst->mlen == 9);
500 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
501 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
502 }
503 break;
504 case SHADER_OPCODE_TXL:
505 if (inst->shadow_compare) {
506 assert(inst->mlen == 6);
507 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
508 } else {
509 assert(inst->mlen == 9);
510 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
511 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
512 }
513 break;
514 case SHADER_OPCODE_TXD:
515 /* There is no sample_d_c message; comparisons are done manually */
516 assert(inst->mlen == 7 || inst->mlen == 10);
517 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
518 break;
519 case SHADER_OPCODE_TXF:
520 assert(inst->mlen == 9);
521 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
522 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
523 break;
524 case SHADER_OPCODE_TXS:
525 assert(inst->mlen == 3);
526 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
527 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
528 break;
529 default:
530 assert(!"not reached");
531 break;
532 }
533 }
534 assert(msg_type != -1);
535
536 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
537 rlen = 8;
538 dst = vec16(dst);
539 }
540
541 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
542 /* The send-from-GRF for SIMD16 texturing with a header has an extra
543 * hardware register allocated to it, which we need to skip over (since
544 * our coordinates in the payload are in the even-numbered registers,
545 * and the header comes right before the first one).
546 */
547 assert(src.file == BRW_GENERAL_REGISTER_FILE);
548 src.nr++;
549 }
550
551 /* Load the message header if present. If there's a texture offset,
552 * we need to set it up explicitly and load the offset bitfield.
553 * Otherwise, we can use an implied move from g0 to the first message reg.
554 */
555 if (inst->header_present) {
556 if (brw->gen < 6 && !inst->texture_offset) {
557 /* Set up an implied move from g0 to the MRF. */
558 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
559 } else {
560 struct brw_reg header_reg;
561
562 if (brw->gen >= 7) {
563 header_reg = src;
564 } else {
565 assert(inst->base_mrf != -1);
566 header_reg = brw_message_reg(inst->base_mrf);
567 }
568
569 brw_push_insn_state(p);
570 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
571 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
572 /* Explicitly set up the message header by copying g0 to the MRF. */
573 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
574
575 if (inst->texture_offset) {
576 /* Set the offset bits in DWord 2. */
577 brw_MOV(p, get_element_ud(header_reg, 2),
578 brw_imm_ud(inst->texture_offset));
579 }
580
581 if (inst->sampler >= 16) {
582 /* The "Sampler Index" field can only store values between 0 and 15.
583 * However, we can add an offset to the "Sampler State Pointer"
584 * field, effectively selecting a different set of 16 samplers.
585 *
586 * The "Sampler State Pointer" needs to be aligned to a 32-byte
587 * offset, and each sampler state is only 16-bytes, so we can't
588 * exclusively use the offset - we have to use both.
589 */
590 assert(brw->is_haswell); /* field only exists on Haswell */
591 brw_ADD(p,
592 get_element_ud(header_reg, 3),
593 get_element_ud(brw_vec8_grf(0, 0), 3),
594 brw_imm_ud(16 * (inst->sampler / 16) *
595 sizeof(gen7_sampler_state)));
596 }
597 brw_pop_insn_state(p);
598 }
599 }
600
601 uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
602 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
603 ? prog_data->base.binding_table.gather_texture_start
604 : prog_data->base.binding_table.texture_start) + inst->sampler;
605
606 brw_SAMPLE(p,
607 retype(dst, BRW_REGISTER_TYPE_UW),
608 inst->base_mrf,
609 src,
610 surface_index,
611 inst->sampler % 16,
612 msg_type,
613 rlen,
614 inst->mlen,
615 inst->header_present,
616 simd_mode,
617 return_format);
618
619 brw_mark_surface_used(&prog_data->base, surface_index);
620 }
621
622
623 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
624 * looking like:
625 *
626 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
627 *
628 * Ideally, we want to produce:
629 *
630 * DDX DDY
631 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
632 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
633 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
634 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
635 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
636 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
637 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
638 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
639 *
640 * and add another set of two more subspans if in 16-pixel dispatch mode.
641 *
642 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
643 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
644 * pair. But the ideal approximation may impose a huge performance cost on
645 * sample_d. On at least Haswell, sample_d instruction does some
646 * optimizations if the same LOD is used for all pixels in the subspan.
647 *
648 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
649 * appropriate swizzling.
650 */
651 void
652 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
653 {
654 unsigned vstride, width;
655
656 if (key->high_quality_derivatives) {
657 /* produce accurate derivatives */
658 vstride = BRW_VERTICAL_STRIDE_2;
659 width = BRW_WIDTH_2;
660 }
661 else {
662 /* replicate the derivative at the top-left pixel to other pixels */
663 vstride = BRW_VERTICAL_STRIDE_4;
664 width = BRW_WIDTH_4;
665 }
666
667 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
668 BRW_REGISTER_TYPE_F,
669 vstride,
670 width,
671 BRW_HORIZONTAL_STRIDE_0,
672 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
673 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
674 BRW_REGISTER_TYPE_F,
675 vstride,
676 width,
677 BRW_HORIZONTAL_STRIDE_0,
678 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
679 brw_ADD(p, dst, src0, negate(src1));
680 }
681
682 /* The negate_value boolean is used to negate the derivative computation for
683 * FBOs, since they place the origin at the upper left instead of the lower
684 * left.
685 */
686 void
687 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
688 bool negate_value)
689 {
690 if (key->high_quality_derivatives) {
691 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
692 * Region Restrictions):
693 *
694 * In Align16 access mode, SIMD16 is not allowed for DW operations
695 * and SIMD8 is not allowed for DF operations.
696 *
697 * In this context, "DW operations" means "operations acting on 32-bit
698 * values", so it includes operations on floats.
699 *
700 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
701 * (Instruction Compression -> Rules and Restrictions):
702 *
703 * A compressed instruction must be in Align1 access mode. Align16
704 * mode instructions cannot be compressed.
705 *
706 * Similar text exists in the g45 PRM.
707 *
708 * On these platforms, if we're building a SIMD16 shader, we need to
709 * manually unroll to a pair of SIMD8 instructions.
710 */
711 bool unroll_to_simd8 =
712 (dispatch_width == 16 &&
713 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
714
715 /* produce accurate derivatives */
716 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
717 BRW_REGISTER_TYPE_F,
718 BRW_VERTICAL_STRIDE_4,
719 BRW_WIDTH_4,
720 BRW_HORIZONTAL_STRIDE_1,
721 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
722 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
723 BRW_REGISTER_TYPE_F,
724 BRW_VERTICAL_STRIDE_4,
725 BRW_WIDTH_4,
726 BRW_HORIZONTAL_STRIDE_1,
727 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
728 brw_push_insn_state(p);
729 brw_set_default_access_mode(p, BRW_ALIGN_16);
730 if (unroll_to_simd8)
731 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
732 if (negate_value)
733 brw_ADD(p, dst, src1, negate(src0));
734 else
735 brw_ADD(p, dst, src0, negate(src1));
736 if (unroll_to_simd8) {
737 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
738 src0 = sechalf(src0);
739 src1 = sechalf(src1);
740 dst = sechalf(dst);
741 if (negate_value)
742 brw_ADD(p, dst, src1, negate(src0));
743 else
744 brw_ADD(p, dst, src0, negate(src1));
745 }
746 brw_pop_insn_state(p);
747 } else {
748 /* replicate the derivative at the top-left pixel to other pixels */
749 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
750 BRW_REGISTER_TYPE_F,
751 BRW_VERTICAL_STRIDE_4,
752 BRW_WIDTH_4,
753 BRW_HORIZONTAL_STRIDE_0,
754 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
755 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
756 BRW_REGISTER_TYPE_F,
757 BRW_VERTICAL_STRIDE_4,
758 BRW_WIDTH_4,
759 BRW_HORIZONTAL_STRIDE_0,
760 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
761 if (negate_value)
762 brw_ADD(p, dst, src1, negate(src0));
763 else
764 brw_ADD(p, dst, src0, negate(src1));
765 }
766 }
767
768 void
769 fs_generator::generate_discard_jump(fs_inst *inst)
770 {
771 assert(brw->gen >= 6);
772
773 /* This HALT will be patched up at FB write time to point UIP at the end of
774 * the program, and at brw_uip_jip() JIP will be set to the end of the
775 * current block (or the program).
776 */
777 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
778
779 brw_push_insn_state(p);
780 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
781 gen6_HALT(p);
782 brw_pop_insn_state(p);
783 }
784
785 void
786 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
787 {
788 assert(inst->mlen != 0);
789
790 brw_MOV(p,
791 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
792 retype(src, BRW_REGISTER_TYPE_UD));
793 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
794 dispatch_width / 8, inst->offset);
795 }
796
797 void
798 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
799 {
800 assert(inst->mlen != 0);
801
802 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
803 dispatch_width / 8, inst->offset);
804 }
805
806 void
807 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
808 {
809 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
810 }
811
812 void
813 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
814 struct brw_reg dst,
815 struct brw_reg index,
816 struct brw_reg offset)
817 {
818 assert(inst->mlen != 0);
819
820 assert(index.file == BRW_IMMEDIATE_VALUE &&
821 index.type == BRW_REGISTER_TYPE_UD);
822 uint32_t surf_index = index.dw1.ud;
823
824 assert(offset.file == BRW_IMMEDIATE_VALUE &&
825 offset.type == BRW_REGISTER_TYPE_UD);
826 uint32_t read_offset = offset.dw1.ud;
827
828 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
829 read_offset, surf_index);
830
831 brw_mark_surface_used(&prog_data->base, surf_index);
832 }
833
834 void
835 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
836 struct brw_reg dst,
837 struct brw_reg index,
838 struct brw_reg offset)
839 {
840 assert(inst->mlen == 0);
841
842 assert(index.file == BRW_IMMEDIATE_VALUE &&
843 index.type == BRW_REGISTER_TYPE_UD);
844 uint32_t surf_index = index.dw1.ud;
845
846 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
847 /* Reference just the dword we need, to avoid angering validate_reg(). */
848 offset = brw_vec1_grf(offset.nr, 0);
849
850 brw_push_insn_state(p);
851 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
852 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
853 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
854 brw_pop_insn_state(p);
855
856 /* We use the SIMD4x2 mode because we want to end up with 4 components in
857 * the destination loaded consecutively from the same offset (which appears
858 * in the first component, and the rest are ignored).
859 */
860 dst.width = BRW_WIDTH_4;
861 brw_set_dest(p, send, dst);
862 brw_set_src0(p, send, offset);
863 brw_set_sampler_message(p, send,
864 surf_index,
865 0, /* LD message ignores sampler unit */
866 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
867 1, /* rlen */
868 1, /* mlen */
869 false, /* no header */
870 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
871 0);
872
873 brw_mark_surface_used(&prog_data->base, surf_index);
874 }
875
876 void
877 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
878 struct brw_reg dst,
879 struct brw_reg index,
880 struct brw_reg offset)
881 {
882 assert(brw->gen < 7); /* Should use the gen7 variant. */
883 assert(inst->header_present);
884 assert(inst->mlen);
885
886 assert(index.file == BRW_IMMEDIATE_VALUE &&
887 index.type == BRW_REGISTER_TYPE_UD);
888 uint32_t surf_index = index.dw1.ud;
889
890 uint32_t simd_mode, rlen, msg_type;
891 if (dispatch_width == 16) {
892 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
893 rlen = 8;
894 } else {
895 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
896 rlen = 4;
897 }
898
899 if (brw->gen >= 5)
900 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
901 else {
902 /* We always use the SIMD16 message so that we only have to load U, and
903 * not V or R.
904 */
905 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
906 assert(inst->mlen == 3);
907 assert(inst->regs_written == 8);
908 rlen = 8;
909 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
910 }
911
912 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
913 BRW_REGISTER_TYPE_D);
914 brw_MOV(p, offset_mrf, offset);
915
916 struct brw_reg header = brw_vec8_grf(0, 0);
917 gen6_resolve_implied_move(p, &header, inst->base_mrf);
918
919 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
920 send->header.compression_control = BRW_COMPRESSION_NONE;
921 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
922 brw_set_src0(p, send, header);
923 if (brw->gen < 6)
924 send->header.destreg__conditionalmod = inst->base_mrf;
925
926 /* Our surface is set up as floats, regardless of what actual data is
927 * stored in it.
928 */
929 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
930 brw_set_sampler_message(p, send,
931 surf_index,
932 0, /* sampler (unused) */
933 msg_type,
934 rlen,
935 inst->mlen,
936 inst->header_present,
937 simd_mode,
938 return_format);
939
940 brw_mark_surface_used(&prog_data->base, surf_index);
941 }
942
943 void
944 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
945 struct brw_reg dst,
946 struct brw_reg index,
947 struct brw_reg offset)
948 {
949 assert(brw->gen >= 7);
950 /* Varying-offset pull constant loads are treated as a normal expression on
951 * gen7, so the fact that it's a send message is hidden at the IR level.
952 */
953 assert(!inst->header_present);
954 assert(!inst->mlen);
955
956 assert(index.file == BRW_IMMEDIATE_VALUE &&
957 index.type == BRW_REGISTER_TYPE_UD);
958 uint32_t surf_index = index.dw1.ud;
959
960 uint32_t simd_mode, rlen, mlen;
961 if (dispatch_width == 16) {
962 mlen = 2;
963 rlen = 8;
964 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
965 } else {
966 mlen = 1;
967 rlen = 4;
968 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
969 }
970
971 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
972 brw_set_dest(p, send, dst);
973 brw_set_src0(p, send, offset);
974 brw_set_sampler_message(p, send,
975 surf_index,
976 0, /* LD message ignores sampler unit */
977 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
978 rlen,
979 mlen,
980 false, /* no header */
981 simd_mode,
982 0);
983
984 brw_mark_surface_used(&prog_data->base, surf_index);
985 }
986
987 /**
988 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
989 * into the flags register (f0.0).
990 *
991 * Used only on Gen6 and above.
992 */
993 void
994 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
995 {
996 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
997 struct brw_reg dispatch_mask;
998
999 if (brw->gen >= 6)
1000 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1001 else
1002 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1003
1004 brw_push_insn_state(p);
1005 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1006 brw_MOV(p, flags, dispatch_mask);
1007 brw_pop_insn_state(p);
1008 }
1009
1010
1011 static uint32_t brw_file_from_reg(fs_reg *reg)
1012 {
1013 switch (reg->file) {
1014 case GRF:
1015 return BRW_GENERAL_REGISTER_FILE;
1016 case MRF:
1017 return BRW_MESSAGE_REGISTER_FILE;
1018 case IMM:
1019 return BRW_IMMEDIATE_VALUE;
1020 default:
1021 assert(!"not reached");
1022 return BRW_GENERAL_REGISTER_FILE;
1023 }
1024 }
1025
1026 struct brw_reg
1027 brw_reg_from_fs_reg(fs_reg *reg)
1028 {
1029 struct brw_reg brw_reg;
1030
1031 switch (reg->file) {
1032 case GRF:
1033 case MRF:
1034 if (reg->stride == 0) {
1035 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
1036 } else {
1037 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1038 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1039 }
1040
1041 brw_reg = retype(brw_reg, reg->type);
1042 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1043 break;
1044 case IMM:
1045 switch (reg->type) {
1046 case BRW_REGISTER_TYPE_F:
1047 brw_reg = brw_imm_f(reg->imm.f);
1048 break;
1049 case BRW_REGISTER_TYPE_D:
1050 brw_reg = brw_imm_d(reg->imm.i);
1051 break;
1052 case BRW_REGISTER_TYPE_UD:
1053 brw_reg = brw_imm_ud(reg->imm.u);
1054 break;
1055 default:
1056 assert(!"not reached");
1057 brw_reg = brw_null_reg();
1058 break;
1059 }
1060 break;
1061 case HW_REG:
1062 assert(reg->type == reg->fixed_hw_reg.type);
1063 brw_reg = reg->fixed_hw_reg;
1064 break;
1065 case BAD_FILE:
1066 /* Probably unused. */
1067 brw_reg = brw_null_reg();
1068 break;
1069 case UNIFORM:
1070 assert(!"not reached");
1071 brw_reg = brw_null_reg();
1072 break;
1073 default:
1074 assert(!"not reached");
1075 brw_reg = brw_null_reg();
1076 break;
1077 }
1078 if (reg->abs)
1079 brw_reg = brw_abs(brw_reg);
1080 if (reg->negate)
1081 brw_reg = negate(brw_reg);
1082
1083 return brw_reg;
1084 }
1085
1086 /**
1087 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1088 * sampler LD messages.
1089 *
1090 * We don't want to bake it into the send message's code generation because
1091 * that means we don't get a chance to schedule the instructions.
1092 */
1093 void
1094 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1095 struct brw_reg dst,
1096 struct brw_reg value)
1097 {
1098 assert(value.file == BRW_IMMEDIATE_VALUE);
1099
1100 brw_push_insn_state(p);
1101 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1102 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1103 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1104 brw_pop_insn_state(p);
1105 }
1106
1107 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1108 * (when mask is passed as a uniform) of register mask before moving it
1109 * to register dst.
1110 */
1111 void
1112 fs_generator::generate_set_omask(fs_inst *inst,
1113 struct brw_reg dst,
1114 struct brw_reg mask)
1115 {
1116 bool stride_8_8_1 =
1117 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1118 mask.width == BRW_WIDTH_8 &&
1119 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1120
1121 bool stride_0_1_0 =
1122 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1123 mask.width == BRW_WIDTH_1 &&
1124 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1125
1126 assert(stride_8_8_1 || stride_0_1_0);
1127 assert(dst.type == BRW_REGISTER_TYPE_UW);
1128
1129 if (dispatch_width == 16)
1130 dst = vec16(dst);
1131 brw_push_insn_state(p);
1132 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1133 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1134
1135 if (stride_8_8_1) {
1136 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1137 } else if (stride_0_1_0) {
1138 brw_MOV(p, dst, retype(mask, dst.type));
1139 }
1140 brw_pop_insn_state(p);
1141 }
1142
1143 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1144 * the ADD instruction.
1145 */
1146 void
1147 fs_generator::generate_set_sample_id(fs_inst *inst,
1148 struct brw_reg dst,
1149 struct brw_reg src0,
1150 struct brw_reg src1)
1151 {
1152 assert(dst.type == BRW_REGISTER_TYPE_D ||
1153 dst.type == BRW_REGISTER_TYPE_UD);
1154 assert(src0.type == BRW_REGISTER_TYPE_D ||
1155 src0.type == BRW_REGISTER_TYPE_UD);
1156
1157 brw_push_insn_state(p);
1158 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1159 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1160 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1161 brw_ADD(p, dst, src0, reg);
1162 if (dispatch_width == 16)
1163 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1164 brw_pop_insn_state(p);
1165 }
1166
1167 /**
1168 * Change the register's data type from UD to W, doubling the strides in order
1169 * to compensate for halving the data type width.
1170 */
1171 static struct brw_reg
1172 ud_reg_to_w(struct brw_reg r)
1173 {
1174 assert(r.type == BRW_REGISTER_TYPE_UD);
1175 r.type = BRW_REGISTER_TYPE_W;
1176
1177 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1178 * doubles the real stride.
1179 */
1180 if (r.hstride != 0)
1181 ++r.hstride;
1182 if (r.vstride != 0)
1183 ++r.vstride;
1184
1185 return r;
1186 }
1187
1188 void
1189 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1190 struct brw_reg dst,
1191 struct brw_reg x,
1192 struct brw_reg y)
1193 {
1194 assert(brw->gen >= 7);
1195 assert(dst.type == BRW_REGISTER_TYPE_UD);
1196 assert(x.type == BRW_REGISTER_TYPE_F);
1197 assert(y.type == BRW_REGISTER_TYPE_F);
1198
1199 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1200 *
1201 * Because this instruction does not have a 16-bit floating-point type,
1202 * the destination data type must be Word (W).
1203 *
1204 * The destination must be DWord-aligned and specify a horizontal stride
1205 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1206 * each destination channel and the upper word is not modified.
1207 */
1208 struct brw_reg dst_w = ud_reg_to_w(dst);
1209
1210 /* Give each 32-bit channel of dst the form below , where "." means
1211 * unchanged.
1212 * 0x....hhhh
1213 */
1214 brw_F32TO16(p, dst_w, y);
1215
1216 /* Now the form:
1217 * 0xhhhh0000
1218 */
1219 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1220
1221 /* And, finally the form of packHalf2x16's output:
1222 * 0xhhhhllll
1223 */
1224 brw_F32TO16(p, dst_w, x);
1225 }
1226
1227 void
1228 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1229 struct brw_reg dst,
1230 struct brw_reg src)
1231 {
1232 assert(brw->gen >= 7);
1233 assert(dst.type == BRW_REGISTER_TYPE_F);
1234 assert(src.type == BRW_REGISTER_TYPE_UD);
1235
1236 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1237 *
1238 * Because this instruction does not have a 16-bit floating-point type,
1239 * the source data type must be Word (W). The destination type must be
1240 * F (Float).
1241 */
1242 struct brw_reg src_w = ud_reg_to_w(src);
1243
1244 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1245 * For the Y case, we wish to access only the upper word; therefore
1246 * a 16-bit subregister offset is needed.
1247 */
1248 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1249 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1250 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1251 src_w.subnr += 2;
1252
1253 brw_F16TO32(p, dst, src_w);
1254 }
1255
1256 void
1257 fs_generator::generate_shader_time_add(fs_inst *inst,
1258 struct brw_reg payload,
1259 struct brw_reg offset,
1260 struct brw_reg value)
1261 {
1262 assert(brw->gen >= 7);
1263 brw_push_insn_state(p);
1264 brw_set_default_mask_control(p, true);
1265
1266 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1267 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1268 offset.type);
1269 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1270 value.type);
1271
1272 assert(offset.file == BRW_IMMEDIATE_VALUE);
1273 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1274 value.width = BRW_WIDTH_1;
1275 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1276 value.vstride = BRW_VERTICAL_STRIDE_0;
1277 } else {
1278 assert(value.file == BRW_IMMEDIATE_VALUE);
1279 }
1280
1281 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1282 * case, and we don't really care about squeezing every bit of performance
1283 * out of this path, so we just emit the MOVs from here.
1284 */
1285 brw_MOV(p, payload_offset, offset);
1286 brw_MOV(p, payload_value, value);
1287 brw_shader_time_add(p, payload,
1288 prog_data->base.binding_table.shader_time_start);
1289 brw_pop_insn_state(p);
1290
1291 brw_mark_surface_used(&prog_data->base,
1292 prog_data->base.binding_table.shader_time_start);
1293 }
1294
1295 void
1296 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1297 struct brw_reg atomic_op,
1298 struct brw_reg surf_index)
1299 {
1300 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1301 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1302 surf_index.file == BRW_IMMEDIATE_VALUE &&
1303 surf_index.type == BRW_REGISTER_TYPE_UD);
1304
1305 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1306 atomic_op.dw1.ud, surf_index.dw1.ud,
1307 inst->mlen, dispatch_width / 8);
1308
1309 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1310 }
1311
1312 void
1313 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1314 struct brw_reg surf_index)
1315 {
1316 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1317 surf_index.type == BRW_REGISTER_TYPE_UD);
1318
1319 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1320 surf_index.dw1.ud,
1321 inst->mlen, dispatch_width / 8);
1322
1323 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1324 }
1325
1326 void
1327 fs_generator::generate_code(exec_list *instructions)
1328 {
1329 int start_offset = p->next_insn_offset;
1330
1331 struct annotation_info annotation;
1332 memset(&annotation, 0, sizeof(annotation));
1333
1334 cfg_t *cfg = NULL;
1335 if (unlikely(debug_flag))
1336 cfg = new(mem_ctx) cfg_t(instructions);
1337
1338 foreach_list(node, instructions) {
1339 fs_inst *inst = (fs_inst *)node;
1340 struct brw_reg src[3], dst;
1341 unsigned int last_insn_offset = p->next_insn_offset;
1342
1343 if (unlikely(debug_flag))
1344 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1345
1346 for (unsigned int i = 0; i < inst->sources; i++) {
1347 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1348
1349 /* The accumulator result appears to get used for the
1350 * conditional modifier generation. When negating a UD
1351 * value, there is a 33rd bit generated for the sign in the
1352 * accumulator value, so now you can't check, for example,
1353 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1354 */
1355 assert(!inst->conditional_mod ||
1356 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1357 !inst->src[i].negate);
1358 }
1359 dst = brw_reg_from_fs_reg(&inst->dst);
1360
1361 brw_set_default_predicate_control(p, inst->predicate);
1362 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1363 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1364 brw_set_default_saturate(p, inst->saturate);
1365 brw_set_default_mask_control(p, inst->force_writemask_all);
1366 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1367
1368 if (inst->force_uncompressed || dispatch_width == 8) {
1369 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1370 } else if (inst->force_sechalf) {
1371 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1372 } else {
1373 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1374 }
1375
1376 switch (inst->opcode) {
1377 case BRW_OPCODE_MOV:
1378 brw_MOV(p, dst, src[0]);
1379 break;
1380 case BRW_OPCODE_ADD:
1381 brw_ADD(p, dst, src[0], src[1]);
1382 break;
1383 case BRW_OPCODE_MUL:
1384 brw_MUL(p, dst, src[0], src[1]);
1385 break;
1386 case BRW_OPCODE_AVG:
1387 brw_AVG(p, dst, src[0], src[1]);
1388 break;
1389 case BRW_OPCODE_MACH:
1390 brw_MACH(p, dst, src[0], src[1]);
1391 break;
1392
1393 case BRW_OPCODE_MAD:
1394 assert(brw->gen >= 6);
1395 brw_set_default_access_mode(p, BRW_ALIGN_16);
1396 if (dispatch_width == 16 && !brw->is_haswell) {
1397 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1398 brw_MAD(p, dst, src[0], src[1], src[2]);
1399 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1400 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1401 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1402 } else {
1403 brw_MAD(p, dst, src[0], src[1], src[2]);
1404 }
1405 brw_set_default_access_mode(p, BRW_ALIGN_1);
1406 break;
1407
1408 case BRW_OPCODE_LRP:
1409 assert(brw->gen >= 6);
1410 brw_set_default_access_mode(p, BRW_ALIGN_16);
1411 if (dispatch_width == 16 && !brw->is_haswell) {
1412 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1413 brw_LRP(p, dst, src[0], src[1], src[2]);
1414 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1415 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1416 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1417 } else {
1418 brw_LRP(p, dst, src[0], src[1], src[2]);
1419 }
1420 brw_set_default_access_mode(p, BRW_ALIGN_1);
1421 break;
1422
1423 case BRW_OPCODE_FRC:
1424 brw_FRC(p, dst, src[0]);
1425 break;
1426 case BRW_OPCODE_RNDD:
1427 brw_RNDD(p, dst, src[0]);
1428 break;
1429 case BRW_OPCODE_RNDE:
1430 brw_RNDE(p, dst, src[0]);
1431 break;
1432 case BRW_OPCODE_RNDZ:
1433 brw_RNDZ(p, dst, src[0]);
1434 break;
1435
1436 case BRW_OPCODE_AND:
1437 brw_AND(p, dst, src[0], src[1]);
1438 break;
1439 case BRW_OPCODE_OR:
1440 brw_OR(p, dst, src[0], src[1]);
1441 break;
1442 case BRW_OPCODE_XOR:
1443 brw_XOR(p, dst, src[0], src[1]);
1444 break;
1445 case BRW_OPCODE_NOT:
1446 brw_NOT(p, dst, src[0]);
1447 break;
1448 case BRW_OPCODE_ASR:
1449 brw_ASR(p, dst, src[0], src[1]);
1450 break;
1451 case BRW_OPCODE_SHR:
1452 brw_SHR(p, dst, src[0], src[1]);
1453 break;
1454 case BRW_OPCODE_SHL:
1455 brw_SHL(p, dst, src[0], src[1]);
1456 break;
1457 case BRW_OPCODE_F32TO16:
1458 assert(brw->gen >= 7);
1459 brw_F32TO16(p, dst, src[0]);
1460 break;
1461 case BRW_OPCODE_F16TO32:
1462 assert(brw->gen >= 7);
1463 brw_F16TO32(p, dst, src[0]);
1464 break;
1465 case BRW_OPCODE_CMP:
1466 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1467 break;
1468 case BRW_OPCODE_SEL:
1469 brw_SEL(p, dst, src[0], src[1]);
1470 break;
1471 case BRW_OPCODE_BFREV:
1472 assert(brw->gen >= 7);
1473 /* BFREV only supports UD type for src and dst. */
1474 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1475 retype(src[0], BRW_REGISTER_TYPE_UD));
1476 break;
1477 case BRW_OPCODE_FBH:
1478 assert(brw->gen >= 7);
1479 /* FBH only supports UD type for dst. */
1480 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1481 break;
1482 case BRW_OPCODE_FBL:
1483 assert(brw->gen >= 7);
1484 /* FBL only supports UD type for dst. */
1485 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1486 break;
1487 case BRW_OPCODE_CBIT:
1488 assert(brw->gen >= 7);
1489 /* CBIT only supports UD type for dst. */
1490 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1491 break;
1492 case BRW_OPCODE_ADDC:
1493 assert(brw->gen >= 7);
1494 brw_ADDC(p, dst, src[0], src[1]);
1495 break;
1496 case BRW_OPCODE_SUBB:
1497 assert(brw->gen >= 7);
1498 brw_SUBB(p, dst, src[0], src[1]);
1499 break;
1500 case BRW_OPCODE_MAC:
1501 brw_MAC(p, dst, src[0], src[1]);
1502 break;
1503
1504 case BRW_OPCODE_BFE:
1505 assert(brw->gen >= 7);
1506 brw_set_default_access_mode(p, BRW_ALIGN_16);
1507 if (dispatch_width == 16 && !brw->is_haswell) {
1508 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1509 brw_BFE(p, dst, src[0], src[1], src[2]);
1510 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1511 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1512 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1513 } else {
1514 brw_BFE(p, dst, src[0], src[1], src[2]);
1515 }
1516 brw_set_default_access_mode(p, BRW_ALIGN_1);
1517 break;
1518
1519 case BRW_OPCODE_BFI1:
1520 assert(brw->gen >= 7);
1521 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1522 * should
1523 *
1524 * "Force BFI instructions to be executed always in SIMD8."
1525 */
1526 if (dispatch_width == 16 && brw->is_haswell) {
1527 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1528 brw_BFI1(p, dst, src[0], src[1]);
1529 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1530 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1531 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1532 } else {
1533 brw_BFI1(p, dst, src[0], src[1]);
1534 }
1535 break;
1536 case BRW_OPCODE_BFI2:
1537 assert(brw->gen >= 7);
1538 brw_set_default_access_mode(p, BRW_ALIGN_16);
1539 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1540 * should
1541 *
1542 * "Force BFI instructions to be executed always in SIMD8."
1543 *
1544 * Otherwise we would be able to emit compressed instructions like we
1545 * do for the other three-source instructions.
1546 */
1547 if (dispatch_width == 16) {
1548 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1549 brw_BFI2(p, dst, src[0], src[1], src[2]);
1550 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1551 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1552 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1553 } else {
1554 brw_BFI2(p, dst, src[0], src[1], src[2]);
1555 }
1556 brw_set_default_access_mode(p, BRW_ALIGN_1);
1557 break;
1558
1559 case BRW_OPCODE_IF:
1560 if (inst->src[0].file != BAD_FILE) {
1561 /* The instruction has an embedded compare (only allowed on gen6) */
1562 assert(brw->gen == 6);
1563 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1564 } else {
1565 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1566 }
1567 break;
1568
1569 case BRW_OPCODE_ELSE:
1570 brw_ELSE(p);
1571 break;
1572 case BRW_OPCODE_ENDIF:
1573 brw_ENDIF(p);
1574 break;
1575
1576 case BRW_OPCODE_DO:
1577 brw_DO(p, BRW_EXECUTE_8);
1578 break;
1579
1580 case BRW_OPCODE_BREAK:
1581 brw_BREAK(p);
1582 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1583 break;
1584 case BRW_OPCODE_CONTINUE:
1585 /* FINISHME: We need to write the loop instruction support still. */
1586 if (brw->gen >= 6)
1587 gen6_CONT(p);
1588 else
1589 brw_CONT(p);
1590 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1591 break;
1592
1593 case BRW_OPCODE_WHILE:
1594 brw_WHILE(p);
1595 break;
1596
1597 case SHADER_OPCODE_RCP:
1598 case SHADER_OPCODE_RSQ:
1599 case SHADER_OPCODE_SQRT:
1600 case SHADER_OPCODE_EXP2:
1601 case SHADER_OPCODE_LOG2:
1602 case SHADER_OPCODE_SIN:
1603 case SHADER_OPCODE_COS:
1604 if (brw->gen >= 7) {
1605 generate_math1_gen7(inst, dst, src[0]);
1606 } else if (brw->gen == 6) {
1607 generate_math1_gen6(inst, dst, src[0]);
1608 } else if (brw->gen == 5 || brw->is_g4x) {
1609 generate_math_g45(inst, dst, src[0]);
1610 } else {
1611 generate_math_gen4(inst, dst, src[0]);
1612 }
1613 break;
1614 case SHADER_OPCODE_INT_QUOTIENT:
1615 case SHADER_OPCODE_INT_REMAINDER:
1616 case SHADER_OPCODE_POW:
1617 if (brw->gen >= 7) {
1618 generate_math2_gen7(inst, dst, src[0], src[1]);
1619 } else if (brw->gen == 6) {
1620 generate_math2_gen6(inst, dst, src[0], src[1]);
1621 } else {
1622 generate_math_gen4(inst, dst, src[0]);
1623 }
1624 break;
1625 case FS_OPCODE_PIXEL_X:
1626 generate_pixel_xy(dst, true);
1627 break;
1628 case FS_OPCODE_PIXEL_Y:
1629 generate_pixel_xy(dst, false);
1630 break;
1631 case FS_OPCODE_CINTERP:
1632 brw_MOV(p, dst, src[0]);
1633 break;
1634 case FS_OPCODE_LINTERP:
1635 generate_linterp(inst, dst, src);
1636 break;
1637 case SHADER_OPCODE_TEX:
1638 case FS_OPCODE_TXB:
1639 case SHADER_OPCODE_TXD:
1640 case SHADER_OPCODE_TXF:
1641 case SHADER_OPCODE_TXF_CMS:
1642 case SHADER_OPCODE_TXF_UMS:
1643 case SHADER_OPCODE_TXF_MCS:
1644 case SHADER_OPCODE_TXL:
1645 case SHADER_OPCODE_TXS:
1646 case SHADER_OPCODE_LOD:
1647 case SHADER_OPCODE_TG4:
1648 case SHADER_OPCODE_TG4_OFFSET:
1649 generate_tex(inst, dst, src[0]);
1650 break;
1651 case FS_OPCODE_DDX:
1652 generate_ddx(inst, dst, src[0]);
1653 break;
1654 case FS_OPCODE_DDY:
1655 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1656 * guarantee that key->render_to_fbo is set).
1657 */
1658 assert(fp->UsesDFdy);
1659 generate_ddy(inst, dst, src[0], key->render_to_fbo);
1660 break;
1661
1662 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1663 generate_scratch_write(inst, src[0]);
1664 break;
1665
1666 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1667 generate_scratch_read(inst, dst);
1668 break;
1669
1670 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1671 generate_scratch_read_gen7(inst, dst);
1672 break;
1673
1674 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1675 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1676 break;
1677
1678 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1679 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1680 break;
1681
1682 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1683 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1684 break;
1685
1686 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1687 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1688 break;
1689
1690 case FS_OPCODE_FB_WRITE:
1691 generate_fb_write(inst);
1692 break;
1693
1694 case FS_OPCODE_BLORP_FB_WRITE:
1695 generate_blorp_fb_write(inst);
1696 break;
1697
1698 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1699 generate_mov_dispatch_to_flags(inst);
1700 break;
1701
1702 case FS_OPCODE_DISCARD_JUMP:
1703 generate_discard_jump(inst);
1704 break;
1705
1706 case SHADER_OPCODE_SHADER_TIME_ADD:
1707 generate_shader_time_add(inst, src[0], src[1], src[2]);
1708 break;
1709
1710 case SHADER_OPCODE_UNTYPED_ATOMIC:
1711 generate_untyped_atomic(inst, dst, src[0], src[1]);
1712 break;
1713
1714 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1715 generate_untyped_surface_read(inst, dst, src[0]);
1716 break;
1717
1718 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1719 generate_set_simd4x2_offset(inst, dst, src[0]);
1720 break;
1721
1722 case FS_OPCODE_SET_OMASK:
1723 generate_set_omask(inst, dst, src[0]);
1724 break;
1725
1726 case FS_OPCODE_SET_SAMPLE_ID:
1727 generate_set_sample_id(inst, dst, src[0], src[1]);
1728 break;
1729
1730 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1731 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1732 break;
1733
1734 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1735 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1736 generate_unpack_half_2x16_split(inst, dst, src[0]);
1737 break;
1738
1739 case FS_OPCODE_PLACEHOLDER_HALT:
1740 /* This is the place where the final HALT needs to be inserted if
1741 * we've emitted any discards. If not, this will emit no code.
1742 */
1743 if (!patch_discard_jumps_to_fb_writes()) {
1744 if (unlikely(debug_flag)) {
1745 annotation.ann_count--;
1746 }
1747 }
1748 break;
1749
1750 default:
1751 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1752 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1753 opcode_descs[inst->opcode].name);
1754 } else {
1755 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1756 }
1757 abort();
1758 }
1759
1760 if (inst->conditional_mod) {
1761 /* Set the conditional modifier on the last instruction we generated.
1762 * Also, make sure we only emitted one instruction - anything else
1763 * doesn't make sense.
1764 */
1765 assert(p->next_insn_offset == last_insn_offset + 16);
1766 struct brw_instruction *last = &p->store[last_insn_offset / 16];
1767 last->header.destreg__conditionalmod = inst->conditional_mod;
1768 }
1769 }
1770
1771 brw_set_uip_jip(p);
1772 annotation_finalize(&annotation, p->next_insn_offset);
1773
1774 int before_size = p->next_insn_offset - start_offset;
1775 brw_compact_instructions(p, start_offset, annotation.ann_count,
1776 annotation.ann);
1777 int after_size = p->next_insn_offset - start_offset;
1778
1779 if (unlikely(debug_flag)) {
1780 if (prog) {
1781 fprintf(stderr,
1782 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
1783 prog->Label ? prog->Label : "unnamed",
1784 prog->Name, dispatch_width);
1785 } else if (fp) {
1786 fprintf(stderr,
1787 "Native code for fragment program %d (SIMD%d dispatch):\n",
1788 fp->Base.Id, dispatch_width);
1789 } else {
1790 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
1791 dispatch_width);
1792 }
1793 fprintf(stderr, "SIMD%d shader: %d instructions. Compacted %d to %d"
1794 " bytes (%.0f%%)\n",
1795 dispatch_width, before_size / 16, before_size, after_size,
1796 100.0f * (before_size - after_size) / before_size);
1797
1798 const struct gl_program *prog = fp ? &fp->Base : NULL;
1799
1800 dump_assembly(p->store, annotation.ann_count, annotation.ann,
1801 brw, prog, brw_disassemble);
1802 ralloc_free(annotation.ann);
1803 }
1804 }
1805
1806 const unsigned *
1807 fs_generator::generate_assembly(exec_list *simd8_instructions,
1808 exec_list *simd16_instructions,
1809 unsigned *assembly_size)
1810 {
1811 assert(simd8_instructions || simd16_instructions);
1812
1813 if (simd8_instructions) {
1814 dispatch_width = 8;
1815 generate_code(simd8_instructions);
1816 }
1817
1818 if (simd16_instructions) {
1819 /* align to 64 byte boundary. */
1820 while (p->next_insn_offset % 64) {
1821 brw_NOP(p);
1822 }
1823
1824 /* Save off the start of this SIMD16 program */
1825 prog_data->prog_offset_16 = p->next_insn_offset;
1826
1827 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1828
1829 dispatch_width = 16;
1830 generate_code(simd16_instructions);
1831 }
1832
1833 return brw_get_program(p, assembly_size);
1834 }