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i965/fs: Add stage variable to fs_generator
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 void *mem_ctx,
41 const struct brw_wm_prog_key *key,
42 struct brw_wm_prog_data *prog_data,
43 struct gl_shader_program *prog,
44 struct gl_fragment_program *fp,
45 bool runtime_check_aads_emit,
46 bool debug_flag)
47
48 : brw(brw), stage(MESA_SHADER_FRAGMENT), key(key),
49 prog_data(prog_data), prog(prog), fp(fp),
50 runtime_check_aads_emit(runtime_check_aads_emit),
51 debug_flag(debug_flag), mem_ctx(mem_ctx)
52 {
53 ctx = &brw->ctx;
54
55 p = rzalloc(mem_ctx, struct brw_compile);
56 brw_init_compile(brw, p, mem_ctx);
57 }
58
59 fs_generator::~fs_generator()
60 {
61 }
62
63 bool
64 fs_generator::patch_discard_jumps_to_fb_writes()
65 {
66 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
67 return false;
68
69 int scale = brw_jump_scale(brw);
70
71 /* There is a somewhat strange undocumented requirement of using
72 * HALT, according to the simulator. If some channel has HALTed to
73 * a particular UIP, then by the end of the program, every channel
74 * must have HALTed to that UIP. Furthermore, the tracking is a
75 * stack, so you can't do the final halt of a UIP after starting
76 * halting to a new UIP.
77 *
78 * Symptoms of not emitting this instruction on actual hardware
79 * included GPU hangs and sparkly rendering on the piglit discard
80 * tests.
81 */
82 brw_inst *last_halt = gen6_HALT(p);
83 brw_inst_set_uip(brw, last_halt, 1 * scale);
84 brw_inst_set_jip(brw, last_halt, 1 * scale);
85
86 int ip = p->nr_insn;
87
88 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
89 brw_inst *patch = &p->store[patch_ip->ip];
90
91 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
92 /* HALT takes a half-instruction distance from the pre-incremented IP. */
93 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
94 }
95
96 this->discard_halt_patches.make_empty();
97 return true;
98 }
99
100 void
101 fs_generator::fire_fb_write(fs_inst *inst,
102 GLuint base_reg,
103 struct brw_reg implied_header,
104 GLuint nr)
105 {
106 uint32_t msg_control;
107
108 if (brw->gen < 6) {
109 brw_push_insn_state(p);
110 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
111 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
112 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
113 brw_MOV(p,
114 brw_message_reg(base_reg + 1),
115 brw_vec8_grf(1, 0));
116 brw_pop_insn_state(p);
117 }
118
119 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
120 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
121 else if (prog_data->dual_src_blend)
122 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
123 else if (dispatch_width == 16)
124 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
125 else
126 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
127
128 uint32_t surf_index =
129 prog_data->binding_table.render_target_start + inst->target;
130
131 brw_fb_WRITE(p,
132 dispatch_width,
133 base_reg,
134 implied_header,
135 msg_control,
136 surf_index,
137 nr,
138 0,
139 inst->eot,
140 inst->header_present);
141
142 brw_mark_surface_used(&prog_data->base, surf_index);
143 }
144
145 void
146 fs_generator::generate_fb_write(fs_inst *inst)
147 {
148 struct brw_reg implied_header;
149
150 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
151 * move, here's g1.
152 */
153 if (inst->header_present) {
154 brw_push_insn_state(p);
155 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
156 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
157 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
158 brw_set_default_flag_reg(p, 0, 0);
159
160 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
161 * present.
162 */
163 if ((fp && fp->UsesKill) || key->alpha_test_func) {
164 struct brw_reg pixel_mask;
165
166 if (brw->gen >= 6)
167 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
168 else
169 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
170
171 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
172 }
173
174 if (brw->gen >= 6) {
175 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
176 brw_MOV(p,
177 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
178 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
179 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
180
181 if (inst->target > 0 && key->replicate_alpha) {
182 /* Set "Source0 Alpha Present to RenderTarget" bit in message
183 * header.
184 */
185 brw_OR(p,
186 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
187 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
188 brw_imm_ud(0x1 << 11));
189 }
190
191 if (inst->target > 0) {
192 /* Set the render target index for choosing BLEND_STATE. */
193 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
194 inst->base_mrf, 2),
195 BRW_REGISTER_TYPE_UD),
196 brw_imm_ud(inst->target));
197 }
198
199 implied_header = brw_null_reg();
200 } else {
201 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
202 }
203
204 brw_pop_insn_state(p);
205 } else {
206 implied_header = brw_null_reg();
207 }
208
209 if (!runtime_check_aads_emit) {
210 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
211 } else {
212 /* This can only happen in gen < 6 */
213 assert(brw->gen < 6);
214
215 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
216
217 /* Check runtime bit to detect if we have to send AA data or not */
218 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
219 brw_AND(p,
220 v1_null_ud,
221 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
222 brw_imm_ud(1<<26));
223 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
224
225 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
226 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
227 {
228 /* Don't send AA data */
229 fire_fb_write(inst, inst->base_mrf+1, implied_header, inst->mlen-1);
230 }
231 brw_land_fwd_jump(p, jmp);
232 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
233 }
234 }
235
236 void
237 fs_generator::generate_blorp_fb_write(fs_inst *inst)
238 {
239 brw_fb_WRITE(p,
240 16 /* dispatch_width */,
241 inst->base_mrf,
242 brw_reg_from_fs_reg(&inst->src[0]),
243 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
244 inst->target,
245 inst->mlen,
246 0,
247 true,
248 inst->header_present);
249 }
250
251 /* Computes the integer pixel x,y values from the origin.
252 *
253 * This is the basis of gl_FragCoord computation, but is also used
254 * pre-gen6 for computing the deltas from v0 for computing
255 * interpolation.
256 */
257 void
258 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
259 {
260 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
261 struct brw_reg src;
262 struct brw_reg deltas;
263
264 if (is_x) {
265 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
266 deltas = brw_imm_v(0x10101010);
267 } else {
268 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
269 deltas = brw_imm_v(0x11001100);
270 }
271
272 if (dispatch_width == 16) {
273 dst = vec16(dst);
274 }
275
276 /* We do this SIMD8 or SIMD16, but since the destination is UW we
277 * don't do compression in the SIMD16 case.
278 */
279 brw_push_insn_state(p);
280 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
281 brw_ADD(p, dst, src, deltas);
282 brw_pop_insn_state(p);
283 }
284
285 void
286 fs_generator::generate_linterp(fs_inst *inst,
287 struct brw_reg dst, struct brw_reg *src)
288 {
289 struct brw_reg delta_x = src[0];
290 struct brw_reg delta_y = src[1];
291 struct brw_reg interp = src[2];
292
293 if (brw->has_pln &&
294 delta_y.nr == delta_x.nr + 1 &&
295 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
296 brw_PLN(p, dst, interp, delta_x);
297 } else {
298 brw_LINE(p, brw_null_reg(), interp, delta_x);
299 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
300 }
301 }
302
303 void
304 fs_generator::generate_math_gen6(fs_inst *inst,
305 struct brw_reg dst,
306 struct brw_reg src0,
307 struct brw_reg src1)
308 {
309 int op = brw_math_function(inst->opcode);
310 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
311
312 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
313 gen6_math(p, dst, op, src0, src1);
314
315 if (dispatch_width == 16) {
316 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
317 gen6_math(p, sechalf(dst), op, sechalf(src0),
318 binop ? sechalf(src1) : brw_null_reg());
319 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
320 }
321 }
322
323 void
324 fs_generator::generate_math_gen4(fs_inst *inst,
325 struct brw_reg dst,
326 struct brw_reg src)
327 {
328 int op = brw_math_function(inst->opcode);
329
330 assert(inst->mlen >= 1);
331
332 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
333 gen4_math(p, dst,
334 op,
335 inst->base_mrf, src,
336 BRW_MATH_DATA_VECTOR,
337 BRW_MATH_PRECISION_FULL);
338
339 if (dispatch_width == 16) {
340 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
341 gen4_math(p, sechalf(dst),
342 op,
343 inst->base_mrf + 1, sechalf(src),
344 BRW_MATH_DATA_VECTOR,
345 BRW_MATH_PRECISION_FULL);
346
347 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
348 }
349 }
350
351 void
352 fs_generator::generate_math_g45(fs_inst *inst,
353 struct brw_reg dst,
354 struct brw_reg src)
355 {
356 if (inst->opcode == SHADER_OPCODE_POW ||
357 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
358 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
359 generate_math_gen4(inst, dst, src);
360 return;
361 }
362
363 int op = brw_math_function(inst->opcode);
364
365 assert(inst->mlen >= 1);
366
367 gen4_math(p, dst,
368 op,
369 inst->base_mrf, src,
370 BRW_MATH_DATA_VECTOR,
371 BRW_MATH_PRECISION_FULL);
372 }
373
374 void
375 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
376 struct brw_reg sampler_index)
377 {
378 int msg_type = -1;
379 int rlen = 4;
380 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
381 uint32_t return_format;
382
383 switch (dst.type) {
384 case BRW_REGISTER_TYPE_D:
385 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
386 break;
387 case BRW_REGISTER_TYPE_UD:
388 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
389 break;
390 default:
391 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
392 break;
393 }
394
395 if (dispatch_width == 16 &&
396 !inst->force_uncompressed && !inst->force_sechalf)
397 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
398
399 if (brw->gen >= 5) {
400 switch (inst->opcode) {
401 case SHADER_OPCODE_TEX:
402 if (inst->shadow_compare) {
403 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
404 } else {
405 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
406 }
407 break;
408 case FS_OPCODE_TXB:
409 if (inst->shadow_compare) {
410 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
411 } else {
412 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
413 }
414 break;
415 case SHADER_OPCODE_TXL:
416 if (inst->shadow_compare) {
417 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
418 } else {
419 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
420 }
421 break;
422 case SHADER_OPCODE_TXS:
423 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
424 break;
425 case SHADER_OPCODE_TXD:
426 if (inst->shadow_compare) {
427 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
428 assert(brw->gen >= 8 || brw->is_haswell);
429 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
430 } else {
431 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
432 }
433 break;
434 case SHADER_OPCODE_TXF:
435 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
436 break;
437 case SHADER_OPCODE_TXF_CMS:
438 if (brw->gen >= 7)
439 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
440 else
441 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
442 break;
443 case SHADER_OPCODE_TXF_UMS:
444 assert(brw->gen >= 7);
445 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
446 break;
447 case SHADER_OPCODE_TXF_MCS:
448 assert(brw->gen >= 7);
449 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
450 break;
451 case SHADER_OPCODE_LOD:
452 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
453 break;
454 case SHADER_OPCODE_TG4:
455 if (inst->shadow_compare) {
456 assert(brw->gen >= 7);
457 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
458 } else {
459 assert(brw->gen >= 6);
460 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
461 }
462 break;
463 case SHADER_OPCODE_TG4_OFFSET:
464 assert(brw->gen >= 7);
465 if (inst->shadow_compare) {
466 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
467 } else {
468 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
469 }
470 break;
471 default:
472 unreachable("not reached");
473 }
474 } else {
475 switch (inst->opcode) {
476 case SHADER_OPCODE_TEX:
477 /* Note that G45 and older determines shadow compare and dispatch width
478 * from message length for most messages.
479 */
480 assert(dispatch_width == 8);
481 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
482 if (inst->shadow_compare) {
483 assert(inst->mlen == 6);
484 } else {
485 assert(inst->mlen <= 4);
486 }
487 break;
488 case FS_OPCODE_TXB:
489 if (inst->shadow_compare) {
490 assert(inst->mlen == 6);
491 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
492 } else {
493 assert(inst->mlen == 9);
494 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
495 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
496 }
497 break;
498 case SHADER_OPCODE_TXL:
499 if (inst->shadow_compare) {
500 assert(inst->mlen == 6);
501 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
502 } else {
503 assert(inst->mlen == 9);
504 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
505 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
506 }
507 break;
508 case SHADER_OPCODE_TXD:
509 /* There is no sample_d_c message; comparisons are done manually */
510 assert(inst->mlen == 7 || inst->mlen == 10);
511 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
512 break;
513 case SHADER_OPCODE_TXF:
514 assert(inst->mlen == 9);
515 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
516 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
517 break;
518 case SHADER_OPCODE_TXS:
519 assert(inst->mlen == 3);
520 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
521 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
522 break;
523 default:
524 unreachable("not reached");
525 }
526 }
527 assert(msg_type != -1);
528
529 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
530 rlen = 8;
531 dst = vec16(dst);
532 }
533
534 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
535 /* The send-from-GRF for SIMD16 texturing with a header has an extra
536 * hardware register allocated to it, which we need to skip over (since
537 * our coordinates in the payload are in the even-numbered registers,
538 * and the header comes right before the first one).
539 */
540 assert(src.file == BRW_GENERAL_REGISTER_FILE);
541 src.nr++;
542 }
543
544 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
545
546 /* Load the message header if present. If there's a texture offset,
547 * we need to set it up explicitly and load the offset bitfield.
548 * Otherwise, we can use an implied move from g0 to the first message reg.
549 */
550 if (inst->header_present) {
551 if (brw->gen < 6 && !inst->texture_offset) {
552 /* Set up an implied move from g0 to the MRF. */
553 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
554 } else {
555 struct brw_reg header_reg;
556
557 if (brw->gen >= 7) {
558 header_reg = src;
559 } else {
560 assert(inst->base_mrf != -1);
561 header_reg = brw_message_reg(inst->base_mrf);
562 }
563
564 brw_push_insn_state(p);
565 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
566 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
567 /* Explicitly set up the message header by copying g0 to the MRF. */
568 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
569
570 if (inst->texture_offset) {
571 /* Set the offset bits in DWord 2. */
572 brw_MOV(p, get_element_ud(header_reg, 2),
573 brw_imm_ud(inst->texture_offset));
574 }
575
576 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index, dst);
577 brw_pop_insn_state(p);
578 }
579 }
580
581 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
582 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
583 ? prog_data->base.binding_table.gather_texture_start
584 : prog_data->base.binding_table.texture_start;
585
586 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
587 uint32_t sampler = sampler_index.dw1.ud;
588
589 brw_SAMPLE(p,
590 retype(dst, BRW_REGISTER_TYPE_UW),
591 inst->base_mrf,
592 src,
593 sampler + base_binding_table_index,
594 sampler % 16,
595 msg_type,
596 rlen,
597 inst->mlen,
598 inst->header_present,
599 simd_mode,
600 return_format);
601
602 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
603 } else {
604 /* Non-const sampler index */
605 /* Note: this clobbers `dst` as a temporary before emitting the send */
606
607 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
608 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
609
610 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
611
612 brw_push_insn_state(p);
613 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
614 brw_set_default_access_mode(p, BRW_ALIGN_1);
615
616 /* Some care required: `sampler` and `temp` may alias:
617 * addr = sampler & 0xff
618 * temp = (sampler << 8) & 0xf00
619 * addr = addr | temp
620 */
621 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
622 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
623 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
624 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
625 brw_OR(p, addr, addr, temp);
626
627 /* a0.0 |= <descriptor> */
628 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
629 brw_set_sampler_message(p, insn_or,
630 0 /* surface */,
631 0 /* sampler */,
632 msg_type,
633 rlen,
634 inst->mlen /* mlen */,
635 inst->header_present /* header */,
636 simd_mode,
637 return_format);
638 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
639 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
640 brw_set_src0(p, insn_or, addr);
641 brw_set_dest(p, insn_or, addr);
642
643
644 /* dst = send(offset, a0.0) */
645 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
646 brw_set_dest(p, insn_send, dst);
647 brw_set_src0(p, insn_send, src);
648 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
649
650 brw_pop_insn_state(p);
651
652 /* visitor knows more than we do about the surface limit required,
653 * so has already done marking.
654 */
655 }
656 }
657
658
659 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
660 * looking like:
661 *
662 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
663 *
664 * Ideally, we want to produce:
665 *
666 * DDX DDY
667 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
668 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
669 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
670 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
671 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
672 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
673 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
674 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
675 *
676 * and add another set of two more subspans if in 16-pixel dispatch mode.
677 *
678 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
679 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
680 * pair. But the ideal approximation may impose a huge performance cost on
681 * sample_d. On at least Haswell, sample_d instruction does some
682 * optimizations if the same LOD is used for all pixels in the subspan.
683 *
684 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
685 * appropriate swizzling.
686 */
687 void
688 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
689 struct brw_reg quality)
690 {
691 unsigned vstride, width;
692 assert(quality.file == BRW_IMMEDIATE_VALUE);
693 assert(quality.type == BRW_REGISTER_TYPE_D);
694
695 int quality_value = quality.dw1.d;
696
697 if (quality_value == BRW_DERIVATIVE_FINE ||
698 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
699 /* produce accurate derivatives */
700 vstride = BRW_VERTICAL_STRIDE_2;
701 width = BRW_WIDTH_2;
702 }
703 else {
704 /* replicate the derivative at the top-left pixel to other pixels */
705 vstride = BRW_VERTICAL_STRIDE_4;
706 width = BRW_WIDTH_4;
707 }
708
709 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
710 BRW_REGISTER_TYPE_F,
711 vstride,
712 width,
713 BRW_HORIZONTAL_STRIDE_0,
714 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
715 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
716 BRW_REGISTER_TYPE_F,
717 vstride,
718 width,
719 BRW_HORIZONTAL_STRIDE_0,
720 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
721 brw_ADD(p, dst, src0, negate(src1));
722 }
723
724 /* The negate_value boolean is used to negate the derivative computation for
725 * FBOs, since they place the origin at the upper left instead of the lower
726 * left.
727 */
728 void
729 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
730 struct brw_reg quality, bool negate_value)
731 {
732 assert(quality.file == BRW_IMMEDIATE_VALUE);
733 assert(quality.type == BRW_REGISTER_TYPE_D);
734
735 int quality_value = quality.dw1.d;
736
737 if (quality_value == BRW_DERIVATIVE_FINE ||
738 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
739 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
740 * Region Restrictions):
741 *
742 * In Align16 access mode, SIMD16 is not allowed for DW operations
743 * and SIMD8 is not allowed for DF operations.
744 *
745 * In this context, "DW operations" means "operations acting on 32-bit
746 * values", so it includes operations on floats.
747 *
748 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
749 * (Instruction Compression -> Rules and Restrictions):
750 *
751 * A compressed instruction must be in Align1 access mode. Align16
752 * mode instructions cannot be compressed.
753 *
754 * Similar text exists in the g45 PRM.
755 *
756 * On these platforms, if we're building a SIMD16 shader, we need to
757 * manually unroll to a pair of SIMD8 instructions.
758 */
759 bool unroll_to_simd8 =
760 (dispatch_width == 16 &&
761 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
762
763 /* produce accurate derivatives */
764 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
765 BRW_REGISTER_TYPE_F,
766 BRW_VERTICAL_STRIDE_4,
767 BRW_WIDTH_4,
768 BRW_HORIZONTAL_STRIDE_1,
769 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
770 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
771 BRW_REGISTER_TYPE_F,
772 BRW_VERTICAL_STRIDE_4,
773 BRW_WIDTH_4,
774 BRW_HORIZONTAL_STRIDE_1,
775 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
776 brw_push_insn_state(p);
777 brw_set_default_access_mode(p, BRW_ALIGN_16);
778 if (unroll_to_simd8)
779 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
780 if (negate_value)
781 brw_ADD(p, dst, src1, negate(src0));
782 else
783 brw_ADD(p, dst, src0, negate(src1));
784 if (unroll_to_simd8) {
785 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
786 src0 = sechalf(src0);
787 src1 = sechalf(src1);
788 dst = sechalf(dst);
789 if (negate_value)
790 brw_ADD(p, dst, src1, negate(src0));
791 else
792 brw_ADD(p, dst, src0, negate(src1));
793 }
794 brw_pop_insn_state(p);
795 } else {
796 /* replicate the derivative at the top-left pixel to other pixels */
797 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
798 BRW_REGISTER_TYPE_F,
799 BRW_VERTICAL_STRIDE_4,
800 BRW_WIDTH_4,
801 BRW_HORIZONTAL_STRIDE_0,
802 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
803 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
804 BRW_REGISTER_TYPE_F,
805 BRW_VERTICAL_STRIDE_4,
806 BRW_WIDTH_4,
807 BRW_HORIZONTAL_STRIDE_0,
808 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
809 if (negate_value)
810 brw_ADD(p, dst, src1, negate(src0));
811 else
812 brw_ADD(p, dst, src0, negate(src1));
813 }
814 }
815
816 void
817 fs_generator::generate_discard_jump(fs_inst *inst)
818 {
819 assert(brw->gen >= 6);
820
821 /* This HALT will be patched up at FB write time to point UIP at the end of
822 * the program, and at brw_uip_jip() JIP will be set to the end of the
823 * current block (or the program).
824 */
825 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
826
827 brw_push_insn_state(p);
828 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
829 gen6_HALT(p);
830 brw_pop_insn_state(p);
831 }
832
833 void
834 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
835 {
836 assert(inst->mlen != 0);
837
838 brw_MOV(p,
839 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
840 retype(src, BRW_REGISTER_TYPE_UD));
841 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
842 dispatch_width / 8, inst->offset);
843 }
844
845 void
846 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
847 {
848 assert(inst->mlen != 0);
849
850 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
851 dispatch_width / 8, inst->offset);
852 }
853
854 void
855 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
856 {
857 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
858 }
859
860 void
861 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
862 struct brw_reg dst,
863 struct brw_reg index,
864 struct brw_reg offset)
865 {
866 assert(inst->mlen != 0);
867
868 assert(index.file == BRW_IMMEDIATE_VALUE &&
869 index.type == BRW_REGISTER_TYPE_UD);
870 uint32_t surf_index = index.dw1.ud;
871
872 assert(offset.file == BRW_IMMEDIATE_VALUE &&
873 offset.type == BRW_REGISTER_TYPE_UD);
874 uint32_t read_offset = offset.dw1.ud;
875
876 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
877 read_offset, surf_index);
878
879 brw_mark_surface_used(&prog_data->base, surf_index);
880 }
881
882 void
883 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
884 struct brw_reg dst,
885 struct brw_reg index,
886 struct brw_reg offset)
887 {
888 assert(inst->mlen == 0);
889 assert(index.type == BRW_REGISTER_TYPE_UD);
890
891 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
892 /* Reference just the dword we need, to avoid angering validate_reg(). */
893 offset = brw_vec1_grf(offset.nr, 0);
894
895 /* We use the SIMD4x2 mode because we want to end up with 4 components in
896 * the destination loaded consecutively from the same offset (which appears
897 * in the first component, and the rest are ignored).
898 */
899 dst.width = BRW_WIDTH_4;
900
901 if (index.file == BRW_IMMEDIATE_VALUE) {
902
903 uint32_t surf_index = index.dw1.ud;
904
905 brw_push_insn_state(p);
906 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
907 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
908 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
909 brw_pop_insn_state(p);
910
911 brw_set_dest(p, send, dst);
912 brw_set_src0(p, send, offset);
913 brw_set_sampler_message(p, send,
914 surf_index,
915 0, /* LD message ignores sampler unit */
916 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
917 1, /* rlen */
918 1, /* mlen */
919 false, /* no header */
920 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
921 0);
922
923 brw_mark_surface_used(&prog_data->base, surf_index);
924
925 } else {
926
927 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
928
929 brw_push_insn_state(p);
930 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
931 brw_set_default_access_mode(p, BRW_ALIGN_1);
932
933 /* a0.0 = surf_index & 0xff */
934 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
935 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
936 brw_set_dest(p, insn_and, addr);
937 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
938 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
939
940
941 /* a0.0 |= <descriptor> */
942 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
943 brw_set_sampler_message(p, insn_or,
944 0 /* surface */,
945 0 /* sampler */,
946 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
947 1 /* rlen */,
948 1 /* mlen */,
949 false /* header */,
950 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
951 0);
952 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
953 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
954 brw_set_src0(p, insn_or, addr);
955 brw_set_dest(p, insn_or, addr);
956
957
958 /* dst = send(offset, a0.0) */
959 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
960 brw_set_dest(p, insn_send, dst);
961 brw_set_src0(p, insn_send, offset);
962 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
963
964 brw_pop_insn_state(p);
965
966 /* visitor knows more than we do about the surface limit required,
967 * so has already done marking.
968 */
969
970 }
971 }
972
973 void
974 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
975 struct brw_reg dst,
976 struct brw_reg index,
977 struct brw_reg offset)
978 {
979 assert(brw->gen < 7); /* Should use the gen7 variant. */
980 assert(inst->header_present);
981 assert(inst->mlen);
982
983 assert(index.file == BRW_IMMEDIATE_VALUE &&
984 index.type == BRW_REGISTER_TYPE_UD);
985 uint32_t surf_index = index.dw1.ud;
986
987 uint32_t simd_mode, rlen, msg_type;
988 if (dispatch_width == 16) {
989 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
990 rlen = 8;
991 } else {
992 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
993 rlen = 4;
994 }
995
996 if (brw->gen >= 5)
997 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
998 else {
999 /* We always use the SIMD16 message so that we only have to load U, and
1000 * not V or R.
1001 */
1002 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1003 assert(inst->mlen == 3);
1004 assert(inst->regs_written == 8);
1005 rlen = 8;
1006 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1007 }
1008
1009 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1010 BRW_REGISTER_TYPE_D);
1011 brw_MOV(p, offset_mrf, offset);
1012
1013 struct brw_reg header = brw_vec8_grf(0, 0);
1014 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1015
1016 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1017 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
1018 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1019 brw_set_src0(p, send, header);
1020 if (brw->gen < 6)
1021 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
1022
1023 /* Our surface is set up as floats, regardless of what actual data is
1024 * stored in it.
1025 */
1026 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1027 brw_set_sampler_message(p, send,
1028 surf_index,
1029 0, /* sampler (unused) */
1030 msg_type,
1031 rlen,
1032 inst->mlen,
1033 inst->header_present,
1034 simd_mode,
1035 return_format);
1036
1037 brw_mark_surface_used(&prog_data->base, surf_index);
1038 }
1039
1040 void
1041 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1042 struct brw_reg dst,
1043 struct brw_reg index,
1044 struct brw_reg offset)
1045 {
1046 assert(brw->gen >= 7);
1047 /* Varying-offset pull constant loads are treated as a normal expression on
1048 * gen7, so the fact that it's a send message is hidden at the IR level.
1049 */
1050 assert(!inst->header_present);
1051 assert(!inst->mlen);
1052 assert(index.type == BRW_REGISTER_TYPE_UD);
1053
1054 uint32_t simd_mode, rlen, mlen;
1055 if (dispatch_width == 16) {
1056 mlen = 2;
1057 rlen = 8;
1058 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1059 } else {
1060 mlen = 1;
1061 rlen = 4;
1062 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1063 }
1064
1065 if (index.file == BRW_IMMEDIATE_VALUE) {
1066
1067 uint32_t surf_index = index.dw1.ud;
1068
1069 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1070 brw_set_dest(p, send, dst);
1071 brw_set_src0(p, send, offset);
1072 brw_set_sampler_message(p, send,
1073 surf_index,
1074 0, /* LD message ignores sampler unit */
1075 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1076 rlen,
1077 mlen,
1078 false, /* no header */
1079 simd_mode,
1080 0);
1081
1082 brw_mark_surface_used(&prog_data->base, surf_index);
1083
1084 } else {
1085
1086 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1087
1088 brw_push_insn_state(p);
1089 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1090 brw_set_default_access_mode(p, BRW_ALIGN_1);
1091
1092 /* a0.0 = surf_index & 0xff */
1093 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1094 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1095 brw_set_dest(p, insn_and, addr);
1096 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1097 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1098
1099
1100 /* a0.0 |= <descriptor> */
1101 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1102 brw_set_sampler_message(p, insn_or,
1103 0 /* surface */,
1104 0 /* sampler */,
1105 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1106 rlen /* rlen */,
1107 mlen /* mlen */,
1108 false /* header */,
1109 simd_mode,
1110 0);
1111 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1112 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1113 brw_set_src0(p, insn_or, addr);
1114 brw_set_dest(p, insn_or, addr);
1115
1116
1117 /* dst = send(offset, a0.0) */
1118 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1119 brw_set_dest(p, insn_send, dst);
1120 brw_set_src0(p, insn_send, offset);
1121 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1122
1123 brw_pop_insn_state(p);
1124
1125 /* visitor knows more than we do about the surface limit required,
1126 * so has already done marking.
1127 */
1128 }
1129 }
1130
1131 /**
1132 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1133 * into the flags register (f0.0).
1134 *
1135 * Used only on Gen6 and above.
1136 */
1137 void
1138 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1139 {
1140 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1141 struct brw_reg dispatch_mask;
1142
1143 if (brw->gen >= 6)
1144 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1145 else
1146 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1147
1148 brw_push_insn_state(p);
1149 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1150 brw_MOV(p, flags, dispatch_mask);
1151 brw_pop_insn_state(p);
1152 }
1153
1154 void
1155 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1156 struct brw_reg dst,
1157 struct brw_reg src,
1158 struct brw_reg msg_data,
1159 unsigned msg_type)
1160 {
1161 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1162 msg_data.type == BRW_REGISTER_TYPE_UD);
1163
1164 brw_pixel_interpolator_query(p,
1165 retype(dst, BRW_REGISTER_TYPE_UW),
1166 src,
1167 inst->pi_noperspective,
1168 msg_type,
1169 msg_data.dw1.ud,
1170 inst->mlen,
1171 inst->regs_written);
1172 }
1173
1174
1175 static uint32_t brw_file_from_reg(fs_reg *reg)
1176 {
1177 switch (reg->file) {
1178 case GRF:
1179 return BRW_GENERAL_REGISTER_FILE;
1180 case MRF:
1181 return BRW_MESSAGE_REGISTER_FILE;
1182 case IMM:
1183 return BRW_IMMEDIATE_VALUE;
1184 default:
1185 unreachable("not reached");
1186 }
1187 }
1188
1189 struct brw_reg
1190 brw_reg_from_fs_reg(fs_reg *reg)
1191 {
1192 struct brw_reg brw_reg;
1193
1194 switch (reg->file) {
1195 case GRF:
1196 case MRF:
1197 if (reg->stride == 0) {
1198 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
1199 } else {
1200 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1201 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1202 }
1203
1204 brw_reg = retype(brw_reg, reg->type);
1205 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1206 break;
1207 case IMM:
1208 switch (reg->type) {
1209 case BRW_REGISTER_TYPE_F:
1210 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
1211 break;
1212 case BRW_REGISTER_TYPE_D:
1213 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
1214 break;
1215 case BRW_REGISTER_TYPE_UD:
1216 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
1217 break;
1218 default:
1219 unreachable("not reached");
1220 }
1221 break;
1222 case HW_REG:
1223 assert(reg->type == reg->fixed_hw_reg.type);
1224 brw_reg = reg->fixed_hw_reg;
1225 break;
1226 case BAD_FILE:
1227 /* Probably unused. */
1228 brw_reg = brw_null_reg();
1229 break;
1230 case UNIFORM:
1231 unreachable("not reached");
1232 default:
1233 unreachable("not reached");
1234 }
1235 if (reg->abs)
1236 brw_reg = brw_abs(brw_reg);
1237 if (reg->negate)
1238 brw_reg = negate(brw_reg);
1239
1240 return brw_reg;
1241 }
1242
1243 /**
1244 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1245 * sampler LD messages.
1246 *
1247 * We don't want to bake it into the send message's code generation because
1248 * that means we don't get a chance to schedule the instructions.
1249 */
1250 void
1251 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1252 struct brw_reg dst,
1253 struct brw_reg value)
1254 {
1255 assert(value.file == BRW_IMMEDIATE_VALUE);
1256
1257 brw_push_insn_state(p);
1258 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1259 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1260 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1261 brw_pop_insn_state(p);
1262 }
1263
1264 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1265 * (when mask is passed as a uniform) of register mask before moving it
1266 * to register dst.
1267 */
1268 void
1269 fs_generator::generate_set_omask(fs_inst *inst,
1270 struct brw_reg dst,
1271 struct brw_reg mask)
1272 {
1273 bool stride_8_8_1 =
1274 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1275 mask.width == BRW_WIDTH_8 &&
1276 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1277
1278 bool stride_0_1_0 =
1279 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1280 mask.width == BRW_WIDTH_1 &&
1281 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1282
1283 assert(stride_8_8_1 || stride_0_1_0);
1284 assert(dst.type == BRW_REGISTER_TYPE_UW);
1285
1286 if (dispatch_width == 16)
1287 dst = vec16(dst);
1288 brw_push_insn_state(p);
1289 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1290 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1291
1292 if (stride_8_8_1) {
1293 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1294 } else if (stride_0_1_0) {
1295 brw_MOV(p, dst, retype(mask, dst.type));
1296 }
1297 brw_pop_insn_state(p);
1298 }
1299
1300 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1301 * the ADD instruction.
1302 */
1303 void
1304 fs_generator::generate_set_sample_id(fs_inst *inst,
1305 struct brw_reg dst,
1306 struct brw_reg src0,
1307 struct brw_reg src1)
1308 {
1309 assert(dst.type == BRW_REGISTER_TYPE_D ||
1310 dst.type == BRW_REGISTER_TYPE_UD);
1311 assert(src0.type == BRW_REGISTER_TYPE_D ||
1312 src0.type == BRW_REGISTER_TYPE_UD);
1313
1314 brw_push_insn_state(p);
1315 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1316 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1317 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1318 brw_ADD(p, dst, src0, reg);
1319 if (dispatch_width == 16)
1320 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1321 brw_pop_insn_state(p);
1322 }
1323
1324 /**
1325 * Change the register's data type from UD to W, doubling the strides in order
1326 * to compensate for halving the data type width.
1327 */
1328 static struct brw_reg
1329 ud_reg_to_w(struct brw_reg r)
1330 {
1331 assert(r.type == BRW_REGISTER_TYPE_UD);
1332 r.type = BRW_REGISTER_TYPE_W;
1333
1334 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1335 * doubles the real stride.
1336 */
1337 if (r.hstride != 0)
1338 ++r.hstride;
1339 if (r.vstride != 0)
1340 ++r.vstride;
1341
1342 return r;
1343 }
1344
1345 void
1346 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1347 struct brw_reg dst,
1348 struct brw_reg x,
1349 struct brw_reg y)
1350 {
1351 assert(brw->gen >= 7);
1352 assert(dst.type == BRW_REGISTER_TYPE_UD);
1353 assert(x.type == BRW_REGISTER_TYPE_F);
1354 assert(y.type == BRW_REGISTER_TYPE_F);
1355
1356 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1357 *
1358 * Because this instruction does not have a 16-bit floating-point type,
1359 * the destination data type must be Word (W).
1360 *
1361 * The destination must be DWord-aligned and specify a horizontal stride
1362 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1363 * each destination channel and the upper word is not modified.
1364 */
1365 struct brw_reg dst_w = ud_reg_to_w(dst);
1366
1367 /* Give each 32-bit channel of dst the form below , where "." means
1368 * unchanged.
1369 * 0x....hhhh
1370 */
1371 brw_F32TO16(p, dst_w, y);
1372
1373 /* Now the form:
1374 * 0xhhhh0000
1375 */
1376 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1377
1378 /* And, finally the form of packHalf2x16's output:
1379 * 0xhhhhllll
1380 */
1381 brw_F32TO16(p, dst_w, x);
1382 }
1383
1384 void
1385 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1386 struct brw_reg dst,
1387 struct brw_reg src)
1388 {
1389 assert(brw->gen >= 7);
1390 assert(dst.type == BRW_REGISTER_TYPE_F);
1391 assert(src.type == BRW_REGISTER_TYPE_UD);
1392
1393 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1394 *
1395 * Because this instruction does not have a 16-bit floating-point type,
1396 * the source data type must be Word (W). The destination type must be
1397 * F (Float).
1398 */
1399 struct brw_reg src_w = ud_reg_to_w(src);
1400
1401 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1402 * For the Y case, we wish to access only the upper word; therefore
1403 * a 16-bit subregister offset is needed.
1404 */
1405 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1406 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1407 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1408 src_w.subnr += 2;
1409
1410 brw_F16TO32(p, dst, src_w);
1411 }
1412
1413 void
1414 fs_generator::generate_shader_time_add(fs_inst *inst,
1415 struct brw_reg payload,
1416 struct brw_reg offset,
1417 struct brw_reg value)
1418 {
1419 assert(brw->gen >= 7);
1420 brw_push_insn_state(p);
1421 brw_set_default_mask_control(p, true);
1422
1423 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1424 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1425 offset.type);
1426 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1427 value.type);
1428
1429 assert(offset.file == BRW_IMMEDIATE_VALUE);
1430 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1431 value.width = BRW_WIDTH_1;
1432 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1433 value.vstride = BRW_VERTICAL_STRIDE_0;
1434 } else {
1435 assert(value.file == BRW_IMMEDIATE_VALUE);
1436 }
1437
1438 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1439 * case, and we don't really care about squeezing every bit of performance
1440 * out of this path, so we just emit the MOVs from here.
1441 */
1442 brw_MOV(p, payload_offset, offset);
1443 brw_MOV(p, payload_value, value);
1444 brw_shader_time_add(p, payload,
1445 prog_data->base.binding_table.shader_time_start);
1446 brw_pop_insn_state(p);
1447
1448 brw_mark_surface_used(&prog_data->base,
1449 prog_data->base.binding_table.shader_time_start);
1450 }
1451
1452 void
1453 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1454 struct brw_reg atomic_op,
1455 struct brw_reg surf_index)
1456 {
1457 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1458 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1459 surf_index.file == BRW_IMMEDIATE_VALUE &&
1460 surf_index.type == BRW_REGISTER_TYPE_UD);
1461
1462 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1463 atomic_op.dw1.ud, surf_index.dw1.ud,
1464 inst->mlen, dispatch_width / 8);
1465
1466 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1467 }
1468
1469 void
1470 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1471 struct brw_reg surf_index)
1472 {
1473 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1474 surf_index.type == BRW_REGISTER_TYPE_UD);
1475
1476 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1477 surf_index.dw1.ud,
1478 inst->mlen, dispatch_width / 8);
1479
1480 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1481 }
1482
1483 void
1484 fs_generator::generate_code(const cfg_t *cfg)
1485 {
1486 int start_offset = p->next_insn_offset;
1487 int loop_count = 0;
1488
1489 struct annotation_info annotation;
1490 memset(&annotation, 0, sizeof(annotation));
1491
1492 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1493 struct brw_reg src[3], dst;
1494 unsigned int last_insn_offset = p->next_insn_offset;
1495
1496 if (unlikely(debug_flag))
1497 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1498
1499 for (unsigned int i = 0; i < inst->sources; i++) {
1500 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1501
1502 /* The accumulator result appears to get used for the
1503 * conditional modifier generation. When negating a UD
1504 * value, there is a 33rd bit generated for the sign in the
1505 * accumulator value, so now you can't check, for example,
1506 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1507 */
1508 assert(!inst->conditional_mod ||
1509 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1510 !inst->src[i].negate);
1511 }
1512 dst = brw_reg_from_fs_reg(&inst->dst);
1513
1514 brw_set_default_predicate_control(p, inst->predicate);
1515 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1516 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1517 brw_set_default_saturate(p, inst->saturate);
1518 brw_set_default_mask_control(p, inst->force_writemask_all);
1519 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1520
1521 if (inst->force_uncompressed || dispatch_width == 8) {
1522 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1523 } else if (inst->force_sechalf) {
1524 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1525 } else {
1526 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1527 }
1528
1529 switch (inst->opcode) {
1530 case BRW_OPCODE_MOV:
1531 brw_MOV(p, dst, src[0]);
1532 break;
1533 case BRW_OPCODE_ADD:
1534 brw_ADD(p, dst, src[0], src[1]);
1535 break;
1536 case BRW_OPCODE_MUL:
1537 brw_MUL(p, dst, src[0], src[1]);
1538 break;
1539 case BRW_OPCODE_AVG:
1540 brw_AVG(p, dst, src[0], src[1]);
1541 break;
1542 case BRW_OPCODE_MACH:
1543 brw_MACH(p, dst, src[0], src[1]);
1544 break;
1545
1546 case BRW_OPCODE_MAD:
1547 assert(brw->gen >= 6);
1548 brw_set_default_access_mode(p, BRW_ALIGN_16);
1549 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1550 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1551 brw_MAD(p, dst, src[0], src[1], src[2]);
1552 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1553 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1554 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1555 } else {
1556 brw_MAD(p, dst, src[0], src[1], src[2]);
1557 }
1558 brw_set_default_access_mode(p, BRW_ALIGN_1);
1559 break;
1560
1561 case BRW_OPCODE_LRP:
1562 assert(brw->gen >= 6);
1563 brw_set_default_access_mode(p, BRW_ALIGN_16);
1564 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1565 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1566 brw_LRP(p, dst, src[0], src[1], src[2]);
1567 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1568 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1569 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1570 } else {
1571 brw_LRP(p, dst, src[0], src[1], src[2]);
1572 }
1573 brw_set_default_access_mode(p, BRW_ALIGN_1);
1574 break;
1575
1576 case BRW_OPCODE_FRC:
1577 brw_FRC(p, dst, src[0]);
1578 break;
1579 case BRW_OPCODE_RNDD:
1580 brw_RNDD(p, dst, src[0]);
1581 break;
1582 case BRW_OPCODE_RNDE:
1583 brw_RNDE(p, dst, src[0]);
1584 break;
1585 case BRW_OPCODE_RNDZ:
1586 brw_RNDZ(p, dst, src[0]);
1587 break;
1588
1589 case BRW_OPCODE_AND:
1590 brw_AND(p, dst, src[0], src[1]);
1591 break;
1592 case BRW_OPCODE_OR:
1593 brw_OR(p, dst, src[0], src[1]);
1594 break;
1595 case BRW_OPCODE_XOR:
1596 brw_XOR(p, dst, src[0], src[1]);
1597 break;
1598 case BRW_OPCODE_NOT:
1599 brw_NOT(p, dst, src[0]);
1600 break;
1601 case BRW_OPCODE_ASR:
1602 brw_ASR(p, dst, src[0], src[1]);
1603 break;
1604 case BRW_OPCODE_SHR:
1605 brw_SHR(p, dst, src[0], src[1]);
1606 break;
1607 case BRW_OPCODE_SHL:
1608 brw_SHL(p, dst, src[0], src[1]);
1609 break;
1610 case BRW_OPCODE_F32TO16:
1611 assert(brw->gen >= 7);
1612 brw_F32TO16(p, dst, src[0]);
1613 break;
1614 case BRW_OPCODE_F16TO32:
1615 assert(brw->gen >= 7);
1616 brw_F16TO32(p, dst, src[0]);
1617 break;
1618 case BRW_OPCODE_CMP:
1619 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1620 break;
1621 case BRW_OPCODE_SEL:
1622 brw_SEL(p, dst, src[0], src[1]);
1623 break;
1624 case BRW_OPCODE_BFREV:
1625 assert(brw->gen >= 7);
1626 /* BFREV only supports UD type for src and dst. */
1627 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1628 retype(src[0], BRW_REGISTER_TYPE_UD));
1629 break;
1630 case BRW_OPCODE_FBH:
1631 assert(brw->gen >= 7);
1632 /* FBH only supports UD type for dst. */
1633 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1634 break;
1635 case BRW_OPCODE_FBL:
1636 assert(brw->gen >= 7);
1637 /* FBL only supports UD type for dst. */
1638 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1639 break;
1640 case BRW_OPCODE_CBIT:
1641 assert(brw->gen >= 7);
1642 /* CBIT only supports UD type for dst. */
1643 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1644 break;
1645 case BRW_OPCODE_ADDC:
1646 assert(brw->gen >= 7);
1647 brw_ADDC(p, dst, src[0], src[1]);
1648 break;
1649 case BRW_OPCODE_SUBB:
1650 assert(brw->gen >= 7);
1651 brw_SUBB(p, dst, src[0], src[1]);
1652 break;
1653 case BRW_OPCODE_MAC:
1654 brw_MAC(p, dst, src[0], src[1]);
1655 break;
1656
1657 case BRW_OPCODE_BFE:
1658 assert(brw->gen >= 7);
1659 brw_set_default_access_mode(p, BRW_ALIGN_16);
1660 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1661 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1662 brw_BFE(p, dst, src[0], src[1], src[2]);
1663 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1664 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1665 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1666 } else {
1667 brw_BFE(p, dst, src[0], src[1], src[2]);
1668 }
1669 brw_set_default_access_mode(p, BRW_ALIGN_1);
1670 break;
1671
1672 case BRW_OPCODE_BFI1:
1673 assert(brw->gen >= 7);
1674 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1675 * should
1676 *
1677 * "Force BFI instructions to be executed always in SIMD8."
1678 */
1679 if (dispatch_width == 16 && brw->is_haswell) {
1680 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1681 brw_BFI1(p, dst, src[0], src[1]);
1682 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1683 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1684 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1685 } else {
1686 brw_BFI1(p, dst, src[0], src[1]);
1687 }
1688 break;
1689 case BRW_OPCODE_BFI2:
1690 assert(brw->gen >= 7);
1691 brw_set_default_access_mode(p, BRW_ALIGN_16);
1692 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1693 * should
1694 *
1695 * "Force BFI instructions to be executed always in SIMD8."
1696 *
1697 * Otherwise we would be able to emit compressed instructions like we
1698 * do for the other three-source instructions.
1699 */
1700 if (dispatch_width == 16) {
1701 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1702 brw_BFI2(p, dst, src[0], src[1], src[2]);
1703 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1704 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1705 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1706 } else {
1707 brw_BFI2(p, dst, src[0], src[1], src[2]);
1708 }
1709 brw_set_default_access_mode(p, BRW_ALIGN_1);
1710 break;
1711
1712 case BRW_OPCODE_IF:
1713 if (inst->src[0].file != BAD_FILE) {
1714 /* The instruction has an embedded compare (only allowed on gen6) */
1715 assert(brw->gen == 6);
1716 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1717 } else {
1718 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1719 }
1720 break;
1721
1722 case BRW_OPCODE_ELSE:
1723 brw_ELSE(p);
1724 break;
1725 case BRW_OPCODE_ENDIF:
1726 brw_ENDIF(p);
1727 break;
1728
1729 case BRW_OPCODE_DO:
1730 brw_DO(p, BRW_EXECUTE_8);
1731 break;
1732
1733 case BRW_OPCODE_BREAK:
1734 brw_BREAK(p);
1735 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1736 break;
1737 case BRW_OPCODE_CONTINUE:
1738 brw_CONT(p);
1739 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1740 break;
1741
1742 case BRW_OPCODE_WHILE:
1743 brw_WHILE(p);
1744 loop_count++;
1745 break;
1746
1747 case SHADER_OPCODE_RCP:
1748 case SHADER_OPCODE_RSQ:
1749 case SHADER_OPCODE_SQRT:
1750 case SHADER_OPCODE_EXP2:
1751 case SHADER_OPCODE_LOG2:
1752 case SHADER_OPCODE_SIN:
1753 case SHADER_OPCODE_COS:
1754 assert(brw->gen < 6 || inst->mlen == 0);
1755 if (brw->gen >= 7) {
1756 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1757 brw_null_reg());
1758 } else if (brw->gen == 6) {
1759 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1760 } else if (brw->gen == 5 || brw->is_g4x) {
1761 generate_math_g45(inst, dst, src[0]);
1762 } else {
1763 generate_math_gen4(inst, dst, src[0]);
1764 }
1765 break;
1766 case SHADER_OPCODE_INT_QUOTIENT:
1767 case SHADER_OPCODE_INT_REMAINDER:
1768 case SHADER_OPCODE_POW:
1769 assert(brw->gen < 6 || inst->mlen == 0);
1770 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1771 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1772 } else if (brw->gen >= 6) {
1773 generate_math_gen6(inst, dst, src[0], src[1]);
1774 } else {
1775 generate_math_gen4(inst, dst, src[0]);
1776 }
1777 break;
1778 case FS_OPCODE_PIXEL_X:
1779 generate_pixel_xy(dst, true);
1780 break;
1781 case FS_OPCODE_PIXEL_Y:
1782 generate_pixel_xy(dst, false);
1783 break;
1784 case FS_OPCODE_CINTERP:
1785 brw_MOV(p, dst, src[0]);
1786 break;
1787 case FS_OPCODE_LINTERP:
1788 generate_linterp(inst, dst, src);
1789 break;
1790 case SHADER_OPCODE_TEX:
1791 case FS_OPCODE_TXB:
1792 case SHADER_OPCODE_TXD:
1793 case SHADER_OPCODE_TXF:
1794 case SHADER_OPCODE_TXF_CMS:
1795 case SHADER_OPCODE_TXF_UMS:
1796 case SHADER_OPCODE_TXF_MCS:
1797 case SHADER_OPCODE_TXL:
1798 case SHADER_OPCODE_TXS:
1799 case SHADER_OPCODE_LOD:
1800 case SHADER_OPCODE_TG4:
1801 case SHADER_OPCODE_TG4_OFFSET:
1802 generate_tex(inst, dst, src[0], src[1]);
1803 break;
1804 case FS_OPCODE_DDX:
1805 generate_ddx(inst, dst, src[0], src[1]);
1806 break;
1807 case FS_OPCODE_DDY:
1808 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1809 * guarantee that key->render_to_fbo is set).
1810 */
1811 assert(fp->UsesDFdy);
1812 generate_ddy(inst, dst, src[0], src[1], key->render_to_fbo);
1813 break;
1814
1815 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1816 generate_scratch_write(inst, src[0]);
1817 break;
1818
1819 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1820 generate_scratch_read(inst, dst);
1821 break;
1822
1823 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1824 generate_scratch_read_gen7(inst, dst);
1825 break;
1826
1827 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1828 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1829 break;
1830
1831 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1832 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1833 break;
1834
1835 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1836 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1837 break;
1838
1839 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1840 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1841 break;
1842
1843 case FS_OPCODE_REP_FB_WRITE:
1844 case FS_OPCODE_FB_WRITE:
1845 generate_fb_write(inst);
1846 break;
1847
1848 case FS_OPCODE_BLORP_FB_WRITE:
1849 generate_blorp_fb_write(inst);
1850 break;
1851
1852 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1853 generate_mov_dispatch_to_flags(inst);
1854 break;
1855
1856 case FS_OPCODE_DISCARD_JUMP:
1857 generate_discard_jump(inst);
1858 break;
1859
1860 case SHADER_OPCODE_SHADER_TIME_ADD:
1861 generate_shader_time_add(inst, src[0], src[1], src[2]);
1862 break;
1863
1864 case SHADER_OPCODE_UNTYPED_ATOMIC:
1865 generate_untyped_atomic(inst, dst, src[0], src[1]);
1866 break;
1867
1868 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1869 generate_untyped_surface_read(inst, dst, src[0]);
1870 break;
1871
1872 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1873 generate_set_simd4x2_offset(inst, dst, src[0]);
1874 break;
1875
1876 case FS_OPCODE_SET_OMASK:
1877 generate_set_omask(inst, dst, src[0]);
1878 break;
1879
1880 case FS_OPCODE_SET_SAMPLE_ID:
1881 generate_set_sample_id(inst, dst, src[0], src[1]);
1882 break;
1883
1884 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1885 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1886 break;
1887
1888 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1889 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1890 generate_unpack_half_2x16_split(inst, dst, src[0]);
1891 break;
1892
1893 case FS_OPCODE_PLACEHOLDER_HALT:
1894 /* This is the place where the final HALT needs to be inserted if
1895 * we've emitted any discards. If not, this will emit no code.
1896 */
1897 if (!patch_discard_jumps_to_fb_writes()) {
1898 if (unlikely(debug_flag)) {
1899 annotation.ann_count--;
1900 }
1901 }
1902 break;
1903
1904 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
1905 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1906 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
1907 break;
1908
1909 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
1910 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1911 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
1912 break;
1913
1914 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
1915 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1916 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
1917 break;
1918
1919 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
1920 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1921 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
1922 break;
1923
1924 default:
1925 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1926 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1927 opcode_descs[inst->opcode].name);
1928 } else {
1929 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1930 }
1931 abort();
1932
1933 case SHADER_OPCODE_LOAD_PAYLOAD:
1934 unreachable("Should be lowered by lower_load_payload()");
1935 }
1936
1937 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1938 assert(p->next_insn_offset == last_insn_offset + 16 ||
1939 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1940 "emitting more than 1 instruction");
1941
1942 brw_inst *last = &p->store[last_insn_offset / 16];
1943
1944 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1945 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1946 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1947 }
1948 }
1949
1950 brw_set_uip_jip(p);
1951 annotation_finalize(&annotation, p->next_insn_offset);
1952
1953 int before_size = p->next_insn_offset - start_offset;
1954 brw_compact_instructions(p, start_offset, annotation.ann_count,
1955 annotation.ann);
1956 int after_size = p->next_insn_offset - start_offset;
1957
1958 if (unlikely(debug_flag)) {
1959 if (prog) {
1960 fprintf(stderr,
1961 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
1962 prog->Label ? prog->Label : "unnamed",
1963 prog->Name, dispatch_width);
1964 } else if (fp) {
1965 fprintf(stderr,
1966 "Native code for fragment program %d (SIMD%d dispatch):\n",
1967 fp->Base.Id, dispatch_width);
1968 } else {
1969 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
1970 dispatch_width);
1971 }
1972 fprintf(stderr, "SIMD%d shader: %d instructions. %d loops. Compacted %d to %d"
1973 " bytes (%.0f%%)\n",
1974 dispatch_width, before_size / 16, loop_count, before_size, after_size,
1975 100.0f * (before_size - after_size) / before_size);
1976
1977 const struct gl_program *prog = fp ? &fp->Base : NULL;
1978
1979 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1980 ralloc_free(annotation.ann);
1981 }
1982 }
1983
1984 const unsigned *
1985 fs_generator::generate_assembly(const cfg_t *simd8_cfg,
1986 const cfg_t *simd16_cfg,
1987 unsigned *assembly_size)
1988 {
1989 assert(simd8_cfg || simd16_cfg);
1990
1991 if (simd8_cfg) {
1992 dispatch_width = 8;
1993 generate_code(simd8_cfg);
1994 }
1995
1996 if (simd16_cfg) {
1997 /* align to 64 byte boundary. */
1998 while (p->next_insn_offset % 64) {
1999 brw_NOP(p);
2000 }
2001
2002 /* Save off the start of this SIMD16 program */
2003 prog_data->prog_offset_16 = p->next_insn_offset;
2004
2005 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
2006
2007 dispatch_width = 16;
2008 generate_code(simd16_cfg);
2009 }
2010
2011 return brw_get_program(p, assembly_size);
2012 }