projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
i965/skl: Use an exec size of 8 to initialise the message header
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "main/macros.h"
31 #include "brw_context.h"
32 #include "brw_eu.h"
33 #include "brw_fs.h"
34 #include "brw_cfg.h"
35
36 static uint32_t brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case GRF:
40 return BRW_GENERAL_REGISTER_FILE;
41 case MRF:
42 return BRW_MESSAGE_REGISTER_FILE;
43 case IMM:
44 return BRW_IMMEDIATE_VALUE;
45 default:
46 unreachable("not reached");
47 }
48 }
49
50 static struct brw_reg
51 brw_reg_from_fs_reg(fs_reg *reg)
52 {
53 struct brw_reg brw_reg;
54
55 switch (reg->file) {
56 case GRF:
57 case MRF:
58 if (reg->stride == 0) {
59 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
60 } else if (reg->width < 8) {
61 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
62 brw_reg = stride(brw_reg, reg->width * reg->stride,
63 reg->width, reg->stride);
64 } else {
65 /* From the Haswell PRM:
66 *
67 * VertStride must be used to cross GRF register boundaries. This
68 * rule implies that elements within a 'Width' cannot cross GRF
69 * boundaries.
70 *
71 * So, for registers with width > 8, we have to use a width of 8
72 * and trust the compression state to sort out the exec size.
73 */
74 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
75 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
76 }
77
78 brw_reg = retype(brw_reg, reg->type);
79 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
80 break;
81 case IMM:
82 switch (reg->type) {
83 case BRW_REGISTER_TYPE_F:
84 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
85 break;
86 case BRW_REGISTER_TYPE_D:
87 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
88 break;
89 case BRW_REGISTER_TYPE_UD:
90 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
91 break;
92 case BRW_REGISTER_TYPE_W:
93 brw_reg = brw_imm_w(reg->fixed_hw_reg.dw1.d);
94 break;
95 case BRW_REGISTER_TYPE_UW:
96 brw_reg = brw_imm_uw(reg->fixed_hw_reg.dw1.ud);
97 break;
98 case BRW_REGISTER_TYPE_VF:
99 brw_reg = brw_imm_vf(reg->fixed_hw_reg.dw1.ud);
100 break;
101 default:
102 unreachable("not reached");
103 }
104 break;
105 case HW_REG:
106 assert(reg->type == reg->fixed_hw_reg.type);
107 brw_reg = reg->fixed_hw_reg;
108 break;
109 case BAD_FILE:
110 /* Probably unused. */
111 brw_reg = brw_null_reg();
112 break;
113 default:
114 unreachable("not reached");
115 }
116 if (reg->abs)
117 brw_reg = brw_abs(brw_reg);
118 if (reg->negate)
119 brw_reg = negate(brw_reg);
120
121 return brw_reg;
122 }
123
124 fs_generator::fs_generator(struct brw_context *brw,
125 void *mem_ctx,
126 const void *key,
127 struct brw_stage_prog_data *prog_data,
128 struct gl_program *prog,
129 unsigned promoted_constants,
130 bool runtime_check_aads_emit,
131 const char *stage_abbrev)
132
133 : brw(brw), key(key),
134 prog_data(prog_data),
135 prog(prog), promoted_constants(promoted_constants),
136 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
137 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
138 {
139 ctx = &brw->ctx;
140
141 p = rzalloc(mem_ctx, struct brw_compile);
142 brw_init_compile(brw, p, mem_ctx);
143 }
144
145 fs_generator::~fs_generator()
146 {
147 }
148
149 class ip_record : public exec_node {
150 public:
151 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
152
153 ip_record(int ip)
154 {
155 this->ip = ip;
156 }
157
158 int ip;
159 };
160
161 bool
162 fs_generator::patch_discard_jumps_to_fb_writes()
163 {
164 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
165 return false;
166
167 int scale = brw_jump_scale(brw);
168
169 /* There is a somewhat strange undocumented requirement of using
170 * HALT, according to the simulator. If some channel has HALTed to
171 * a particular UIP, then by the end of the program, every channel
172 * must have HALTed to that UIP. Furthermore, the tracking is a
173 * stack, so you can't do the final halt of a UIP after starting
174 * halting to a new UIP.
175 *
176 * Symptoms of not emitting this instruction on actual hardware
177 * included GPU hangs and sparkly rendering on the piglit discard
178 * tests.
179 */
180 brw_inst *last_halt = gen6_HALT(p);
181 brw_inst_set_uip(brw, last_halt, 1 * scale);
182 brw_inst_set_jip(brw, last_halt, 1 * scale);
183
184 int ip = p->nr_insn;
185
186 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
187 brw_inst *patch = &p->store[patch_ip->ip];
188
189 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
190 /* HALT takes a half-instruction distance from the pre-incremented IP. */
191 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
192 }
193
194 this->discard_halt_patches.make_empty();
195 return true;
196 }
197
198 void
199 fs_generator::fire_fb_write(fs_inst *inst,
200 struct brw_reg payload,
201 struct brw_reg implied_header,
202 GLuint nr)
203 {
204 uint32_t msg_control;
205
206 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
207
208 if (brw->gen < 6) {
209 brw_push_insn_state(p);
210 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
211 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
212 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
213 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
214 brw_pop_insn_state(p);
215 }
216
217 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
218 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
219 else if (prog_data->dual_src_blend) {
220 if (dispatch_width == 8 || !inst->eot)
221 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
222 else
223 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
224 } else if (dispatch_width == 16)
225 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
226 else
227 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
228
229 uint32_t surf_index =
230 prog_data->binding_table.render_target_start + inst->target;
231
232 bool last_render_target = inst->eot ||
233 (prog_data->dual_src_blend && dispatch_width == 16);
234
235
236 brw_fb_WRITE(p,
237 dispatch_width,
238 payload,
239 implied_header,
240 msg_control,
241 surf_index,
242 nr,
243 0,
244 inst->eot,
245 last_render_target,
246 inst->header_present);
247
248 brw_mark_surface_used(&prog_data->base, surf_index);
249 }
250
251 void
252 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
253 {
254 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
255 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
256 struct brw_reg implied_header;
257
258 if (brw->gen < 8 && !brw->is_haswell) {
259 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
260 }
261
262 if (inst->base_mrf >= 0)
263 payload = brw_message_reg(inst->base_mrf);
264
265 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
266 * move, here's g1.
267 */
268 if (inst->header_present) {
269 brw_push_insn_state(p);
270 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
271 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
272 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
273 brw_set_default_flag_reg(p, 0, 0);
274
275 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
276 * present.
277 */
278 if (prog_data->uses_kill) {
279 struct brw_reg pixel_mask;
280
281 if (brw->gen >= 6)
282 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
283 else
284 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
285
286 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
287 }
288
289 if (brw->gen >= 6) {
290 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
291 brw_MOV(p,
292 retype(payload, BRW_REGISTER_TYPE_UD),
293 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
294 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
295
296 if (inst->target > 0 && key->replicate_alpha) {
297 /* Set "Source0 Alpha Present to RenderTarget" bit in message
298 * header.
299 */
300 brw_OR(p,
301 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
302 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
303 brw_imm_ud(0x1 << 11));
304 }
305
306 if (inst->target > 0) {
307 /* Set the render target index for choosing BLEND_STATE. */
308 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
309 BRW_REGISTER_TYPE_UD),
310 brw_imm_ud(inst->target));
311 }
312
313 implied_header = brw_null_reg();
314 } else {
315 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
316 }
317
318 brw_pop_insn_state(p);
319 } else {
320 implied_header = brw_null_reg();
321 }
322
323 if (!runtime_check_aads_emit) {
324 fire_fb_write(inst, payload, implied_header, inst->mlen);
325 } else {
326 /* This can only happen in gen < 6 */
327 assert(brw->gen < 6);
328
329 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
330
331 /* Check runtime bit to detect if we have to send AA data or not */
332 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
333 brw_AND(p,
334 v1_null_ud,
335 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
336 brw_imm_ud(1<<26));
337 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
338
339 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
340 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
341 {
342 /* Don't send AA data */
343 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
344 }
345 brw_land_fwd_jump(p, jmp);
346 fire_fb_write(inst, payload, implied_header, inst->mlen);
347 }
348 }
349
350 void
351 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
352 {
353 brw_inst *insn;
354
355 insn = brw_next_insn(p, BRW_OPCODE_SEND);
356
357 brw_set_dest(p, insn, brw_null_reg());
358 brw_set_src0(p, insn, payload);
359 brw_set_src1(p, insn, brw_imm_d(0));
360
361 brw_inst_set_sfid(brw, insn, BRW_SFID_URB);
362 brw_inst_set_urb_opcode(brw, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
363
364 brw_inst_set_mlen(brw, insn, inst->mlen);
365 brw_inst_set_rlen(brw, insn, 0);
366 brw_inst_set_eot(brw, insn, inst->eot);
367 brw_inst_set_header_present(brw, insn, true);
368 brw_inst_set_urb_global_offset(brw, insn, inst->offset);
369 }
370
371 void
372 fs_generator::generate_blorp_fb_write(fs_inst *inst)
373 {
374 brw_fb_WRITE(p,
375 16 /* dispatch_width */,
376 brw_message_reg(inst->base_mrf),
377 brw_reg_from_fs_reg(&inst->src[0]),
378 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
379 inst->target,
380 inst->mlen,
381 0,
382 true,
383 true,
384 inst->header_present);
385 }
386
387 /* Computes the integer pixel x,y values from the origin.
388 *
389 * This is the basis of gl_FragCoord computation, but is also used
390 * pre-gen6 for computing the deltas from v0 for computing
391 * interpolation.
392 */
393 void
394 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
395 {
396 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
397 struct brw_reg src;
398 struct brw_reg deltas;
399
400 if (is_x) {
401 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
402 deltas = brw_imm_v(0x10101010);
403 } else {
404 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
405 deltas = brw_imm_v(0x11001100);
406 }
407
408 if (dispatch_width == 16) {
409 dst = vec16(dst);
410 }
411
412 /* We do this SIMD8 or SIMD16, but since the destination is UW we
413 * don't do compression in the SIMD16 case.
414 */
415 brw_push_insn_state(p);
416 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
417 brw_ADD(p, dst, src, deltas);
418 brw_pop_insn_state(p);
419 }
420
421 void
422 fs_generator::generate_linterp(fs_inst *inst,
423 struct brw_reg dst, struct brw_reg *src)
424 {
425 struct brw_reg delta_x = src[0];
426 struct brw_reg delta_y = src[1];
427 struct brw_reg interp = src[2];
428
429 if (brw->has_pln &&
430 delta_y.nr == delta_x.nr + 1 &&
431 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
432 brw_PLN(p, dst, interp, delta_x);
433 } else {
434 brw_LINE(p, brw_null_reg(), interp, delta_x);
435 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
436 }
437 }
438
439 void
440 fs_generator::generate_math_gen6(fs_inst *inst,
441 struct brw_reg dst,
442 struct brw_reg src0,
443 struct brw_reg src1)
444 {
445 int op = brw_math_function(inst->opcode);
446 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
447
448 if (dispatch_width == 8) {
449 gen6_math(p, dst, op, src0, src1);
450 } else if (dispatch_width == 16) {
451 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
452 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
453 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
454 gen6_math(p, sechalf(dst), op, sechalf(src0),
455 binop ? sechalf(src1) : brw_null_reg());
456 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
457 }
458 }
459
460 void
461 fs_generator::generate_math_gen4(fs_inst *inst,
462 struct brw_reg dst,
463 struct brw_reg src)
464 {
465 int op = brw_math_function(inst->opcode);
466
467 assert(inst->mlen >= 1);
468
469 if (dispatch_width == 8) {
470 gen4_math(p, dst,
471 op,
472 inst->base_mrf, src,
473 BRW_MATH_PRECISION_FULL);
474 } else if (dispatch_width == 16) {
475 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
476 gen4_math(p, firsthalf(dst),
477 op,
478 inst->base_mrf, firsthalf(src),
479 BRW_MATH_PRECISION_FULL);
480 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
481 gen4_math(p, sechalf(dst),
482 op,
483 inst->base_mrf + 1, sechalf(src),
484 BRW_MATH_PRECISION_FULL);
485
486 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
487 }
488 }
489
490 void
491 fs_generator::generate_math_g45(fs_inst *inst,
492 struct brw_reg dst,
493 struct brw_reg src)
494 {
495 if (inst->opcode == SHADER_OPCODE_POW ||
496 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
497 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
498 generate_math_gen4(inst, dst, src);
499 return;
500 }
501
502 int op = brw_math_function(inst->opcode);
503
504 assert(inst->mlen >= 1);
505
506 gen4_math(p, dst,
507 op,
508 inst->base_mrf, src,
509 BRW_MATH_PRECISION_FULL);
510 }
511
512 void
513 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
514 struct brw_reg sampler_index)
515 {
516 int msg_type = -1;
517 int rlen = 4;
518 uint32_t simd_mode;
519 uint32_t return_format;
520
521 switch (dst.type) {
522 case BRW_REGISTER_TYPE_D:
523 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
524 break;
525 case BRW_REGISTER_TYPE_UD:
526 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
527 break;
528 default:
529 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
530 break;
531 }
532
533 switch (inst->exec_size) {
534 case 8:
535 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
536 break;
537 case 16:
538 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
539 break;
540 default:
541 unreachable("Invalid width for texture instruction");
542 }
543
544 if (brw->gen >= 5) {
545 switch (inst->opcode) {
546 case SHADER_OPCODE_TEX:
547 if (inst->shadow_compare) {
548 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
549 } else {
550 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
551 }
552 break;
553 case FS_OPCODE_TXB:
554 if (inst->shadow_compare) {
555 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
556 } else {
557 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
558 }
559 break;
560 case SHADER_OPCODE_TXL:
561 if (inst->shadow_compare) {
562 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
563 } else {
564 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
565 }
566 break;
567 case SHADER_OPCODE_TXS:
568 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
569 break;
570 case SHADER_OPCODE_TXD:
571 if (inst->shadow_compare) {
572 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
573 assert(brw->gen >= 8 || brw->is_haswell);
574 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
575 } else {
576 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
577 }
578 break;
579 case SHADER_OPCODE_TXF:
580 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
581 break;
582 case SHADER_OPCODE_TXF_CMS:
583 if (brw->gen >= 7)
584 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
585 else
586 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
587 break;
588 case SHADER_OPCODE_TXF_UMS:
589 assert(brw->gen >= 7);
590 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
591 break;
592 case SHADER_OPCODE_TXF_MCS:
593 assert(brw->gen >= 7);
594 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
595 break;
596 case SHADER_OPCODE_LOD:
597 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
598 break;
599 case SHADER_OPCODE_TG4:
600 if (inst->shadow_compare) {
601 assert(brw->gen >= 7);
602 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
603 } else {
604 assert(brw->gen >= 6);
605 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
606 }
607 break;
608 case SHADER_OPCODE_TG4_OFFSET:
609 assert(brw->gen >= 7);
610 if (inst->shadow_compare) {
611 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
612 } else {
613 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
614 }
615 break;
616 default:
617 unreachable("not reached");
618 }
619 } else {
620 switch (inst->opcode) {
621 case SHADER_OPCODE_TEX:
622 /* Note that G45 and older determines shadow compare and dispatch width
623 * from message length for most messages.
624 */
625 if (dispatch_width == 8) {
626 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
627 if (inst->shadow_compare) {
628 assert(inst->mlen == 6);
629 } else {
630 assert(inst->mlen <= 4);
631 }
632 } else {
633 if (inst->shadow_compare) {
634 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
635 assert(inst->mlen == 9);
636 } else {
637 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
638 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
639 }
640 }
641 break;
642 case FS_OPCODE_TXB:
643 if (inst->shadow_compare) {
644 assert(dispatch_width == 8);
645 assert(inst->mlen == 6);
646 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
647 } else {
648 assert(inst->mlen == 9);
649 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
650 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
651 }
652 break;
653 case SHADER_OPCODE_TXL:
654 if (inst->shadow_compare) {
655 assert(dispatch_width == 8);
656 assert(inst->mlen == 6);
657 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
658 } else {
659 assert(inst->mlen == 9);
660 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
661 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
662 }
663 break;
664 case SHADER_OPCODE_TXD:
665 /* There is no sample_d_c message; comparisons are done manually */
666 assert(dispatch_width == 8);
667 assert(inst->mlen == 7 || inst->mlen == 10);
668 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
669 break;
670 case SHADER_OPCODE_TXF:
671 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
672 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
673 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
674 break;
675 case SHADER_OPCODE_TXS:
676 assert(inst->mlen == 3);
677 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
678 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
679 break;
680 default:
681 unreachable("not reached");
682 }
683 }
684 assert(msg_type != -1);
685
686 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
687 rlen = 8;
688 dst = vec16(dst);
689 }
690
691 assert(brw->gen < 7 || !inst->header_present ||
692 src.file == BRW_GENERAL_REGISTER_FILE);
693
694 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
695
696 /* Load the message header if present. If there's a texture offset,
697 * we need to set it up explicitly and load the offset bitfield.
698 * Otherwise, we can use an implied move from g0 to the first message reg.
699 */
700 if (inst->header_present) {
701 if (brw->gen < 6 && !inst->offset) {
702 /* Set up an implied move from g0 to the MRF. */
703 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
704 } else {
705 struct brw_reg header_reg;
706
707 if (brw->gen >= 7) {
708 header_reg = src;
709 } else {
710 assert(inst->base_mrf != -1);
711 header_reg = brw_message_reg(inst->base_mrf);
712 }
713
714 brw_push_insn_state(p);
715 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
716 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
717 /* Explicitly set up the message header by copying g0 to the MRF. */
718 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
719
720 if (inst->offset) {
721 /* Set the offset bits in DWord 2. */
722 brw_MOV(p, get_element_ud(header_reg, 2),
723 brw_imm_ud(inst->offset));
724 }
725
726 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
727 brw_pop_insn_state(p);
728 }
729 }
730
731 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
732 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
733 ? prog_data->binding_table.gather_texture_start
734 : prog_data->binding_table.texture_start;
735
736 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
737 uint32_t sampler = sampler_index.dw1.ud;
738
739 brw_SAMPLE(p,
740 retype(dst, BRW_REGISTER_TYPE_UW),
741 inst->base_mrf,
742 src,
743 sampler + base_binding_table_index,
744 sampler % 16,
745 msg_type,
746 rlen,
747 inst->mlen,
748 inst->header_present,
749 simd_mode,
750 return_format);
751
752 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
753 } else {
754 /* Non-const sampler index */
755 /* Note: this clobbers `dst` as a temporary before emitting the send */
756
757 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
758 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
759
760 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
761
762 brw_push_insn_state(p);
763 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
764 brw_set_default_access_mode(p, BRW_ALIGN_1);
765
766 /* Some care required: `sampler` and `temp` may alias:
767 * addr = sampler & 0xff
768 * temp = (sampler << 8) & 0xf00
769 * addr = addr | temp
770 */
771 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
772 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
773 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
774 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
775 brw_OR(p, addr, addr, temp);
776
777 brw_pop_insn_state(p);
778
779 /* dst = send(offset, a0.0 | <descriptor>) */
780 brw_inst *insn = brw_send_indirect_message(
781 p, BRW_SFID_SAMPLER, dst, src, addr);
782 brw_set_sampler_message(p, insn,
783 0 /* surface */,
784 0 /* sampler */,
785 msg_type,
786 rlen,
787 inst->mlen /* mlen */,
788 inst->header_present /* header */,
789 simd_mode,
790 return_format);
791
792 /* visitor knows more than we do about the surface limit required,
793 * so has already done marking.
794 */
795 }
796 }
797
798
799 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
800 * looking like:
801 *
802 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
803 *
804 * Ideally, we want to produce:
805 *
806 * DDX DDY
807 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
808 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
809 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
810 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
811 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
812 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
813 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
814 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
815 *
816 * and add another set of two more subspans if in 16-pixel dispatch mode.
817 *
818 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
819 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
820 * pair. But the ideal approximation may impose a huge performance cost on
821 * sample_d. On at least Haswell, sample_d instruction does some
822 * optimizations if the same LOD is used for all pixels in the subspan.
823 *
824 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
825 * appropriate swizzling.
826 */
827 void
828 fs_generator::generate_ddx(enum opcode opcode,
829 struct brw_reg dst, struct brw_reg src)
830 {
831 unsigned vstride, width;
832
833 if (opcode == FS_OPCODE_DDX_FINE) {
834 /* produce accurate derivatives */
835 vstride = BRW_VERTICAL_STRIDE_2;
836 width = BRW_WIDTH_2;
837 } else {
838 /* replicate the derivative at the top-left pixel to other pixels */
839 vstride = BRW_VERTICAL_STRIDE_4;
840 width = BRW_WIDTH_4;
841 }
842
843 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
844 src.negate, src.abs,
845 BRW_REGISTER_TYPE_F,
846 vstride,
847 width,
848 BRW_HORIZONTAL_STRIDE_0,
849 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
850 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
851 src.negate, src.abs,
852 BRW_REGISTER_TYPE_F,
853 vstride,
854 width,
855 BRW_HORIZONTAL_STRIDE_0,
856 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
857 brw_ADD(p, dst, src0, negate(src1));
858 }
859
860 /* The negate_value boolean is used to negate the derivative computation for
861 * FBOs, since they place the origin at the upper left instead of the lower
862 * left.
863 */
864 void
865 fs_generator::generate_ddy(enum opcode opcode,
866 struct brw_reg dst, struct brw_reg src,
867 bool negate_value)
868 {
869 if (opcode == FS_OPCODE_DDY_FINE) {
870 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
871 * Region Restrictions):
872 *
873 * In Align16 access mode, SIMD16 is not allowed for DW operations
874 * and SIMD8 is not allowed for DF operations.
875 *
876 * In this context, "DW operations" means "operations acting on 32-bit
877 * values", so it includes operations on floats.
878 *
879 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
880 * (Instruction Compression -> Rules and Restrictions):
881 *
882 * A compressed instruction must be in Align1 access mode. Align16
883 * mode instructions cannot be compressed.
884 *
885 * Similar text exists in the g45 PRM.
886 *
887 * On these platforms, if we're building a SIMD16 shader, we need to
888 * manually unroll to a pair of SIMD8 instructions.
889 */
890 bool unroll_to_simd8 =
891 (dispatch_width == 16 &&
892 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
893
894 /* produce accurate derivatives */
895 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
896 src.negate, src.abs,
897 BRW_REGISTER_TYPE_F,
898 BRW_VERTICAL_STRIDE_4,
899 BRW_WIDTH_4,
900 BRW_HORIZONTAL_STRIDE_1,
901 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
902 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
903 src.negate, src.abs,
904 BRW_REGISTER_TYPE_F,
905 BRW_VERTICAL_STRIDE_4,
906 BRW_WIDTH_4,
907 BRW_HORIZONTAL_STRIDE_1,
908 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
909 brw_push_insn_state(p);
910 brw_set_default_access_mode(p, BRW_ALIGN_16);
911 if (unroll_to_simd8) {
912 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
913 if (negate_value) {
914 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
915 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
916 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
917 } else {
918 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
919 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
920 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
921 }
922 } else {
923 if (negate_value)
924 brw_ADD(p, dst, src1, negate(src0));
925 else
926 brw_ADD(p, dst, src0, negate(src1));
927 }
928 brw_pop_insn_state(p);
929 } else {
930 /* replicate the derivative at the top-left pixel to other pixels */
931 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
932 src.negate, src.abs,
933 BRW_REGISTER_TYPE_F,
934 BRW_VERTICAL_STRIDE_4,
935 BRW_WIDTH_4,
936 BRW_HORIZONTAL_STRIDE_0,
937 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
938 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
939 src.negate, src.abs,
940 BRW_REGISTER_TYPE_F,
941 BRW_VERTICAL_STRIDE_4,
942 BRW_WIDTH_4,
943 BRW_HORIZONTAL_STRIDE_0,
944 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
945 if (negate_value)
946 brw_ADD(p, dst, src1, negate(src0));
947 else
948 brw_ADD(p, dst, src0, negate(src1));
949 }
950 }
951
952 void
953 fs_generator::generate_discard_jump(fs_inst *inst)
954 {
955 assert(brw->gen >= 6);
956
957 /* This HALT will be patched up at FB write time to point UIP at the end of
958 * the program, and at brw_uip_jip() JIP will be set to the end of the
959 * current block (or the program).
960 */
961 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
962
963 brw_push_insn_state(p);
964 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
965 gen6_HALT(p);
966 brw_pop_insn_state(p);
967 }
968
969 void
970 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
971 {
972 assert(inst->mlen != 0);
973
974 brw_MOV(p,
975 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
976 retype(src, BRW_REGISTER_TYPE_UD));
977 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
978 inst->exec_size / 8, inst->offset);
979 }
980
981 void
982 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
983 {
984 assert(inst->mlen != 0);
985
986 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
987 inst->exec_size / 8, inst->offset);
988 }
989
990 void
991 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
992 {
993 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
994 }
995
996 void
997 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
998 struct brw_reg dst,
999 struct brw_reg index,
1000 struct brw_reg offset)
1001 {
1002 assert(inst->mlen != 0);
1003
1004 assert(index.file == BRW_IMMEDIATE_VALUE &&
1005 index.type == BRW_REGISTER_TYPE_UD);
1006 uint32_t surf_index = index.dw1.ud;
1007
1008 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1009 offset.type == BRW_REGISTER_TYPE_UD);
1010 uint32_t read_offset = offset.dw1.ud;
1011
1012 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1013 read_offset, surf_index);
1014
1015 brw_mark_surface_used(prog_data, surf_index);
1016 }
1017
1018 void
1019 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1020 struct brw_reg dst,
1021 struct brw_reg index,
1022 struct brw_reg offset)
1023 {
1024 assert(inst->mlen == 0);
1025 assert(index.type == BRW_REGISTER_TYPE_UD);
1026
1027 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1028 /* Reference just the dword we need, to avoid angering validate_reg(). */
1029 offset = brw_vec1_grf(offset.nr, 0);
1030
1031 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1032 * the destination loaded consecutively from the same offset (which appears
1033 * in the first component, and the rest are ignored).
1034 */
1035 dst.width = BRW_WIDTH_4;
1036
1037 struct brw_reg src = offset;
1038 bool header_present = false;
1039 int mlen = 1;
1040
1041 if (brw->gen >= 9) {
1042 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1043 src = retype(brw_vec4_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD);
1044 mlen = 2;
1045 header_present = true;
1046
1047 brw_push_insn_state(p);
1048 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1049 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1050 brw_set_default_access_mode(p, BRW_ALIGN_1);
1051
1052 brw_MOV(p, get_element_ud(src, 2),
1053 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1054 brw_pop_insn_state(p);
1055 }
1056
1057 if (index.file == BRW_IMMEDIATE_VALUE) {
1058
1059 uint32_t surf_index = index.dw1.ud;
1060
1061 brw_push_insn_state(p);
1062 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1063 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1064 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1065 brw_pop_insn_state(p);
1066
1067 brw_set_dest(p, send, dst);
1068 brw_set_src0(p, send, src);
1069 brw_set_sampler_message(p, send,
1070 surf_index,
1071 0, /* LD message ignores sampler unit */
1072 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1073 1, /* rlen */
1074 mlen,
1075 header_present,
1076 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1077 0);
1078
1079 brw_mark_surface_used(prog_data, surf_index);
1080
1081 } else {
1082
1083 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1084
1085 brw_push_insn_state(p);
1086 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1087 brw_set_default_access_mode(p, BRW_ALIGN_1);
1088
1089 /* a0.0 = surf_index & 0xff */
1090 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1091 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1092 brw_set_dest(p, insn_and, addr);
1093 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1094 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1095
1096 /* dst = send(payload, a0.0 | <descriptor>) */
1097 brw_inst *insn = brw_send_indirect_message(
1098 p, BRW_SFID_SAMPLER, dst, src, addr);
1099 brw_set_sampler_message(p, insn,
1100 0,
1101 0, /* LD message ignores sampler unit */
1102 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1103 1, /* rlen */
1104 mlen,
1105 header_present,
1106 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1107 0);
1108
1109 brw_pop_insn_state(p);
1110
1111 /* visitor knows more than we do about the surface limit required,
1112 * so has already done marking.
1113 */
1114
1115 }
1116 }
1117
1118 void
1119 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1120 struct brw_reg dst,
1121 struct brw_reg index,
1122 struct brw_reg offset)
1123 {
1124 assert(brw->gen < 7); /* Should use the gen7 variant. */
1125 assert(inst->header_present);
1126 assert(inst->mlen);
1127
1128 assert(index.file == BRW_IMMEDIATE_VALUE &&
1129 index.type == BRW_REGISTER_TYPE_UD);
1130 uint32_t surf_index = index.dw1.ud;
1131
1132 uint32_t simd_mode, rlen, msg_type;
1133 if (dispatch_width == 16) {
1134 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1135 rlen = 8;
1136 } else {
1137 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1138 rlen = 4;
1139 }
1140
1141 if (brw->gen >= 5)
1142 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1143 else {
1144 /* We always use the SIMD16 message so that we only have to load U, and
1145 * not V or R.
1146 */
1147 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1148 assert(inst->mlen == 3);
1149 assert(inst->regs_written == 8);
1150 rlen = 8;
1151 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1152 }
1153
1154 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1155 BRW_REGISTER_TYPE_D);
1156 brw_MOV(p, offset_mrf, offset);
1157
1158 struct brw_reg header = brw_vec8_grf(0, 0);
1159 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1160
1161 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1162 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
1163 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1164 brw_set_src0(p, send, header);
1165 if (brw->gen < 6)
1166 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
1167
1168 /* Our surface is set up as floats, regardless of what actual data is
1169 * stored in it.
1170 */
1171 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1172 brw_set_sampler_message(p, send,
1173 surf_index,
1174 0, /* sampler (unused) */
1175 msg_type,
1176 rlen,
1177 inst->mlen,
1178 inst->header_present,
1179 simd_mode,
1180 return_format);
1181
1182 brw_mark_surface_used(prog_data, surf_index);
1183 }
1184
1185 void
1186 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1187 struct brw_reg dst,
1188 struct brw_reg index,
1189 struct brw_reg offset)
1190 {
1191 assert(brw->gen >= 7);
1192 /* Varying-offset pull constant loads are treated as a normal expression on
1193 * gen7, so the fact that it's a send message is hidden at the IR level.
1194 */
1195 assert(!inst->header_present);
1196 assert(!inst->mlen);
1197 assert(index.type == BRW_REGISTER_TYPE_UD);
1198
1199 uint32_t simd_mode, rlen, mlen;
1200 if (dispatch_width == 16) {
1201 mlen = 2;
1202 rlen = 8;
1203 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1204 } else {
1205 mlen = 1;
1206 rlen = 4;
1207 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1208 }
1209
1210 if (index.file == BRW_IMMEDIATE_VALUE) {
1211
1212 uint32_t surf_index = index.dw1.ud;
1213
1214 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1215 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1216 brw_set_src0(p, send, offset);
1217 brw_set_sampler_message(p, send,
1218 surf_index,
1219 0, /* LD message ignores sampler unit */
1220 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1221 rlen,
1222 mlen,
1223 false, /* no header */
1224 simd_mode,
1225 0);
1226
1227 brw_mark_surface_used(prog_data, surf_index);
1228
1229 } else {
1230
1231 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1232
1233 brw_push_insn_state(p);
1234 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1235 brw_set_default_access_mode(p, BRW_ALIGN_1);
1236
1237 /* a0.0 = surf_index & 0xff */
1238 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1239 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1240 brw_set_dest(p, insn_and, addr);
1241 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1242 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1243
1244 brw_pop_insn_state(p);
1245
1246 /* dst = send(offset, a0.0 | <descriptor>) */
1247 brw_inst *insn = brw_send_indirect_message(
1248 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1249 offset, addr);
1250 brw_set_sampler_message(p, insn,
1251 0 /* surface */,
1252 0 /* sampler */,
1253 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1254 rlen /* rlen */,
1255 mlen /* mlen */,
1256 false /* header */,
1257 simd_mode,
1258 0);
1259
1260 /* visitor knows more than we do about the surface limit required,
1261 * so has already done marking.
1262 */
1263 }
1264 }
1265
1266 /**
1267 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1268 * into the flags register (f0.0).
1269 *
1270 * Used only on Gen6 and above.
1271 */
1272 void
1273 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1274 {
1275 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1276 struct brw_reg dispatch_mask;
1277
1278 if (brw->gen >= 6)
1279 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1280 else
1281 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1282
1283 brw_push_insn_state(p);
1284 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1285 brw_MOV(p, flags, dispatch_mask);
1286 brw_pop_insn_state(p);
1287 }
1288
1289 void
1290 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1291 struct brw_reg dst,
1292 struct brw_reg src,
1293 struct brw_reg msg_data,
1294 unsigned msg_type)
1295 {
1296 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1297 msg_data.type == BRW_REGISTER_TYPE_UD);
1298
1299 brw_pixel_interpolator_query(p,
1300 retype(dst, BRW_REGISTER_TYPE_UW),
1301 src,
1302 inst->pi_noperspective,
1303 msg_type,
1304 msg_data.dw1.ud,
1305 inst->mlen,
1306 inst->regs_written);
1307 }
1308
1309
1310 /**
1311 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1312 * sampler LD messages.
1313 *
1314 * We don't want to bake it into the send message's code generation because
1315 * that means we don't get a chance to schedule the instructions.
1316 */
1317 void
1318 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1319 struct brw_reg dst,
1320 struct brw_reg value)
1321 {
1322 assert(value.file == BRW_IMMEDIATE_VALUE);
1323
1324 brw_push_insn_state(p);
1325 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1326 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1327 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1328 brw_pop_insn_state(p);
1329 }
1330
1331 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1332 * (when mask is passed as a uniform) of register mask before moving it
1333 * to register dst.
1334 */
1335 void
1336 fs_generator::generate_set_omask(fs_inst *inst,
1337 struct brw_reg dst,
1338 struct brw_reg mask)
1339 {
1340 bool stride_8_8_1 =
1341 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1342 mask.width == BRW_WIDTH_8 &&
1343 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1344
1345 bool stride_0_1_0 = has_scalar_region(mask);
1346
1347 assert(stride_8_8_1 || stride_0_1_0);
1348 assert(dst.type == BRW_REGISTER_TYPE_UW);
1349
1350 if (dispatch_width == 16)
1351 dst = vec16(dst);
1352 brw_push_insn_state(p);
1353 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1354 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1355
1356 if (stride_8_8_1) {
1357 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1358 } else if (stride_0_1_0) {
1359 brw_MOV(p, dst, retype(mask, dst.type));
1360 }
1361 brw_pop_insn_state(p);
1362 }
1363
1364 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1365 * the ADD instruction.
1366 */
1367 void
1368 fs_generator::generate_set_sample_id(fs_inst *inst,
1369 struct brw_reg dst,
1370 struct brw_reg src0,
1371 struct brw_reg src1)
1372 {
1373 assert(dst.type == BRW_REGISTER_TYPE_D ||
1374 dst.type == BRW_REGISTER_TYPE_UD);
1375 assert(src0.type == BRW_REGISTER_TYPE_D ||
1376 src0.type == BRW_REGISTER_TYPE_UD);
1377
1378 brw_push_insn_state(p);
1379 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1380 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1381 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1382 if (dispatch_width == 8) {
1383 brw_ADD(p, dst, src0, reg);
1384 } else if (dispatch_width == 16) {
1385 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1386 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1387 }
1388 brw_pop_insn_state(p);
1389 }
1390
1391 void
1392 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1393 struct brw_reg dst,
1394 struct brw_reg x,
1395 struct brw_reg y)
1396 {
1397 assert(brw->gen >= 7);
1398 assert(dst.type == BRW_REGISTER_TYPE_UD);
1399 assert(x.type == BRW_REGISTER_TYPE_F);
1400 assert(y.type == BRW_REGISTER_TYPE_F);
1401
1402 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1403 *
1404 * Because this instruction does not have a 16-bit floating-point type,
1405 * the destination data type must be Word (W).
1406 *
1407 * The destination must be DWord-aligned and specify a horizontal stride
1408 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1409 * each destination channel and the upper word is not modified.
1410 */
1411 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1412
1413 /* Give each 32-bit channel of dst the form below, where "." means
1414 * unchanged.
1415 * 0x....hhhh
1416 */
1417 brw_F32TO16(p, dst_w, y);
1418
1419 /* Now the form:
1420 * 0xhhhh0000
1421 */
1422 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1423
1424 /* And, finally the form of packHalf2x16's output:
1425 * 0xhhhhllll
1426 */
1427 brw_F32TO16(p, dst_w, x);
1428 }
1429
1430 void
1431 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1432 struct brw_reg dst,
1433 struct brw_reg src)
1434 {
1435 assert(brw->gen >= 7);
1436 assert(dst.type == BRW_REGISTER_TYPE_F);
1437 assert(src.type == BRW_REGISTER_TYPE_UD);
1438
1439 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1440 *
1441 * Because this instruction does not have a 16-bit floating-point type,
1442 * the source data type must be Word (W). The destination type must be
1443 * F (Float).
1444 */
1445 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1446
1447 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1448 * For the Y case, we wish to access only the upper word; therefore
1449 * a 16-bit subregister offset is needed.
1450 */
1451 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1452 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1453 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1454 src_w.subnr += 2;
1455
1456 brw_F16TO32(p, dst, src_w);
1457 }
1458
1459 void
1460 fs_generator::generate_shader_time_add(fs_inst *inst,
1461 struct brw_reg payload,
1462 struct brw_reg offset,
1463 struct brw_reg value)
1464 {
1465 assert(brw->gen >= 7);
1466 brw_push_insn_state(p);
1467 brw_set_default_mask_control(p, true);
1468
1469 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1470 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1471 offset.type);
1472 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1473 value.type);
1474
1475 assert(offset.file == BRW_IMMEDIATE_VALUE);
1476 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1477 value.width = BRW_WIDTH_1;
1478 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1479 value.vstride = BRW_VERTICAL_STRIDE_0;
1480 } else {
1481 assert(value.file == BRW_IMMEDIATE_VALUE);
1482 }
1483
1484 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1485 * case, and we don't really care about squeezing every bit of performance
1486 * out of this path, so we just emit the MOVs from here.
1487 */
1488 brw_MOV(p, payload_offset, offset);
1489 brw_MOV(p, payload_value, value);
1490 brw_shader_time_add(p, payload,
1491 prog_data->binding_table.shader_time_start);
1492 brw_pop_insn_state(p);
1493
1494 brw_mark_surface_used(prog_data,
1495 prog_data->binding_table.shader_time_start);
1496 }
1497
1498 void
1499 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1500 struct brw_reg payload,
1501 struct brw_reg atomic_op,
1502 struct brw_reg surf_index)
1503 {
1504 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1505 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1506 surf_index.file == BRW_IMMEDIATE_VALUE &&
1507 surf_index.type == BRW_REGISTER_TYPE_UD);
1508
1509 brw_untyped_atomic(p, dst, payload,
1510 atomic_op.dw1.ud, surf_index.dw1.ud,
1511 inst->mlen, true);
1512
1513 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1514 }
1515
1516 void
1517 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1518 struct brw_reg payload,
1519 struct brw_reg surf_index)
1520 {
1521 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1522 surf_index.type == BRW_REGISTER_TYPE_UD);
1523
1524 brw_untyped_surface_read(p, dst, payload, surf_index.dw1.ud, inst->mlen, 1);
1525
1526 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1527 }
1528
1529 void
1530 fs_generator::enable_debug(const char *shader_name)
1531 {
1532 debug_flag = true;
1533 this->shader_name = shader_name;
1534 }
1535
1536 /**
1537 * Some hardware doesn't support SIMD16 instructions with 3 sources.
1538 */
1539 static bool
1540 brw_supports_simd16_3src(const struct brw_context *brw)
1541 {
1542 /* WaDisableSIMD16On3SrcInstr: 3-source instructions don't work in SIMD16
1543 * on a few steppings of Skylake.
1544 */
1545 if (brw->gen == 9)
1546 return brw->revision != 2 && brw->revision != 3 && brw->revision != -1;
1547
1548 return brw->is_haswell || brw->gen >= 8;
1549 }
1550
1551 int
1552 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1553 {
1554 /* align to 64 byte boundary. */
1555 while (p->next_insn_offset % 64)
1556 brw_NOP(p);
1557
1558 this->dispatch_width = dispatch_width;
1559 if (dispatch_width == 16)
1560 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1561
1562 int start_offset = p->next_insn_offset;
1563 int spill_count = 0, fill_count = 0;
1564 int loop_count = 0;
1565
1566 struct annotation_info annotation;
1567 memset(&annotation, 0, sizeof(annotation));
1568
1569 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1570 struct brw_reg src[3], dst;
1571 unsigned int last_insn_offset = p->next_insn_offset;
1572 bool multiple_instructions_emitted = false;
1573
1574 if (unlikely(debug_flag))
1575 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1576
1577 for (unsigned int i = 0; i < inst->sources; i++) {
1578 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1579
1580 /* The accumulator result appears to get used for the
1581 * conditional modifier generation. When negating a UD
1582 * value, there is a 33rd bit generated for the sign in the
1583 * accumulator value, so now you can't check, for example,
1584 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1585 */
1586 assert(!inst->conditional_mod ||
1587 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1588 !inst->src[i].negate);
1589 }
1590 dst = brw_reg_from_fs_reg(&inst->dst);
1591
1592 brw_set_default_predicate_control(p, inst->predicate);
1593 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1594 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1595 brw_set_default_saturate(p, inst->saturate);
1596 brw_set_default_mask_control(p, inst->force_writemask_all);
1597 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1598
1599 switch (inst->exec_size) {
1600 case 1:
1601 case 2:
1602 case 4:
1603 assert(inst->force_writemask_all);
1604 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1605 break;
1606 case 8:
1607 if (inst->force_sechalf) {
1608 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1609 } else {
1610 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1611 }
1612 break;
1613 case 16:
1614 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1615 break;
1616 default:
1617 unreachable("Invalid instruction width");
1618 }
1619
1620 switch (inst->opcode) {
1621 case BRW_OPCODE_MOV:
1622 brw_MOV(p, dst, src[0]);
1623 break;
1624 case BRW_OPCODE_ADD:
1625 brw_ADD(p, dst, src[0], src[1]);
1626 break;
1627 case BRW_OPCODE_MUL:
1628 brw_MUL(p, dst, src[0], src[1]);
1629 break;
1630 case BRW_OPCODE_AVG:
1631 brw_AVG(p, dst, src[0], src[1]);
1632 break;
1633 case BRW_OPCODE_MACH:
1634 brw_MACH(p, dst, src[0], src[1]);
1635 break;
1636
1637 case BRW_OPCODE_LINE:
1638 brw_LINE(p, dst, src[0], src[1]);
1639 break;
1640
1641 case BRW_OPCODE_MAD:
1642 assert(brw->gen >= 6);
1643 brw_set_default_access_mode(p, BRW_ALIGN_16);
1644 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1645 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1646 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1647 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1648 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1649 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1650
1651 if (inst->conditional_mod) {
1652 brw_inst_set_cond_modifier(brw, f, inst->conditional_mod);
1653 brw_inst_set_cond_modifier(brw, s, inst->conditional_mod);
1654 multiple_instructions_emitted = true;
1655 }
1656 } else {
1657 brw_MAD(p, dst, src[0], src[1], src[2]);
1658 }
1659 brw_set_default_access_mode(p, BRW_ALIGN_1);
1660 break;
1661
1662 case BRW_OPCODE_LRP:
1663 assert(brw->gen >= 6);
1664 brw_set_default_access_mode(p, BRW_ALIGN_16);
1665 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1666 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1667 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1668 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1669 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1670 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1671
1672 if (inst->conditional_mod) {
1673 brw_inst_set_cond_modifier(brw, f, inst->conditional_mod);
1674 brw_inst_set_cond_modifier(brw, s, inst->conditional_mod);
1675 multiple_instructions_emitted = true;
1676 }
1677 } else {
1678 brw_LRP(p, dst, src[0], src[1], src[2]);
1679 }
1680 brw_set_default_access_mode(p, BRW_ALIGN_1);
1681 break;
1682
1683 case BRW_OPCODE_FRC:
1684 brw_FRC(p, dst, src[0]);
1685 break;
1686 case BRW_OPCODE_RNDD:
1687 brw_RNDD(p, dst, src[0]);
1688 break;
1689 case BRW_OPCODE_RNDE:
1690 brw_RNDE(p, dst, src[0]);
1691 break;
1692 case BRW_OPCODE_RNDZ:
1693 brw_RNDZ(p, dst, src[0]);
1694 break;
1695
1696 case BRW_OPCODE_AND:
1697 brw_AND(p, dst, src[0], src[1]);
1698 break;
1699 case BRW_OPCODE_OR:
1700 brw_OR(p, dst, src[0], src[1]);
1701 break;
1702 case BRW_OPCODE_XOR:
1703 brw_XOR(p, dst, src[0], src[1]);
1704 break;
1705 case BRW_OPCODE_NOT:
1706 brw_NOT(p, dst, src[0]);
1707 break;
1708 case BRW_OPCODE_ASR:
1709 brw_ASR(p, dst, src[0], src[1]);
1710 break;
1711 case BRW_OPCODE_SHR:
1712 brw_SHR(p, dst, src[0], src[1]);
1713 break;
1714 case BRW_OPCODE_SHL:
1715 brw_SHL(p, dst, src[0], src[1]);
1716 break;
1717 case BRW_OPCODE_F32TO16:
1718 assert(brw->gen >= 7);
1719 brw_F32TO16(p, dst, src[0]);
1720 break;
1721 case BRW_OPCODE_F16TO32:
1722 assert(brw->gen >= 7);
1723 brw_F16TO32(p, dst, src[0]);
1724 break;
1725 case BRW_OPCODE_CMP:
1726 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1727 * that when the destination is a GRF that the dependency-clear bit on
1728 * the flag register is cleared early.
1729 *
1730 * Suggested workarounds are to disable coissuing CMP instructions
1731 * or to split CMP(16) instructions into two CMP(8) instructions.
1732 *
1733 * We choose to split into CMP(8) instructions since disabling
1734 * coissuing would affect CMP instructions not otherwise affected by
1735 * the errata.
1736 */
1737 if (dispatch_width == 16 && brw->gen == 7 && !brw->is_haswell) {
1738 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1739 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1740 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1741 firsthalf(src[0]), firsthalf(src[1]));
1742 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1743 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1744 sechalf(src[0]), sechalf(src[1]));
1745 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1746
1747 multiple_instructions_emitted = true;
1748 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1749 /* For unknown reasons, the aforementioned workaround is not
1750 * sufficient. Overriding the type when the destination is the
1751 * null register is necessary but not sufficient by itself.
1752 */
1753 assert(dst.nr == BRW_ARF_NULL);
1754 dst.type = BRW_REGISTER_TYPE_D;
1755 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1756 } else {
1757 unreachable("not reached");
1758 }
1759 } else {
1760 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1761 }
1762 break;
1763 case BRW_OPCODE_SEL:
1764 brw_SEL(p, dst, src[0], src[1]);
1765 break;
1766 case BRW_OPCODE_BFREV:
1767 assert(brw->gen >= 7);
1768 /* BFREV only supports UD type for src and dst. */
1769 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1770 retype(src[0], BRW_REGISTER_TYPE_UD));
1771 break;
1772 case BRW_OPCODE_FBH:
1773 assert(brw->gen >= 7);
1774 /* FBH only supports UD type for dst. */
1775 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1776 break;
1777 case BRW_OPCODE_FBL:
1778 assert(brw->gen >= 7);
1779 /* FBL only supports UD type for dst. */
1780 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1781 break;
1782 case BRW_OPCODE_CBIT:
1783 assert(brw->gen >= 7);
1784 /* CBIT only supports UD type for dst. */
1785 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1786 break;
1787 case BRW_OPCODE_ADDC:
1788 assert(brw->gen >= 7);
1789 brw_ADDC(p, dst, src[0], src[1]);
1790 break;
1791 case BRW_OPCODE_SUBB:
1792 assert(brw->gen >= 7);
1793 brw_SUBB(p, dst, src[0], src[1]);
1794 break;
1795 case BRW_OPCODE_MAC:
1796 brw_MAC(p, dst, src[0], src[1]);
1797 break;
1798
1799 case BRW_OPCODE_BFE:
1800 assert(brw->gen >= 7);
1801 brw_set_default_access_mode(p, BRW_ALIGN_16);
1802 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1803 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1804 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1805 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1806 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1807 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1808 } else {
1809 brw_BFE(p, dst, src[0], src[1], src[2]);
1810 }
1811 brw_set_default_access_mode(p, BRW_ALIGN_1);
1812 break;
1813
1814 case BRW_OPCODE_BFI1:
1815 assert(brw->gen >= 7);
1816 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1817 * should
1818 *
1819 * "Force BFI instructions to be executed always in SIMD8."
1820 */
1821 if (dispatch_width == 16 && brw->is_haswell) {
1822 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1823 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1824 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1825 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1826 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1827 } else {
1828 brw_BFI1(p, dst, src[0], src[1]);
1829 }
1830 break;
1831 case BRW_OPCODE_BFI2:
1832 assert(brw->gen >= 7);
1833 brw_set_default_access_mode(p, BRW_ALIGN_16);
1834 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1835 * should
1836 *
1837 * "Force BFI instructions to be executed always in SIMD8."
1838 *
1839 * Otherwise we would be able to emit compressed instructions like we
1840 * do for the other three-source instructions.
1841 */
1842 if (dispatch_width == 16 &&
1843 (brw->is_haswell || !brw_supports_simd16_3src(brw))) {
1844 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1845 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1846 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1847 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1848 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1849 } else {
1850 brw_BFI2(p, dst, src[0], src[1], src[2]);
1851 }
1852 brw_set_default_access_mode(p, BRW_ALIGN_1);
1853 break;
1854
1855 case BRW_OPCODE_IF:
1856 if (inst->src[0].file != BAD_FILE) {
1857 /* The instruction has an embedded compare (only allowed on gen6) */
1858 assert(brw->gen == 6);
1859 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1860 } else {
1861 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1862 }
1863 break;
1864
1865 case BRW_OPCODE_ELSE:
1866 brw_ELSE(p);
1867 break;
1868 case BRW_OPCODE_ENDIF:
1869 brw_ENDIF(p);
1870 break;
1871
1872 case BRW_OPCODE_DO:
1873 brw_DO(p, BRW_EXECUTE_8);
1874 break;
1875
1876 case BRW_OPCODE_BREAK:
1877 brw_BREAK(p);
1878 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1879 break;
1880 case BRW_OPCODE_CONTINUE:
1881 brw_CONT(p);
1882 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1883 break;
1884
1885 case BRW_OPCODE_WHILE:
1886 brw_WHILE(p);
1887 loop_count++;
1888 break;
1889
1890 case SHADER_OPCODE_RCP:
1891 case SHADER_OPCODE_RSQ:
1892 case SHADER_OPCODE_SQRT:
1893 case SHADER_OPCODE_EXP2:
1894 case SHADER_OPCODE_LOG2:
1895 case SHADER_OPCODE_SIN:
1896 case SHADER_OPCODE_COS:
1897 assert(brw->gen < 6 || inst->mlen == 0);
1898 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1899 if (brw->gen >= 7) {
1900 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1901 brw_null_reg());
1902 } else if (brw->gen == 6) {
1903 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1904 } else if (brw->gen == 5 || brw->is_g4x) {
1905 generate_math_g45(inst, dst, src[0]);
1906 } else {
1907 generate_math_gen4(inst, dst, src[0]);
1908 }
1909 break;
1910 case SHADER_OPCODE_INT_QUOTIENT:
1911 case SHADER_OPCODE_INT_REMAINDER:
1912 case SHADER_OPCODE_POW:
1913 assert(brw->gen < 6 || inst->mlen == 0);
1914 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1915 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1916 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1917 } else if (brw->gen >= 6) {
1918 generate_math_gen6(inst, dst, src[0], src[1]);
1919 } else {
1920 generate_math_gen4(inst, dst, src[0]);
1921 }
1922 break;
1923 case FS_OPCODE_PIXEL_X:
1924 generate_pixel_xy(dst, true);
1925 break;
1926 case FS_OPCODE_PIXEL_Y:
1927 generate_pixel_xy(dst, false);
1928 break;
1929 case FS_OPCODE_CINTERP:
1930 brw_MOV(p, dst, src[0]);
1931 break;
1932 case FS_OPCODE_LINTERP:
1933 generate_linterp(inst, dst, src);
1934 break;
1935 case SHADER_OPCODE_TEX:
1936 case FS_OPCODE_TXB:
1937 case SHADER_OPCODE_TXD:
1938 case SHADER_OPCODE_TXF:
1939 case SHADER_OPCODE_TXF_CMS:
1940 case SHADER_OPCODE_TXF_UMS:
1941 case SHADER_OPCODE_TXF_MCS:
1942 case SHADER_OPCODE_TXL:
1943 case SHADER_OPCODE_TXS:
1944 case SHADER_OPCODE_LOD:
1945 case SHADER_OPCODE_TG4:
1946 case SHADER_OPCODE_TG4_OFFSET:
1947 generate_tex(inst, dst, src[0], src[1]);
1948 break;
1949 case FS_OPCODE_DDX_COARSE:
1950 case FS_OPCODE_DDX_FINE:
1951 generate_ddx(inst->opcode, dst, src[0]);
1952 break;
1953 case FS_OPCODE_DDY_COARSE:
1954 case FS_OPCODE_DDY_FINE:
1955 assert(src[1].file == BRW_IMMEDIATE_VALUE);
1956 generate_ddy(inst->opcode, dst, src[0], src[1].dw1.ud);
1957 break;
1958
1959 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1960 generate_scratch_write(inst, src[0]);
1961 spill_count++;
1962 break;
1963
1964 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1965 generate_scratch_read(inst, dst);
1966 fill_count++;
1967 break;
1968
1969 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1970 generate_scratch_read_gen7(inst, dst);
1971 fill_count++;
1972 break;
1973
1974 case SHADER_OPCODE_URB_WRITE_SIMD8:
1975 generate_urb_write(inst, src[0]);
1976 break;
1977
1978 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1979 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1980 break;
1981
1982 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1983 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1984 break;
1985
1986 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1987 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1988 break;
1989
1990 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1991 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1992 break;
1993
1994 case FS_OPCODE_REP_FB_WRITE:
1995 case FS_OPCODE_FB_WRITE:
1996 generate_fb_write(inst, src[0]);
1997 break;
1998
1999 case FS_OPCODE_BLORP_FB_WRITE:
2000 generate_blorp_fb_write(inst);
2001 break;
2002
2003 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2004 generate_mov_dispatch_to_flags(inst);
2005 break;
2006
2007 case FS_OPCODE_DISCARD_JUMP:
2008 generate_discard_jump(inst);
2009 break;
2010
2011 case SHADER_OPCODE_SHADER_TIME_ADD:
2012 generate_shader_time_add(inst, src[0], src[1], src[2]);
2013 break;
2014
2015 case SHADER_OPCODE_UNTYPED_ATOMIC:
2016 generate_untyped_atomic(inst, dst, src[0], src[1], src[2]);
2017 break;
2018
2019 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2020 generate_untyped_surface_read(inst, dst, src[0], src[1]);
2021 break;
2022
2023 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2024 generate_set_simd4x2_offset(inst, dst, src[0]);
2025 break;
2026
2027 case FS_OPCODE_SET_OMASK:
2028 generate_set_omask(inst, dst, src[0]);
2029 break;
2030
2031 case FS_OPCODE_SET_SAMPLE_ID:
2032 generate_set_sample_id(inst, dst, src[0], src[1]);
2033 break;
2034
2035 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2036 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2037 break;
2038
2039 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2040 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2041 generate_unpack_half_2x16_split(inst, dst, src[0]);
2042 break;
2043
2044 case FS_OPCODE_PLACEHOLDER_HALT:
2045 /* This is the place where the final HALT needs to be inserted if
2046 * we've emitted any discards. If not, this will emit no code.
2047 */
2048 if (!patch_discard_jumps_to_fb_writes()) {
2049 if (unlikely(debug_flag)) {
2050 annotation.ann_count--;
2051 }
2052 }
2053 break;
2054
2055 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2056 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2057 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2058 break;
2059
2060 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2061 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2062 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2063 break;
2064
2065 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2066 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2067 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2068 break;
2069
2070 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2071 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2072 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2073 break;
2074
2075 default:
2076 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
2077 _mesa_problem(ctx, "Unsupported opcode `%s' in %s",
2078 opcode_descs[inst->opcode].name, stage_abbrev);
2079 } else {
2080 _mesa_problem(ctx, "Unsupported opcode %d in %s", inst->opcode,
2081 stage_abbrev);
2082 }
2083 abort();
2084
2085 case SHADER_OPCODE_LOAD_PAYLOAD:
2086 unreachable("Should be lowered by lower_load_payload()");
2087 }
2088
2089 if (multiple_instructions_emitted)
2090 continue;
2091
2092 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2093 assert(p->next_insn_offset == last_insn_offset + 16 ||
2094 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2095 "emitting more than 1 instruction");
2096
2097 brw_inst *last = &p->store[last_insn_offset / 16];
2098
2099 if (inst->conditional_mod)
2100 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
2101 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
2102 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
2103 }
2104 }
2105
2106 brw_set_uip_jip(p);
2107 annotation_finalize(&annotation, p->next_insn_offset);
2108
2109 int before_size = p->next_insn_offset - start_offset;
2110 brw_compact_instructions(p, start_offset, annotation.ann_count,
2111 annotation.ann);
2112 int after_size = p->next_insn_offset - start_offset;
2113
2114 if (unlikely(debug_flag)) {
2115 fprintf(stderr, "Native code for %s\n"
2116 "SIMD%d shader: %d instructions. %d loops. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2117 " bytes (%.0f%%)\n",
2118 shader_name, dispatch_width, before_size / 16, loop_count,
2119 spill_count, fill_count, promoted_constants, before_size, after_size,
2120 100.0f * (before_size - after_size) / before_size);
2121
2122 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
2123 ralloc_free(annotation.ann);
2124 }
2125
2126 static GLuint msg_id = 0;
2127 _mesa_gl_debug(&brw->ctx, &msg_id,
2128 MESA_DEBUG_SOURCE_SHADER_COMPILER,
2129 MESA_DEBUG_TYPE_OTHER,
2130 MESA_DEBUG_SEVERITY_NOTIFICATION,
2131 "%s SIMD%d shader: %d inst, %d loops, %d:%d spills:fills, "
2132 "Promoted %u constants, compacted %d to %d bytes.\n",
2133 stage_abbrev, dispatch_width, before_size / 16, loop_count,
2134 spill_count, fill_count, promoted_constants, before_size, after_size);
2135
2136 return start_offset;
2137 }
2138
2139 const unsigned *
2140 fs_generator::get_assembly(unsigned int *assembly_size)
2141 {
2142 return brw_get_program(p, assembly_size);
2143 }