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i965: Move MRF register asserts out of brw_reg.h
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "main/macros.h"
31 #include "brw_context.h"
32 #include "brw_eu.h"
33 #include "brw_fs.h"
34 #include "brw_cfg.h"
35
36 static uint32_t brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case GRF:
40 return BRW_GENERAL_REGISTER_FILE;
41 case MRF:
42 return BRW_MESSAGE_REGISTER_FILE;
43 case IMM:
44 return BRW_IMMEDIATE_VALUE;
45 default:
46 unreachable("not reached");
47 }
48 }
49
50 static struct brw_reg
51 brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg)
52 {
53 struct brw_reg brw_reg;
54
55 switch (reg->file) {
56 case MRF:
57 assert((reg->reg & ~(1 << 7)) < BRW_MAX_MRF);
58 /* Fallthrough */
59 case GRF:
60 if (reg->stride == 0) {
61 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
62 } else if (inst->exec_size < 8) {
63 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
64 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
65 inst->exec_size, reg->stride);
66 } else {
67 /* From the Haswell PRM:
68 *
69 * VertStride must be used to cross GRF register boundaries. This
70 * rule implies that elements within a 'Width' cannot cross GRF
71 * boundaries.
72 *
73 * So, for registers with width > 8, we have to use a width of 8
74 * and trust the compression state to sort out the exec size.
75 */
76 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
77 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
78 }
79
80 brw_reg = retype(brw_reg, reg->type);
81 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
82 break;
83 case IMM:
84 assert(reg->stride == ((reg->type == BRW_REGISTER_TYPE_V ||
85 reg->type == BRW_REGISTER_TYPE_UV ||
86 reg->type == BRW_REGISTER_TYPE_VF) ? 1 : 0));
87
88 switch (reg->type) {
89 case BRW_REGISTER_TYPE_F:
90 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
91 break;
92 case BRW_REGISTER_TYPE_D:
93 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
94 break;
95 case BRW_REGISTER_TYPE_UD:
96 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
97 break;
98 case BRW_REGISTER_TYPE_W:
99 brw_reg = brw_imm_w(reg->fixed_hw_reg.dw1.d);
100 break;
101 case BRW_REGISTER_TYPE_UW:
102 brw_reg = brw_imm_uw(reg->fixed_hw_reg.dw1.ud);
103 break;
104 case BRW_REGISTER_TYPE_VF:
105 brw_reg = brw_imm_vf(reg->fixed_hw_reg.dw1.ud);
106 break;
107 default:
108 unreachable("not reached");
109 }
110 break;
111 case HW_REG:
112 assert(reg->type == reg->fixed_hw_reg.type);
113 brw_reg = reg->fixed_hw_reg;
114 break;
115 case BAD_FILE:
116 /* Probably unused. */
117 brw_reg = brw_null_reg();
118 break;
119 default:
120 unreachable("not reached");
121 }
122 if (reg->abs)
123 brw_reg = brw_abs(brw_reg);
124 if (reg->negate)
125 brw_reg = negate(brw_reg);
126
127 return brw_reg;
128 }
129
130 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
131 void *mem_ctx,
132 const void *key,
133 struct brw_stage_prog_data *prog_data,
134 struct gl_program *prog,
135 unsigned promoted_constants,
136 bool runtime_check_aads_emit,
137 const char *stage_abbrev)
138
139 : compiler(compiler), log_data(log_data),
140 devinfo(compiler->devinfo), key(key),
141 prog_data(prog_data),
142 prog(prog), promoted_constants(promoted_constants),
143 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
144 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
145 {
146 p = rzalloc(mem_ctx, struct brw_codegen);
147 brw_init_codegen(devinfo, p, mem_ctx);
148 }
149
150 fs_generator::~fs_generator()
151 {
152 }
153
154 class ip_record : public exec_node {
155 public:
156 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
157
158 ip_record(int ip)
159 {
160 this->ip = ip;
161 }
162
163 int ip;
164 };
165
166 bool
167 fs_generator::patch_discard_jumps_to_fb_writes()
168 {
169 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
170 return false;
171
172 int scale = brw_jump_scale(p->devinfo);
173
174 /* There is a somewhat strange undocumented requirement of using
175 * HALT, according to the simulator. If some channel has HALTed to
176 * a particular UIP, then by the end of the program, every channel
177 * must have HALTed to that UIP. Furthermore, the tracking is a
178 * stack, so you can't do the final halt of a UIP after starting
179 * halting to a new UIP.
180 *
181 * Symptoms of not emitting this instruction on actual hardware
182 * included GPU hangs and sparkly rendering on the piglit discard
183 * tests.
184 */
185 brw_inst *last_halt = gen6_HALT(p);
186 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
187 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
188
189 int ip = p->nr_insn;
190
191 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
192 brw_inst *patch = &p->store[patch_ip->ip];
193
194 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
195 /* HALT takes a half-instruction distance from the pre-incremented IP. */
196 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
197 }
198
199 this->discard_halt_patches.make_empty();
200 return true;
201 }
202
203 void
204 fs_generator::fire_fb_write(fs_inst *inst,
205 struct brw_reg payload,
206 struct brw_reg implied_header,
207 GLuint nr)
208 {
209 uint32_t msg_control;
210
211 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
212
213 if (devinfo->gen < 6) {
214 brw_push_insn_state(p);
215 brw_set_default_exec_size(p, BRW_EXECUTE_8);
216 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
217 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
218 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
219 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
220 brw_pop_insn_state(p);
221 }
222
223 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
224 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
225 else if (prog_data->dual_src_blend) {
226 if (!inst->force_sechalf)
227 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
228 else
229 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
230 } else if (inst->exec_size == 16)
231 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
232 else
233 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
234
235 uint32_t surf_index =
236 prog_data->binding_table.render_target_start + inst->target;
237
238 bool last_render_target = inst->eot ||
239 (prog_data->dual_src_blend && dispatch_width == 16);
240
241
242 brw_fb_WRITE(p,
243 dispatch_width,
244 payload,
245 implied_header,
246 msg_control,
247 surf_index,
248 nr,
249 0,
250 inst->eot,
251 last_render_target,
252 inst->header_size != 0);
253
254 brw_mark_surface_used(&prog_data->base, surf_index);
255 }
256
257 void
258 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
259 {
260 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
261 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
262 struct brw_reg implied_header;
263
264 if (devinfo->gen < 8 && !devinfo->is_haswell) {
265 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
266 }
267
268 if (inst->base_mrf >= 0)
269 payload = brw_message_reg(inst->base_mrf);
270
271 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
272 * move, here's g1.
273 */
274 if (inst->header_size != 0) {
275 brw_push_insn_state(p);
276 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
277 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
278 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
279 brw_set_default_flag_reg(p, 0, 0);
280
281 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
282 * present.
283 */
284 if (prog_data->uses_kill) {
285 struct brw_reg pixel_mask;
286
287 if (devinfo->gen >= 6)
288 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
289 else
290 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
291
292 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
293 }
294
295 if (devinfo->gen >= 6) {
296 brw_push_insn_state(p);
297 brw_set_default_exec_size(p, BRW_EXECUTE_16);
298 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
299 brw_MOV(p,
300 retype(payload, BRW_REGISTER_TYPE_UD),
301 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
302 brw_pop_insn_state(p);
303
304 if (inst->target > 0 && key->replicate_alpha) {
305 /* Set "Source0 Alpha Present to RenderTarget" bit in message
306 * header.
307 */
308 brw_OR(p,
309 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
310 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
311 brw_imm_ud(0x1 << 11));
312 }
313
314 if (inst->target > 0) {
315 /* Set the render target index for choosing BLEND_STATE. */
316 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
317 BRW_REGISTER_TYPE_UD),
318 brw_imm_ud(inst->target));
319 }
320
321 implied_header = brw_null_reg();
322 } else {
323 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
324 }
325
326 brw_pop_insn_state(p);
327 } else {
328 implied_header = brw_null_reg();
329 }
330
331 if (!runtime_check_aads_emit) {
332 fire_fb_write(inst, payload, implied_header, inst->mlen);
333 } else {
334 /* This can only happen in gen < 6 */
335 assert(devinfo->gen < 6);
336
337 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
338
339 /* Check runtime bit to detect if we have to send AA data or not */
340 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
341 brw_AND(p,
342 v1_null_ud,
343 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
344 brw_imm_ud(1<<26));
345 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
346
347 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
348 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
349 {
350 /* Don't send AA data */
351 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
352 }
353 brw_land_fwd_jump(p, jmp);
354 fire_fb_write(inst, payload, implied_header, inst->mlen);
355 }
356 }
357
358 void
359 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
360 {
361 brw_inst *insn;
362
363 insn = brw_next_insn(p, BRW_OPCODE_SEND);
364
365 brw_set_dest(p, insn, brw_null_reg());
366 brw_set_src0(p, insn, payload);
367 brw_set_src1(p, insn, brw_imm_d(0));
368
369 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
370 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
371
372 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
373 brw_inst_set_rlen(p->devinfo, insn, 0);
374 brw_inst_set_eot(p->devinfo, insn, inst->eot);
375 brw_inst_set_header_present(p->devinfo, insn, true);
376 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
377 }
378
379 void
380 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
381 {
382 struct brw_inst *insn;
383
384 insn = brw_next_insn(p, BRW_OPCODE_SEND);
385
386 brw_set_dest(p, insn, brw_null_reg());
387 brw_set_src0(p, insn, payload);
388 brw_set_src1(p, insn, brw_imm_d(0));
389
390 /* Terminate a compute shader by sending a message to the thread spawner.
391 */
392 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
393 brw_inst_set_mlen(devinfo, insn, 1);
394 brw_inst_set_rlen(devinfo, insn, 0);
395 brw_inst_set_eot(devinfo, insn, inst->eot);
396 brw_inst_set_header_present(devinfo, insn, false);
397
398 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
399 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
400
401 /* Note that even though the thread has a URB resource associated with it,
402 * we set the "do not dereference URB" bit, because the URB resource is
403 * managed by the fixed-function unit, so it will free it automatically.
404 */
405 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
406
407 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
408 }
409
410 void
411 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
412 {
413 brw_barrier(p, src);
414 brw_WAIT(p);
415 }
416
417 void
418 fs_generator::generate_blorp_fb_write(fs_inst *inst)
419 {
420 brw_fb_WRITE(p,
421 16 /* dispatch_width */,
422 brw_message_reg(inst->base_mrf),
423 brw_reg_from_fs_reg(inst, &inst->src[0]),
424 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
425 inst->target,
426 inst->mlen,
427 0,
428 true,
429 true,
430 inst->header_size != 0);
431 }
432
433 void
434 fs_generator::generate_linterp(fs_inst *inst,
435 struct brw_reg dst, struct brw_reg *src)
436 {
437 /* PLN reads:
438 * / in SIMD16 \
439 * -----------------------------------
440 * | src1+0 | src1+1 | src1+2 | src1+3 |
441 * |-----------------------------------|
442 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
443 * -----------------------------------
444 *
445 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
446 *
447 * -----------------------------------
448 * | src1+0 | src1+1 | src1+2 | src1+3 |
449 * |-----------------------------------|
450 * |(x0, x1)|(y0, y1)| | | in SIMD8
451 * |-----------------------------------|
452 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
453 * -----------------------------------
454 *
455 * See also: emit_interpolation_setup_gen4().
456 */
457 struct brw_reg delta_x = src[0];
458 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
459 struct brw_reg interp = src[1];
460
461 if (devinfo->has_pln &&
462 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
463 brw_PLN(p, dst, interp, delta_x);
464 } else {
465 brw_LINE(p, brw_null_reg(), interp, delta_x);
466 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
467 }
468 }
469
470 void
471 fs_generator::generate_math_gen6(fs_inst *inst,
472 struct brw_reg dst,
473 struct brw_reg src0,
474 struct brw_reg src1)
475 {
476 int op = brw_math_function(inst->opcode);
477 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
478
479 if (dispatch_width == 8) {
480 gen6_math(p, dst, op, src0, src1);
481 } else if (dispatch_width == 16) {
482 brw_push_insn_state(p);
483 brw_set_default_exec_size(p, BRW_EXECUTE_8);
484 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
485 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
486 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
487 gen6_math(p, sechalf(dst), op, sechalf(src0),
488 binop ? sechalf(src1) : brw_null_reg());
489 brw_pop_insn_state(p);
490 }
491 }
492
493 void
494 fs_generator::generate_math_gen4(fs_inst *inst,
495 struct brw_reg dst,
496 struct brw_reg src)
497 {
498 int op = brw_math_function(inst->opcode);
499
500 assert(inst->mlen >= 1);
501
502 if (dispatch_width == 8) {
503 gen4_math(p, dst,
504 op,
505 inst->base_mrf, src,
506 BRW_MATH_PRECISION_FULL);
507 } else if (dispatch_width == 16) {
508 brw_set_default_exec_size(p, BRW_EXECUTE_8);
509 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
510 gen4_math(p, firsthalf(dst),
511 op,
512 inst->base_mrf, firsthalf(src),
513 BRW_MATH_PRECISION_FULL);
514 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
515 gen4_math(p, sechalf(dst),
516 op,
517 inst->base_mrf + 1, sechalf(src),
518 BRW_MATH_PRECISION_FULL);
519
520 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
521 }
522 }
523
524 void
525 fs_generator::generate_math_g45(fs_inst *inst,
526 struct brw_reg dst,
527 struct brw_reg src)
528 {
529 if (inst->opcode == SHADER_OPCODE_POW ||
530 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
531 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
532 generate_math_gen4(inst, dst, src);
533 return;
534 }
535
536 int op = brw_math_function(inst->opcode);
537
538 assert(inst->mlen >= 1);
539
540 gen4_math(p, dst,
541 op,
542 inst->base_mrf, src,
543 BRW_MATH_PRECISION_FULL);
544 }
545
546 void
547 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
548 struct brw_reg sampler_index)
549 {
550 int msg_type = -1;
551 int rlen = 4;
552 uint32_t simd_mode;
553 uint32_t return_format;
554 bool is_combined_send = inst->eot;
555
556 switch (dst.type) {
557 case BRW_REGISTER_TYPE_D:
558 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
559 break;
560 case BRW_REGISTER_TYPE_UD:
561 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
562 break;
563 default:
564 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
565 break;
566 }
567
568 switch (inst->exec_size) {
569 case 8:
570 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
571 break;
572 case 16:
573 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
574 break;
575 default:
576 unreachable("Invalid width for texture instruction");
577 }
578
579 if (devinfo->gen >= 5) {
580 switch (inst->opcode) {
581 case SHADER_OPCODE_TEX:
582 if (inst->shadow_compare) {
583 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
584 } else {
585 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
586 }
587 break;
588 case FS_OPCODE_TXB:
589 if (inst->shadow_compare) {
590 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
591 } else {
592 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
593 }
594 break;
595 case SHADER_OPCODE_TXL:
596 if (inst->shadow_compare) {
597 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
598 } else {
599 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
600 }
601 break;
602 case SHADER_OPCODE_TXS:
603 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
604 break;
605 case SHADER_OPCODE_TXD:
606 if (inst->shadow_compare) {
607 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
608 assert(devinfo->gen >= 8 || devinfo->is_haswell);
609 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
610 } else {
611 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
612 }
613 break;
614 case SHADER_OPCODE_TXF:
615 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
616 break;
617 case SHADER_OPCODE_TXF_CMS:
618 if (devinfo->gen >= 7)
619 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
620 else
621 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
622 break;
623 case SHADER_OPCODE_TXF_UMS:
624 assert(devinfo->gen >= 7);
625 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
626 break;
627 case SHADER_OPCODE_TXF_MCS:
628 assert(devinfo->gen >= 7);
629 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
630 break;
631 case SHADER_OPCODE_LOD:
632 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
633 break;
634 case SHADER_OPCODE_TG4:
635 if (inst->shadow_compare) {
636 assert(devinfo->gen >= 7);
637 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
638 } else {
639 assert(devinfo->gen >= 6);
640 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
641 }
642 break;
643 case SHADER_OPCODE_TG4_OFFSET:
644 assert(devinfo->gen >= 7);
645 if (inst->shadow_compare) {
646 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
647 } else {
648 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
649 }
650 break;
651 case SHADER_OPCODE_SAMPLEINFO:
652 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
653 break;
654 default:
655 unreachable("not reached");
656 }
657 } else {
658 switch (inst->opcode) {
659 case SHADER_OPCODE_TEX:
660 /* Note that G45 and older determines shadow compare and dispatch width
661 * from message length for most messages.
662 */
663 if (inst->exec_size == 8) {
664 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
665 if (inst->shadow_compare) {
666 assert(inst->mlen == 6);
667 } else {
668 assert(inst->mlen <= 4);
669 }
670 } else {
671 if (inst->shadow_compare) {
672 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
673 assert(inst->mlen == 9);
674 } else {
675 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
676 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
677 }
678 }
679 break;
680 case FS_OPCODE_TXB:
681 if (inst->shadow_compare) {
682 assert(inst->exec_size == 8);
683 assert(inst->mlen == 6);
684 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
685 } else {
686 assert(inst->mlen == 9);
687 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
688 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
689 }
690 break;
691 case SHADER_OPCODE_TXL:
692 if (inst->shadow_compare) {
693 assert(inst->exec_size == 8);
694 assert(inst->mlen == 6);
695 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
696 } else {
697 assert(inst->mlen == 9);
698 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
699 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
700 }
701 break;
702 case SHADER_OPCODE_TXD:
703 /* There is no sample_d_c message; comparisons are done manually */
704 assert(inst->exec_size == 8);
705 assert(inst->mlen == 7 || inst->mlen == 10);
706 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
707 break;
708 case SHADER_OPCODE_TXF:
709 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
710 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
711 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
712 break;
713 case SHADER_OPCODE_TXS:
714 assert(inst->mlen == 3);
715 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
716 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
717 break;
718 default:
719 unreachable("not reached");
720 }
721 }
722 assert(msg_type != -1);
723
724 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
725 rlen = 8;
726 dst = vec16(dst);
727 }
728
729 if (is_combined_send) {
730 assert(devinfo->gen >= 9 || devinfo->is_cherryview);
731 rlen = 0;
732 }
733
734 assert(devinfo->gen < 7 || inst->header_size == 0 ||
735 src.file == BRW_GENERAL_REGISTER_FILE);
736
737 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
738
739 /* Load the message header if present. If there's a texture offset,
740 * we need to set it up explicitly and load the offset bitfield.
741 * Otherwise, we can use an implied move from g0 to the first message reg.
742 */
743 if (inst->header_size != 0) {
744 if (devinfo->gen < 6 && !inst->offset) {
745 /* Set up an implied move from g0 to the MRF. */
746 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
747 } else {
748 struct brw_reg header_reg;
749
750 if (devinfo->gen >= 7) {
751 header_reg = src;
752 } else {
753 assert(inst->base_mrf != -1);
754 header_reg = brw_message_reg(inst->base_mrf);
755 }
756
757 brw_push_insn_state(p);
758 brw_set_default_exec_size(p, BRW_EXECUTE_8);
759 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
760 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
761 /* Explicitly set up the message header by copying g0 to the MRF. */
762 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
763
764 if (inst->offset) {
765 /* Set the offset bits in DWord 2. */
766 brw_MOV(p, get_element_ud(header_reg, 2),
767 brw_imm_ud(inst->offset));
768 }
769
770 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
771 brw_pop_insn_state(p);
772 }
773 }
774
775 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
776 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
777 ? prog_data->binding_table.gather_texture_start
778 : prog_data->binding_table.texture_start;
779
780 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
781 uint32_t sampler = sampler_index.dw1.ud;
782
783 brw_SAMPLE(p,
784 retype(dst, BRW_REGISTER_TYPE_UW),
785 inst->base_mrf,
786 src,
787 sampler + base_binding_table_index,
788 sampler % 16,
789 msg_type,
790 rlen,
791 inst->mlen,
792 inst->header_size != 0,
793 simd_mode,
794 return_format);
795
796 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
797 } else {
798 /* Non-const sampler index */
799
800 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
801 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
802
803 brw_push_insn_state(p);
804 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
805 brw_set_default_access_mode(p, BRW_ALIGN_1);
806
807 /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
808 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
809 if (base_binding_table_index)
810 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
811 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
812
813 brw_pop_insn_state(p);
814
815 /* dst = send(offset, a0.0 | <descriptor>) */
816 brw_inst *insn = brw_send_indirect_message(
817 p, BRW_SFID_SAMPLER, dst, src, addr);
818 brw_set_sampler_message(p, insn,
819 0 /* surface */,
820 0 /* sampler */,
821 msg_type,
822 rlen,
823 inst->mlen /* mlen */,
824 inst->header_size != 0 /* header */,
825 simd_mode,
826 return_format);
827
828 /* visitor knows more than we do about the surface limit required,
829 * so has already done marking.
830 */
831 }
832
833 if (is_combined_send) {
834 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
835 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
836 }
837 }
838
839
840 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
841 * looking like:
842 *
843 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
844 *
845 * Ideally, we want to produce:
846 *
847 * DDX DDY
848 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
849 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
850 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
851 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
852 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
853 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
854 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
855 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
856 *
857 * and add another set of two more subspans if in 16-pixel dispatch mode.
858 *
859 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
860 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
861 * pair. But the ideal approximation may impose a huge performance cost on
862 * sample_d. On at least Haswell, sample_d instruction does some
863 * optimizations if the same LOD is used for all pixels in the subspan.
864 *
865 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
866 * appropriate swizzling.
867 */
868 void
869 fs_generator::generate_ddx(enum opcode opcode,
870 struct brw_reg dst, struct brw_reg src)
871 {
872 unsigned vstride, width;
873
874 if (opcode == FS_OPCODE_DDX_FINE) {
875 /* produce accurate derivatives */
876 vstride = BRW_VERTICAL_STRIDE_2;
877 width = BRW_WIDTH_2;
878 } else {
879 /* replicate the derivative at the top-left pixel to other pixels */
880 vstride = BRW_VERTICAL_STRIDE_4;
881 width = BRW_WIDTH_4;
882 }
883
884 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
885 src.negate, src.abs,
886 BRW_REGISTER_TYPE_F,
887 vstride,
888 width,
889 BRW_HORIZONTAL_STRIDE_0,
890 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
891 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
892 src.negate, src.abs,
893 BRW_REGISTER_TYPE_F,
894 vstride,
895 width,
896 BRW_HORIZONTAL_STRIDE_0,
897 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
898 brw_ADD(p, dst, src0, negate(src1));
899 }
900
901 /* The negate_value boolean is used to negate the derivative computation for
902 * FBOs, since they place the origin at the upper left instead of the lower
903 * left.
904 */
905 void
906 fs_generator::generate_ddy(enum opcode opcode,
907 struct brw_reg dst, struct brw_reg src,
908 bool negate_value)
909 {
910 if (opcode == FS_OPCODE_DDY_FINE) {
911 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
912 * Region Restrictions):
913 *
914 * In Align16 access mode, SIMD16 is not allowed for DW operations
915 * and SIMD8 is not allowed for DF operations.
916 *
917 * In this context, "DW operations" means "operations acting on 32-bit
918 * values", so it includes operations on floats.
919 *
920 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
921 * (Instruction Compression -> Rules and Restrictions):
922 *
923 * A compressed instruction must be in Align1 access mode. Align16
924 * mode instructions cannot be compressed.
925 *
926 * Similar text exists in the g45 PRM.
927 *
928 * On these platforms, if we're building a SIMD16 shader, we need to
929 * manually unroll to a pair of SIMD8 instructions.
930 */
931 bool unroll_to_simd8 =
932 (dispatch_width == 16 &&
933 (devinfo->gen == 4 || (devinfo->gen == 7 && !devinfo->is_haswell)));
934
935 /* produce accurate derivatives */
936 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
937 src.negate, src.abs,
938 BRW_REGISTER_TYPE_F,
939 BRW_VERTICAL_STRIDE_4,
940 BRW_WIDTH_4,
941 BRW_HORIZONTAL_STRIDE_1,
942 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
943 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
944 src.negate, src.abs,
945 BRW_REGISTER_TYPE_F,
946 BRW_VERTICAL_STRIDE_4,
947 BRW_WIDTH_4,
948 BRW_HORIZONTAL_STRIDE_1,
949 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
950 brw_push_insn_state(p);
951 brw_set_default_access_mode(p, BRW_ALIGN_16);
952 if (unroll_to_simd8) {
953 brw_set_default_exec_size(p, BRW_EXECUTE_8);
954 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
955 if (negate_value) {
956 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
957 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
958 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
959 } else {
960 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
961 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
962 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
963 }
964 } else {
965 if (negate_value)
966 brw_ADD(p, dst, src1, negate(src0));
967 else
968 brw_ADD(p, dst, src0, negate(src1));
969 }
970 brw_pop_insn_state(p);
971 } else {
972 /* replicate the derivative at the top-left pixel to other pixels */
973 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
974 src.negate, src.abs,
975 BRW_REGISTER_TYPE_F,
976 BRW_VERTICAL_STRIDE_4,
977 BRW_WIDTH_4,
978 BRW_HORIZONTAL_STRIDE_0,
979 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
980 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
981 src.negate, src.abs,
982 BRW_REGISTER_TYPE_F,
983 BRW_VERTICAL_STRIDE_4,
984 BRW_WIDTH_4,
985 BRW_HORIZONTAL_STRIDE_0,
986 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
987 if (negate_value)
988 brw_ADD(p, dst, src1, negate(src0));
989 else
990 brw_ADD(p, dst, src0, negate(src1));
991 }
992 }
993
994 void
995 fs_generator::generate_discard_jump(fs_inst *inst)
996 {
997 assert(devinfo->gen >= 6);
998
999 /* This HALT will be patched up at FB write time to point UIP at the end of
1000 * the program, and at brw_uip_jip() JIP will be set to the end of the
1001 * current block (or the program).
1002 */
1003 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1004
1005 brw_push_insn_state(p);
1006 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1007 gen6_HALT(p);
1008 brw_pop_insn_state(p);
1009 }
1010
1011 void
1012 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1013 {
1014 assert(inst->mlen != 0);
1015
1016 brw_MOV(p,
1017 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1018 retype(src, BRW_REGISTER_TYPE_UD));
1019 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1020 inst->exec_size / 8, inst->offset);
1021 }
1022
1023 void
1024 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1025 {
1026 assert(inst->mlen != 0);
1027
1028 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1029 inst->exec_size / 8, inst->offset);
1030 }
1031
1032 void
1033 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1034 {
1035 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1036 }
1037
1038 void
1039 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1040 struct brw_reg dst,
1041 struct brw_reg index,
1042 struct brw_reg offset)
1043 {
1044 assert(inst->mlen != 0);
1045
1046 assert(index.file == BRW_IMMEDIATE_VALUE &&
1047 index.type == BRW_REGISTER_TYPE_UD);
1048 uint32_t surf_index = index.dw1.ud;
1049
1050 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1051 offset.type == BRW_REGISTER_TYPE_UD);
1052 uint32_t read_offset = offset.dw1.ud;
1053
1054 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1055 read_offset, surf_index);
1056
1057 brw_mark_surface_used(prog_data, surf_index);
1058 }
1059
1060 void
1061 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1062 struct brw_reg dst,
1063 struct brw_reg index,
1064 struct brw_reg offset)
1065 {
1066 assert(index.type == BRW_REGISTER_TYPE_UD);
1067
1068 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1069 /* Reference just the dword we need, to avoid angering validate_reg(). */
1070 offset = brw_vec1_grf(offset.nr, 0);
1071
1072 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1073 * the destination loaded consecutively from the same offset (which appears
1074 * in the first component, and the rest are ignored).
1075 */
1076 dst.width = BRW_WIDTH_4;
1077
1078 struct brw_reg src = offset;
1079 bool header_present = false;
1080
1081 if (devinfo->gen >= 9) {
1082 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1083 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1084 header_present = true;
1085
1086 brw_push_insn_state(p);
1087 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1088 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1089 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1090 brw_set_default_access_mode(p, BRW_ALIGN_1);
1091
1092 brw_MOV(p, get_element_ud(src, 2),
1093 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1094 brw_pop_insn_state(p);
1095 }
1096
1097 if (index.file == BRW_IMMEDIATE_VALUE) {
1098
1099 uint32_t surf_index = index.dw1.ud;
1100
1101 brw_push_insn_state(p);
1102 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1103 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1104 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1105 brw_pop_insn_state(p);
1106
1107 brw_set_dest(p, send, dst);
1108 brw_set_src0(p, send, src);
1109 brw_set_sampler_message(p, send,
1110 surf_index,
1111 0, /* LD message ignores sampler unit */
1112 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1113 1, /* rlen */
1114 inst->mlen,
1115 header_present,
1116 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1117 0);
1118
1119 brw_mark_surface_used(prog_data, surf_index);
1120
1121 } else {
1122
1123 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1124
1125 brw_push_insn_state(p);
1126 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1127 brw_set_default_access_mode(p, BRW_ALIGN_1);
1128
1129 /* a0.0 = surf_index & 0xff */
1130 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1131 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1132 brw_set_dest(p, insn_and, addr);
1133 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1134 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1135
1136 /* dst = send(payload, a0.0 | <descriptor>) */
1137 brw_inst *insn = brw_send_indirect_message(
1138 p, BRW_SFID_SAMPLER, dst, src, addr);
1139 brw_set_sampler_message(p, insn,
1140 0,
1141 0, /* LD message ignores sampler unit */
1142 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1143 1, /* rlen */
1144 inst->mlen,
1145 header_present,
1146 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1147 0);
1148
1149 brw_pop_insn_state(p);
1150
1151 /* visitor knows more than we do about the surface limit required,
1152 * so has already done marking.
1153 */
1154
1155 }
1156 }
1157
1158 void
1159 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1160 struct brw_reg dst,
1161 struct brw_reg index,
1162 struct brw_reg offset)
1163 {
1164 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1165 assert(inst->header_size != 0);
1166 assert(inst->mlen);
1167
1168 assert(index.file == BRW_IMMEDIATE_VALUE &&
1169 index.type == BRW_REGISTER_TYPE_UD);
1170 uint32_t surf_index = index.dw1.ud;
1171
1172 uint32_t simd_mode, rlen, msg_type;
1173 if (dispatch_width == 16) {
1174 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1175 rlen = 8;
1176 } else {
1177 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1178 rlen = 4;
1179 }
1180
1181 if (devinfo->gen >= 5)
1182 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1183 else {
1184 /* We always use the SIMD16 message so that we only have to load U, and
1185 * not V or R.
1186 */
1187 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1188 assert(inst->mlen == 3);
1189 assert(inst->regs_written == 8);
1190 rlen = 8;
1191 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1192 }
1193
1194 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1195 BRW_REGISTER_TYPE_D);
1196 brw_MOV(p, offset_mrf, offset);
1197
1198 struct brw_reg header = brw_vec8_grf(0, 0);
1199 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1200
1201 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1202 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1203 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1204 brw_set_src0(p, send, header);
1205 if (devinfo->gen < 6)
1206 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1207
1208 /* Our surface is set up as floats, regardless of what actual data is
1209 * stored in it.
1210 */
1211 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1212 brw_set_sampler_message(p, send,
1213 surf_index,
1214 0, /* sampler (unused) */
1215 msg_type,
1216 rlen,
1217 inst->mlen,
1218 inst->header_size != 0,
1219 simd_mode,
1220 return_format);
1221
1222 brw_mark_surface_used(prog_data, surf_index);
1223 }
1224
1225 void
1226 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1227 struct brw_reg dst,
1228 struct brw_reg index,
1229 struct brw_reg offset)
1230 {
1231 assert(devinfo->gen >= 7);
1232 /* Varying-offset pull constant loads are treated as a normal expression on
1233 * gen7, so the fact that it's a send message is hidden at the IR level.
1234 */
1235 assert(inst->header_size == 0);
1236 assert(!inst->mlen);
1237 assert(index.type == BRW_REGISTER_TYPE_UD);
1238
1239 uint32_t simd_mode, rlen, mlen;
1240 if (dispatch_width == 16) {
1241 mlen = 2;
1242 rlen = 8;
1243 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1244 } else {
1245 mlen = 1;
1246 rlen = 4;
1247 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1248 }
1249
1250 if (index.file == BRW_IMMEDIATE_VALUE) {
1251
1252 uint32_t surf_index = index.dw1.ud;
1253
1254 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1255 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1256 brw_set_src0(p, send, offset);
1257 brw_set_sampler_message(p, send,
1258 surf_index,
1259 0, /* LD message ignores sampler unit */
1260 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1261 rlen,
1262 mlen,
1263 false, /* no header */
1264 simd_mode,
1265 0);
1266
1267 brw_mark_surface_used(prog_data, surf_index);
1268
1269 } else {
1270
1271 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1272
1273 brw_push_insn_state(p);
1274 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1275 brw_set_default_access_mode(p, BRW_ALIGN_1);
1276
1277 /* a0.0 = surf_index & 0xff */
1278 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1279 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1280 brw_set_dest(p, insn_and, addr);
1281 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1282 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1283
1284 brw_pop_insn_state(p);
1285
1286 /* dst = send(offset, a0.0 | <descriptor>) */
1287 brw_inst *insn = brw_send_indirect_message(
1288 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1289 offset, addr);
1290 brw_set_sampler_message(p, insn,
1291 0 /* surface */,
1292 0 /* sampler */,
1293 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1294 rlen /* rlen */,
1295 mlen /* mlen */,
1296 false /* header */,
1297 simd_mode,
1298 0);
1299
1300 /* visitor knows more than we do about the surface limit required,
1301 * so has already done marking.
1302 */
1303 }
1304 }
1305
1306 /**
1307 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1308 * into the flags register (f0.0).
1309 *
1310 * Used only on Gen6 and above.
1311 */
1312 void
1313 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1314 {
1315 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1316 struct brw_reg dispatch_mask;
1317
1318 if (devinfo->gen >= 6)
1319 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1320 else
1321 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1322
1323 brw_push_insn_state(p);
1324 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1325 brw_MOV(p, flags, dispatch_mask);
1326 brw_pop_insn_state(p);
1327 }
1328
1329 void
1330 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1331 struct brw_reg dst,
1332 struct brw_reg src,
1333 struct brw_reg msg_data,
1334 unsigned msg_type)
1335 {
1336 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1337 msg_data.type == BRW_REGISTER_TYPE_UD);
1338
1339 brw_pixel_interpolator_query(p,
1340 retype(dst, BRW_REGISTER_TYPE_UW),
1341 src,
1342 inst->pi_noperspective,
1343 msg_type,
1344 msg_data.dw1.ud,
1345 inst->mlen,
1346 inst->regs_written);
1347 }
1348
1349
1350 /**
1351 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1352 * sampler LD messages.
1353 *
1354 * We don't want to bake it into the send message's code generation because
1355 * that means we don't get a chance to schedule the instructions.
1356 */
1357 void
1358 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1359 struct brw_reg dst,
1360 struct brw_reg value)
1361 {
1362 assert(value.file == BRW_IMMEDIATE_VALUE);
1363
1364 brw_push_insn_state(p);
1365 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1366 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1367 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1368 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1369 brw_pop_insn_state(p);
1370 }
1371
1372 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1373 * the ADD instruction.
1374 */
1375 void
1376 fs_generator::generate_set_sample_id(fs_inst *inst,
1377 struct brw_reg dst,
1378 struct brw_reg src0,
1379 struct brw_reg src1)
1380 {
1381 assert(dst.type == BRW_REGISTER_TYPE_D ||
1382 dst.type == BRW_REGISTER_TYPE_UD);
1383 assert(src0.type == BRW_REGISTER_TYPE_D ||
1384 src0.type == BRW_REGISTER_TYPE_UD);
1385
1386 brw_push_insn_state(p);
1387 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1388 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1389 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1390 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1391 if (dispatch_width == 8) {
1392 brw_ADD(p, dst, src0, reg);
1393 } else if (dispatch_width == 16) {
1394 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1395 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1396 }
1397 brw_pop_insn_state(p);
1398 }
1399
1400 void
1401 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1402 struct brw_reg dst,
1403 struct brw_reg x,
1404 struct brw_reg y)
1405 {
1406 assert(devinfo->gen >= 7);
1407 assert(dst.type == BRW_REGISTER_TYPE_UD);
1408 assert(x.type == BRW_REGISTER_TYPE_F);
1409 assert(y.type == BRW_REGISTER_TYPE_F);
1410
1411 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1412 *
1413 * Because this instruction does not have a 16-bit floating-point type,
1414 * the destination data type must be Word (W).
1415 *
1416 * The destination must be DWord-aligned and specify a horizontal stride
1417 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1418 * each destination channel and the upper word is not modified.
1419 */
1420 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1421
1422 /* Give each 32-bit channel of dst the form below, where "." means
1423 * unchanged.
1424 * 0x....hhhh
1425 */
1426 brw_F32TO16(p, dst_w, y);
1427
1428 /* Now the form:
1429 * 0xhhhh0000
1430 */
1431 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1432
1433 /* And, finally the form of packHalf2x16's output:
1434 * 0xhhhhllll
1435 */
1436 brw_F32TO16(p, dst_w, x);
1437 }
1438
1439 void
1440 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1441 struct brw_reg dst,
1442 struct brw_reg src)
1443 {
1444 assert(devinfo->gen >= 7);
1445 assert(dst.type == BRW_REGISTER_TYPE_F);
1446 assert(src.type == BRW_REGISTER_TYPE_UD);
1447
1448 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1449 *
1450 * Because this instruction does not have a 16-bit floating-point type,
1451 * the source data type must be Word (W). The destination type must be
1452 * F (Float).
1453 */
1454 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1455
1456 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1457 * For the Y case, we wish to access only the upper word; therefore
1458 * a 16-bit subregister offset is needed.
1459 */
1460 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1461 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1462 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1463 src_w.subnr += 2;
1464
1465 brw_F16TO32(p, dst, src_w);
1466 }
1467
1468 void
1469 fs_generator::generate_shader_time_add(fs_inst *inst,
1470 struct brw_reg payload,
1471 struct brw_reg offset,
1472 struct brw_reg value)
1473 {
1474 assert(devinfo->gen >= 7);
1475 brw_push_insn_state(p);
1476 brw_set_default_mask_control(p, true);
1477
1478 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1479 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1480 offset.type);
1481 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1482 value.type);
1483
1484 assert(offset.file == BRW_IMMEDIATE_VALUE);
1485 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1486 value.width = BRW_WIDTH_1;
1487 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1488 value.vstride = BRW_VERTICAL_STRIDE_0;
1489 } else {
1490 assert(value.file == BRW_IMMEDIATE_VALUE);
1491 }
1492
1493 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1494 * case, and we don't really care about squeezing every bit of performance
1495 * out of this path, so we just emit the MOVs from here.
1496 */
1497 brw_MOV(p, payload_offset, offset);
1498 brw_MOV(p, payload_value, value);
1499 brw_shader_time_add(p, payload,
1500 prog_data->binding_table.shader_time_start);
1501 brw_pop_insn_state(p);
1502
1503 brw_mark_surface_used(prog_data,
1504 prog_data->binding_table.shader_time_start);
1505 }
1506
1507 void
1508 fs_generator::enable_debug(const char *shader_name)
1509 {
1510 debug_flag = true;
1511 this->shader_name = shader_name;
1512 }
1513
1514 int
1515 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1516 {
1517 /* align to 64 byte boundary. */
1518 while (p->next_insn_offset % 64)
1519 brw_NOP(p);
1520
1521 this->dispatch_width = dispatch_width;
1522 if (dispatch_width == 16)
1523 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1524
1525 int start_offset = p->next_insn_offset;
1526 int spill_count = 0, fill_count = 0;
1527 int loop_count = 0;
1528
1529 struct annotation_info annotation;
1530 memset(&annotation, 0, sizeof(annotation));
1531
1532 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1533 struct brw_reg src[3], dst;
1534 unsigned int last_insn_offset = p->next_insn_offset;
1535 bool multiple_instructions_emitted = false;
1536
1537 if (unlikely(debug_flag))
1538 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1539
1540 for (unsigned int i = 0; i < inst->sources; i++) {
1541 src[i] = brw_reg_from_fs_reg(inst, &inst->src[i]);
1542
1543 /* The accumulator result appears to get used for the
1544 * conditional modifier generation. When negating a UD
1545 * value, there is a 33rd bit generated for the sign in the
1546 * accumulator value, so now you can't check, for example,
1547 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1548 */
1549 assert(!inst->conditional_mod ||
1550 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1551 !inst->src[i].negate);
1552 }
1553 dst = brw_reg_from_fs_reg(inst, &inst->dst);
1554
1555 brw_set_default_predicate_control(p, inst->predicate);
1556 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1557 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1558 brw_set_default_saturate(p, inst->saturate);
1559 brw_set_default_mask_control(p, inst->force_writemask_all);
1560 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1561 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1562
1563 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF);
1564 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1565
1566 switch (inst->exec_size) {
1567 case 1:
1568 case 2:
1569 case 4:
1570 assert(inst->force_writemask_all);
1571 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1572 break;
1573 case 8:
1574 if (inst->force_sechalf) {
1575 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1576 } else {
1577 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1578 }
1579 break;
1580 case 16:
1581 case 32:
1582 /* If the instruction writes to more than one register, it needs to
1583 * be a "compressed" instruction on Gen <= 5.
1584 */
1585 if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
1586 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1587 else
1588 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1589 break;
1590 default:
1591 unreachable("Invalid instruction width");
1592 }
1593
1594 switch (inst->opcode) {
1595 case BRW_OPCODE_MOV:
1596 brw_MOV(p, dst, src[0]);
1597 break;
1598 case BRW_OPCODE_ADD:
1599 brw_ADD(p, dst, src[0], src[1]);
1600 break;
1601 case BRW_OPCODE_MUL:
1602 brw_MUL(p, dst, src[0], src[1]);
1603 break;
1604 case BRW_OPCODE_AVG:
1605 brw_AVG(p, dst, src[0], src[1]);
1606 break;
1607 case BRW_OPCODE_MACH:
1608 brw_MACH(p, dst, src[0], src[1]);
1609 break;
1610
1611 case BRW_OPCODE_LINE:
1612 brw_LINE(p, dst, src[0], src[1]);
1613 break;
1614
1615 case BRW_OPCODE_MAD:
1616 assert(devinfo->gen >= 6);
1617 brw_set_default_access_mode(p, BRW_ALIGN_16);
1618 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1619 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1620 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1621 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1622 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1623 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1624 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1625
1626 if (inst->conditional_mod) {
1627 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1628 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1629 multiple_instructions_emitted = true;
1630 }
1631 } else {
1632 brw_MAD(p, dst, src[0], src[1], src[2]);
1633 }
1634 brw_set_default_access_mode(p, BRW_ALIGN_1);
1635 break;
1636
1637 case BRW_OPCODE_LRP:
1638 assert(devinfo->gen >= 6);
1639 brw_set_default_access_mode(p, BRW_ALIGN_16);
1640 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1641 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1642 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1643 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1644 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1645 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1646 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1647
1648 if (inst->conditional_mod) {
1649 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1650 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1651 multiple_instructions_emitted = true;
1652 }
1653 } else {
1654 brw_LRP(p, dst, src[0], src[1], src[2]);
1655 }
1656 brw_set_default_access_mode(p, BRW_ALIGN_1);
1657 break;
1658
1659 case BRW_OPCODE_FRC:
1660 brw_FRC(p, dst, src[0]);
1661 break;
1662 case BRW_OPCODE_RNDD:
1663 brw_RNDD(p, dst, src[0]);
1664 break;
1665 case BRW_OPCODE_RNDE:
1666 brw_RNDE(p, dst, src[0]);
1667 break;
1668 case BRW_OPCODE_RNDZ:
1669 brw_RNDZ(p, dst, src[0]);
1670 break;
1671
1672 case BRW_OPCODE_AND:
1673 brw_AND(p, dst, src[0], src[1]);
1674 break;
1675 case BRW_OPCODE_OR:
1676 brw_OR(p, dst, src[0], src[1]);
1677 break;
1678 case BRW_OPCODE_XOR:
1679 brw_XOR(p, dst, src[0], src[1]);
1680 break;
1681 case BRW_OPCODE_NOT:
1682 brw_NOT(p, dst, src[0]);
1683 break;
1684 case BRW_OPCODE_ASR:
1685 brw_ASR(p, dst, src[0], src[1]);
1686 break;
1687 case BRW_OPCODE_SHR:
1688 brw_SHR(p, dst, src[0], src[1]);
1689 break;
1690 case BRW_OPCODE_SHL:
1691 brw_SHL(p, dst, src[0], src[1]);
1692 break;
1693 case BRW_OPCODE_F32TO16:
1694 assert(devinfo->gen >= 7);
1695 brw_F32TO16(p, dst, src[0]);
1696 break;
1697 case BRW_OPCODE_F16TO32:
1698 assert(devinfo->gen >= 7);
1699 brw_F16TO32(p, dst, src[0]);
1700 break;
1701 case BRW_OPCODE_CMP:
1702 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1703 * that when the destination is a GRF that the dependency-clear bit on
1704 * the flag register is cleared early.
1705 *
1706 * Suggested workarounds are to disable coissuing CMP instructions
1707 * or to split CMP(16) instructions into two CMP(8) instructions.
1708 *
1709 * We choose to split into CMP(8) instructions since disabling
1710 * coissuing would affect CMP instructions not otherwise affected by
1711 * the errata.
1712 */
1713 if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) {
1714 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1715 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1716 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1717 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1718 firsthalf(src[0]), firsthalf(src[1]));
1719 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1720 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1721 sechalf(src[0]), sechalf(src[1]));
1722 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1723
1724 multiple_instructions_emitted = true;
1725 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1726 /* For unknown reasons, the aforementioned workaround is not
1727 * sufficient. Overriding the type when the destination is the
1728 * null register is necessary but not sufficient by itself.
1729 */
1730 assert(dst.nr == BRW_ARF_NULL);
1731 dst.type = BRW_REGISTER_TYPE_D;
1732 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1733 } else {
1734 unreachable("not reached");
1735 }
1736 } else {
1737 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1738 }
1739 break;
1740 case BRW_OPCODE_SEL:
1741 brw_SEL(p, dst, src[0], src[1]);
1742 break;
1743 case BRW_OPCODE_BFREV:
1744 assert(devinfo->gen >= 7);
1745 /* BFREV only supports UD type for src and dst. */
1746 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1747 retype(src[0], BRW_REGISTER_TYPE_UD));
1748 break;
1749 case BRW_OPCODE_FBH:
1750 assert(devinfo->gen >= 7);
1751 /* FBH only supports UD type for dst. */
1752 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1753 break;
1754 case BRW_OPCODE_FBL:
1755 assert(devinfo->gen >= 7);
1756 /* FBL only supports UD type for dst. */
1757 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1758 break;
1759 case BRW_OPCODE_CBIT:
1760 assert(devinfo->gen >= 7);
1761 /* CBIT only supports UD type for dst. */
1762 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1763 break;
1764 case BRW_OPCODE_ADDC:
1765 assert(devinfo->gen >= 7);
1766 brw_ADDC(p, dst, src[0], src[1]);
1767 break;
1768 case BRW_OPCODE_SUBB:
1769 assert(devinfo->gen >= 7);
1770 brw_SUBB(p, dst, src[0], src[1]);
1771 break;
1772 case BRW_OPCODE_MAC:
1773 brw_MAC(p, dst, src[0], src[1]);
1774 break;
1775
1776 case BRW_OPCODE_BFE:
1777 assert(devinfo->gen >= 7);
1778 brw_set_default_access_mode(p, BRW_ALIGN_16);
1779 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1780 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1781 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1782 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1783 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1784 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1785 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1786 } else {
1787 brw_BFE(p, dst, src[0], src[1], src[2]);
1788 }
1789 brw_set_default_access_mode(p, BRW_ALIGN_1);
1790 break;
1791
1792 case BRW_OPCODE_BFI1:
1793 assert(devinfo->gen >= 7);
1794 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1795 * should
1796 *
1797 * "Force BFI instructions to be executed always in SIMD8."
1798 */
1799 if (dispatch_width == 16 && devinfo->is_haswell) {
1800 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1801 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1802 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1803 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1804 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1805 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1806 } else {
1807 brw_BFI1(p, dst, src[0], src[1]);
1808 }
1809 break;
1810 case BRW_OPCODE_BFI2:
1811 assert(devinfo->gen >= 7);
1812 brw_set_default_access_mode(p, BRW_ALIGN_16);
1813 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1814 * should
1815 *
1816 * "Force BFI instructions to be executed always in SIMD8."
1817 *
1818 * Otherwise we would be able to emit compressed instructions like we
1819 * do for the other three-source instructions.
1820 */
1821 if (dispatch_width == 16 &&
1822 (devinfo->is_haswell || !devinfo->supports_simd16_3src)) {
1823 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1824 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1825 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1826 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1827 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1828 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1829 } else {
1830 brw_BFI2(p, dst, src[0], src[1], src[2]);
1831 }
1832 brw_set_default_access_mode(p, BRW_ALIGN_1);
1833 break;
1834
1835 case BRW_OPCODE_IF:
1836 if (inst->src[0].file != BAD_FILE) {
1837 /* The instruction has an embedded compare (only allowed on gen6) */
1838 assert(devinfo->gen == 6);
1839 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1840 } else {
1841 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1842 }
1843 break;
1844
1845 case BRW_OPCODE_ELSE:
1846 brw_ELSE(p);
1847 break;
1848 case BRW_OPCODE_ENDIF:
1849 brw_ENDIF(p);
1850 break;
1851
1852 case BRW_OPCODE_DO:
1853 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1854 break;
1855
1856 case BRW_OPCODE_BREAK:
1857 brw_BREAK(p);
1858 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1859 break;
1860 case BRW_OPCODE_CONTINUE:
1861 brw_CONT(p);
1862 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1863 break;
1864
1865 case BRW_OPCODE_WHILE:
1866 brw_WHILE(p);
1867 loop_count++;
1868 break;
1869
1870 case SHADER_OPCODE_RCP:
1871 case SHADER_OPCODE_RSQ:
1872 case SHADER_OPCODE_SQRT:
1873 case SHADER_OPCODE_EXP2:
1874 case SHADER_OPCODE_LOG2:
1875 case SHADER_OPCODE_SIN:
1876 case SHADER_OPCODE_COS:
1877 assert(devinfo->gen < 6 || inst->mlen == 0);
1878 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1879 if (devinfo->gen >= 7) {
1880 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1881 brw_null_reg());
1882 } else if (devinfo->gen == 6) {
1883 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1884 } else if (devinfo->gen == 5 || devinfo->is_g4x) {
1885 generate_math_g45(inst, dst, src[0]);
1886 } else {
1887 generate_math_gen4(inst, dst, src[0]);
1888 }
1889 break;
1890 case SHADER_OPCODE_INT_QUOTIENT:
1891 case SHADER_OPCODE_INT_REMAINDER:
1892 case SHADER_OPCODE_POW:
1893 assert(devinfo->gen < 6 || inst->mlen == 0);
1894 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1895 if (devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1896 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1897 } else if (devinfo->gen >= 6) {
1898 generate_math_gen6(inst, dst, src[0], src[1]);
1899 } else {
1900 generate_math_gen4(inst, dst, src[0]);
1901 }
1902 break;
1903 case FS_OPCODE_CINTERP:
1904 brw_MOV(p, dst, src[0]);
1905 break;
1906 case FS_OPCODE_LINTERP:
1907 generate_linterp(inst, dst, src);
1908 break;
1909 case FS_OPCODE_PIXEL_X:
1910 assert(src[0].type == BRW_REGISTER_TYPE_UW);
1911 src[0].subnr = 0 * type_sz(src[0].type);
1912 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1913 break;
1914 case FS_OPCODE_PIXEL_Y:
1915 assert(src[0].type == BRW_REGISTER_TYPE_UW);
1916 src[0].subnr = 4 * type_sz(src[0].type);
1917 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1918 break;
1919 case SHADER_OPCODE_TEX:
1920 case FS_OPCODE_TXB:
1921 case SHADER_OPCODE_TXD:
1922 case SHADER_OPCODE_TXF:
1923 case SHADER_OPCODE_TXF_CMS:
1924 case SHADER_OPCODE_TXF_UMS:
1925 case SHADER_OPCODE_TXF_MCS:
1926 case SHADER_OPCODE_TXL:
1927 case SHADER_OPCODE_TXS:
1928 case SHADER_OPCODE_LOD:
1929 case SHADER_OPCODE_TG4:
1930 case SHADER_OPCODE_TG4_OFFSET:
1931 case SHADER_OPCODE_SAMPLEINFO:
1932 generate_tex(inst, dst, src[0], src[1]);
1933 break;
1934 case FS_OPCODE_DDX_COARSE:
1935 case FS_OPCODE_DDX_FINE:
1936 generate_ddx(inst->opcode, dst, src[0]);
1937 break;
1938 case FS_OPCODE_DDY_COARSE:
1939 case FS_OPCODE_DDY_FINE:
1940 assert(src[1].file == BRW_IMMEDIATE_VALUE);
1941 generate_ddy(inst->opcode, dst, src[0], src[1].dw1.ud);
1942 break;
1943
1944 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1945 generate_scratch_write(inst, src[0]);
1946 spill_count++;
1947 break;
1948
1949 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1950 generate_scratch_read(inst, dst);
1951 fill_count++;
1952 break;
1953
1954 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1955 generate_scratch_read_gen7(inst, dst);
1956 fill_count++;
1957 break;
1958
1959 case SHADER_OPCODE_URB_WRITE_SIMD8:
1960 generate_urb_write(inst, src[0]);
1961 break;
1962
1963 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1964 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1965 break;
1966
1967 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1968 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1969 break;
1970
1971 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1972 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1973 break;
1974
1975 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1976 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1977 break;
1978
1979 case FS_OPCODE_REP_FB_WRITE:
1980 case FS_OPCODE_FB_WRITE:
1981 generate_fb_write(inst, src[0]);
1982 break;
1983
1984 case FS_OPCODE_BLORP_FB_WRITE:
1985 generate_blorp_fb_write(inst);
1986 break;
1987
1988 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1989 generate_mov_dispatch_to_flags(inst);
1990 break;
1991
1992 case FS_OPCODE_DISCARD_JUMP:
1993 generate_discard_jump(inst);
1994 break;
1995
1996 case SHADER_OPCODE_SHADER_TIME_ADD:
1997 generate_shader_time_add(inst, src[0], src[1], src[2]);
1998 break;
1999
2000 case SHADER_OPCODE_UNTYPED_ATOMIC:
2001 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2002 brw_untyped_atomic(p, dst, src[0], src[1], src[2].dw1.ud,
2003 inst->mlen, !inst->dst.is_null());
2004 break;
2005
2006 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2007 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2008 brw_untyped_surface_read(p, dst, src[0], src[1],
2009 inst->mlen, src[2].dw1.ud);
2010 break;
2011
2012 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2013 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2014 brw_untyped_surface_write(p, src[0], src[1],
2015 inst->mlen, src[2].dw1.ud);
2016 break;
2017
2018 case SHADER_OPCODE_TYPED_ATOMIC:
2019 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2020 brw_typed_atomic(p, dst, src[0], src[1],
2021 src[2].dw1.ud, inst->mlen, !inst->dst.is_null());
2022 break;
2023
2024 case SHADER_OPCODE_TYPED_SURFACE_READ:
2025 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2026 brw_typed_surface_read(p, dst, src[0], src[1],
2027 inst->mlen, src[2].dw1.ud);
2028 break;
2029
2030 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2031 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2032 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].dw1.ud);
2033 break;
2034
2035 case SHADER_OPCODE_MEMORY_FENCE:
2036 brw_memory_fence(p, dst);
2037 break;
2038
2039 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2040 generate_set_simd4x2_offset(inst, dst, src[0]);
2041 break;
2042
2043 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
2044 brw_find_live_channel(p, dst);
2045 break;
2046
2047 case SHADER_OPCODE_BROADCAST:
2048 brw_broadcast(p, dst, src[0], src[1]);
2049 break;
2050
2051 case FS_OPCODE_SET_SAMPLE_ID:
2052 generate_set_sample_id(inst, dst, src[0], src[1]);
2053 break;
2054
2055 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2056 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2057 break;
2058
2059 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2060 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2061 generate_unpack_half_2x16_split(inst, dst, src[0]);
2062 break;
2063
2064 case FS_OPCODE_PLACEHOLDER_HALT:
2065 /* This is the place where the final HALT needs to be inserted if
2066 * we've emitted any discards. If not, this will emit no code.
2067 */
2068 if (!patch_discard_jumps_to_fb_writes()) {
2069 if (unlikely(debug_flag)) {
2070 annotation.ann_count--;
2071 }
2072 }
2073 break;
2074
2075 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2076 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2077 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2078 break;
2079
2080 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2081 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2082 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2083 break;
2084
2085 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2086 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2087 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2088 break;
2089
2090 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2091 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2092 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2093 break;
2094
2095 case CS_OPCODE_CS_TERMINATE:
2096 generate_cs_terminate(inst, src[0]);
2097 break;
2098
2099 case SHADER_OPCODE_BARRIER:
2100 generate_barrier(inst, src[0]);
2101 break;
2102
2103 default:
2104 unreachable("Unsupported opcode");
2105
2106 case SHADER_OPCODE_LOAD_PAYLOAD:
2107 unreachable("Should be lowered by lower_load_payload()");
2108 }
2109
2110 if (multiple_instructions_emitted)
2111 continue;
2112
2113 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2114 assert(p->next_insn_offset == last_insn_offset + 16 ||
2115 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2116 "emitting more than 1 instruction");
2117
2118 brw_inst *last = &p->store[last_insn_offset / 16];
2119
2120 if (inst->conditional_mod)
2121 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2122 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2123 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2124 }
2125 }
2126
2127 brw_set_uip_jip(p);
2128 annotation_finalize(&annotation, p->next_insn_offset);
2129
2130 int before_size = p->next_insn_offset - start_offset;
2131 brw_compact_instructions(p, start_offset, annotation.ann_count,
2132 annotation.ann);
2133 int after_size = p->next_insn_offset - start_offset;
2134
2135 if (unlikely(debug_flag)) {
2136 fprintf(stderr, "Native code for %s\n"
2137 "SIMD%d shader: %d instructions. %d loops. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2138 " bytes (%.0f%%)\n",
2139 shader_name, dispatch_width, before_size / 16, loop_count,
2140 spill_count, fill_count, promoted_constants, before_size, after_size,
2141 100.0f * (before_size - after_size) / before_size);
2142
2143 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2144 p->devinfo, prog);
2145 ralloc_free(annotation.ann);
2146 }
2147
2148 compiler->shader_debug_log(log_data,
2149 "%s SIMD%d shader: %d inst, %d loops, "
2150 "%d:%d spills:fills, Promoted %u constants, "
2151 "compacted %d to %d bytes.\n",
2152 stage_abbrev, dispatch_width, before_size / 16,
2153 loop_count, spill_count, fill_count,
2154 promoted_constants, before_size, after_size);
2155
2156 return start_offset;
2157 }
2158
2159 const unsigned *
2160 fs_generator::get_assembly(unsigned int *assembly_size)
2161 {
2162 return brw_get_program(p, assembly_size);
2163 }