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i965: Add initial assembly validation pass.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "main/macros.h"
31 #include "brw_context.h"
32 #include "brw_eu.h"
33 #include "brw_fs.h"
34 #include "brw_cfg.h"
35
36 static uint32_t brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case GRF:
40 return BRW_GENERAL_REGISTER_FILE;
41 case MRF:
42 return BRW_MESSAGE_REGISTER_FILE;
43 case IMM:
44 return BRW_IMMEDIATE_VALUE;
45 case BAD_FILE:
46 case HW_REG:
47 case ATTR:
48 case UNIFORM:
49 unreachable("not reached");
50 }
51 return 0;
52 }
53
54 static struct brw_reg
55 brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
56 {
57 struct brw_reg brw_reg;
58
59 switch (reg->file) {
60 case MRF:
61 assert((reg->reg & ~(1 << 7)) < BRW_MAX_MRF(gen));
62 /* Fallthrough */
63 case GRF:
64 if (reg->stride == 0) {
65 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
66 } else if (inst->exec_size < 8) {
67 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
68 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
69 inst->exec_size, reg->stride);
70 } else {
71 /* From the Haswell PRM:
72 *
73 * VertStride must be used to cross GRF register boundaries. This
74 * rule implies that elements within a 'Width' cannot cross GRF
75 * boundaries.
76 *
77 * So, for registers with width > 8, we have to use a width of 8
78 * and trust the compression state to sort out the exec size.
79 */
80 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
81 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
82 }
83
84 brw_reg = retype(brw_reg, reg->type);
85 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
86 break;
87 case IMM:
88 assert(reg->stride == ((reg->type == BRW_REGISTER_TYPE_V ||
89 reg->type == BRW_REGISTER_TYPE_UV ||
90 reg->type == BRW_REGISTER_TYPE_VF) ? 1 : 0));
91
92 switch (reg->type) {
93 case BRW_REGISTER_TYPE_F:
94 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
95 break;
96 case BRW_REGISTER_TYPE_D:
97 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
98 break;
99 case BRW_REGISTER_TYPE_UD:
100 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
101 break;
102 case BRW_REGISTER_TYPE_W:
103 brw_reg = brw_imm_w(reg->fixed_hw_reg.dw1.d);
104 break;
105 case BRW_REGISTER_TYPE_UW:
106 brw_reg = brw_imm_uw(reg->fixed_hw_reg.dw1.ud);
107 break;
108 case BRW_REGISTER_TYPE_VF:
109 brw_reg = brw_imm_vf(reg->fixed_hw_reg.dw1.ud);
110 break;
111 default:
112 unreachable("not reached");
113 }
114 break;
115 case HW_REG:
116 assert(reg->type == reg->fixed_hw_reg.type);
117 brw_reg = reg->fixed_hw_reg;
118 break;
119 case BAD_FILE:
120 /* Probably unused. */
121 brw_reg = brw_null_reg();
122 break;
123 case ATTR:
124 case UNIFORM:
125 unreachable("not reached");
126 }
127 if (reg->abs)
128 brw_reg = brw_abs(brw_reg);
129 if (reg->negate)
130 brw_reg = negate(brw_reg);
131
132 return brw_reg;
133 }
134
135 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
136 void *mem_ctx,
137 const void *key,
138 struct brw_stage_prog_data *prog_data,
139 unsigned promoted_constants,
140 bool runtime_check_aads_emit,
141 const char *stage_abbrev)
142
143 : compiler(compiler), log_data(log_data),
144 devinfo(compiler->devinfo), key(key),
145 prog_data(prog_data),
146 promoted_constants(promoted_constants),
147 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
148 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
149 {
150 p = rzalloc(mem_ctx, struct brw_codegen);
151 brw_init_codegen(devinfo, p, mem_ctx);
152 }
153
154 fs_generator::~fs_generator()
155 {
156 }
157
158 class ip_record : public exec_node {
159 public:
160 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
161
162 ip_record(int ip)
163 {
164 this->ip = ip;
165 }
166
167 int ip;
168 };
169
170 bool
171 fs_generator::patch_discard_jumps_to_fb_writes()
172 {
173 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
174 return false;
175
176 int scale = brw_jump_scale(p->devinfo);
177
178 /* There is a somewhat strange undocumented requirement of using
179 * HALT, according to the simulator. If some channel has HALTed to
180 * a particular UIP, then by the end of the program, every channel
181 * must have HALTed to that UIP. Furthermore, the tracking is a
182 * stack, so you can't do the final halt of a UIP after starting
183 * halting to a new UIP.
184 *
185 * Symptoms of not emitting this instruction on actual hardware
186 * included GPU hangs and sparkly rendering on the piglit discard
187 * tests.
188 */
189 brw_inst *last_halt = gen6_HALT(p);
190 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
191 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
192
193 int ip = p->nr_insn;
194
195 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
196 brw_inst *patch = &p->store[patch_ip->ip];
197
198 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
199 /* HALT takes a half-instruction distance from the pre-incremented IP. */
200 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
201 }
202
203 this->discard_halt_patches.make_empty();
204 return true;
205 }
206
207 void
208 fs_generator::fire_fb_write(fs_inst *inst,
209 struct brw_reg payload,
210 struct brw_reg implied_header,
211 GLuint nr)
212 {
213 uint32_t msg_control;
214
215 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
216
217 if (devinfo->gen < 6) {
218 brw_push_insn_state(p);
219 brw_set_default_exec_size(p, BRW_EXECUTE_8);
220 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
221 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
222 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
223 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
224 brw_pop_insn_state(p);
225 }
226
227 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
228 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
229 else if (prog_data->dual_src_blend) {
230 if (!inst->force_sechalf)
231 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
232 else
233 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
234 } else if (inst->exec_size == 16)
235 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
236 else
237 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
238
239 uint32_t surf_index =
240 prog_data->binding_table.render_target_start + inst->target;
241
242 bool last_render_target = inst->eot ||
243 (prog_data->dual_src_blend && dispatch_width == 16);
244
245
246 brw_fb_WRITE(p,
247 dispatch_width,
248 payload,
249 implied_header,
250 msg_control,
251 surf_index,
252 nr,
253 0,
254 inst->eot,
255 last_render_target,
256 inst->header_size != 0);
257
258 brw_mark_surface_used(&prog_data->base, surf_index);
259 }
260
261 void
262 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
263 {
264 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
265 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
266 struct brw_reg implied_header;
267
268 if (devinfo->gen < 8 && !devinfo->is_haswell) {
269 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
270 }
271
272 if (inst->base_mrf >= 0)
273 payload = brw_message_reg(inst->base_mrf);
274
275 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
276 * move, here's g1.
277 */
278 if (inst->header_size != 0) {
279 brw_push_insn_state(p);
280 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
281 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
282 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
283 brw_set_default_flag_reg(p, 0, 0);
284
285 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
286 * present.
287 */
288 if (prog_data->uses_kill) {
289 struct brw_reg pixel_mask;
290
291 if (devinfo->gen >= 6)
292 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
293 else
294 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
295
296 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
297 }
298
299 if (devinfo->gen >= 6) {
300 brw_push_insn_state(p);
301 brw_set_default_exec_size(p, BRW_EXECUTE_16);
302 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
303 brw_MOV(p,
304 retype(payload, BRW_REGISTER_TYPE_UD),
305 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
306 brw_pop_insn_state(p);
307
308 if (inst->target > 0 && key->replicate_alpha) {
309 /* Set "Source0 Alpha Present to RenderTarget" bit in message
310 * header.
311 */
312 brw_OR(p,
313 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
314 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
315 brw_imm_ud(0x1 << 11));
316 }
317
318 if (inst->target > 0) {
319 /* Set the render target index for choosing BLEND_STATE. */
320 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
321 BRW_REGISTER_TYPE_UD),
322 brw_imm_ud(inst->target));
323 }
324
325 /* Set computes stencil to render target */
326 if (prog_data->computed_stencil) {
327 brw_OR(p,
328 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
329 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
330 brw_imm_ud(0x1 << 14));
331 }
332
333 implied_header = brw_null_reg();
334 } else {
335 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
336 }
337
338 brw_pop_insn_state(p);
339 } else {
340 implied_header = brw_null_reg();
341 }
342
343 if (!runtime_check_aads_emit) {
344 fire_fb_write(inst, payload, implied_header, inst->mlen);
345 } else {
346 /* This can only happen in gen < 6 */
347 assert(devinfo->gen < 6);
348
349 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
350
351 /* Check runtime bit to detect if we have to send AA data or not */
352 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
353 brw_AND(p,
354 v1_null_ud,
355 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
356 brw_imm_ud(1<<26));
357 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
358
359 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
360 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
361 {
362 /* Don't send AA data */
363 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
364 }
365 brw_land_fwd_jump(p, jmp);
366 fire_fb_write(inst, payload, implied_header, inst->mlen);
367 }
368 }
369
370 void
371 fs_generator::generate_urb_read(fs_inst *inst,
372 struct brw_reg dst,
373 struct brw_reg header)
374 {
375 assert(header.file == BRW_GENERAL_REGISTER_FILE);
376 assert(header.type == BRW_REGISTER_TYPE_UD);
377
378 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
379 brw_set_dest(p, send, dst);
380 brw_set_src0(p, send, header);
381 brw_set_src1(p, send, brw_imm_ud(0u));
382
383 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
384 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
385
386 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
387 brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
388 brw_inst_set_header_present(p->devinfo, send, true);
389 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
390 }
391
392 void
393 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
394 {
395 brw_inst *insn;
396
397 insn = brw_next_insn(p, BRW_OPCODE_SEND);
398
399 brw_set_dest(p, insn, brw_null_reg());
400 brw_set_src0(p, insn, payload);
401 brw_set_src1(p, insn, brw_imm_d(0));
402
403 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
404 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
405
406 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
407 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
408 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
409
410 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
411 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
412 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
413
414 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
415 brw_inst_set_rlen(p->devinfo, insn, 0);
416 brw_inst_set_eot(p->devinfo, insn, inst->eot);
417 brw_inst_set_header_present(p->devinfo, insn, true);
418 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
419 }
420
421 void
422 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
423 {
424 struct brw_inst *insn;
425
426 insn = brw_next_insn(p, BRW_OPCODE_SEND);
427
428 brw_set_dest(p, insn, brw_null_reg());
429 brw_set_src0(p, insn, payload);
430 brw_set_src1(p, insn, brw_imm_d(0));
431
432 /* Terminate a compute shader by sending a message to the thread spawner.
433 */
434 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
435 brw_inst_set_mlen(devinfo, insn, 1);
436 brw_inst_set_rlen(devinfo, insn, 0);
437 brw_inst_set_eot(devinfo, insn, inst->eot);
438 brw_inst_set_header_present(devinfo, insn, false);
439
440 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
441 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
442
443 /* Note that even though the thread has a URB resource associated with it,
444 * we set the "do not dereference URB" bit, because the URB resource is
445 * managed by the fixed-function unit, so it will free it automatically.
446 */
447 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
448
449 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
450 }
451
452 void
453 fs_generator::generate_stencil_ref_packing(fs_inst *inst,
454 struct brw_reg dst,
455 struct brw_reg src)
456 {
457 assert(dispatch_width == 8);
458 assert(devinfo->gen >= 9);
459
460 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
461 * Presumably, in order to save memory bandwidth, the stencil reference
462 * values written from the FS need to be packed into 2 dwords (this makes
463 * sense because the stencil values are limited to 1 byte each and a SIMD8
464 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
465 *
466 * The spec is confusing here because in the payload definition of MDP_RTW_S8
467 * (Message Data Payload for Render Target Writes with Stencil 8b) the
468 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
469 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
470 * packed values specified above and diagrammed below:
471 *
472 * 31 0
473 * --------------------------------
474 * DW | |
475 * 2-7 | IGNORED |
476 * | |
477 * --------------------------------
478 * DW1 | STC | STC | STC | STC |
479 * | slot7 | slot6 | slot5 | slot4|
480 * --------------------------------
481 * DW0 | STC | STC | STC | STC |
482 * | slot3 | slot2 | slot1 | slot0|
483 * --------------------------------
484 */
485
486 src.vstride = BRW_VERTICAL_STRIDE_4;
487 src.width = BRW_WIDTH_1;
488 src.hstride = BRW_HORIZONTAL_STRIDE_0;
489 assert(src.type == BRW_REGISTER_TYPE_UB);
490 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UB), src);
491 }
492
493 void
494 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
495 {
496 brw_barrier(p, src);
497 brw_WAIT(p);
498 }
499
500 void
501 fs_generator::generate_blorp_fb_write(fs_inst *inst)
502 {
503 brw_fb_WRITE(p,
504 16 /* dispatch_width */,
505 brw_message_reg(inst->base_mrf),
506 brw_reg_from_fs_reg(inst, &inst->src[0], devinfo->gen),
507 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
508 inst->target,
509 inst->mlen,
510 0,
511 true,
512 true,
513 inst->header_size != 0);
514 }
515
516 void
517 fs_generator::generate_linterp(fs_inst *inst,
518 struct brw_reg dst, struct brw_reg *src)
519 {
520 /* PLN reads:
521 * / in SIMD16 \
522 * -----------------------------------
523 * | src1+0 | src1+1 | src1+2 | src1+3 |
524 * |-----------------------------------|
525 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
526 * -----------------------------------
527 *
528 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
529 *
530 * -----------------------------------
531 * | src1+0 | src1+1 | src1+2 | src1+3 |
532 * |-----------------------------------|
533 * |(x0, x1)|(y0, y1)| | | in SIMD8
534 * |-----------------------------------|
535 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
536 * -----------------------------------
537 *
538 * See also: emit_interpolation_setup_gen4().
539 */
540 struct brw_reg delta_x = src[0];
541 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
542 struct brw_reg interp = src[1];
543
544 if (devinfo->has_pln &&
545 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
546 brw_PLN(p, dst, interp, delta_x);
547 } else {
548 brw_LINE(p, brw_null_reg(), interp, delta_x);
549 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
550 }
551 }
552
553 void
554 fs_generator::generate_math_gen6(fs_inst *inst,
555 struct brw_reg dst,
556 struct brw_reg src0,
557 struct brw_reg src1)
558 {
559 int op = brw_math_function(inst->opcode);
560 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
561
562 if (dispatch_width == 8) {
563 gen6_math(p, dst, op, src0, src1);
564 } else if (dispatch_width == 16) {
565 brw_push_insn_state(p);
566 brw_set_default_exec_size(p, BRW_EXECUTE_8);
567 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
568 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
569 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
570 gen6_math(p, sechalf(dst), op, sechalf(src0),
571 binop ? sechalf(src1) : brw_null_reg());
572 brw_pop_insn_state(p);
573 }
574 }
575
576 void
577 fs_generator::generate_math_gen4(fs_inst *inst,
578 struct brw_reg dst,
579 struct brw_reg src)
580 {
581 int op = brw_math_function(inst->opcode);
582
583 assert(inst->mlen >= 1);
584
585 if (dispatch_width == 8) {
586 gen4_math(p, dst,
587 op,
588 inst->base_mrf, src,
589 BRW_MATH_PRECISION_FULL);
590 } else if (dispatch_width == 16) {
591 brw_set_default_exec_size(p, BRW_EXECUTE_8);
592 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
593 gen4_math(p, firsthalf(dst),
594 op,
595 inst->base_mrf, firsthalf(src),
596 BRW_MATH_PRECISION_FULL);
597 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
598 gen4_math(p, sechalf(dst),
599 op,
600 inst->base_mrf + 1, sechalf(src),
601 BRW_MATH_PRECISION_FULL);
602
603 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
604 }
605 }
606
607 void
608 fs_generator::generate_math_g45(fs_inst *inst,
609 struct brw_reg dst,
610 struct brw_reg src)
611 {
612 if (inst->opcode == SHADER_OPCODE_POW ||
613 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
614 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
615 generate_math_gen4(inst, dst, src);
616 return;
617 }
618
619 int op = brw_math_function(inst->opcode);
620
621 assert(inst->mlen >= 1);
622
623 gen4_math(p, dst,
624 op,
625 inst->base_mrf, src,
626 BRW_MATH_PRECISION_FULL);
627 }
628
629 void
630 fs_generator::generate_get_buffer_size(fs_inst *inst,
631 struct brw_reg dst,
632 struct brw_reg src,
633 struct brw_reg surf_index)
634 {
635 assert(devinfo->gen >= 7);
636 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
637
638 uint32_t simd_mode;
639 int rlen = 4;
640
641 switch (inst->exec_size) {
642 case 8:
643 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
644 break;
645 case 16:
646 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
647 break;
648 default:
649 unreachable("Invalid width for texture instruction");
650 }
651
652 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
653 rlen = 8;
654 dst = vec16(dst);
655 }
656
657 brw_SAMPLE(p,
658 retype(dst, BRW_REGISTER_TYPE_UW),
659 inst->base_mrf,
660 src,
661 surf_index.dw1.ud,
662 0,
663 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
664 rlen, /* response length */
665 inst->mlen,
666 inst->header_size > 0,
667 simd_mode,
668 BRW_SAMPLER_RETURN_FORMAT_SINT32);
669 }
670
671 void
672 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
673 struct brw_reg sampler_index)
674 {
675 int msg_type = -1;
676 int rlen = 4;
677 uint32_t simd_mode;
678 uint32_t return_format;
679 bool is_combined_send = inst->eot;
680
681 switch (dst.type) {
682 case BRW_REGISTER_TYPE_D:
683 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
684 break;
685 case BRW_REGISTER_TYPE_UD:
686 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
687 break;
688 default:
689 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
690 break;
691 }
692
693 switch (inst->exec_size) {
694 case 8:
695 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
696 break;
697 case 16:
698 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
699 break;
700 default:
701 unreachable("Invalid width for texture instruction");
702 }
703
704 if (devinfo->gen >= 5) {
705 switch (inst->opcode) {
706 case SHADER_OPCODE_TEX:
707 if (inst->shadow_compare) {
708 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
709 } else {
710 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
711 }
712 break;
713 case FS_OPCODE_TXB:
714 if (inst->shadow_compare) {
715 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
716 } else {
717 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
718 }
719 break;
720 case SHADER_OPCODE_TXL:
721 if (inst->shadow_compare) {
722 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
723 } else {
724 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
725 }
726 break;
727 case SHADER_OPCODE_TXS:
728 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
729 break;
730 case SHADER_OPCODE_TXD:
731 if (inst->shadow_compare) {
732 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
733 assert(devinfo->gen >= 8 || devinfo->is_haswell);
734 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
735 } else {
736 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
737 }
738 break;
739 case SHADER_OPCODE_TXF:
740 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
741 break;
742 case SHADER_OPCODE_TXF_CMS_W:
743 assert(devinfo->gen >= 9);
744 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
745 break;
746 case SHADER_OPCODE_TXF_CMS:
747 if (devinfo->gen >= 7)
748 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
749 else
750 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
751 break;
752 case SHADER_OPCODE_TXF_UMS:
753 assert(devinfo->gen >= 7);
754 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
755 break;
756 case SHADER_OPCODE_TXF_MCS:
757 assert(devinfo->gen >= 7);
758 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
759 break;
760 case SHADER_OPCODE_LOD:
761 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
762 break;
763 case SHADER_OPCODE_TG4:
764 if (inst->shadow_compare) {
765 assert(devinfo->gen >= 7);
766 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
767 } else {
768 assert(devinfo->gen >= 6);
769 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
770 }
771 break;
772 case SHADER_OPCODE_TG4_OFFSET:
773 assert(devinfo->gen >= 7);
774 if (inst->shadow_compare) {
775 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
776 } else {
777 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
778 }
779 break;
780 case SHADER_OPCODE_SAMPLEINFO:
781 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
782 break;
783 default:
784 unreachable("not reached");
785 }
786 } else {
787 switch (inst->opcode) {
788 case SHADER_OPCODE_TEX:
789 /* Note that G45 and older determines shadow compare and dispatch width
790 * from message length for most messages.
791 */
792 if (inst->exec_size == 8) {
793 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
794 if (inst->shadow_compare) {
795 assert(inst->mlen == 6);
796 } else {
797 assert(inst->mlen <= 4);
798 }
799 } else {
800 if (inst->shadow_compare) {
801 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
802 assert(inst->mlen == 9);
803 } else {
804 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
805 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
806 }
807 }
808 break;
809 case FS_OPCODE_TXB:
810 if (inst->shadow_compare) {
811 assert(inst->exec_size == 8);
812 assert(inst->mlen == 6);
813 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
814 } else {
815 assert(inst->mlen == 9);
816 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
817 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
818 }
819 break;
820 case SHADER_OPCODE_TXL:
821 if (inst->shadow_compare) {
822 assert(inst->exec_size == 8);
823 assert(inst->mlen == 6);
824 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
825 } else {
826 assert(inst->mlen == 9);
827 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
828 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
829 }
830 break;
831 case SHADER_OPCODE_TXD:
832 /* There is no sample_d_c message; comparisons are done manually */
833 assert(inst->exec_size == 8);
834 assert(inst->mlen == 7 || inst->mlen == 10);
835 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
836 break;
837 case SHADER_OPCODE_TXF:
838 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
839 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
840 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
841 break;
842 case SHADER_OPCODE_TXS:
843 assert(inst->mlen == 3);
844 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
845 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
846 break;
847 default:
848 unreachable("not reached");
849 }
850 }
851 assert(msg_type != -1);
852
853 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
854 rlen = 8;
855 dst = vec16(dst);
856 }
857
858 if (is_combined_send) {
859 assert(devinfo->gen >= 9 || devinfo->is_cherryview);
860 rlen = 0;
861 }
862
863 assert(devinfo->gen < 7 || inst->header_size == 0 ||
864 src.file == BRW_GENERAL_REGISTER_FILE);
865
866 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
867
868 /* Load the message header if present. If there's a texture offset,
869 * we need to set it up explicitly and load the offset bitfield.
870 * Otherwise, we can use an implied move from g0 to the first message reg.
871 */
872 if (inst->header_size != 0) {
873 if (devinfo->gen < 6 && !inst->offset) {
874 /* Set up an implied move from g0 to the MRF. */
875 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
876 } else {
877 struct brw_reg header_reg;
878
879 if (devinfo->gen >= 7) {
880 header_reg = src;
881 } else {
882 assert(inst->base_mrf != -1);
883 header_reg = brw_message_reg(inst->base_mrf);
884 }
885
886 brw_push_insn_state(p);
887 brw_set_default_exec_size(p, BRW_EXECUTE_8);
888 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
889 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
890 /* Explicitly set up the message header by copying g0 to the MRF. */
891 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
892
893 if (inst->offset) {
894 /* Set the offset bits in DWord 2. */
895 brw_MOV(p, get_element_ud(header_reg, 2),
896 brw_imm_ud(inst->offset));
897 }
898
899 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
900 brw_pop_insn_state(p);
901 }
902 }
903
904 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
905 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
906 ? prog_data->binding_table.gather_texture_start
907 : prog_data->binding_table.texture_start;
908
909 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
910 uint32_t sampler = sampler_index.dw1.ud;
911
912 brw_SAMPLE(p,
913 retype(dst, BRW_REGISTER_TYPE_UW),
914 inst->base_mrf,
915 src,
916 sampler + base_binding_table_index,
917 sampler % 16,
918 msg_type,
919 rlen,
920 inst->mlen,
921 inst->header_size != 0,
922 simd_mode,
923 return_format);
924
925 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
926 } else {
927 /* Non-const sampler index */
928
929 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
930 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
931
932 brw_push_insn_state(p);
933 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
934 brw_set_default_access_mode(p, BRW_ALIGN_1);
935
936 /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
937 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
938 if (base_binding_table_index)
939 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
940 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
941
942 brw_pop_insn_state(p);
943
944 /* dst = send(offset, a0.0 | <descriptor>) */
945 brw_inst *insn = brw_send_indirect_message(
946 p, BRW_SFID_SAMPLER, dst, src, addr);
947 brw_set_sampler_message(p, insn,
948 0 /* surface */,
949 0 /* sampler */,
950 msg_type,
951 rlen,
952 inst->mlen /* mlen */,
953 inst->header_size != 0 /* header */,
954 simd_mode,
955 return_format);
956
957 /* visitor knows more than we do about the surface limit required,
958 * so has already done marking.
959 */
960 }
961
962 if (is_combined_send) {
963 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
964 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
965 }
966 }
967
968
969 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
970 * looking like:
971 *
972 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
973 *
974 * Ideally, we want to produce:
975 *
976 * DDX DDY
977 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
978 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
979 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
980 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
981 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
982 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
983 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
984 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
985 *
986 * and add another set of two more subspans if in 16-pixel dispatch mode.
987 *
988 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
989 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
990 * pair. But the ideal approximation may impose a huge performance cost on
991 * sample_d. On at least Haswell, sample_d instruction does some
992 * optimizations if the same LOD is used for all pixels in the subspan.
993 *
994 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
995 * appropriate swizzling.
996 */
997 void
998 fs_generator::generate_ddx(enum opcode opcode,
999 struct brw_reg dst, struct brw_reg src)
1000 {
1001 unsigned vstride, width;
1002
1003 if (opcode == FS_OPCODE_DDX_FINE) {
1004 /* produce accurate derivatives */
1005 vstride = BRW_VERTICAL_STRIDE_2;
1006 width = BRW_WIDTH_2;
1007 } else {
1008 /* replicate the derivative at the top-left pixel to other pixels */
1009 vstride = BRW_VERTICAL_STRIDE_4;
1010 width = BRW_WIDTH_4;
1011 }
1012
1013 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
1014 src.negate, src.abs,
1015 BRW_REGISTER_TYPE_F,
1016 vstride,
1017 width,
1018 BRW_HORIZONTAL_STRIDE_0,
1019 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1020 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1021 src.negate, src.abs,
1022 BRW_REGISTER_TYPE_F,
1023 vstride,
1024 width,
1025 BRW_HORIZONTAL_STRIDE_0,
1026 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1027 brw_ADD(p, dst, src0, negate(src1));
1028 }
1029
1030 /* The negate_value boolean is used to negate the derivative computation for
1031 * FBOs, since they place the origin at the upper left instead of the lower
1032 * left.
1033 */
1034 void
1035 fs_generator::generate_ddy(enum opcode opcode,
1036 struct brw_reg dst, struct brw_reg src,
1037 bool negate_value)
1038 {
1039 if (opcode == FS_OPCODE_DDY_FINE) {
1040 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1041 * Region Restrictions):
1042 *
1043 * In Align16 access mode, SIMD16 is not allowed for DW operations
1044 * and SIMD8 is not allowed for DF operations.
1045 *
1046 * In this context, "DW operations" means "operations acting on 32-bit
1047 * values", so it includes operations on floats.
1048 *
1049 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1050 * (Instruction Compression -> Rules and Restrictions):
1051 *
1052 * A compressed instruction must be in Align1 access mode. Align16
1053 * mode instructions cannot be compressed.
1054 *
1055 * Similar text exists in the g45 PRM.
1056 *
1057 * On these platforms, if we're building a SIMD16 shader, we need to
1058 * manually unroll to a pair of SIMD8 instructions.
1059 */
1060 bool unroll_to_simd8 =
1061 (dispatch_width == 16 &&
1062 (devinfo->gen == 4 || (devinfo->gen == 7 && !devinfo->is_haswell)));
1063
1064 /* produce accurate derivatives */
1065 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1066 src.negate, src.abs,
1067 BRW_REGISTER_TYPE_F,
1068 BRW_VERTICAL_STRIDE_4,
1069 BRW_WIDTH_4,
1070 BRW_HORIZONTAL_STRIDE_1,
1071 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
1072 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1073 src.negate, src.abs,
1074 BRW_REGISTER_TYPE_F,
1075 BRW_VERTICAL_STRIDE_4,
1076 BRW_WIDTH_4,
1077 BRW_HORIZONTAL_STRIDE_1,
1078 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
1079 brw_push_insn_state(p);
1080 brw_set_default_access_mode(p, BRW_ALIGN_16);
1081 if (unroll_to_simd8) {
1082 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1083 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1084 if (negate_value) {
1085 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
1086 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1087 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
1088 } else {
1089 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
1090 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1091 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
1092 }
1093 } else {
1094 if (negate_value)
1095 brw_ADD(p, dst, src1, negate(src0));
1096 else
1097 brw_ADD(p, dst, src0, negate(src1));
1098 }
1099 brw_pop_insn_state(p);
1100 } else {
1101 /* replicate the derivative at the top-left pixel to other pixels */
1102 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1103 src.negate, src.abs,
1104 BRW_REGISTER_TYPE_F,
1105 BRW_VERTICAL_STRIDE_4,
1106 BRW_WIDTH_4,
1107 BRW_HORIZONTAL_STRIDE_0,
1108 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1109 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1110 src.negate, src.abs,
1111 BRW_REGISTER_TYPE_F,
1112 BRW_VERTICAL_STRIDE_4,
1113 BRW_WIDTH_4,
1114 BRW_HORIZONTAL_STRIDE_0,
1115 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1116 if (negate_value)
1117 brw_ADD(p, dst, src1, negate(src0));
1118 else
1119 brw_ADD(p, dst, src0, negate(src1));
1120 }
1121 }
1122
1123 void
1124 fs_generator::generate_discard_jump(fs_inst *inst)
1125 {
1126 assert(devinfo->gen >= 6);
1127
1128 /* This HALT will be patched up at FB write time to point UIP at the end of
1129 * the program, and at brw_uip_jip() JIP will be set to the end of the
1130 * current block (or the program).
1131 */
1132 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1133
1134 brw_push_insn_state(p);
1135 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1136 gen6_HALT(p);
1137 brw_pop_insn_state(p);
1138 }
1139
1140 void
1141 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1142 {
1143 assert(inst->mlen != 0);
1144
1145 brw_MOV(p,
1146 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1147 retype(src, BRW_REGISTER_TYPE_UD));
1148 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1149 inst->exec_size / 8, inst->offset);
1150 }
1151
1152 void
1153 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1154 {
1155 assert(inst->mlen != 0);
1156
1157 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1158 inst->exec_size / 8, inst->offset);
1159 }
1160
1161 void
1162 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1163 {
1164 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1165 }
1166
1167 void
1168 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1169 struct brw_reg dst,
1170 struct brw_reg index,
1171 struct brw_reg offset)
1172 {
1173 assert(inst->mlen != 0);
1174
1175 assert(index.file == BRW_IMMEDIATE_VALUE &&
1176 index.type == BRW_REGISTER_TYPE_UD);
1177 uint32_t surf_index = index.dw1.ud;
1178
1179 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1180 offset.type == BRW_REGISTER_TYPE_UD);
1181 uint32_t read_offset = offset.dw1.ud;
1182
1183 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1184 read_offset, surf_index);
1185 }
1186
1187 void
1188 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1189 struct brw_reg dst,
1190 struct brw_reg index,
1191 struct brw_reg offset)
1192 {
1193 assert(index.type == BRW_REGISTER_TYPE_UD);
1194
1195 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1196 /* Reference just the dword we need, to avoid angering validate_reg(). */
1197 offset = brw_vec1_grf(offset.nr, 0);
1198
1199 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1200 * the destination loaded consecutively from the same offset (which appears
1201 * in the first component, and the rest are ignored).
1202 */
1203 dst.width = BRW_WIDTH_4;
1204
1205 struct brw_reg src = offset;
1206 bool header_present = false;
1207
1208 if (devinfo->gen >= 9) {
1209 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1210 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1211 header_present = true;
1212
1213 brw_push_insn_state(p);
1214 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1215 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1216 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1217 brw_set_default_access_mode(p, BRW_ALIGN_1);
1218
1219 brw_MOV(p, get_element_ud(src, 2),
1220 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1221 brw_pop_insn_state(p);
1222 }
1223
1224 if (index.file == BRW_IMMEDIATE_VALUE) {
1225
1226 uint32_t surf_index = index.dw1.ud;
1227
1228 brw_push_insn_state(p);
1229 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1230 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1231 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1232 brw_pop_insn_state(p);
1233
1234 brw_set_dest(p, send, dst);
1235 brw_set_src0(p, send, src);
1236 brw_set_sampler_message(p, send,
1237 surf_index,
1238 0, /* LD message ignores sampler unit */
1239 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1240 1, /* rlen */
1241 inst->mlen,
1242 header_present,
1243 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1244 0);
1245 } else {
1246
1247 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1248
1249 brw_push_insn_state(p);
1250 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1251 brw_set_default_access_mode(p, BRW_ALIGN_1);
1252
1253 /* a0.0 = surf_index & 0xff */
1254 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1255 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1256 brw_set_dest(p, insn_and, addr);
1257 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1258 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1259
1260 /* dst = send(payload, a0.0 | <descriptor>) */
1261 brw_inst *insn = brw_send_indirect_message(
1262 p, BRW_SFID_SAMPLER, dst, src, addr);
1263 brw_set_sampler_message(p, insn,
1264 0,
1265 0, /* LD message ignores sampler unit */
1266 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1267 1, /* rlen */
1268 inst->mlen,
1269 header_present,
1270 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1271 0);
1272
1273 brw_pop_insn_state(p);
1274 }
1275 }
1276
1277 void
1278 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1279 struct brw_reg dst,
1280 struct brw_reg index,
1281 struct brw_reg offset)
1282 {
1283 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1284 assert(inst->header_size != 0);
1285 assert(inst->mlen);
1286
1287 assert(index.file == BRW_IMMEDIATE_VALUE &&
1288 index.type == BRW_REGISTER_TYPE_UD);
1289 uint32_t surf_index = index.dw1.ud;
1290
1291 uint32_t simd_mode, rlen, msg_type;
1292 if (dispatch_width == 16) {
1293 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1294 rlen = 8;
1295 } else {
1296 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1297 rlen = 4;
1298 }
1299
1300 if (devinfo->gen >= 5)
1301 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1302 else {
1303 /* We always use the SIMD16 message so that we only have to load U, and
1304 * not V or R.
1305 */
1306 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1307 assert(inst->mlen == 3);
1308 assert(inst->regs_written == 8);
1309 rlen = 8;
1310 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1311 }
1312
1313 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1314 BRW_REGISTER_TYPE_D);
1315 brw_MOV(p, offset_mrf, offset);
1316
1317 struct brw_reg header = brw_vec8_grf(0, 0);
1318 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1319
1320 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1321 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1322 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1323 brw_set_src0(p, send, header);
1324 if (devinfo->gen < 6)
1325 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1326
1327 /* Our surface is set up as floats, regardless of what actual data is
1328 * stored in it.
1329 */
1330 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1331 brw_set_sampler_message(p, send,
1332 surf_index,
1333 0, /* sampler (unused) */
1334 msg_type,
1335 rlen,
1336 inst->mlen,
1337 inst->header_size != 0,
1338 simd_mode,
1339 return_format);
1340 }
1341
1342 void
1343 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1344 struct brw_reg dst,
1345 struct brw_reg index,
1346 struct brw_reg offset)
1347 {
1348 assert(devinfo->gen >= 7);
1349 /* Varying-offset pull constant loads are treated as a normal expression on
1350 * gen7, so the fact that it's a send message is hidden at the IR level.
1351 */
1352 assert(inst->header_size == 0);
1353 assert(!inst->mlen);
1354 assert(index.type == BRW_REGISTER_TYPE_UD);
1355
1356 uint32_t simd_mode, rlen, mlen;
1357 if (dispatch_width == 16) {
1358 mlen = 2;
1359 rlen = 8;
1360 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1361 } else {
1362 mlen = 1;
1363 rlen = 4;
1364 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1365 }
1366
1367 if (index.file == BRW_IMMEDIATE_VALUE) {
1368
1369 uint32_t surf_index = index.dw1.ud;
1370
1371 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1372 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1373 brw_set_src0(p, send, offset);
1374 brw_set_sampler_message(p, send,
1375 surf_index,
1376 0, /* LD message ignores sampler unit */
1377 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1378 rlen,
1379 mlen,
1380 false, /* no header */
1381 simd_mode,
1382 0);
1383
1384 } else {
1385
1386 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1387
1388 brw_push_insn_state(p);
1389 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1390 brw_set_default_access_mode(p, BRW_ALIGN_1);
1391
1392 /* a0.0 = surf_index & 0xff */
1393 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1394 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1395 brw_set_dest(p, insn_and, addr);
1396 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1397 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1398
1399 brw_pop_insn_state(p);
1400
1401 /* dst = send(offset, a0.0 | <descriptor>) */
1402 brw_inst *insn = brw_send_indirect_message(
1403 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1404 offset, addr);
1405 brw_set_sampler_message(p, insn,
1406 0 /* surface */,
1407 0 /* sampler */,
1408 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1409 rlen /* rlen */,
1410 mlen /* mlen */,
1411 false /* header */,
1412 simd_mode,
1413 0);
1414 }
1415 }
1416
1417 /**
1418 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1419 * into the flags register (f0.0).
1420 *
1421 * Used only on Gen6 and above.
1422 */
1423 void
1424 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1425 {
1426 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1427 struct brw_reg dispatch_mask;
1428
1429 if (devinfo->gen >= 6)
1430 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1431 else
1432 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1433
1434 brw_push_insn_state(p);
1435 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1436 brw_MOV(p, flags, dispatch_mask);
1437 brw_pop_insn_state(p);
1438 }
1439
1440 void
1441 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1442 struct brw_reg dst,
1443 struct brw_reg src,
1444 struct brw_reg msg_data,
1445 unsigned msg_type)
1446 {
1447 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1448
1449 brw_pixel_interpolator_query(p,
1450 retype(dst, BRW_REGISTER_TYPE_UW),
1451 src,
1452 inst->pi_noperspective,
1453 msg_type,
1454 msg_data,
1455 inst->mlen,
1456 inst->regs_written);
1457 }
1458
1459
1460 /**
1461 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1462 * sampler LD messages.
1463 *
1464 * We don't want to bake it into the send message's code generation because
1465 * that means we don't get a chance to schedule the instructions.
1466 */
1467 void
1468 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1469 struct brw_reg dst,
1470 struct brw_reg value)
1471 {
1472 assert(value.file == BRW_IMMEDIATE_VALUE);
1473
1474 brw_push_insn_state(p);
1475 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1476 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1477 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1478 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1479 brw_pop_insn_state(p);
1480 }
1481
1482 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1483 * the ADD instruction.
1484 */
1485 void
1486 fs_generator::generate_set_sample_id(fs_inst *inst,
1487 struct brw_reg dst,
1488 struct brw_reg src0,
1489 struct brw_reg src1)
1490 {
1491 assert(dst.type == BRW_REGISTER_TYPE_D ||
1492 dst.type == BRW_REGISTER_TYPE_UD);
1493 assert(src0.type == BRW_REGISTER_TYPE_D ||
1494 src0.type == BRW_REGISTER_TYPE_UD);
1495
1496 struct brw_reg reg = stride(src1, 1, 4, 0);
1497 if (devinfo->gen >= 8 || dispatch_width == 8) {
1498 brw_ADD(p, dst, src0, reg);
1499 } else if (dispatch_width == 16) {
1500 brw_push_insn_state(p);
1501 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1502 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1503 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1504 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1505 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1506 brw_pop_insn_state(p);
1507 }
1508 }
1509
1510 void
1511 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1512 struct brw_reg dst,
1513 struct brw_reg x,
1514 struct brw_reg y)
1515 {
1516 assert(devinfo->gen >= 7);
1517 assert(dst.type == BRW_REGISTER_TYPE_UD);
1518 assert(x.type == BRW_REGISTER_TYPE_F);
1519 assert(y.type == BRW_REGISTER_TYPE_F);
1520
1521 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1522 *
1523 * Because this instruction does not have a 16-bit floating-point type,
1524 * the destination data type must be Word (W).
1525 *
1526 * The destination must be DWord-aligned and specify a horizontal stride
1527 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1528 * each destination channel and the upper word is not modified.
1529 */
1530 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1531
1532 /* Give each 32-bit channel of dst the form below, where "." means
1533 * unchanged.
1534 * 0x....hhhh
1535 */
1536 brw_F32TO16(p, dst_w, y);
1537
1538 /* Now the form:
1539 * 0xhhhh0000
1540 */
1541 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1542
1543 /* And, finally the form of packHalf2x16's output:
1544 * 0xhhhhllll
1545 */
1546 brw_F32TO16(p, dst_w, x);
1547 }
1548
1549 void
1550 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1551 struct brw_reg dst,
1552 struct brw_reg src)
1553 {
1554 assert(devinfo->gen >= 7);
1555 assert(dst.type == BRW_REGISTER_TYPE_F);
1556 assert(src.type == BRW_REGISTER_TYPE_UD);
1557
1558 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1559 *
1560 * Because this instruction does not have a 16-bit floating-point type,
1561 * the source data type must be Word (W). The destination type must be
1562 * F (Float).
1563 */
1564 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1565
1566 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1567 * For the Y case, we wish to access only the upper word; therefore
1568 * a 16-bit subregister offset is needed.
1569 */
1570 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1571 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1572 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1573 src_w.subnr += 2;
1574
1575 brw_F16TO32(p, dst, src_w);
1576 }
1577
1578 void
1579 fs_generator::generate_shader_time_add(fs_inst *inst,
1580 struct brw_reg payload,
1581 struct brw_reg offset,
1582 struct brw_reg value)
1583 {
1584 assert(devinfo->gen >= 7);
1585 brw_push_insn_state(p);
1586 brw_set_default_mask_control(p, true);
1587
1588 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1589 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1590 offset.type);
1591 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1592 value.type);
1593
1594 assert(offset.file == BRW_IMMEDIATE_VALUE);
1595 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1596 value.width = BRW_WIDTH_1;
1597 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1598 value.vstride = BRW_VERTICAL_STRIDE_0;
1599 } else {
1600 assert(value.file == BRW_IMMEDIATE_VALUE);
1601 }
1602
1603 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1604 * case, and we don't really care about squeezing every bit of performance
1605 * out of this path, so we just emit the MOVs from here.
1606 */
1607 brw_MOV(p, payload_offset, offset);
1608 brw_MOV(p, payload_value, value);
1609 brw_shader_time_add(p, payload,
1610 prog_data->binding_table.shader_time_start);
1611 brw_pop_insn_state(p);
1612
1613 brw_mark_surface_used(prog_data,
1614 prog_data->binding_table.shader_time_start);
1615 }
1616
1617 void
1618 fs_generator::enable_debug(const char *shader_name)
1619 {
1620 debug_flag = true;
1621 this->shader_name = shader_name;
1622 }
1623
1624 int
1625 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1626 {
1627 /* align to 64 byte boundary. */
1628 while (p->next_insn_offset % 64)
1629 brw_NOP(p);
1630
1631 this->dispatch_width = dispatch_width;
1632 if (dispatch_width == 16)
1633 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1634
1635 int start_offset = p->next_insn_offset;
1636 int spill_count = 0, fill_count = 0;
1637 int loop_count = 0;
1638
1639 struct annotation_info annotation;
1640 memset(&annotation, 0, sizeof(annotation));
1641
1642 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1643 struct brw_reg src[3], dst;
1644 unsigned int last_insn_offset = p->next_insn_offset;
1645 bool multiple_instructions_emitted = false;
1646
1647 if (unlikely(debug_flag))
1648 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1649
1650 for (unsigned int i = 0; i < inst->sources; i++) {
1651 src[i] = brw_reg_from_fs_reg(inst, &inst->src[i], devinfo->gen);
1652
1653 /* The accumulator result appears to get used for the
1654 * conditional modifier generation. When negating a UD
1655 * value, there is a 33rd bit generated for the sign in the
1656 * accumulator value, so now you can't check, for example,
1657 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1658 */
1659 assert(!inst->conditional_mod ||
1660 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1661 !inst->src[i].negate);
1662 }
1663 dst = brw_reg_from_fs_reg(inst, &inst->dst, devinfo->gen);
1664
1665 brw_set_default_predicate_control(p, inst->predicate);
1666 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1667 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1668 brw_set_default_saturate(p, inst->saturate);
1669 brw_set_default_mask_control(p, inst->force_writemask_all);
1670 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1671 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1672
1673 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1674 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1675
1676 switch (inst->exec_size) {
1677 case 1:
1678 case 2:
1679 case 4:
1680 assert(inst->force_writemask_all);
1681 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1682 break;
1683 case 8:
1684 if (inst->force_sechalf) {
1685 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1686 } else {
1687 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1688 }
1689 break;
1690 case 16:
1691 case 32:
1692 /* If the instruction writes to more than one register, it needs to
1693 * be a "compressed" instruction on Gen <= 5.
1694 */
1695 if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
1696 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1697 else
1698 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1699 break;
1700 default:
1701 unreachable("Invalid instruction width");
1702 }
1703
1704 switch (inst->opcode) {
1705 case BRW_OPCODE_MOV:
1706 brw_MOV(p, dst, src[0]);
1707 break;
1708 case BRW_OPCODE_ADD:
1709 brw_ADD(p, dst, src[0], src[1]);
1710 break;
1711 case BRW_OPCODE_MUL:
1712 brw_MUL(p, dst, src[0], src[1]);
1713 break;
1714 case BRW_OPCODE_AVG:
1715 brw_AVG(p, dst, src[0], src[1]);
1716 break;
1717 case BRW_OPCODE_MACH:
1718 brw_MACH(p, dst, src[0], src[1]);
1719 break;
1720
1721 case BRW_OPCODE_LINE:
1722 brw_LINE(p, dst, src[0], src[1]);
1723 break;
1724
1725 case BRW_OPCODE_MAD:
1726 assert(devinfo->gen >= 6);
1727 brw_set_default_access_mode(p, BRW_ALIGN_16);
1728 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1729 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1730 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1731 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1732 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1733 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1734 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1735
1736 if (inst->conditional_mod) {
1737 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1738 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1739 multiple_instructions_emitted = true;
1740 }
1741 } else {
1742 brw_MAD(p, dst, src[0], src[1], src[2]);
1743 }
1744 brw_set_default_access_mode(p, BRW_ALIGN_1);
1745 break;
1746
1747 case BRW_OPCODE_LRP:
1748 assert(devinfo->gen >= 6);
1749 brw_set_default_access_mode(p, BRW_ALIGN_16);
1750 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1751 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1752 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1753 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1754 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1755 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1756 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1757
1758 if (inst->conditional_mod) {
1759 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1760 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1761 multiple_instructions_emitted = true;
1762 }
1763 } else {
1764 brw_LRP(p, dst, src[0], src[1], src[2]);
1765 }
1766 brw_set_default_access_mode(p, BRW_ALIGN_1);
1767 break;
1768
1769 case BRW_OPCODE_FRC:
1770 brw_FRC(p, dst, src[0]);
1771 break;
1772 case BRW_OPCODE_RNDD:
1773 brw_RNDD(p, dst, src[0]);
1774 break;
1775 case BRW_OPCODE_RNDE:
1776 brw_RNDE(p, dst, src[0]);
1777 break;
1778 case BRW_OPCODE_RNDZ:
1779 brw_RNDZ(p, dst, src[0]);
1780 break;
1781
1782 case BRW_OPCODE_AND:
1783 brw_AND(p, dst, src[0], src[1]);
1784 break;
1785 case BRW_OPCODE_OR:
1786 brw_OR(p, dst, src[0], src[1]);
1787 break;
1788 case BRW_OPCODE_XOR:
1789 brw_XOR(p, dst, src[0], src[1]);
1790 break;
1791 case BRW_OPCODE_NOT:
1792 brw_NOT(p, dst, src[0]);
1793 break;
1794 case BRW_OPCODE_ASR:
1795 brw_ASR(p, dst, src[0], src[1]);
1796 break;
1797 case BRW_OPCODE_SHR:
1798 brw_SHR(p, dst, src[0], src[1]);
1799 break;
1800 case BRW_OPCODE_SHL:
1801 brw_SHL(p, dst, src[0], src[1]);
1802 break;
1803 case BRW_OPCODE_F32TO16:
1804 assert(devinfo->gen >= 7);
1805 brw_F32TO16(p, dst, src[0]);
1806 break;
1807 case BRW_OPCODE_F16TO32:
1808 assert(devinfo->gen >= 7);
1809 brw_F16TO32(p, dst, src[0]);
1810 break;
1811 case BRW_OPCODE_CMP:
1812 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1813 * that when the destination is a GRF that the dependency-clear bit on
1814 * the flag register is cleared early.
1815 *
1816 * Suggested workarounds are to disable coissuing CMP instructions
1817 * or to split CMP(16) instructions into two CMP(8) instructions.
1818 *
1819 * We choose to split into CMP(8) instructions since disabling
1820 * coissuing would affect CMP instructions not otherwise affected by
1821 * the errata.
1822 */
1823 if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) {
1824 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1825 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1826 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1827 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1828 firsthalf(src[0]), firsthalf(src[1]));
1829 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1830 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1831 sechalf(src[0]), sechalf(src[1]));
1832 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1833
1834 multiple_instructions_emitted = true;
1835 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1836 /* For unknown reasons, the aforementioned workaround is not
1837 * sufficient. Overriding the type when the destination is the
1838 * null register is necessary but not sufficient by itself.
1839 */
1840 assert(dst.nr == BRW_ARF_NULL);
1841 dst.type = BRW_REGISTER_TYPE_D;
1842 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1843 } else {
1844 unreachable("not reached");
1845 }
1846 } else {
1847 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1848 }
1849 break;
1850 case BRW_OPCODE_SEL:
1851 brw_SEL(p, dst, src[0], src[1]);
1852 break;
1853 case BRW_OPCODE_BFREV:
1854 assert(devinfo->gen >= 7);
1855 /* BFREV only supports UD type for src and dst. */
1856 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1857 retype(src[0], BRW_REGISTER_TYPE_UD));
1858 break;
1859 case BRW_OPCODE_FBH:
1860 assert(devinfo->gen >= 7);
1861 /* FBH only supports UD type for dst. */
1862 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1863 break;
1864 case BRW_OPCODE_FBL:
1865 assert(devinfo->gen >= 7);
1866 /* FBL only supports UD type for dst. */
1867 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1868 break;
1869 case BRW_OPCODE_CBIT:
1870 assert(devinfo->gen >= 7);
1871 /* CBIT only supports UD type for dst. */
1872 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1873 break;
1874 case BRW_OPCODE_ADDC:
1875 assert(devinfo->gen >= 7);
1876 brw_ADDC(p, dst, src[0], src[1]);
1877 break;
1878 case BRW_OPCODE_SUBB:
1879 assert(devinfo->gen >= 7);
1880 brw_SUBB(p, dst, src[0], src[1]);
1881 break;
1882 case BRW_OPCODE_MAC:
1883 brw_MAC(p, dst, src[0], src[1]);
1884 break;
1885
1886 case BRW_OPCODE_BFE:
1887 assert(devinfo->gen >= 7);
1888 brw_set_default_access_mode(p, BRW_ALIGN_16);
1889 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1890 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1891 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1892 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1893 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1894 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1895 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1896 } else {
1897 brw_BFE(p, dst, src[0], src[1], src[2]);
1898 }
1899 brw_set_default_access_mode(p, BRW_ALIGN_1);
1900 break;
1901
1902 case BRW_OPCODE_BFI1:
1903 assert(devinfo->gen >= 7);
1904 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1905 * should
1906 *
1907 * "Force BFI instructions to be executed always in SIMD8."
1908 */
1909 if (dispatch_width == 16 && devinfo->is_haswell) {
1910 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1911 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1912 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1913 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1914 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1915 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1916 } else {
1917 brw_BFI1(p, dst, src[0], src[1]);
1918 }
1919 break;
1920 case BRW_OPCODE_BFI2:
1921 assert(devinfo->gen >= 7);
1922 brw_set_default_access_mode(p, BRW_ALIGN_16);
1923 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1924 * should
1925 *
1926 * "Force BFI instructions to be executed always in SIMD8."
1927 *
1928 * Otherwise we would be able to emit compressed instructions like we
1929 * do for the other three-source instructions.
1930 */
1931 if (dispatch_width == 16 &&
1932 (devinfo->is_haswell || !devinfo->supports_simd16_3src)) {
1933 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1934 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1935 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1936 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1937 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1938 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1939 } else {
1940 brw_BFI2(p, dst, src[0], src[1], src[2]);
1941 }
1942 brw_set_default_access_mode(p, BRW_ALIGN_1);
1943 break;
1944
1945 case BRW_OPCODE_IF:
1946 if (inst->src[0].file != BAD_FILE) {
1947 /* The instruction has an embedded compare (only allowed on gen6) */
1948 assert(devinfo->gen == 6);
1949 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1950 } else {
1951 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1952 }
1953 break;
1954
1955 case BRW_OPCODE_ELSE:
1956 brw_ELSE(p);
1957 break;
1958 case BRW_OPCODE_ENDIF:
1959 brw_ENDIF(p);
1960 break;
1961
1962 case BRW_OPCODE_DO:
1963 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1964 break;
1965
1966 case BRW_OPCODE_BREAK:
1967 brw_BREAK(p);
1968 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1969 break;
1970 case BRW_OPCODE_CONTINUE:
1971 brw_CONT(p);
1972 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1973 break;
1974
1975 case BRW_OPCODE_WHILE:
1976 brw_WHILE(p);
1977 loop_count++;
1978 break;
1979
1980 case SHADER_OPCODE_RCP:
1981 case SHADER_OPCODE_RSQ:
1982 case SHADER_OPCODE_SQRT:
1983 case SHADER_OPCODE_EXP2:
1984 case SHADER_OPCODE_LOG2:
1985 case SHADER_OPCODE_SIN:
1986 case SHADER_OPCODE_COS:
1987 assert(devinfo->gen < 6 || inst->mlen == 0);
1988 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1989 if (devinfo->gen >= 7) {
1990 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1991 brw_null_reg());
1992 } else if (devinfo->gen == 6) {
1993 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1994 } else if (devinfo->gen == 5 || devinfo->is_g4x) {
1995 generate_math_g45(inst, dst, src[0]);
1996 } else {
1997 generate_math_gen4(inst, dst, src[0]);
1998 }
1999 break;
2000 case SHADER_OPCODE_INT_QUOTIENT:
2001 case SHADER_OPCODE_INT_REMAINDER:
2002 case SHADER_OPCODE_POW:
2003 assert(devinfo->gen < 6 || inst->mlen == 0);
2004 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2005 if (devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
2006 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
2007 } else if (devinfo->gen >= 6) {
2008 generate_math_gen6(inst, dst, src[0], src[1]);
2009 } else {
2010 generate_math_gen4(inst, dst, src[0]);
2011 }
2012 break;
2013 case FS_OPCODE_CINTERP:
2014 brw_MOV(p, dst, src[0]);
2015 break;
2016 case FS_OPCODE_LINTERP:
2017 generate_linterp(inst, dst, src);
2018 break;
2019 case FS_OPCODE_PIXEL_X:
2020 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2021 src[0].subnr = 0 * type_sz(src[0].type);
2022 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2023 break;
2024 case FS_OPCODE_PIXEL_Y:
2025 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2026 src[0].subnr = 4 * type_sz(src[0].type);
2027 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2028 break;
2029 case FS_OPCODE_GET_BUFFER_SIZE:
2030 generate_get_buffer_size(inst, dst, src[0], src[1]);
2031 break;
2032 case SHADER_OPCODE_TEX:
2033 case FS_OPCODE_TXB:
2034 case SHADER_OPCODE_TXD:
2035 case SHADER_OPCODE_TXF:
2036 case SHADER_OPCODE_TXF_CMS:
2037 case SHADER_OPCODE_TXF_CMS_W:
2038 case SHADER_OPCODE_TXF_UMS:
2039 case SHADER_OPCODE_TXF_MCS:
2040 case SHADER_OPCODE_TXL:
2041 case SHADER_OPCODE_TXS:
2042 case SHADER_OPCODE_LOD:
2043 case SHADER_OPCODE_TG4:
2044 case SHADER_OPCODE_TG4_OFFSET:
2045 case SHADER_OPCODE_SAMPLEINFO:
2046 generate_tex(inst, dst, src[0], src[1]);
2047 break;
2048 case FS_OPCODE_DDX_COARSE:
2049 case FS_OPCODE_DDX_FINE:
2050 generate_ddx(inst->opcode, dst, src[0]);
2051 break;
2052 case FS_OPCODE_DDY_COARSE:
2053 case FS_OPCODE_DDY_FINE:
2054 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2055 generate_ddy(inst->opcode, dst, src[0], src[1].dw1.ud);
2056 break;
2057
2058 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
2059 generate_scratch_write(inst, src[0]);
2060 spill_count++;
2061 break;
2062
2063 case SHADER_OPCODE_GEN4_SCRATCH_READ:
2064 generate_scratch_read(inst, dst);
2065 fill_count++;
2066 break;
2067
2068 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2069 generate_scratch_read_gen7(inst, dst);
2070 fill_count++;
2071 break;
2072
2073 case SHADER_OPCODE_URB_READ_SIMD8:
2074 generate_urb_read(inst, dst, src[0]);
2075 break;
2076
2077 case SHADER_OPCODE_URB_WRITE_SIMD8:
2078 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
2079 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
2080 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
2081 generate_urb_write(inst, src[0]);
2082 break;
2083
2084 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2085 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2086 break;
2087
2088 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2089 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2090 break;
2091
2092 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
2093 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
2094 break;
2095
2096 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2097 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2098 break;
2099
2100 case FS_OPCODE_REP_FB_WRITE:
2101 case FS_OPCODE_FB_WRITE:
2102 generate_fb_write(inst, src[0]);
2103 break;
2104
2105 case FS_OPCODE_BLORP_FB_WRITE:
2106 generate_blorp_fb_write(inst);
2107 break;
2108
2109 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2110 generate_mov_dispatch_to_flags(inst);
2111 break;
2112
2113 case FS_OPCODE_DISCARD_JUMP:
2114 generate_discard_jump(inst);
2115 break;
2116
2117 case SHADER_OPCODE_SHADER_TIME_ADD:
2118 generate_shader_time_add(inst, src[0], src[1], src[2]);
2119 break;
2120
2121 case SHADER_OPCODE_UNTYPED_ATOMIC:
2122 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2123 brw_untyped_atomic(p, dst, src[0], src[1], src[2].dw1.ud,
2124 inst->mlen, !inst->dst.is_null());
2125 break;
2126
2127 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2128 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2129 brw_untyped_surface_read(p, dst, src[0], src[1],
2130 inst->mlen, src[2].dw1.ud);
2131 break;
2132
2133 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2134 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2135 brw_untyped_surface_write(p, src[0], src[1],
2136 inst->mlen, src[2].dw1.ud);
2137 break;
2138
2139 case SHADER_OPCODE_TYPED_ATOMIC:
2140 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2141 brw_typed_atomic(p, dst, src[0], src[1],
2142 src[2].dw1.ud, inst->mlen, !inst->dst.is_null());
2143 break;
2144
2145 case SHADER_OPCODE_TYPED_SURFACE_READ:
2146 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2147 brw_typed_surface_read(p, dst, src[0], src[1],
2148 inst->mlen, src[2].dw1.ud);
2149 break;
2150
2151 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2152 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2153 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].dw1.ud);
2154 break;
2155
2156 case SHADER_OPCODE_MEMORY_FENCE:
2157 brw_memory_fence(p, dst);
2158 break;
2159
2160 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2161 generate_set_simd4x2_offset(inst, dst, src[0]);
2162 break;
2163
2164 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
2165 brw_find_live_channel(p, dst);
2166 break;
2167
2168 case SHADER_OPCODE_BROADCAST:
2169 brw_broadcast(p, dst, src[0], src[1]);
2170 break;
2171
2172 case FS_OPCODE_SET_SAMPLE_ID:
2173 generate_set_sample_id(inst, dst, src[0], src[1]);
2174 break;
2175
2176 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2177 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2178 break;
2179
2180 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2181 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2182 generate_unpack_half_2x16_split(inst, dst, src[0]);
2183 break;
2184
2185 case FS_OPCODE_PLACEHOLDER_HALT:
2186 /* This is the place where the final HALT needs to be inserted if
2187 * we've emitted any discards. If not, this will emit no code.
2188 */
2189 if (!patch_discard_jumps_to_fb_writes()) {
2190 if (unlikely(debug_flag)) {
2191 annotation.ann_count--;
2192 }
2193 }
2194 break;
2195
2196 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2197 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2198 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2199 break;
2200
2201 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2202 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2203 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2204 break;
2205
2206 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2207 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2208 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2209 break;
2210
2211 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2212 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2213 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2214 break;
2215
2216 case CS_OPCODE_CS_TERMINATE:
2217 generate_cs_terminate(inst, src[0]);
2218 break;
2219
2220 case SHADER_OPCODE_BARRIER:
2221 generate_barrier(inst, src[0]);
2222 break;
2223
2224 case FS_OPCODE_PACK_STENCIL_REF:
2225 generate_stencil_ref_packing(inst, dst, src[0]);
2226 break;
2227
2228 default:
2229 unreachable("Unsupported opcode");
2230
2231 case SHADER_OPCODE_LOAD_PAYLOAD:
2232 unreachable("Should be lowered by lower_load_payload()");
2233 }
2234
2235 if (multiple_instructions_emitted)
2236 continue;
2237
2238 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2239 assert(p->next_insn_offset == last_insn_offset + 16 ||
2240 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2241 "emitting more than 1 instruction");
2242
2243 brw_inst *last = &p->store[last_insn_offset / 16];
2244
2245 if (inst->conditional_mod)
2246 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2247 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2248 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2249 }
2250 }
2251
2252 brw_set_uip_jip(p);
2253 annotation_finalize(&annotation, p->next_insn_offset);
2254
2255 #ifndef NDEBUG
2256 bool validated = brw_validate_instructions(p, start_offset, &annotation);
2257 #else
2258 if (unlikely(debug_flag))
2259 brw_validate_instructions(p, start_offset, &annotation);
2260 #endif
2261
2262 int before_size = p->next_insn_offset - start_offset;
2263 brw_compact_instructions(p, start_offset, annotation.ann_count,
2264 annotation.ann);
2265 int after_size = p->next_insn_offset - start_offset;
2266
2267 if (unlikely(debug_flag)) {
2268 fprintf(stderr, "Native code for %s\n"
2269 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2270 " bytes (%.0f%%)\n",
2271 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2272 spill_count, fill_count, promoted_constants, before_size, after_size,
2273 100.0f * (before_size - after_size) / before_size);
2274
2275 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2276 p->devinfo);
2277 ralloc_free(annotation.mem_ctx);
2278 }
2279 assert(validated);
2280
2281 compiler->shader_debug_log(log_data,
2282 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2283 "%d:%d spills:fills, Promoted %u constants, "
2284 "compacted %d to %d bytes.\n",
2285 stage_abbrev, dispatch_width, before_size / 16,
2286 loop_count, cfg->cycle_count, spill_count,
2287 fill_count, promoted_constants, before_size,
2288 after_size);
2289
2290 return start_offset;
2291 }
2292
2293 const unsigned *
2294 fs_generator::get_assembly(unsigned int *assembly_size)
2295 {
2296 return brw_get_program(p, assembly_size);
2297 }