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Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "main/macros.h"
31 #include "brw_context.h"
32 #include "brw_eu.h"
33 #include "brw_fs.h"
34 #include "brw_cfg.h"
35
36 static enum brw_reg_file
37 brw_file_from_reg(fs_reg *reg)
38 {
39 switch (reg->file) {
40 case ARF:
41 return BRW_ARCHITECTURE_REGISTER_FILE;
42 case FIXED_GRF:
43 case VGRF:
44 return BRW_GENERAL_REGISTER_FILE;
45 case MRF:
46 return BRW_MESSAGE_REGISTER_FILE;
47 case IMM:
48 return BRW_IMMEDIATE_VALUE;
49 case BAD_FILE:
50 case ATTR:
51 case UNIFORM:
52 unreachable("not reached");
53 }
54 return BRW_ARCHITECTURE_REGISTER_FILE;
55 }
56
57 static struct brw_reg
58 brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
59 {
60 struct brw_reg brw_reg;
61
62 switch (reg->file) {
63 case MRF:
64 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(gen));
65 /* Fallthrough */
66 case VGRF:
67 if (reg->stride == 0) {
68 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
69 } else if (inst->exec_size < 8) {
70 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
71 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
72 inst->exec_size, reg->stride);
73 } else {
74 /* From the Haswell PRM:
75 *
76 * VertStride must be used to cross GRF register boundaries. This
77 * rule implies that elements within a 'Width' cannot cross GRF
78 * boundaries.
79 *
80 * So, for registers with width > 8, we have to use a width of 8
81 * and trust the compression state to sort out the exec size.
82 */
83 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
84 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
85 }
86
87 brw_reg = retype(brw_reg, reg->type);
88 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
89 brw_reg.abs = reg->abs;
90 brw_reg.negate = reg->negate;
91 break;
92 case IMM:
93 assert(reg->stride == ((reg->type == BRW_REGISTER_TYPE_V ||
94 reg->type == BRW_REGISTER_TYPE_UV ||
95 reg->type == BRW_REGISTER_TYPE_VF) ? 1 : 0));
96
97 switch (reg->type) {
98 case BRW_REGISTER_TYPE_F:
99 brw_reg = brw_imm_f(reg->f);
100 break;
101 case BRW_REGISTER_TYPE_D:
102 brw_reg = brw_imm_d(reg->d);
103 break;
104 case BRW_REGISTER_TYPE_UD:
105 brw_reg = brw_imm_ud(reg->ud);
106 break;
107 case BRW_REGISTER_TYPE_W:
108 brw_reg = brw_imm_w(reg->d);
109 break;
110 case BRW_REGISTER_TYPE_UW:
111 brw_reg = brw_imm_uw(reg->ud);
112 break;
113 case BRW_REGISTER_TYPE_VF:
114 brw_reg = brw_imm_vf(reg->ud);
115 break;
116 case BRW_REGISTER_TYPE_V:
117 brw_reg = brw_imm_v(reg->ud);
118 break;
119 default:
120 unreachable("not reached");
121 }
122 break;
123 case ARF:
124 case FIXED_GRF:
125 brw_reg = *static_cast<struct brw_reg *>(reg);
126 break;
127 case BAD_FILE:
128 /* Probably unused. */
129 brw_reg = brw_null_reg();
130 break;
131 case ATTR:
132 case UNIFORM:
133 unreachable("not reached");
134 }
135
136 return brw_reg;
137 }
138
139 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
140 void *mem_ctx,
141 const void *key,
142 struct brw_stage_prog_data *prog_data,
143 unsigned promoted_constants,
144 bool runtime_check_aads_emit,
145 const char *stage_abbrev)
146
147 : compiler(compiler), log_data(log_data),
148 devinfo(compiler->devinfo), key(key),
149 prog_data(prog_data),
150 promoted_constants(promoted_constants),
151 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
152 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
153 {
154 p = rzalloc(mem_ctx, struct brw_codegen);
155 brw_init_codegen(devinfo, p, mem_ctx);
156 }
157
158 fs_generator::~fs_generator()
159 {
160 }
161
162 class ip_record : public exec_node {
163 public:
164 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
165
166 ip_record(int ip)
167 {
168 this->ip = ip;
169 }
170
171 int ip;
172 };
173
174 bool
175 fs_generator::patch_discard_jumps_to_fb_writes()
176 {
177 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
178 return false;
179
180 int scale = brw_jump_scale(p->devinfo);
181
182 /* There is a somewhat strange undocumented requirement of using
183 * HALT, according to the simulator. If some channel has HALTed to
184 * a particular UIP, then by the end of the program, every channel
185 * must have HALTed to that UIP. Furthermore, the tracking is a
186 * stack, so you can't do the final halt of a UIP after starting
187 * halting to a new UIP.
188 *
189 * Symptoms of not emitting this instruction on actual hardware
190 * included GPU hangs and sparkly rendering on the piglit discard
191 * tests.
192 */
193 brw_inst *last_halt = gen6_HALT(p);
194 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
195 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
196
197 int ip = p->nr_insn;
198
199 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
200 brw_inst *patch = &p->store[patch_ip->ip];
201
202 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
203 /* HALT takes a half-instruction distance from the pre-incremented IP. */
204 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
205 }
206
207 this->discard_halt_patches.make_empty();
208 return true;
209 }
210
211 void
212 fs_generator::fire_fb_write(fs_inst *inst,
213 struct brw_reg payload,
214 struct brw_reg implied_header,
215 GLuint nr)
216 {
217 uint32_t msg_control;
218
219 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
220
221 if (devinfo->gen < 6) {
222 brw_push_insn_state(p);
223 brw_set_default_exec_size(p, BRW_EXECUTE_8);
224 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
225 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
226 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
227 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
228 brw_pop_insn_state(p);
229 }
230
231 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
232 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
233 else if (prog_data->dual_src_blend) {
234 if (!inst->force_sechalf)
235 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
236 else
237 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
238 } else if (inst->exec_size == 16)
239 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
240 else
241 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
242
243 uint32_t surf_index =
244 prog_data->binding_table.render_target_start + inst->target;
245
246 bool last_render_target = inst->eot ||
247 (prog_data->dual_src_blend && dispatch_width == 16);
248
249
250 brw_fb_WRITE(p,
251 dispatch_width,
252 payload,
253 implied_header,
254 msg_control,
255 surf_index,
256 nr,
257 0,
258 inst->eot,
259 last_render_target,
260 inst->header_size != 0);
261
262 brw_mark_surface_used(&prog_data->base, surf_index);
263 }
264
265 void
266 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
267 {
268 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
269 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
270 struct brw_reg implied_header;
271
272 if (devinfo->gen < 8 && !devinfo->is_haswell) {
273 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
274 }
275
276 if (inst->base_mrf >= 0)
277 payload = brw_message_reg(inst->base_mrf);
278
279 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
280 * move, here's g1.
281 */
282 if (inst->header_size != 0) {
283 brw_push_insn_state(p);
284 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
285 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
286 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
287 brw_set_default_flag_reg(p, 0, 0);
288
289 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
290 * present.
291 */
292 if (prog_data->uses_kill) {
293 struct brw_reg pixel_mask;
294
295 if (devinfo->gen >= 6)
296 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
297 else
298 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
299
300 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
301 }
302
303 if (devinfo->gen >= 6) {
304 brw_push_insn_state(p);
305 brw_set_default_exec_size(p, BRW_EXECUTE_16);
306 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
307 brw_MOV(p,
308 retype(payload, BRW_REGISTER_TYPE_UD),
309 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
310 brw_pop_insn_state(p);
311
312 if (inst->target > 0 && key->replicate_alpha) {
313 /* Set "Source0 Alpha Present to RenderTarget" bit in message
314 * header.
315 */
316 brw_OR(p,
317 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
318 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
319 brw_imm_ud(0x1 << 11));
320 }
321
322 if (inst->target > 0) {
323 /* Set the render target index for choosing BLEND_STATE. */
324 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
325 BRW_REGISTER_TYPE_UD),
326 brw_imm_ud(inst->target));
327 }
328
329 /* Set computes stencil to render target */
330 if (prog_data->computed_stencil) {
331 brw_OR(p,
332 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
333 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
334 brw_imm_ud(0x1 << 14));
335 }
336
337 implied_header = brw_null_reg();
338 } else {
339 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
340 }
341
342 brw_pop_insn_state(p);
343 } else {
344 implied_header = brw_null_reg();
345 }
346
347 if (!runtime_check_aads_emit) {
348 fire_fb_write(inst, payload, implied_header, inst->mlen);
349 } else {
350 /* This can only happen in gen < 6 */
351 assert(devinfo->gen < 6);
352
353 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
354
355 /* Check runtime bit to detect if we have to send AA data or not */
356 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
357 brw_AND(p,
358 v1_null_ud,
359 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
360 brw_imm_ud(1<<26));
361 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
362
363 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
364 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
365 {
366 /* Don't send AA data */
367 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
368 }
369 brw_land_fwd_jump(p, jmp);
370 fire_fb_write(inst, payload, implied_header, inst->mlen);
371 }
372 }
373
374 void
375 fs_generator::generate_urb_read(fs_inst *inst,
376 struct brw_reg dst,
377 struct brw_reg header)
378 {
379 assert(header.file == BRW_GENERAL_REGISTER_FILE);
380 assert(header.type == BRW_REGISTER_TYPE_UD);
381
382 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
383 brw_set_dest(p, send, dst);
384 brw_set_src0(p, send, header);
385 brw_set_src1(p, send, brw_imm_ud(0u));
386
387 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
388 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
389
390 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
391 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
392
393 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
394 brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
395 brw_inst_set_header_present(p->devinfo, send, true);
396 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
397 }
398
399 void
400 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
401 {
402 brw_inst *insn;
403
404 insn = brw_next_insn(p, BRW_OPCODE_SEND);
405
406 brw_set_dest(p, insn, brw_null_reg());
407 brw_set_src0(p, insn, payload);
408 brw_set_src1(p, insn, brw_imm_d(0));
409
410 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
411 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
412
413 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
414 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
415 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
416
417 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
418 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
419 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
420
421 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
422 brw_inst_set_rlen(p->devinfo, insn, 0);
423 brw_inst_set_eot(p->devinfo, insn, inst->eot);
424 brw_inst_set_header_present(p->devinfo, insn, true);
425 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
426 }
427
428 void
429 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
430 {
431 struct brw_inst *insn;
432
433 insn = brw_next_insn(p, BRW_OPCODE_SEND);
434
435 brw_set_dest(p, insn, brw_null_reg());
436 brw_set_src0(p, insn, payload);
437 brw_set_src1(p, insn, brw_imm_d(0));
438
439 /* Terminate a compute shader by sending a message to the thread spawner.
440 */
441 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
442 brw_inst_set_mlen(devinfo, insn, 1);
443 brw_inst_set_rlen(devinfo, insn, 0);
444 brw_inst_set_eot(devinfo, insn, inst->eot);
445 brw_inst_set_header_present(devinfo, insn, false);
446
447 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
448 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
449
450 /* Note that even though the thread has a URB resource associated with it,
451 * we set the "do not dereference URB" bit, because the URB resource is
452 * managed by the fixed-function unit, so it will free it automatically.
453 */
454 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
455
456 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
457 }
458
459 void
460 fs_generator::generate_stencil_ref_packing(fs_inst *inst,
461 struct brw_reg dst,
462 struct brw_reg src)
463 {
464 assert(dispatch_width == 8);
465 assert(devinfo->gen >= 9);
466
467 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
468 * Presumably, in order to save memory bandwidth, the stencil reference
469 * values written from the FS need to be packed into 2 dwords (this makes
470 * sense because the stencil values are limited to 1 byte each and a SIMD8
471 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
472 *
473 * The spec is confusing here because in the payload definition of MDP_RTW_S8
474 * (Message Data Payload for Render Target Writes with Stencil 8b) the
475 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
476 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
477 * packed values specified above and diagrammed below:
478 *
479 * 31 0
480 * --------------------------------
481 * DW | |
482 * 2-7 | IGNORED |
483 * | |
484 * --------------------------------
485 * DW1 | STC | STC | STC | STC |
486 * | slot7 | slot6 | slot5 | slot4|
487 * --------------------------------
488 * DW0 | STC | STC | STC | STC |
489 * | slot3 | slot2 | slot1 | slot0|
490 * --------------------------------
491 */
492
493 src.vstride = BRW_VERTICAL_STRIDE_4;
494 src.width = BRW_WIDTH_1;
495 src.hstride = BRW_HORIZONTAL_STRIDE_0;
496 assert(src.type == BRW_REGISTER_TYPE_UB);
497 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UB), src);
498 }
499
500 void
501 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
502 {
503 brw_barrier(p, src);
504 brw_WAIT(p);
505 }
506
507 void
508 fs_generator::generate_blorp_fb_write(fs_inst *inst)
509 {
510 brw_fb_WRITE(p,
511 16 /* dispatch_width */,
512 brw_message_reg(inst->base_mrf),
513 brw_reg_from_fs_reg(inst, &inst->src[0], devinfo->gen),
514 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
515 inst->target,
516 inst->mlen,
517 0,
518 true,
519 true,
520 inst->header_size != 0);
521 }
522
523 void
524 fs_generator::generate_linterp(fs_inst *inst,
525 struct brw_reg dst, struct brw_reg *src)
526 {
527 /* PLN reads:
528 * / in SIMD16 \
529 * -----------------------------------
530 * | src1+0 | src1+1 | src1+2 | src1+3 |
531 * |-----------------------------------|
532 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
533 * -----------------------------------
534 *
535 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
536 *
537 * -----------------------------------
538 * | src1+0 | src1+1 | src1+2 | src1+3 |
539 * |-----------------------------------|
540 * |(x0, x1)|(y0, y1)| | | in SIMD8
541 * |-----------------------------------|
542 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
543 * -----------------------------------
544 *
545 * See also: emit_interpolation_setup_gen4().
546 */
547 struct brw_reg delta_x = src[0];
548 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
549 struct brw_reg interp = src[1];
550
551 if (devinfo->has_pln &&
552 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
553 brw_PLN(p, dst, interp, delta_x);
554 } else {
555 brw_LINE(p, brw_null_reg(), interp, delta_x);
556 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
557 }
558 }
559
560 void
561 fs_generator::generate_math_gen6(fs_inst *inst,
562 struct brw_reg dst,
563 struct brw_reg src0,
564 struct brw_reg src1)
565 {
566 int op = brw_math_function(inst->opcode);
567 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
568
569 if (dispatch_width == 8) {
570 gen6_math(p, dst, op, src0, src1);
571 } else if (dispatch_width == 16) {
572 brw_push_insn_state(p);
573 brw_set_default_exec_size(p, BRW_EXECUTE_8);
574 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
575 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
576 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
577 gen6_math(p, sechalf(dst), op, sechalf(src0),
578 binop ? sechalf(src1) : brw_null_reg());
579 brw_pop_insn_state(p);
580 }
581 }
582
583 void
584 fs_generator::generate_math_gen4(fs_inst *inst,
585 struct brw_reg dst,
586 struct brw_reg src)
587 {
588 int op = brw_math_function(inst->opcode);
589
590 assert(inst->mlen >= 1);
591
592 if (dispatch_width == 8) {
593 gen4_math(p, dst,
594 op,
595 inst->base_mrf, src,
596 BRW_MATH_PRECISION_FULL);
597 } else if (dispatch_width == 16) {
598 brw_set_default_exec_size(p, BRW_EXECUTE_8);
599 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
600 gen4_math(p, firsthalf(dst),
601 op,
602 inst->base_mrf, firsthalf(src),
603 BRW_MATH_PRECISION_FULL);
604 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
605 gen4_math(p, sechalf(dst),
606 op,
607 inst->base_mrf + 1, sechalf(src),
608 BRW_MATH_PRECISION_FULL);
609
610 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
611 }
612 }
613
614 void
615 fs_generator::generate_math_g45(fs_inst *inst,
616 struct brw_reg dst,
617 struct brw_reg src)
618 {
619 if (inst->opcode == SHADER_OPCODE_POW ||
620 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
621 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
622 generate_math_gen4(inst, dst, src);
623 return;
624 }
625
626 int op = brw_math_function(inst->opcode);
627
628 assert(inst->mlen >= 1);
629
630 gen4_math(p, dst,
631 op,
632 inst->base_mrf, src,
633 BRW_MATH_PRECISION_FULL);
634 }
635
636 void
637 fs_generator::generate_get_buffer_size(fs_inst *inst,
638 struct brw_reg dst,
639 struct brw_reg src,
640 struct brw_reg surf_index)
641 {
642 assert(devinfo->gen >= 7);
643 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
644
645 uint32_t simd_mode;
646 int rlen = 4;
647
648 switch (inst->exec_size) {
649 case 8:
650 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
651 break;
652 case 16:
653 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
654 break;
655 default:
656 unreachable("Invalid width for texture instruction");
657 }
658
659 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
660 rlen = 8;
661 dst = vec16(dst);
662 }
663
664 brw_SAMPLE(p,
665 retype(dst, BRW_REGISTER_TYPE_UW),
666 inst->base_mrf,
667 src,
668 surf_index.ud,
669 0,
670 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
671 rlen, /* response length */
672 inst->mlen,
673 inst->header_size > 0,
674 simd_mode,
675 BRW_SAMPLER_RETURN_FORMAT_SINT32);
676
677 brw_mark_surface_used(prog_data, surf_index.ud);
678 }
679
680 void
681 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
682 struct brw_reg sampler_index)
683 {
684 int msg_type = -1;
685 int rlen = 4;
686 uint32_t simd_mode;
687 uint32_t return_format;
688 bool is_combined_send = inst->eot;
689
690 switch (dst.type) {
691 case BRW_REGISTER_TYPE_D:
692 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
693 break;
694 case BRW_REGISTER_TYPE_UD:
695 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
696 break;
697 default:
698 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
699 break;
700 }
701
702 switch (inst->exec_size) {
703 case 8:
704 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
705 break;
706 case 16:
707 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
708 break;
709 default:
710 unreachable("Invalid width for texture instruction");
711 }
712
713 if (devinfo->gen >= 5) {
714 switch (inst->opcode) {
715 case SHADER_OPCODE_TEX:
716 if (inst->shadow_compare) {
717 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
718 } else {
719 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
720 }
721 break;
722 case FS_OPCODE_TXB:
723 if (inst->shadow_compare) {
724 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
725 } else {
726 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
727 }
728 break;
729 case SHADER_OPCODE_TXL:
730 if (inst->shadow_compare) {
731 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
732 } else {
733 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
734 }
735 break;
736 case SHADER_OPCODE_TXS:
737 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
738 break;
739 case SHADER_OPCODE_TXD:
740 if (inst->shadow_compare) {
741 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
742 assert(devinfo->gen >= 8 || devinfo->is_haswell);
743 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
744 } else {
745 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
746 }
747 break;
748 case SHADER_OPCODE_TXF:
749 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
750 break;
751 case SHADER_OPCODE_TXF_CMS_W:
752 assert(devinfo->gen >= 9);
753 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
754 break;
755 case SHADER_OPCODE_TXF_CMS:
756 if (devinfo->gen >= 7)
757 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
758 else
759 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
760 break;
761 case SHADER_OPCODE_TXF_UMS:
762 assert(devinfo->gen >= 7);
763 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
764 break;
765 case SHADER_OPCODE_TXF_MCS:
766 assert(devinfo->gen >= 7);
767 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
768 break;
769 case SHADER_OPCODE_LOD:
770 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
771 break;
772 case SHADER_OPCODE_TG4:
773 if (inst->shadow_compare) {
774 assert(devinfo->gen >= 7);
775 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
776 } else {
777 assert(devinfo->gen >= 6);
778 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
779 }
780 break;
781 case SHADER_OPCODE_TG4_OFFSET:
782 assert(devinfo->gen >= 7);
783 if (inst->shadow_compare) {
784 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
785 } else {
786 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
787 }
788 break;
789 case SHADER_OPCODE_SAMPLEINFO:
790 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
791 break;
792 default:
793 unreachable("not reached");
794 }
795 } else {
796 switch (inst->opcode) {
797 case SHADER_OPCODE_TEX:
798 /* Note that G45 and older determines shadow compare and dispatch width
799 * from message length for most messages.
800 */
801 if (inst->exec_size == 8) {
802 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
803 if (inst->shadow_compare) {
804 assert(inst->mlen == 6);
805 } else {
806 assert(inst->mlen <= 4);
807 }
808 } else {
809 if (inst->shadow_compare) {
810 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
811 assert(inst->mlen == 9);
812 } else {
813 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
814 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
815 }
816 }
817 break;
818 case FS_OPCODE_TXB:
819 if (inst->shadow_compare) {
820 assert(inst->exec_size == 8);
821 assert(inst->mlen == 6);
822 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
823 } else {
824 assert(inst->mlen == 9);
825 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
826 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
827 }
828 break;
829 case SHADER_OPCODE_TXL:
830 if (inst->shadow_compare) {
831 assert(inst->exec_size == 8);
832 assert(inst->mlen == 6);
833 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
834 } else {
835 assert(inst->mlen == 9);
836 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
837 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
838 }
839 break;
840 case SHADER_OPCODE_TXD:
841 /* There is no sample_d_c message; comparisons are done manually */
842 assert(inst->exec_size == 8);
843 assert(inst->mlen == 7 || inst->mlen == 10);
844 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
845 break;
846 case SHADER_OPCODE_TXF:
847 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
848 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
849 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
850 break;
851 case SHADER_OPCODE_TXS:
852 assert(inst->mlen == 3);
853 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
854 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
855 break;
856 default:
857 unreachable("not reached");
858 }
859 }
860 assert(msg_type != -1);
861
862 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
863 rlen = 8;
864 dst = vec16(dst);
865 }
866
867 if (is_combined_send) {
868 assert(devinfo->gen >= 9 || devinfo->is_cherryview);
869 rlen = 0;
870 }
871
872 assert(devinfo->gen < 7 || inst->header_size == 0 ||
873 src.file == BRW_GENERAL_REGISTER_FILE);
874
875 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
876
877 /* Load the message header if present. If there's a texture offset,
878 * we need to set it up explicitly and load the offset bitfield.
879 * Otherwise, we can use an implied move from g0 to the first message reg.
880 */
881 if (inst->header_size != 0) {
882 if (devinfo->gen < 6 && !inst->offset) {
883 /* Set up an implied move from g0 to the MRF. */
884 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
885 } else {
886 struct brw_reg header_reg;
887
888 if (devinfo->gen >= 7) {
889 header_reg = src;
890 } else {
891 assert(inst->base_mrf != -1);
892 header_reg = brw_message_reg(inst->base_mrf);
893 }
894
895 brw_push_insn_state(p);
896 brw_set_default_exec_size(p, BRW_EXECUTE_8);
897 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
898 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
899 /* Explicitly set up the message header by copying g0 to the MRF. */
900 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
901
902 if (inst->offset) {
903 /* Set the offset bits in DWord 2. */
904 brw_MOV(p, get_element_ud(header_reg, 2),
905 brw_imm_ud(inst->offset));
906 }
907
908 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
909 brw_pop_insn_state(p);
910 }
911 }
912
913 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
914 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
915 ? prog_data->binding_table.gather_texture_start
916 : prog_data->binding_table.texture_start;
917
918 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
919 uint32_t sampler = sampler_index.ud;
920
921 brw_SAMPLE(p,
922 retype(dst, BRW_REGISTER_TYPE_UW),
923 inst->base_mrf,
924 src,
925 sampler + base_binding_table_index,
926 sampler % 16,
927 msg_type,
928 rlen,
929 inst->mlen,
930 inst->header_size != 0,
931 simd_mode,
932 return_format);
933
934 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
935 } else {
936 /* Non-const sampler index */
937
938 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
939 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
940
941 brw_push_insn_state(p);
942 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
943 brw_set_default_access_mode(p, BRW_ALIGN_1);
944
945 /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
946 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
947 if (base_binding_table_index)
948 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
949 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
950
951 brw_pop_insn_state(p);
952
953 /* dst = send(offset, a0.0 | <descriptor>) */
954 brw_inst *insn = brw_send_indirect_message(
955 p, BRW_SFID_SAMPLER, dst, src, addr);
956 brw_set_sampler_message(p, insn,
957 0 /* surface */,
958 0 /* sampler */,
959 msg_type,
960 rlen,
961 inst->mlen /* mlen */,
962 inst->header_size != 0 /* header */,
963 simd_mode,
964 return_format);
965
966 /* visitor knows more than we do about the surface limit required,
967 * so has already done marking.
968 */
969 }
970
971 if (is_combined_send) {
972 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
973 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
974 }
975 }
976
977
978 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
979 * looking like:
980 *
981 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
982 *
983 * Ideally, we want to produce:
984 *
985 * DDX DDY
986 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
987 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
988 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
989 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
990 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
991 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
992 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
993 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
994 *
995 * and add another set of two more subspans if in 16-pixel dispatch mode.
996 *
997 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
998 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
999 * pair. But the ideal approximation may impose a huge performance cost on
1000 * sample_d. On at least Haswell, sample_d instruction does some
1001 * optimizations if the same LOD is used for all pixels in the subspan.
1002 *
1003 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1004 * appropriate swizzling.
1005 */
1006 void
1007 fs_generator::generate_ddx(enum opcode opcode,
1008 struct brw_reg dst, struct brw_reg src)
1009 {
1010 unsigned vstride, width;
1011
1012 if (opcode == FS_OPCODE_DDX_FINE) {
1013 /* produce accurate derivatives */
1014 vstride = BRW_VERTICAL_STRIDE_2;
1015 width = BRW_WIDTH_2;
1016 } else {
1017 /* replicate the derivative at the top-left pixel to other pixels */
1018 vstride = BRW_VERTICAL_STRIDE_4;
1019 width = BRW_WIDTH_4;
1020 }
1021
1022 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
1023 src.negate, src.abs,
1024 BRW_REGISTER_TYPE_F,
1025 vstride,
1026 width,
1027 BRW_HORIZONTAL_STRIDE_0,
1028 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1029 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1030 src.negate, src.abs,
1031 BRW_REGISTER_TYPE_F,
1032 vstride,
1033 width,
1034 BRW_HORIZONTAL_STRIDE_0,
1035 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1036 brw_ADD(p, dst, src0, negate(src1));
1037 }
1038
1039 /* The negate_value boolean is used to negate the derivative computation for
1040 * FBOs, since they place the origin at the upper left instead of the lower
1041 * left.
1042 */
1043 void
1044 fs_generator::generate_ddy(enum opcode opcode,
1045 struct brw_reg dst, struct brw_reg src,
1046 bool negate_value)
1047 {
1048 if (opcode == FS_OPCODE_DDY_FINE) {
1049 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1050 * Region Restrictions):
1051 *
1052 * In Align16 access mode, SIMD16 is not allowed for DW operations
1053 * and SIMD8 is not allowed for DF operations.
1054 *
1055 * In this context, "DW operations" means "operations acting on 32-bit
1056 * values", so it includes operations on floats.
1057 *
1058 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1059 * (Instruction Compression -> Rules and Restrictions):
1060 *
1061 * A compressed instruction must be in Align1 access mode. Align16
1062 * mode instructions cannot be compressed.
1063 *
1064 * Similar text exists in the g45 PRM.
1065 *
1066 * On these platforms, if we're building a SIMD16 shader, we need to
1067 * manually unroll to a pair of SIMD8 instructions.
1068 */
1069 bool unroll_to_simd8 =
1070 (dispatch_width == 16 &&
1071 (devinfo->gen == 4 || (devinfo->gen == 7 && !devinfo->is_haswell)));
1072
1073 /* produce accurate derivatives */
1074 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1075 src.negate, src.abs,
1076 BRW_REGISTER_TYPE_F,
1077 BRW_VERTICAL_STRIDE_4,
1078 BRW_WIDTH_4,
1079 BRW_HORIZONTAL_STRIDE_1,
1080 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
1081 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1082 src.negate, src.abs,
1083 BRW_REGISTER_TYPE_F,
1084 BRW_VERTICAL_STRIDE_4,
1085 BRW_WIDTH_4,
1086 BRW_HORIZONTAL_STRIDE_1,
1087 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
1088 brw_push_insn_state(p);
1089 brw_set_default_access_mode(p, BRW_ALIGN_16);
1090 if (unroll_to_simd8) {
1091 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1092 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1093 if (negate_value) {
1094 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
1095 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1096 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
1097 } else {
1098 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
1099 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1100 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
1101 }
1102 } else {
1103 if (negate_value)
1104 brw_ADD(p, dst, src1, negate(src0));
1105 else
1106 brw_ADD(p, dst, src0, negate(src1));
1107 }
1108 brw_pop_insn_state(p);
1109 } else {
1110 /* replicate the derivative at the top-left pixel to other pixels */
1111 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1112 src.negate, src.abs,
1113 BRW_REGISTER_TYPE_F,
1114 BRW_VERTICAL_STRIDE_4,
1115 BRW_WIDTH_4,
1116 BRW_HORIZONTAL_STRIDE_0,
1117 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1118 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1119 src.negate, src.abs,
1120 BRW_REGISTER_TYPE_F,
1121 BRW_VERTICAL_STRIDE_4,
1122 BRW_WIDTH_4,
1123 BRW_HORIZONTAL_STRIDE_0,
1124 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1125 if (negate_value)
1126 brw_ADD(p, dst, src1, negate(src0));
1127 else
1128 brw_ADD(p, dst, src0, negate(src1));
1129 }
1130 }
1131
1132 void
1133 fs_generator::generate_discard_jump(fs_inst *inst)
1134 {
1135 assert(devinfo->gen >= 6);
1136
1137 /* This HALT will be patched up at FB write time to point UIP at the end of
1138 * the program, and at brw_uip_jip() JIP will be set to the end of the
1139 * current block (or the program).
1140 */
1141 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1142
1143 brw_push_insn_state(p);
1144 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1145 gen6_HALT(p);
1146 brw_pop_insn_state(p);
1147 }
1148
1149 void
1150 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1151 {
1152 assert(inst->mlen != 0);
1153
1154 brw_MOV(p,
1155 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1156 retype(src, BRW_REGISTER_TYPE_UD));
1157 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1158 inst->exec_size / 8, inst->offset);
1159 }
1160
1161 void
1162 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1163 {
1164 assert(inst->mlen != 0);
1165
1166 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1167 inst->exec_size / 8, inst->offset);
1168 }
1169
1170 void
1171 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1172 {
1173 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1174 }
1175
1176 void
1177 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1178 struct brw_reg dst,
1179 struct brw_reg index,
1180 struct brw_reg offset)
1181 {
1182 assert(inst->mlen != 0);
1183
1184 assert(index.file == BRW_IMMEDIATE_VALUE &&
1185 index.type == BRW_REGISTER_TYPE_UD);
1186 uint32_t surf_index = index.ud;
1187
1188 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1189 offset.type == BRW_REGISTER_TYPE_UD);
1190 uint32_t read_offset = offset.ud;
1191
1192 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1193 read_offset, surf_index);
1194 }
1195
1196 void
1197 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1198 struct brw_reg dst,
1199 struct brw_reg index,
1200 struct brw_reg offset)
1201 {
1202 assert(index.type == BRW_REGISTER_TYPE_UD);
1203
1204 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1205 /* Reference just the dword we need, to avoid angering validate_reg(). */
1206 offset = brw_vec1_grf(offset.nr, 0);
1207
1208 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1209 * the destination loaded consecutively from the same offset (which appears
1210 * in the first component, and the rest are ignored).
1211 */
1212 dst.width = BRW_WIDTH_4;
1213
1214 struct brw_reg src = offset;
1215 bool header_present = false;
1216
1217 if (devinfo->gen >= 9) {
1218 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1219 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1220 header_present = true;
1221
1222 brw_push_insn_state(p);
1223 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1224 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1225 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1226 brw_set_default_access_mode(p, BRW_ALIGN_1);
1227
1228 brw_MOV(p, get_element_ud(src, 2),
1229 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1230 brw_pop_insn_state(p);
1231 }
1232
1233 if (index.file == BRW_IMMEDIATE_VALUE) {
1234
1235 uint32_t surf_index = index.ud;
1236
1237 brw_push_insn_state(p);
1238 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1239 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1240 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1241 brw_pop_insn_state(p);
1242
1243 brw_set_dest(p, send, dst);
1244 brw_set_src0(p, send, src);
1245 brw_set_sampler_message(p, send,
1246 surf_index,
1247 0, /* LD message ignores sampler unit */
1248 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1249 1, /* rlen */
1250 inst->mlen,
1251 header_present,
1252 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1253 0);
1254 } else {
1255
1256 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1257
1258 brw_push_insn_state(p);
1259 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1260 brw_set_default_access_mode(p, BRW_ALIGN_1);
1261
1262 /* a0.0 = surf_index & 0xff */
1263 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1264 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1265 brw_set_dest(p, insn_and, addr);
1266 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1267 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1268
1269 /* dst = send(payload, a0.0 | <descriptor>) */
1270 brw_inst *insn = brw_send_indirect_message(
1271 p, BRW_SFID_SAMPLER, dst, src, addr);
1272 brw_set_sampler_message(p, insn,
1273 0,
1274 0, /* LD message ignores sampler unit */
1275 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1276 1, /* rlen */
1277 inst->mlen,
1278 header_present,
1279 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1280 0);
1281
1282 brw_pop_insn_state(p);
1283 }
1284 }
1285
1286 void
1287 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1288 struct brw_reg dst,
1289 struct brw_reg index,
1290 struct brw_reg offset)
1291 {
1292 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1293 assert(inst->header_size != 0);
1294 assert(inst->mlen);
1295
1296 assert(index.file == BRW_IMMEDIATE_VALUE &&
1297 index.type == BRW_REGISTER_TYPE_UD);
1298 uint32_t surf_index = index.ud;
1299
1300 uint32_t simd_mode, rlen, msg_type;
1301 if (dispatch_width == 16) {
1302 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1303 rlen = 8;
1304 } else {
1305 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1306 rlen = 4;
1307 }
1308
1309 if (devinfo->gen >= 5)
1310 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1311 else {
1312 /* We always use the SIMD16 message so that we only have to load U, and
1313 * not V or R.
1314 */
1315 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1316 assert(inst->mlen == 3);
1317 assert(inst->regs_written == 8);
1318 rlen = 8;
1319 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1320 }
1321
1322 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1323 BRW_REGISTER_TYPE_D);
1324 brw_MOV(p, offset_mrf, offset);
1325
1326 struct brw_reg header = brw_vec8_grf(0, 0);
1327 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1328
1329 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1330 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1331 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1332 brw_set_src0(p, send, header);
1333 if (devinfo->gen < 6)
1334 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1335
1336 /* Our surface is set up as floats, regardless of what actual data is
1337 * stored in it.
1338 */
1339 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1340 brw_set_sampler_message(p, send,
1341 surf_index,
1342 0, /* sampler (unused) */
1343 msg_type,
1344 rlen,
1345 inst->mlen,
1346 inst->header_size != 0,
1347 simd_mode,
1348 return_format);
1349 }
1350
1351 void
1352 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1353 struct brw_reg dst,
1354 struct brw_reg index,
1355 struct brw_reg offset)
1356 {
1357 assert(devinfo->gen >= 7);
1358 /* Varying-offset pull constant loads are treated as a normal expression on
1359 * gen7, so the fact that it's a send message is hidden at the IR level.
1360 */
1361 assert(inst->header_size == 0);
1362 assert(!inst->mlen);
1363 assert(index.type == BRW_REGISTER_TYPE_UD);
1364
1365 uint32_t simd_mode, rlen, mlen;
1366 if (dispatch_width == 16) {
1367 mlen = 2;
1368 rlen = 8;
1369 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1370 } else {
1371 mlen = 1;
1372 rlen = 4;
1373 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1374 }
1375
1376 if (index.file == BRW_IMMEDIATE_VALUE) {
1377
1378 uint32_t surf_index = index.ud;
1379
1380 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1381 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1382 brw_set_src0(p, send, offset);
1383 brw_set_sampler_message(p, send,
1384 surf_index,
1385 0, /* LD message ignores sampler unit */
1386 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1387 rlen,
1388 mlen,
1389 false, /* no header */
1390 simd_mode,
1391 0);
1392
1393 } else {
1394
1395 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1396
1397 brw_push_insn_state(p);
1398 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1399 brw_set_default_access_mode(p, BRW_ALIGN_1);
1400
1401 /* a0.0 = surf_index & 0xff */
1402 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1403 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1404 brw_set_dest(p, insn_and, addr);
1405 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1406 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1407
1408 brw_pop_insn_state(p);
1409
1410 /* dst = send(offset, a0.0 | <descriptor>) */
1411 brw_inst *insn = brw_send_indirect_message(
1412 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1413 offset, addr);
1414 brw_set_sampler_message(p, insn,
1415 0 /* surface */,
1416 0 /* sampler */,
1417 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1418 rlen /* rlen */,
1419 mlen /* mlen */,
1420 false /* header */,
1421 simd_mode,
1422 0);
1423 }
1424 }
1425
1426 /**
1427 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1428 * into the flags register (f0.0).
1429 *
1430 * Used only on Gen6 and above.
1431 */
1432 void
1433 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1434 {
1435 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1436 struct brw_reg dispatch_mask;
1437
1438 if (devinfo->gen >= 6)
1439 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1440 else
1441 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1442
1443 brw_push_insn_state(p);
1444 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1445 brw_MOV(p, flags, dispatch_mask);
1446 brw_pop_insn_state(p);
1447 }
1448
1449 void
1450 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1451 struct brw_reg dst,
1452 struct brw_reg src,
1453 struct brw_reg msg_data,
1454 unsigned msg_type)
1455 {
1456 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1457
1458 brw_pixel_interpolator_query(p,
1459 retype(dst, BRW_REGISTER_TYPE_UW),
1460 src,
1461 inst->pi_noperspective,
1462 msg_type,
1463 msg_data,
1464 inst->mlen,
1465 inst->regs_written);
1466 }
1467
1468
1469 /**
1470 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1471 * sampler LD messages.
1472 *
1473 * We don't want to bake it into the send message's code generation because
1474 * that means we don't get a chance to schedule the instructions.
1475 */
1476 void
1477 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1478 struct brw_reg dst,
1479 struct brw_reg value)
1480 {
1481 assert(value.file == BRW_IMMEDIATE_VALUE);
1482
1483 brw_push_insn_state(p);
1484 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1485 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1486 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1487 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1488 brw_pop_insn_state(p);
1489 }
1490
1491 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1492 * the ADD instruction.
1493 */
1494 void
1495 fs_generator::generate_set_sample_id(fs_inst *inst,
1496 struct brw_reg dst,
1497 struct brw_reg src0,
1498 struct brw_reg src1)
1499 {
1500 assert(dst.type == BRW_REGISTER_TYPE_D ||
1501 dst.type == BRW_REGISTER_TYPE_UD);
1502 assert(src0.type == BRW_REGISTER_TYPE_D ||
1503 src0.type == BRW_REGISTER_TYPE_UD);
1504
1505 struct brw_reg reg = stride(src1, 1, 4, 0);
1506 if (devinfo->gen >= 8 || dispatch_width == 8) {
1507 brw_ADD(p, dst, src0, reg);
1508 } else if (dispatch_width == 16) {
1509 brw_push_insn_state(p);
1510 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1511 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1512 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1513 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1514 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1515 brw_pop_insn_state(p);
1516 }
1517 }
1518
1519 void
1520 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1521 struct brw_reg dst,
1522 struct brw_reg x,
1523 struct brw_reg y)
1524 {
1525 assert(devinfo->gen >= 7);
1526 assert(dst.type == BRW_REGISTER_TYPE_UD);
1527 assert(x.type == BRW_REGISTER_TYPE_F);
1528 assert(y.type == BRW_REGISTER_TYPE_F);
1529
1530 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1531 *
1532 * Because this instruction does not have a 16-bit floating-point type,
1533 * the destination data type must be Word (W).
1534 *
1535 * The destination must be DWord-aligned and specify a horizontal stride
1536 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1537 * each destination channel and the upper word is not modified.
1538 */
1539 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1540
1541 /* Give each 32-bit channel of dst the form below, where "." means
1542 * unchanged.
1543 * 0x....hhhh
1544 */
1545 brw_F32TO16(p, dst_w, y);
1546
1547 /* Now the form:
1548 * 0xhhhh0000
1549 */
1550 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1551
1552 /* And, finally the form of packHalf2x16's output:
1553 * 0xhhhhllll
1554 */
1555 brw_F32TO16(p, dst_w, x);
1556 }
1557
1558 void
1559 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1560 struct brw_reg dst,
1561 struct brw_reg src)
1562 {
1563 assert(devinfo->gen >= 7);
1564 assert(dst.type == BRW_REGISTER_TYPE_F);
1565 assert(src.type == BRW_REGISTER_TYPE_UD);
1566
1567 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1568 *
1569 * Because this instruction does not have a 16-bit floating-point type,
1570 * the source data type must be Word (W). The destination type must be
1571 * F (Float).
1572 */
1573 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1574
1575 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1576 * For the Y case, we wish to access only the upper word; therefore
1577 * a 16-bit subregister offset is needed.
1578 */
1579 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1580 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1581 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1582 src_w.subnr += 2;
1583
1584 brw_F16TO32(p, dst, src_w);
1585 }
1586
1587 void
1588 fs_generator::generate_shader_time_add(fs_inst *inst,
1589 struct brw_reg payload,
1590 struct brw_reg offset,
1591 struct brw_reg value)
1592 {
1593 assert(devinfo->gen >= 7);
1594 brw_push_insn_state(p);
1595 brw_set_default_mask_control(p, true);
1596
1597 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1598 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1599 offset.type);
1600 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1601 value.type);
1602
1603 assert(offset.file == BRW_IMMEDIATE_VALUE);
1604 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1605 value.width = BRW_WIDTH_1;
1606 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1607 value.vstride = BRW_VERTICAL_STRIDE_0;
1608 } else {
1609 assert(value.file == BRW_IMMEDIATE_VALUE);
1610 }
1611
1612 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1613 * case, and we don't really care about squeezing every bit of performance
1614 * out of this path, so we just emit the MOVs from here.
1615 */
1616 brw_MOV(p, payload_offset, offset);
1617 brw_MOV(p, payload_value, value);
1618 brw_shader_time_add(p, payload,
1619 prog_data->binding_table.shader_time_start);
1620 brw_pop_insn_state(p);
1621
1622 brw_mark_surface_used(prog_data,
1623 prog_data->binding_table.shader_time_start);
1624 }
1625
1626 void
1627 fs_generator::enable_debug(const char *shader_name)
1628 {
1629 debug_flag = true;
1630 this->shader_name = shader_name;
1631 }
1632
1633 int
1634 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1635 {
1636 /* align to 64 byte boundary. */
1637 while (p->next_insn_offset % 64)
1638 brw_NOP(p);
1639
1640 this->dispatch_width = dispatch_width;
1641 if (dispatch_width == 16)
1642 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1643
1644 int start_offset = p->next_insn_offset;
1645 int spill_count = 0, fill_count = 0;
1646 int loop_count = 0;
1647
1648 struct annotation_info annotation;
1649 memset(&annotation, 0, sizeof(annotation));
1650
1651 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1652 struct brw_reg src[3], dst;
1653 unsigned int last_insn_offset = p->next_insn_offset;
1654 bool multiple_instructions_emitted = false;
1655
1656 if (unlikely(debug_flag))
1657 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1658
1659 for (unsigned int i = 0; i < inst->sources; i++) {
1660 src[i] = brw_reg_from_fs_reg(inst, &inst->src[i], devinfo->gen);
1661
1662 /* The accumulator result appears to get used for the
1663 * conditional modifier generation. When negating a UD
1664 * value, there is a 33rd bit generated for the sign in the
1665 * accumulator value, so now you can't check, for example,
1666 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1667 */
1668 assert(!inst->conditional_mod ||
1669 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1670 !inst->src[i].negate);
1671 }
1672 dst = brw_reg_from_fs_reg(inst, &inst->dst, devinfo->gen);
1673
1674 brw_set_default_predicate_control(p, inst->predicate);
1675 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1676 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1677 brw_set_default_saturate(p, inst->saturate);
1678 brw_set_default_mask_control(p, inst->force_writemask_all);
1679 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1680 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1681
1682 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1683 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1684
1685 switch (inst->exec_size) {
1686 case 1:
1687 case 2:
1688 case 4:
1689 assert(inst->force_writemask_all);
1690 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1691 break;
1692 case 8:
1693 if (inst->force_sechalf) {
1694 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1695 } else {
1696 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1697 }
1698 break;
1699 case 16:
1700 case 32:
1701 /* If the instruction writes to more than one register, it needs to
1702 * be a "compressed" instruction on Gen <= 5.
1703 */
1704 if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
1705 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1706 else
1707 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1708 break;
1709 default:
1710 unreachable("Invalid instruction width");
1711 }
1712
1713 switch (inst->opcode) {
1714 case BRW_OPCODE_MOV:
1715 brw_MOV(p, dst, src[0]);
1716 break;
1717 case BRW_OPCODE_ADD:
1718 brw_ADD(p, dst, src[0], src[1]);
1719 break;
1720 case BRW_OPCODE_MUL:
1721 brw_MUL(p, dst, src[0], src[1]);
1722 break;
1723 case BRW_OPCODE_AVG:
1724 brw_AVG(p, dst, src[0], src[1]);
1725 break;
1726 case BRW_OPCODE_MACH:
1727 brw_MACH(p, dst, src[0], src[1]);
1728 break;
1729
1730 case BRW_OPCODE_LINE:
1731 brw_LINE(p, dst, src[0], src[1]);
1732 break;
1733
1734 case BRW_OPCODE_MAD:
1735 assert(devinfo->gen >= 6);
1736 brw_set_default_access_mode(p, BRW_ALIGN_16);
1737 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1738 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1739 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1740 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1741 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1742 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1743 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1744
1745 if (inst->conditional_mod) {
1746 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1747 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1748 multiple_instructions_emitted = true;
1749 }
1750 } else {
1751 brw_MAD(p, dst, src[0], src[1], src[2]);
1752 }
1753 brw_set_default_access_mode(p, BRW_ALIGN_1);
1754 break;
1755
1756 case BRW_OPCODE_LRP:
1757 assert(devinfo->gen >= 6);
1758 brw_set_default_access_mode(p, BRW_ALIGN_16);
1759 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1760 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1761 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1762 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1763 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1764 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1765 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1766
1767 if (inst->conditional_mod) {
1768 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1769 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1770 multiple_instructions_emitted = true;
1771 }
1772 } else {
1773 brw_LRP(p, dst, src[0], src[1], src[2]);
1774 }
1775 brw_set_default_access_mode(p, BRW_ALIGN_1);
1776 break;
1777
1778 case BRW_OPCODE_FRC:
1779 brw_FRC(p, dst, src[0]);
1780 break;
1781 case BRW_OPCODE_RNDD:
1782 brw_RNDD(p, dst, src[0]);
1783 break;
1784 case BRW_OPCODE_RNDE:
1785 brw_RNDE(p, dst, src[0]);
1786 break;
1787 case BRW_OPCODE_RNDZ:
1788 brw_RNDZ(p, dst, src[0]);
1789 break;
1790
1791 case BRW_OPCODE_AND:
1792 brw_AND(p, dst, src[0], src[1]);
1793 break;
1794 case BRW_OPCODE_OR:
1795 brw_OR(p, dst, src[0], src[1]);
1796 break;
1797 case BRW_OPCODE_XOR:
1798 brw_XOR(p, dst, src[0], src[1]);
1799 break;
1800 case BRW_OPCODE_NOT:
1801 brw_NOT(p, dst, src[0]);
1802 break;
1803 case BRW_OPCODE_ASR:
1804 brw_ASR(p, dst, src[0], src[1]);
1805 break;
1806 case BRW_OPCODE_SHR:
1807 brw_SHR(p, dst, src[0], src[1]);
1808 break;
1809 case BRW_OPCODE_SHL:
1810 brw_SHL(p, dst, src[0], src[1]);
1811 break;
1812 case BRW_OPCODE_F32TO16:
1813 assert(devinfo->gen >= 7);
1814 brw_F32TO16(p, dst, src[0]);
1815 break;
1816 case BRW_OPCODE_F16TO32:
1817 assert(devinfo->gen >= 7);
1818 brw_F16TO32(p, dst, src[0]);
1819 break;
1820 case BRW_OPCODE_CMP:
1821 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1822 * that when the destination is a GRF that the dependency-clear bit on
1823 * the flag register is cleared early.
1824 *
1825 * Suggested workarounds are to disable coissuing CMP instructions
1826 * or to split CMP(16) instructions into two CMP(8) instructions.
1827 *
1828 * We choose to split into CMP(8) instructions since disabling
1829 * coissuing would affect CMP instructions not otherwise affected by
1830 * the errata.
1831 */
1832 if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) {
1833 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1834 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1835 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1836 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1837 firsthalf(src[0]), firsthalf(src[1]));
1838 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1839 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1840 sechalf(src[0]), sechalf(src[1]));
1841 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1842
1843 multiple_instructions_emitted = true;
1844 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1845 /* For unknown reasons, the aforementioned workaround is not
1846 * sufficient. Overriding the type when the destination is the
1847 * null register is necessary but not sufficient by itself.
1848 */
1849 assert(dst.nr == BRW_ARF_NULL);
1850 dst.type = BRW_REGISTER_TYPE_D;
1851 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1852 } else {
1853 unreachable("not reached");
1854 }
1855 } else {
1856 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1857 }
1858 break;
1859 case BRW_OPCODE_SEL:
1860 brw_SEL(p, dst, src[0], src[1]);
1861 break;
1862 case BRW_OPCODE_BFREV:
1863 assert(devinfo->gen >= 7);
1864 /* BFREV only supports UD type for src and dst. */
1865 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1866 retype(src[0], BRW_REGISTER_TYPE_UD));
1867 break;
1868 case BRW_OPCODE_FBH:
1869 assert(devinfo->gen >= 7);
1870 /* FBH only supports UD type for dst. */
1871 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1872 break;
1873 case BRW_OPCODE_FBL:
1874 assert(devinfo->gen >= 7);
1875 /* FBL only supports UD type for dst. */
1876 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1877 break;
1878 case BRW_OPCODE_CBIT:
1879 assert(devinfo->gen >= 7);
1880 /* CBIT only supports UD type for dst. */
1881 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1882 break;
1883 case BRW_OPCODE_ADDC:
1884 assert(devinfo->gen >= 7);
1885 brw_ADDC(p, dst, src[0], src[1]);
1886 break;
1887 case BRW_OPCODE_SUBB:
1888 assert(devinfo->gen >= 7);
1889 brw_SUBB(p, dst, src[0], src[1]);
1890 break;
1891 case BRW_OPCODE_MAC:
1892 brw_MAC(p, dst, src[0], src[1]);
1893 break;
1894
1895 case BRW_OPCODE_BFE:
1896 assert(devinfo->gen >= 7);
1897 brw_set_default_access_mode(p, BRW_ALIGN_16);
1898 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1899 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1900 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1901 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1902 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1903 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1904 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1905 } else {
1906 brw_BFE(p, dst, src[0], src[1], src[2]);
1907 }
1908 brw_set_default_access_mode(p, BRW_ALIGN_1);
1909 break;
1910
1911 case BRW_OPCODE_BFI1:
1912 assert(devinfo->gen >= 7);
1913 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1914 * should
1915 *
1916 * "Force BFI instructions to be executed always in SIMD8."
1917 */
1918 if (dispatch_width == 16 && devinfo->is_haswell) {
1919 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1920 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1921 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1922 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1923 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1924 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1925 } else {
1926 brw_BFI1(p, dst, src[0], src[1]);
1927 }
1928 break;
1929 case BRW_OPCODE_BFI2:
1930 assert(devinfo->gen >= 7);
1931 brw_set_default_access_mode(p, BRW_ALIGN_16);
1932 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1933 * should
1934 *
1935 * "Force BFI instructions to be executed always in SIMD8."
1936 *
1937 * Otherwise we would be able to emit compressed instructions like we
1938 * do for the other three-source instructions.
1939 */
1940 if (dispatch_width == 16 &&
1941 (devinfo->is_haswell || !devinfo->supports_simd16_3src)) {
1942 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1943 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1944 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1945 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1946 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1947 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1948 } else {
1949 brw_BFI2(p, dst, src[0], src[1], src[2]);
1950 }
1951 brw_set_default_access_mode(p, BRW_ALIGN_1);
1952 break;
1953
1954 case BRW_OPCODE_IF:
1955 if (inst->src[0].file != BAD_FILE) {
1956 /* The instruction has an embedded compare (only allowed on gen6) */
1957 assert(devinfo->gen == 6);
1958 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1959 } else {
1960 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1961 }
1962 break;
1963
1964 case BRW_OPCODE_ELSE:
1965 brw_ELSE(p);
1966 break;
1967 case BRW_OPCODE_ENDIF:
1968 brw_ENDIF(p);
1969 break;
1970
1971 case BRW_OPCODE_DO:
1972 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1973 break;
1974
1975 case BRW_OPCODE_BREAK:
1976 brw_BREAK(p);
1977 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1978 break;
1979 case BRW_OPCODE_CONTINUE:
1980 brw_CONT(p);
1981 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1982 break;
1983
1984 case BRW_OPCODE_WHILE:
1985 brw_WHILE(p);
1986 loop_count++;
1987 break;
1988
1989 case SHADER_OPCODE_RCP:
1990 case SHADER_OPCODE_RSQ:
1991 case SHADER_OPCODE_SQRT:
1992 case SHADER_OPCODE_EXP2:
1993 case SHADER_OPCODE_LOG2:
1994 case SHADER_OPCODE_SIN:
1995 case SHADER_OPCODE_COS:
1996 assert(devinfo->gen < 6 || inst->mlen == 0);
1997 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1998 if (devinfo->gen >= 7) {
1999 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
2000 brw_null_reg());
2001 } else if (devinfo->gen == 6) {
2002 generate_math_gen6(inst, dst, src[0], brw_null_reg());
2003 } else if (devinfo->gen == 5 || devinfo->is_g4x) {
2004 generate_math_g45(inst, dst, src[0]);
2005 } else {
2006 generate_math_gen4(inst, dst, src[0]);
2007 }
2008 break;
2009 case SHADER_OPCODE_INT_QUOTIENT:
2010 case SHADER_OPCODE_INT_REMAINDER:
2011 case SHADER_OPCODE_POW:
2012 assert(devinfo->gen < 6 || inst->mlen == 0);
2013 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2014 if (devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
2015 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
2016 } else if (devinfo->gen >= 6) {
2017 generate_math_gen6(inst, dst, src[0], src[1]);
2018 } else {
2019 generate_math_gen4(inst, dst, src[0]);
2020 }
2021 break;
2022 case FS_OPCODE_CINTERP:
2023 brw_MOV(p, dst, src[0]);
2024 break;
2025 case FS_OPCODE_LINTERP:
2026 generate_linterp(inst, dst, src);
2027 break;
2028 case FS_OPCODE_PIXEL_X:
2029 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2030 src[0].subnr = 0 * type_sz(src[0].type);
2031 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2032 break;
2033 case FS_OPCODE_PIXEL_Y:
2034 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2035 src[0].subnr = 4 * type_sz(src[0].type);
2036 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2037 break;
2038 case FS_OPCODE_GET_BUFFER_SIZE:
2039 generate_get_buffer_size(inst, dst, src[0], src[1]);
2040 break;
2041 case SHADER_OPCODE_TEX:
2042 case FS_OPCODE_TXB:
2043 case SHADER_OPCODE_TXD:
2044 case SHADER_OPCODE_TXF:
2045 case SHADER_OPCODE_TXF_CMS:
2046 case SHADER_OPCODE_TXF_CMS_W:
2047 case SHADER_OPCODE_TXF_UMS:
2048 case SHADER_OPCODE_TXF_MCS:
2049 case SHADER_OPCODE_TXL:
2050 case SHADER_OPCODE_TXS:
2051 case SHADER_OPCODE_LOD:
2052 case SHADER_OPCODE_TG4:
2053 case SHADER_OPCODE_TG4_OFFSET:
2054 case SHADER_OPCODE_SAMPLEINFO:
2055 generate_tex(inst, dst, src[0], src[1]);
2056 break;
2057 case FS_OPCODE_DDX_COARSE:
2058 case FS_OPCODE_DDX_FINE:
2059 generate_ddx(inst->opcode, dst, src[0]);
2060 break;
2061 case FS_OPCODE_DDY_COARSE:
2062 case FS_OPCODE_DDY_FINE:
2063 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2064 generate_ddy(inst->opcode, dst, src[0], src[1].ud);
2065 break;
2066
2067 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
2068 generate_scratch_write(inst, src[0]);
2069 spill_count++;
2070 break;
2071
2072 case SHADER_OPCODE_GEN4_SCRATCH_READ:
2073 generate_scratch_read(inst, dst);
2074 fill_count++;
2075 break;
2076
2077 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2078 generate_scratch_read_gen7(inst, dst);
2079 fill_count++;
2080 break;
2081
2082 case SHADER_OPCODE_URB_READ_SIMD8:
2083 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
2084 generate_urb_read(inst, dst, src[0]);
2085 break;
2086
2087 case SHADER_OPCODE_URB_WRITE_SIMD8:
2088 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
2089 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
2090 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
2091 generate_urb_write(inst, src[0]);
2092 break;
2093
2094 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2095 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2096 break;
2097
2098 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2099 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2100 break;
2101
2102 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
2103 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
2104 break;
2105
2106 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2107 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2108 break;
2109
2110 case FS_OPCODE_REP_FB_WRITE:
2111 case FS_OPCODE_FB_WRITE:
2112 generate_fb_write(inst, src[0]);
2113 break;
2114
2115 case FS_OPCODE_BLORP_FB_WRITE:
2116 generate_blorp_fb_write(inst);
2117 break;
2118
2119 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2120 generate_mov_dispatch_to_flags(inst);
2121 break;
2122
2123 case FS_OPCODE_DISCARD_JUMP:
2124 generate_discard_jump(inst);
2125 break;
2126
2127 case SHADER_OPCODE_SHADER_TIME_ADD:
2128 generate_shader_time_add(inst, src[0], src[1], src[2]);
2129 break;
2130
2131 case SHADER_OPCODE_UNTYPED_ATOMIC:
2132 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2133 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
2134 inst->mlen, !inst->dst.is_null());
2135 break;
2136
2137 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2138 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2139 brw_untyped_surface_read(p, dst, src[0], src[1],
2140 inst->mlen, src[2].ud);
2141 break;
2142
2143 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2144 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2145 brw_untyped_surface_write(p, src[0], src[1],
2146 inst->mlen, src[2].ud);
2147 break;
2148
2149 case SHADER_OPCODE_TYPED_ATOMIC:
2150 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2151 brw_typed_atomic(p, dst, src[0], src[1],
2152 src[2].ud, inst->mlen, !inst->dst.is_null());
2153 break;
2154
2155 case SHADER_OPCODE_TYPED_SURFACE_READ:
2156 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2157 brw_typed_surface_read(p, dst, src[0], src[1],
2158 inst->mlen, src[2].ud);
2159 break;
2160
2161 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2162 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2163 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud);
2164 break;
2165
2166 case SHADER_OPCODE_MEMORY_FENCE:
2167 brw_memory_fence(p, dst);
2168 break;
2169
2170 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2171 generate_set_simd4x2_offset(inst, dst, src[0]);
2172 break;
2173
2174 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
2175 brw_find_live_channel(p, dst);
2176 break;
2177
2178 case SHADER_OPCODE_BROADCAST:
2179 brw_broadcast(p, dst, src[0], src[1]);
2180 break;
2181
2182 case FS_OPCODE_SET_SAMPLE_ID:
2183 generate_set_sample_id(inst, dst, src[0], src[1]);
2184 break;
2185
2186 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2187 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2188 break;
2189
2190 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2191 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2192 generate_unpack_half_2x16_split(inst, dst, src[0]);
2193 break;
2194
2195 case FS_OPCODE_PLACEHOLDER_HALT:
2196 /* This is the place where the final HALT needs to be inserted if
2197 * we've emitted any discards. If not, this will emit no code.
2198 */
2199 if (!patch_discard_jumps_to_fb_writes()) {
2200 if (unlikely(debug_flag)) {
2201 annotation.ann_count--;
2202 }
2203 }
2204 break;
2205
2206 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2207 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2208 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2209 break;
2210
2211 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2212 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2213 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2214 break;
2215
2216 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2217 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2218 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2219 break;
2220
2221 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2222 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2223 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2224 break;
2225
2226 case CS_OPCODE_CS_TERMINATE:
2227 generate_cs_terminate(inst, src[0]);
2228 break;
2229
2230 case SHADER_OPCODE_BARRIER:
2231 generate_barrier(inst, src[0]);
2232 break;
2233
2234 case FS_OPCODE_PACK_STENCIL_REF:
2235 generate_stencil_ref_packing(inst, dst, src[0]);
2236 break;
2237
2238 default:
2239 unreachable("Unsupported opcode");
2240
2241 case SHADER_OPCODE_LOAD_PAYLOAD:
2242 unreachable("Should be lowered by lower_load_payload()");
2243 }
2244
2245 if (multiple_instructions_emitted)
2246 continue;
2247
2248 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2249 assert(p->next_insn_offset == last_insn_offset + 16 ||
2250 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2251 "emitting more than 1 instruction");
2252
2253 brw_inst *last = &p->store[last_insn_offset / 16];
2254
2255 if (inst->conditional_mod)
2256 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2257 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2258 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2259 }
2260 }
2261
2262 brw_set_uip_jip(p);
2263 annotation_finalize(&annotation, p->next_insn_offset);
2264
2265 #ifndef NDEBUG
2266 bool validated = brw_validate_instructions(p, start_offset, &annotation);
2267 #else
2268 if (unlikely(debug_flag))
2269 brw_validate_instructions(p, start_offset, &annotation);
2270 #endif
2271
2272 int before_size = p->next_insn_offset - start_offset;
2273 brw_compact_instructions(p, start_offset, annotation.ann_count,
2274 annotation.ann);
2275 int after_size = p->next_insn_offset - start_offset;
2276
2277 if (unlikely(debug_flag)) {
2278 fprintf(stderr, "Native code for %s\n"
2279 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2280 " bytes (%.0f%%)\n",
2281 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2282 spill_count, fill_count, promoted_constants, before_size, after_size,
2283 100.0f * (before_size - after_size) / before_size);
2284
2285 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2286 p->devinfo);
2287 ralloc_free(annotation.mem_ctx);
2288 }
2289 assert(validated);
2290
2291 compiler->shader_debug_log(log_data,
2292 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2293 "%d:%d spills:fills, Promoted %u constants, "
2294 "compacted %d to %d bytes.\n",
2295 stage_abbrev, dispatch_width, before_size / 16,
2296 loop_count, cfg->cycle_count, spill_count,
2297 fill_count, promoted_constants, before_size,
2298 after_size);
2299
2300 return start_offset;
2301 }
2302
2303 const unsigned *
2304 fs_generator::get_assembly(unsigned int *assembly_size)
2305 {
2306 return brw_get_program(p, assembly_size);
2307 }