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i965/fs: Simplify per-instruction compression control setup in generator.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "brw_eu.h"
31 #include "brw_fs.h"
32 #include "brw_cfg.h"
33 #include "brw_program.h"
34
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case ARF:
40 return BRW_ARCHITECTURE_REGISTER_FILE;
41 case FIXED_GRF:
42 case VGRF:
43 return BRW_GENERAL_REGISTER_FILE;
44 case MRF:
45 return BRW_MESSAGE_REGISTER_FILE;
46 case IMM:
47 return BRW_IMMEDIATE_VALUE;
48 case BAD_FILE:
49 case ATTR:
50 case UNIFORM:
51 unreachable("not reached");
52 }
53 return BRW_ARCHITECTURE_REGISTER_FILE;
54 }
55
56 static struct brw_reg
57 brw_reg_from_fs_reg(const struct brw_codegen *p,
58 fs_inst *inst, fs_reg *reg, unsigned gen)
59 {
60 struct brw_reg brw_reg;
61
62 switch (reg->file) {
63 case MRF:
64 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(gen));
65 /* Fallthrough */
66 case VGRF:
67 if (reg->stride == 0) {
68 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
69 } else if (!p->compressed &&
70 inst->exec_size * reg->stride * type_sz(reg->type) <= 32) {
71 brw_reg = brw_vecn_reg(inst->exec_size, brw_file_from_reg(reg),
72 reg->nr, 0);
73 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
74 inst->exec_size, reg->stride);
75 } else {
76 /* From the Haswell PRM:
77 *
78 * VertStride must be used to cross GRF register boundaries. This
79 * rule implies that elements within a 'Width' cannot cross GRF
80 * boundaries.
81 *
82 * So, for registers that are large enough, we have to split the exec
83 * size in two and trust the compression state to sort it out.
84 */
85 assert(inst->exec_size / 2 * reg->stride * type_sz(reg->type) <= 32);
86 brw_reg = brw_vecn_reg(inst->exec_size / 2, brw_file_from_reg(reg),
87 reg->nr, 0);
88 brw_reg = stride(brw_reg, inst->exec_size / 2 * reg->stride,
89 inst->exec_size / 2, reg->stride);
90 }
91
92 brw_reg = retype(brw_reg, reg->type);
93 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
94 brw_reg.abs = reg->abs;
95 brw_reg.negate = reg->negate;
96 break;
97 case ARF:
98 case FIXED_GRF:
99 case IMM:
100 brw_reg = reg->as_brw_reg();
101 break;
102 case BAD_FILE:
103 /* Probably unused. */
104 brw_reg = brw_null_reg();
105 break;
106 case ATTR:
107 case UNIFORM:
108 unreachable("not reached");
109 }
110
111 return brw_reg;
112 }
113
114 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
115 void *mem_ctx,
116 const void *key,
117 struct brw_stage_prog_data *prog_data,
118 unsigned promoted_constants,
119 bool runtime_check_aads_emit,
120 gl_shader_stage stage)
121
122 : compiler(compiler), log_data(log_data),
123 devinfo(compiler->devinfo), key(key),
124 prog_data(prog_data),
125 promoted_constants(promoted_constants),
126 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
127 stage(stage), mem_ctx(mem_ctx)
128 {
129 p = rzalloc(mem_ctx, struct brw_codegen);
130 brw_init_codegen(devinfo, p, mem_ctx);
131 }
132
133 fs_generator::~fs_generator()
134 {
135 }
136
137 class ip_record : public exec_node {
138 public:
139 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
140
141 ip_record(int ip)
142 {
143 this->ip = ip;
144 }
145
146 int ip;
147 };
148
149 bool
150 fs_generator::patch_discard_jumps_to_fb_writes()
151 {
152 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
153 return false;
154
155 int scale = brw_jump_scale(p->devinfo);
156
157 /* There is a somewhat strange undocumented requirement of using
158 * HALT, according to the simulator. If some channel has HALTed to
159 * a particular UIP, then by the end of the program, every channel
160 * must have HALTed to that UIP. Furthermore, the tracking is a
161 * stack, so you can't do the final halt of a UIP after starting
162 * halting to a new UIP.
163 *
164 * Symptoms of not emitting this instruction on actual hardware
165 * included GPU hangs and sparkly rendering on the piglit discard
166 * tests.
167 */
168 brw_inst *last_halt = gen6_HALT(p);
169 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
170 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
171
172 int ip = p->nr_insn;
173
174 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
175 brw_inst *patch = &p->store[patch_ip->ip];
176
177 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
178 /* HALT takes a half-instruction distance from the pre-incremented IP. */
179 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
180 }
181
182 this->discard_halt_patches.make_empty();
183 return true;
184 }
185
186 void
187 fs_generator::fire_fb_write(fs_inst *inst,
188 struct brw_reg payload,
189 struct brw_reg implied_header,
190 GLuint nr)
191 {
192 uint32_t msg_control;
193
194 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
195
196 if (devinfo->gen < 6) {
197 brw_push_insn_state(p);
198 brw_set_default_exec_size(p, BRW_EXECUTE_8);
199 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
200 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
201 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
202 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
203 brw_pop_insn_state(p);
204 }
205
206 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
207 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
208 else if (prog_data->dual_src_blend) {
209 if (!inst->force_sechalf)
210 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
211 else
212 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
213 } else if (inst->exec_size == 16)
214 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
215 else
216 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
217
218 uint32_t surf_index =
219 prog_data->binding_table.render_target_start + inst->target;
220
221 bool last_render_target = inst->eot ||
222 (prog_data->dual_src_blend && dispatch_width == 16);
223
224
225 brw_fb_WRITE(p,
226 dispatch_width,
227 payload,
228 implied_header,
229 msg_control,
230 surf_index,
231 nr,
232 0,
233 inst->eot,
234 last_render_target,
235 inst->header_size != 0);
236
237 brw_mark_surface_used(&prog_data->base, surf_index);
238 }
239
240 void
241 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
242 {
243 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
244 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
245 struct brw_reg implied_header;
246
247 if (devinfo->gen < 8 && !devinfo->is_haswell) {
248 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
249 }
250
251 if (inst->base_mrf >= 0)
252 payload = brw_message_reg(inst->base_mrf);
253
254 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
255 * move, here's g1.
256 */
257 if (inst->header_size != 0) {
258 brw_push_insn_state(p);
259 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
260 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
261 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
262 brw_set_default_flag_reg(p, 0, 0);
263
264 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
265 * present.
266 */
267 if (prog_data->uses_kill) {
268 struct brw_reg pixel_mask;
269
270 if (devinfo->gen >= 6)
271 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
272 else
273 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
274
275 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
276 }
277
278 if (devinfo->gen >= 6) {
279 brw_push_insn_state(p);
280 brw_set_default_exec_size(p, BRW_EXECUTE_16);
281 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
282 brw_MOV(p,
283 retype(payload, BRW_REGISTER_TYPE_UD),
284 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
285 brw_pop_insn_state(p);
286
287 if (inst->target > 0 && key->replicate_alpha) {
288 /* Set "Source0 Alpha Present to RenderTarget" bit in message
289 * header.
290 */
291 brw_OR(p,
292 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
293 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
294 brw_imm_ud(0x1 << 11));
295 }
296
297 if (inst->target > 0) {
298 /* Set the render target index for choosing BLEND_STATE. */
299 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
300 BRW_REGISTER_TYPE_UD),
301 brw_imm_ud(inst->target));
302 }
303
304 /* Set computes stencil to render target */
305 if (prog_data->computed_stencil) {
306 brw_OR(p,
307 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
308 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
309 brw_imm_ud(0x1 << 14));
310 }
311
312 implied_header = brw_null_reg();
313 } else {
314 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
315 }
316
317 brw_pop_insn_state(p);
318 } else {
319 implied_header = brw_null_reg();
320 }
321
322 if (!runtime_check_aads_emit) {
323 fire_fb_write(inst, payload, implied_header, inst->mlen);
324 } else {
325 /* This can only happen in gen < 6 */
326 assert(devinfo->gen < 6);
327
328 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
329
330 /* Check runtime bit to detect if we have to send AA data or not */
331 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
332 brw_AND(p,
333 v1_null_ud,
334 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
335 brw_imm_ud(1<<26));
336 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
337
338 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
339 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
340 {
341 /* Don't send AA data */
342 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
343 }
344 brw_land_fwd_jump(p, jmp);
345 fire_fb_write(inst, payload, implied_header, inst->mlen);
346 }
347 }
348
349 void
350 fs_generator::generate_mov_indirect(fs_inst *inst,
351 struct brw_reg dst,
352 struct brw_reg reg,
353 struct brw_reg indirect_byte_offset)
354 {
355 assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
356 assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
357
358 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
359
360 if (indirect_byte_offset.file == BRW_IMMEDIATE_VALUE) {
361 imm_byte_offset += indirect_byte_offset.ud;
362
363 reg.nr = imm_byte_offset / REG_SIZE;
364 reg.subnr = imm_byte_offset % REG_SIZE;
365 brw_MOV(p, dst, reg);
366 } else {
367 /* Prior to Broadwell, there are only 8 address registers. */
368 assert(inst->exec_size == 8 || devinfo->gen >= 8);
369
370 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
371 struct brw_reg addr = vec8(brw_address_reg(0));
372
373 /* The destination stride of an instruction (in bytes) must be greater
374 * than or equal to the size of the rest of the instruction. Since the
375 * address register is of type UW, we can't use a D-type instruction.
376 * In order to get around this, re retype to UW and use a stride.
377 */
378 indirect_byte_offset =
379 retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
380
381 struct brw_reg ind_src;
382 if (devinfo->gen < 8) {
383 /* From the Haswell PRM section "Register Region Restrictions":
384 *
385 * "The lower bits of the AddressImmediate must not overflow to
386 * change the register address. The lower 5 bits of Address
387 * Immediate when added to lower 5 bits of address register gives
388 * the sub-register offset. The upper bits of Address Immediate
389 * when added to upper bits of address register gives the register
390 * address. Any overflow from sub-register offset is dropped."
391 *
392 * This restriction is only listed in the Haswell PRM but emperical
393 * testing indicates that it applies on all older generations and is
394 * lifted on Broadwell.
395 *
396 * Since the indirect may cause us to cross a register boundary, this
397 * makes the base offset almost useless. We could try and do
398 * something clever where we use a actual base offset if
399 * base_offset % 32 == 0 but that would mean we were generating
400 * different code depending on the base offset. Instead, for the
401 * sake of consistency, we'll just do the add ourselves.
402 */
403 brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
404 ind_src = brw_VxH_indirect(0, 0);
405 } else {
406 brw_MOV(p, addr, indirect_byte_offset);
407 ind_src = brw_VxH_indirect(0, imm_byte_offset);
408 }
409
410 brw_inst *mov = brw_MOV(p, dst, retype(ind_src, dst.type));
411
412 if (devinfo->gen == 6 && dst.file == BRW_MESSAGE_REGISTER_FILE &&
413 !inst->get_next()->is_tail_sentinel() &&
414 ((fs_inst *)inst->get_next())->mlen > 0) {
415 /* From the Sandybridge PRM:
416 *
417 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
418 * instruction that “indexed/indirect” source AND is followed by a
419 * send, the instruction requires a “Switch”. This is to avoid
420 * race condition where send may dispatch before MRF is updated."
421 */
422 brw_inst_set_thread_control(devinfo, mov, BRW_THREAD_SWITCH);
423 }
424 }
425 }
426
427 void
428 fs_generator::generate_urb_read(fs_inst *inst,
429 struct brw_reg dst,
430 struct brw_reg header)
431 {
432 assert(header.file == BRW_GENERAL_REGISTER_FILE);
433 assert(header.type == BRW_REGISTER_TYPE_UD);
434
435 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
436 brw_set_dest(p, send, dst);
437 brw_set_src0(p, send, header);
438 brw_set_src1(p, send, brw_imm_ud(0u));
439
440 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
441 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
442
443 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
444 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
445
446 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
447 brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
448 brw_inst_set_header_present(p->devinfo, send, true);
449 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
450 }
451
452 void
453 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
454 {
455 brw_inst *insn;
456
457 insn = brw_next_insn(p, BRW_OPCODE_SEND);
458
459 brw_set_dest(p, insn, brw_null_reg());
460 brw_set_src0(p, insn, payload);
461 brw_set_src1(p, insn, brw_imm_d(0));
462
463 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
464 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
465
466 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
467 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
468 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
469
470 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
471 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
472 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
473
474 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
475 brw_inst_set_rlen(p->devinfo, insn, 0);
476 brw_inst_set_eot(p->devinfo, insn, inst->eot);
477 brw_inst_set_header_present(p->devinfo, insn, true);
478 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
479 }
480
481 void
482 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
483 {
484 struct brw_inst *insn;
485
486 insn = brw_next_insn(p, BRW_OPCODE_SEND);
487
488 brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
489 brw_set_src0(p, insn, payload);
490 brw_set_src1(p, insn, brw_imm_d(0));
491
492 /* Terminate a compute shader by sending a message to the thread spawner.
493 */
494 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
495 brw_inst_set_mlen(devinfo, insn, 1);
496 brw_inst_set_rlen(devinfo, insn, 0);
497 brw_inst_set_eot(devinfo, insn, inst->eot);
498 brw_inst_set_header_present(devinfo, insn, false);
499
500 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
501 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
502
503 /* Note that even though the thread has a URB resource associated with it,
504 * we set the "do not dereference URB" bit, because the URB resource is
505 * managed by the fixed-function unit, so it will free it automatically.
506 */
507 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
508
509 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
510 }
511
512 void
513 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
514 {
515 brw_barrier(p, src);
516 brw_WAIT(p);
517 }
518
519 void
520 fs_generator::generate_linterp(fs_inst *inst,
521 struct brw_reg dst, struct brw_reg *src)
522 {
523 /* PLN reads:
524 * / in SIMD16 \
525 * -----------------------------------
526 * | src1+0 | src1+1 | src1+2 | src1+3 |
527 * |-----------------------------------|
528 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
529 * -----------------------------------
530 *
531 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
532 *
533 * -----------------------------------
534 * | src1+0 | src1+1 | src1+2 | src1+3 |
535 * |-----------------------------------|
536 * |(x0, x1)|(y0, y1)| | | in SIMD8
537 * |-----------------------------------|
538 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
539 * -----------------------------------
540 *
541 * See also: emit_interpolation_setup_gen4().
542 */
543 struct brw_reg delta_x = src[0];
544 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
545 struct brw_reg interp = src[1];
546
547 if (devinfo->has_pln &&
548 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
549 brw_PLN(p, dst, interp, delta_x);
550 } else {
551 brw_LINE(p, brw_null_reg(), interp, delta_x);
552 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
553 }
554 }
555
556 void
557 fs_generator::generate_get_buffer_size(fs_inst *inst,
558 struct brw_reg dst,
559 struct brw_reg src,
560 struct brw_reg surf_index)
561 {
562 assert(devinfo->gen >= 7);
563 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
564
565 uint32_t simd_mode;
566 int rlen = 4;
567
568 switch (inst->exec_size) {
569 case 8:
570 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
571 break;
572 case 16:
573 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
574 break;
575 default:
576 unreachable("Invalid width for texture instruction");
577 }
578
579 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
580 rlen = 8;
581 dst = vec16(dst);
582 }
583
584 brw_SAMPLE(p,
585 retype(dst, BRW_REGISTER_TYPE_UW),
586 inst->base_mrf,
587 src,
588 surf_index.ud,
589 0,
590 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
591 rlen, /* response length */
592 inst->mlen,
593 inst->header_size > 0,
594 simd_mode,
595 BRW_SAMPLER_RETURN_FORMAT_SINT32);
596
597 brw_mark_surface_used(prog_data, surf_index.ud);
598 }
599
600 void
601 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
602 struct brw_reg surface_index,
603 struct brw_reg sampler_index)
604 {
605 int msg_type = -1;
606 uint32_t simd_mode;
607 uint32_t return_format;
608 bool is_combined_send = inst->eot;
609
610 switch (dst.type) {
611 case BRW_REGISTER_TYPE_D:
612 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
613 break;
614 case BRW_REGISTER_TYPE_UD:
615 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
616 break;
617 default:
618 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
619 break;
620 }
621
622 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
623 * is set as part of the message descriptor. On gen4, the PRM seems to
624 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
625 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
626 * gone from the message descriptor entirely and you just get UINT32 all
627 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
628 * just stomp it to UINT32 all the time.
629 */
630 if (inst->opcode == SHADER_OPCODE_TXS)
631 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
632
633 switch (inst->exec_size) {
634 case 8:
635 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
636 break;
637 case 16:
638 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
639 break;
640 default:
641 unreachable("Invalid width for texture instruction");
642 }
643
644 if (devinfo->gen >= 5) {
645 switch (inst->opcode) {
646 case SHADER_OPCODE_TEX:
647 if (inst->shadow_compare) {
648 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
649 } else {
650 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
651 }
652 break;
653 case FS_OPCODE_TXB:
654 if (inst->shadow_compare) {
655 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
656 } else {
657 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
658 }
659 break;
660 case SHADER_OPCODE_TXL:
661 if (inst->shadow_compare) {
662 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
663 } else {
664 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
665 }
666 break;
667 case SHADER_OPCODE_TXL_LZ:
668 assert(devinfo->gen >= 9);
669 if (inst->shadow_compare) {
670 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ;
671 } else {
672 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LZ;
673 }
674 break;
675 case SHADER_OPCODE_TXS:
676 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
677 break;
678 case SHADER_OPCODE_TXD:
679 if (inst->shadow_compare) {
680 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
681 assert(devinfo->gen >= 8 || devinfo->is_haswell);
682 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
683 } else {
684 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
685 }
686 break;
687 case SHADER_OPCODE_TXF:
688 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
689 break;
690 case SHADER_OPCODE_TXF_LZ:
691 assert(devinfo->gen >= 9);
692 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ;
693 break;
694 case SHADER_OPCODE_TXF_CMS_W:
695 assert(devinfo->gen >= 9);
696 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
697 break;
698 case SHADER_OPCODE_TXF_CMS:
699 if (devinfo->gen >= 7)
700 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
701 else
702 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
703 break;
704 case SHADER_OPCODE_TXF_UMS:
705 assert(devinfo->gen >= 7);
706 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
707 break;
708 case SHADER_OPCODE_TXF_MCS:
709 assert(devinfo->gen >= 7);
710 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
711 break;
712 case SHADER_OPCODE_LOD:
713 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
714 break;
715 case SHADER_OPCODE_TG4:
716 if (inst->shadow_compare) {
717 assert(devinfo->gen >= 7);
718 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
719 } else {
720 assert(devinfo->gen >= 6);
721 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
722 }
723 break;
724 case SHADER_OPCODE_TG4_OFFSET:
725 assert(devinfo->gen >= 7);
726 if (inst->shadow_compare) {
727 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
728 } else {
729 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
730 }
731 break;
732 case SHADER_OPCODE_SAMPLEINFO:
733 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
734 break;
735 default:
736 unreachable("not reached");
737 }
738 } else {
739 switch (inst->opcode) {
740 case SHADER_OPCODE_TEX:
741 /* Note that G45 and older determines shadow compare and dispatch width
742 * from message length for most messages.
743 */
744 if (inst->exec_size == 8) {
745 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
746 if (inst->shadow_compare) {
747 assert(inst->mlen == 6);
748 } else {
749 assert(inst->mlen <= 4);
750 }
751 } else {
752 if (inst->shadow_compare) {
753 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
754 assert(inst->mlen == 9);
755 } else {
756 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
757 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
758 }
759 }
760 break;
761 case FS_OPCODE_TXB:
762 if (inst->shadow_compare) {
763 assert(inst->exec_size == 8);
764 assert(inst->mlen == 6);
765 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
766 } else {
767 assert(inst->mlen == 9);
768 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
769 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
770 }
771 break;
772 case SHADER_OPCODE_TXL:
773 if (inst->shadow_compare) {
774 assert(inst->exec_size == 8);
775 assert(inst->mlen == 6);
776 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
777 } else {
778 assert(inst->mlen == 9);
779 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
780 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
781 }
782 break;
783 case SHADER_OPCODE_TXD:
784 /* There is no sample_d_c message; comparisons are done manually */
785 assert(inst->exec_size == 8);
786 assert(inst->mlen == 7 || inst->mlen == 10);
787 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
788 break;
789 case SHADER_OPCODE_TXF:
790 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
791 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
792 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
793 break;
794 case SHADER_OPCODE_TXS:
795 assert(inst->mlen == 3);
796 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
797 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
798 break;
799 default:
800 unreachable("not reached");
801 }
802 }
803 assert(msg_type != -1);
804
805 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
806 dst = vec16(dst);
807 }
808
809 assert(devinfo->gen < 7 || inst->header_size == 0 ||
810 src.file == BRW_GENERAL_REGISTER_FILE);
811
812 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
813
814 /* Load the message header if present. If there's a texture offset,
815 * we need to set it up explicitly and load the offset bitfield.
816 * Otherwise, we can use an implied move from g0 to the first message reg.
817 */
818 if (inst->header_size != 0) {
819 if (devinfo->gen < 6 && !inst->offset) {
820 /* Set up an implied move from g0 to the MRF. */
821 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
822 } else {
823 struct brw_reg header_reg;
824
825 if (devinfo->gen >= 7) {
826 header_reg = src;
827 } else {
828 assert(inst->base_mrf != -1);
829 header_reg = brw_message_reg(inst->base_mrf);
830 }
831
832 brw_push_insn_state(p);
833 brw_set_default_exec_size(p, BRW_EXECUTE_8);
834 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
835 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
836 /* Explicitly set up the message header by copying g0 to the MRF. */
837 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
838
839 if (inst->offset) {
840 /* Set the offset bits in DWord 2. */
841 brw_MOV(p, get_element_ud(header_reg, 2),
842 brw_imm_ud(inst->offset));
843 } else if (stage != MESA_SHADER_VERTEX &&
844 stage != MESA_SHADER_FRAGMENT) {
845 /* The vertex and fragment stages have g0.2 set to 0, so
846 * header0.2 is 0 when g0 is copied. Other stages may not, so we
847 * must set it to 0 to avoid setting undesirable bits in the
848 * message.
849 */
850 brw_MOV(p, get_element_ud(header_reg, 2), brw_imm_ud(0));
851 }
852
853 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
854 brw_pop_insn_state(p);
855 }
856 }
857
858 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
859 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
860 ? prog_data->binding_table.gather_texture_start
861 : prog_data->binding_table.texture_start;
862
863 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
864 sampler_index.file == BRW_IMMEDIATE_VALUE) {
865 uint32_t surface = surface_index.ud;
866 uint32_t sampler = sampler_index.ud;
867
868 brw_SAMPLE(p,
869 retype(dst, BRW_REGISTER_TYPE_UW),
870 inst->base_mrf,
871 src,
872 surface + base_binding_table_index,
873 sampler % 16,
874 msg_type,
875 inst->regs_written,
876 inst->mlen,
877 inst->header_size != 0,
878 simd_mode,
879 return_format);
880
881 brw_mark_surface_used(prog_data, surface + base_binding_table_index);
882 } else {
883 /* Non-const sampler index */
884
885 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
886 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
887 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
888
889 brw_push_insn_state(p);
890 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
891 brw_set_default_access_mode(p, BRW_ALIGN_1);
892
893 if (brw_regs_equal(&surface_reg, &sampler_reg)) {
894 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
895 } else {
896 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
897 brw_OR(p, addr, addr, surface_reg);
898 }
899 if (base_binding_table_index)
900 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
901 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
902
903 brw_pop_insn_state(p);
904
905 /* dst = send(offset, a0.0 | <descriptor>) */
906 brw_inst *insn = brw_send_indirect_message(
907 p, BRW_SFID_SAMPLER, dst, src, addr);
908 brw_set_sampler_message(p, insn,
909 0 /* surface */,
910 0 /* sampler */,
911 msg_type,
912 inst->regs_written,
913 inst->mlen /* mlen */,
914 inst->header_size != 0 /* header */,
915 simd_mode,
916 return_format);
917
918 /* visitor knows more than we do about the surface limit required,
919 * so has already done marking.
920 */
921 }
922
923 if (is_combined_send) {
924 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
925 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
926 }
927 }
928
929
930 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
931 * looking like:
932 *
933 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
934 *
935 * Ideally, we want to produce:
936 *
937 * DDX DDY
938 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
939 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
940 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
941 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
942 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
943 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
944 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
945 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
946 *
947 * and add another set of two more subspans if in 16-pixel dispatch mode.
948 *
949 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
950 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
951 * pair. But the ideal approximation may impose a huge performance cost on
952 * sample_d. On at least Haswell, sample_d instruction does some
953 * optimizations if the same LOD is used for all pixels in the subspan.
954 *
955 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
956 * appropriate swizzling.
957 */
958 void
959 fs_generator::generate_ddx(enum opcode opcode,
960 struct brw_reg dst, struct brw_reg src)
961 {
962 unsigned vstride, width;
963
964 if (opcode == FS_OPCODE_DDX_FINE) {
965 /* produce accurate derivatives */
966 vstride = BRW_VERTICAL_STRIDE_2;
967 width = BRW_WIDTH_2;
968 } else {
969 /* replicate the derivative at the top-left pixel to other pixels */
970 vstride = BRW_VERTICAL_STRIDE_4;
971 width = BRW_WIDTH_4;
972 }
973
974 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
975 src.negate, src.abs,
976 BRW_REGISTER_TYPE_F,
977 vstride,
978 width,
979 BRW_HORIZONTAL_STRIDE_0,
980 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
981 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
982 src.negate, src.abs,
983 BRW_REGISTER_TYPE_F,
984 vstride,
985 width,
986 BRW_HORIZONTAL_STRIDE_0,
987 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
988 brw_ADD(p, dst, src0, negate(src1));
989 }
990
991 /* The negate_value boolean is used to negate the derivative computation for
992 * FBOs, since they place the origin at the upper left instead of the lower
993 * left.
994 */
995 void
996 fs_generator::generate_ddy(enum opcode opcode,
997 struct brw_reg dst, struct brw_reg src)
998 {
999 if (opcode == FS_OPCODE_DDY_FINE) {
1000 /* produce accurate derivatives */
1001 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1002 src.negate, src.abs,
1003 BRW_REGISTER_TYPE_F,
1004 BRW_VERTICAL_STRIDE_4,
1005 BRW_WIDTH_4,
1006 BRW_HORIZONTAL_STRIDE_1,
1007 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
1008 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1009 src.negate, src.abs,
1010 BRW_REGISTER_TYPE_F,
1011 BRW_VERTICAL_STRIDE_4,
1012 BRW_WIDTH_4,
1013 BRW_HORIZONTAL_STRIDE_1,
1014 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
1015 brw_push_insn_state(p);
1016 brw_set_default_access_mode(p, BRW_ALIGN_16);
1017 brw_ADD(p, dst, negate(src0), src1);
1018 brw_pop_insn_state(p);
1019 } else {
1020 /* replicate the derivative at the top-left pixel to other pixels */
1021 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1022 src.negate, src.abs,
1023 BRW_REGISTER_TYPE_F,
1024 BRW_VERTICAL_STRIDE_4,
1025 BRW_WIDTH_4,
1026 BRW_HORIZONTAL_STRIDE_0,
1027 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1028 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1029 src.negate, src.abs,
1030 BRW_REGISTER_TYPE_F,
1031 BRW_VERTICAL_STRIDE_4,
1032 BRW_WIDTH_4,
1033 BRW_HORIZONTAL_STRIDE_0,
1034 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1035 brw_ADD(p, dst, negate(src0), src1);
1036 }
1037 }
1038
1039 void
1040 fs_generator::generate_discard_jump(fs_inst *inst)
1041 {
1042 assert(devinfo->gen >= 6);
1043
1044 /* This HALT will be patched up at FB write time to point UIP at the end of
1045 * the program, and at brw_uip_jip() JIP will be set to the end of the
1046 * current block (or the program).
1047 */
1048 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1049
1050 brw_push_insn_state(p);
1051 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1052 gen6_HALT(p);
1053 brw_pop_insn_state(p);
1054 }
1055
1056 void
1057 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1058 {
1059 assert(inst->mlen != 0);
1060
1061 brw_MOV(p,
1062 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1063 retype(src, BRW_REGISTER_TYPE_UD));
1064 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1065 inst->exec_size / 8, inst->offset);
1066 }
1067
1068 void
1069 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1070 {
1071 assert(inst->mlen != 0);
1072
1073 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1074 inst->exec_size / 8, inst->offset);
1075 }
1076
1077 void
1078 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1079 {
1080 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1081 }
1082
1083 void
1084 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1085 struct brw_reg dst,
1086 struct brw_reg index,
1087 struct brw_reg offset)
1088 {
1089 assert(inst->mlen != 0);
1090
1091 assert(index.file == BRW_IMMEDIATE_VALUE &&
1092 index.type == BRW_REGISTER_TYPE_UD);
1093 uint32_t surf_index = index.ud;
1094
1095 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1096 offset.type == BRW_REGISTER_TYPE_UD);
1097 uint32_t read_offset = offset.ud;
1098
1099 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1100 read_offset, surf_index);
1101 }
1102
1103 void
1104 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1105 struct brw_reg dst,
1106 struct brw_reg index,
1107 struct brw_reg offset)
1108 {
1109 assert(index.type == BRW_REGISTER_TYPE_UD);
1110
1111 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1112 /* Reference just the dword we need, to avoid angering validate_reg(). */
1113 offset = brw_vec1_grf(offset.nr, 0);
1114
1115 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1116 * the destination loaded consecutively from the same offset (which appears
1117 * in the first component, and the rest are ignored).
1118 */
1119 dst.width = BRW_WIDTH_4;
1120
1121 struct brw_reg src = offset;
1122 bool header_present = false;
1123
1124 if (devinfo->gen >= 9) {
1125 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1126 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1127 header_present = true;
1128
1129 brw_push_insn_state(p);
1130 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1131 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1132 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1133 brw_set_default_access_mode(p, BRW_ALIGN_1);
1134
1135 brw_MOV(p, get_element_ud(src, 2),
1136 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1137 brw_pop_insn_state(p);
1138 }
1139
1140 if (index.file == BRW_IMMEDIATE_VALUE) {
1141
1142 uint32_t surf_index = index.ud;
1143
1144 brw_push_insn_state(p);
1145 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1146 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1147 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1148 brw_inst_set_exec_size(devinfo, send, BRW_EXECUTE_4);
1149 brw_pop_insn_state(p);
1150
1151 brw_set_dest(p, send, dst);
1152 brw_set_src0(p, send, src);
1153 brw_set_sampler_message(p, send,
1154 surf_index,
1155 0, /* LD message ignores sampler unit */
1156 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1157 1, /* rlen */
1158 inst->mlen,
1159 header_present,
1160 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1161 0);
1162 } else {
1163
1164 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1165
1166 brw_push_insn_state(p);
1167 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1168 brw_set_default_access_mode(p, BRW_ALIGN_1);
1169
1170 /* a0.0 = surf_index & 0xff */
1171 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1172 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1173 brw_set_dest(p, insn_and, addr);
1174 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1175 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1176
1177 /* dst = send(payload, a0.0 | <descriptor>) */
1178 brw_inst *insn = brw_send_indirect_message(
1179 p, BRW_SFID_SAMPLER, dst, src, addr);
1180 brw_set_sampler_message(p, insn,
1181 0,
1182 0, /* LD message ignores sampler unit */
1183 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1184 1, /* rlen */
1185 inst->mlen,
1186 header_present,
1187 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1188 0);
1189
1190 brw_pop_insn_state(p);
1191 }
1192 }
1193
1194 void
1195 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst,
1196 struct brw_reg dst,
1197 struct brw_reg index)
1198 {
1199 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1200 assert(inst->header_size != 0);
1201 assert(inst->mlen);
1202
1203 assert(index.file == BRW_IMMEDIATE_VALUE &&
1204 index.type == BRW_REGISTER_TYPE_UD);
1205 uint32_t surf_index = index.ud;
1206
1207 uint32_t simd_mode, rlen, msg_type;
1208 if (dispatch_width == 16) {
1209 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1210 rlen = 8;
1211 } else {
1212 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1213 rlen = 4;
1214 }
1215
1216 if (devinfo->gen >= 5)
1217 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1218 else {
1219 /* We always use the SIMD16 message so that we only have to load U, and
1220 * not V or R.
1221 */
1222 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1223 assert(inst->mlen == 3);
1224 assert(inst->regs_written == 8);
1225 rlen = 8;
1226 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1227 }
1228
1229 struct brw_reg header = brw_vec8_grf(0, 0);
1230 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1231
1232 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1233 brw_inst_set_compression(devinfo, send, false);
1234 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1235 brw_set_src0(p, send, header);
1236 if (devinfo->gen < 6)
1237 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1238
1239 /* Our surface is set up as floats, regardless of what actual data is
1240 * stored in it.
1241 */
1242 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1243 brw_set_sampler_message(p, send,
1244 surf_index,
1245 0, /* sampler (unused) */
1246 msg_type,
1247 rlen,
1248 inst->mlen,
1249 inst->header_size != 0,
1250 simd_mode,
1251 return_format);
1252 }
1253
1254 void
1255 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1256 struct brw_reg dst,
1257 struct brw_reg index,
1258 struct brw_reg offset)
1259 {
1260 assert(devinfo->gen >= 7);
1261 /* Varying-offset pull constant loads are treated as a normal expression on
1262 * gen7, so the fact that it's a send message is hidden at the IR level.
1263 */
1264 assert(inst->header_size == 0);
1265 assert(!inst->mlen);
1266 assert(index.type == BRW_REGISTER_TYPE_UD);
1267
1268 uint32_t simd_mode, rlen, mlen;
1269 if (dispatch_width == 16) {
1270 mlen = 2;
1271 rlen = 8;
1272 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1273 } else {
1274 mlen = 1;
1275 rlen = 4;
1276 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1277 }
1278
1279 if (index.file == BRW_IMMEDIATE_VALUE) {
1280
1281 uint32_t surf_index = index.ud;
1282
1283 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1284 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1285 brw_set_src0(p, send, offset);
1286 brw_set_sampler_message(p, send,
1287 surf_index,
1288 0, /* LD message ignores sampler unit */
1289 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1290 rlen,
1291 mlen,
1292 false, /* no header */
1293 simd_mode,
1294 0);
1295
1296 } else {
1297
1298 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1299
1300 brw_push_insn_state(p);
1301 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1302 brw_set_default_access_mode(p, BRW_ALIGN_1);
1303
1304 /* a0.0 = surf_index & 0xff */
1305 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1306 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1307 brw_set_dest(p, insn_and, addr);
1308 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1309 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1310
1311 brw_pop_insn_state(p);
1312
1313 /* dst = send(offset, a0.0 | <descriptor>) */
1314 brw_inst *insn = brw_send_indirect_message(
1315 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1316 offset, addr);
1317 brw_set_sampler_message(p, insn,
1318 0 /* surface */,
1319 0 /* sampler */,
1320 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1321 rlen /* rlen */,
1322 mlen /* mlen */,
1323 false /* header */,
1324 simd_mode,
1325 0);
1326 }
1327 }
1328
1329 /**
1330 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1331 * into the flags register (f0.0).
1332 *
1333 * Used only on Gen6 and above.
1334 */
1335 void
1336 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1337 {
1338 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1339 struct brw_reg dispatch_mask;
1340
1341 if (devinfo->gen >= 6)
1342 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1343 else
1344 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1345
1346 brw_push_insn_state(p);
1347 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1348 brw_MOV(p, flags, dispatch_mask);
1349 brw_pop_insn_state(p);
1350 }
1351
1352 void
1353 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1354 struct brw_reg dst,
1355 struct brw_reg src,
1356 struct brw_reg msg_data,
1357 unsigned msg_type)
1358 {
1359 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1360
1361 brw_pixel_interpolator_query(p,
1362 retype(dst, BRW_REGISTER_TYPE_UW),
1363 src,
1364 inst->pi_noperspective,
1365 msg_type,
1366 msg_data,
1367 inst->mlen,
1368 inst->regs_written);
1369 }
1370
1371
1372 /**
1373 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1374 * sampler LD messages.
1375 *
1376 * We don't want to bake it into the send message's code generation because
1377 * that means we don't get a chance to schedule the instructions.
1378 */
1379 void
1380 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1381 struct brw_reg dst,
1382 struct brw_reg value)
1383 {
1384 assert(value.file == BRW_IMMEDIATE_VALUE);
1385
1386 brw_push_insn_state(p);
1387 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1388 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1389 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1390 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1391 brw_pop_insn_state(p);
1392 }
1393
1394 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1395 * the ADD instruction.
1396 */
1397 void
1398 fs_generator::generate_set_sample_id(fs_inst *inst,
1399 struct brw_reg dst,
1400 struct brw_reg src0,
1401 struct brw_reg src1)
1402 {
1403 assert(dst.type == BRW_REGISTER_TYPE_D ||
1404 dst.type == BRW_REGISTER_TYPE_UD);
1405 assert(src0.type == BRW_REGISTER_TYPE_D ||
1406 src0.type == BRW_REGISTER_TYPE_UD);
1407
1408 struct brw_reg reg = stride(src1, 1, 4, 0);
1409 if (devinfo->gen >= 8 || dispatch_width == 8) {
1410 brw_ADD(p, dst, src0, reg);
1411 } else if (dispatch_width == 16) {
1412 brw_push_insn_state(p);
1413 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1414 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1415 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1416 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1417 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1418 brw_pop_insn_state(p);
1419 }
1420 }
1421
1422 void
1423 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1424 struct brw_reg dst,
1425 struct brw_reg x,
1426 struct brw_reg y)
1427 {
1428 assert(devinfo->gen >= 7);
1429 assert(dst.type == BRW_REGISTER_TYPE_UD);
1430 assert(x.type == BRW_REGISTER_TYPE_F);
1431 assert(y.type == BRW_REGISTER_TYPE_F);
1432
1433 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1434 *
1435 * Because this instruction does not have a 16-bit floating-point type,
1436 * the destination data type must be Word (W).
1437 *
1438 * The destination must be DWord-aligned and specify a horizontal stride
1439 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1440 * each destination channel and the upper word is not modified.
1441 */
1442 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1443
1444 /* Give each 32-bit channel of dst the form below, where "." means
1445 * unchanged.
1446 * 0x....hhhh
1447 */
1448 brw_F32TO16(p, dst_w, y);
1449
1450 /* Now the form:
1451 * 0xhhhh0000
1452 */
1453 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1454
1455 /* And, finally the form of packHalf2x16's output:
1456 * 0xhhhhllll
1457 */
1458 brw_F32TO16(p, dst_w, x);
1459 }
1460
1461 void
1462 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1463 struct brw_reg dst,
1464 struct brw_reg src)
1465 {
1466 assert(devinfo->gen >= 7);
1467 assert(dst.type == BRW_REGISTER_TYPE_F);
1468 assert(src.type == BRW_REGISTER_TYPE_UD);
1469
1470 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1471 *
1472 * Because this instruction does not have a 16-bit floating-point type,
1473 * the source data type must be Word (W). The destination type must be
1474 * F (Float).
1475 */
1476 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1477
1478 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1479 * For the Y case, we wish to access only the upper word; therefore
1480 * a 16-bit subregister offset is needed.
1481 */
1482 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1483 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1484 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1485 src_w.subnr += 2;
1486
1487 brw_F16TO32(p, dst, src_w);
1488 }
1489
1490 void
1491 fs_generator::generate_shader_time_add(fs_inst *inst,
1492 struct brw_reg payload,
1493 struct brw_reg offset,
1494 struct brw_reg value)
1495 {
1496 assert(devinfo->gen >= 7);
1497 brw_push_insn_state(p);
1498 brw_set_default_mask_control(p, true);
1499
1500 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1501 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1502 offset.type);
1503 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1504 value.type);
1505
1506 assert(offset.file == BRW_IMMEDIATE_VALUE);
1507 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1508 value.width = BRW_WIDTH_1;
1509 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1510 value.vstride = BRW_VERTICAL_STRIDE_0;
1511 } else {
1512 assert(value.file == BRW_IMMEDIATE_VALUE);
1513 }
1514
1515 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1516 * case, and we don't really care about squeezing every bit of performance
1517 * out of this path, so we just emit the MOVs from here.
1518 */
1519 brw_MOV(p, payload_offset, offset);
1520 brw_MOV(p, payload_value, value);
1521 brw_shader_time_add(p, payload,
1522 prog_data->binding_table.shader_time_start);
1523 brw_pop_insn_state(p);
1524
1525 brw_mark_surface_used(prog_data,
1526 prog_data->binding_table.shader_time_start);
1527 }
1528
1529 void
1530 fs_generator::enable_debug(const char *shader_name)
1531 {
1532 debug_flag = true;
1533 this->shader_name = shader_name;
1534 }
1535
1536 int
1537 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1538 {
1539 /* align to 64 byte boundary. */
1540 while (p->next_insn_offset % 64)
1541 brw_NOP(p);
1542
1543 this->dispatch_width = dispatch_width;
1544
1545 int start_offset = p->next_insn_offset;
1546 int spill_count = 0, fill_count = 0;
1547 int loop_count = 0;
1548
1549 struct annotation_info annotation;
1550 memset(&annotation, 0, sizeof(annotation));
1551
1552 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1553 struct brw_reg src[3], dst;
1554 unsigned int last_insn_offset = p->next_insn_offset;
1555 bool multiple_instructions_emitted = false;
1556
1557 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1558 * "Register Region Restrictions" section: for BDW, SKL:
1559 *
1560 * "A POW/FDIV operation must not be followed by an instruction
1561 * that requires two destination registers."
1562 *
1563 * The documentation is often lacking annotations for Atom parts,
1564 * and empirically this affects CHV as well.
1565 */
1566 if (devinfo->gen >= 8 &&
1567 p->nr_insn > 1 &&
1568 brw_inst_opcode(devinfo, brw_last_inst) == BRW_OPCODE_MATH &&
1569 brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
1570 inst->dst.component_size(inst->exec_size) > REG_SIZE) {
1571 brw_NOP(p);
1572 last_insn_offset = p->next_insn_offset;
1573 }
1574
1575 if (unlikely(debug_flag))
1576 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1577
1578 /* If the instruction writes to more than one register, it needs to be
1579 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1580 * hardware figures out by itself what the right compression mode is,
1581 * but we still need to know whether the instruction is compressed to
1582 * set up the source register regions appropriately.
1583 *
1584 * XXX - This is wrong for instructions that write a single register but
1585 * read more than one which should strictly speaking be treated as
1586 * compressed. For instructions that don't write any registers it
1587 * relies on the destination being a null register of the correct
1588 * type and regioning so the instruction is considered compressed
1589 * or not accordingly.
1590 */
1591 p->compressed = inst->dst.component_size(inst->exec_size) > REG_SIZE;
1592 brw_set_default_compression(p, p->compressed);
1593 brw_set_default_group(p, inst->force_sechalf ? 8 : 0);
1594
1595 for (unsigned int i = 0; i < inst->sources; i++) {
1596 src[i] = brw_reg_from_fs_reg(p, inst, &inst->src[i], devinfo->gen);
1597
1598 /* The accumulator result appears to get used for the
1599 * conditional modifier generation. When negating a UD
1600 * value, there is a 33rd bit generated for the sign in the
1601 * accumulator value, so now you can't check, for example,
1602 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1603 */
1604 assert(!inst->conditional_mod ||
1605 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1606 !inst->src[i].negate);
1607 }
1608 dst = brw_reg_from_fs_reg(p, inst, &inst->dst, devinfo->gen);
1609
1610 brw_set_default_access_mode(p, BRW_ALIGN_1);
1611 brw_set_default_predicate_control(p, inst->predicate);
1612 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1613 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1614 brw_set_default_saturate(p, inst->saturate);
1615 brw_set_default_mask_control(p, inst->force_writemask_all);
1616 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1617 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1618
1619 assert(inst->force_writemask_all || inst->exec_size >= 8);
1620 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1621 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1622
1623 switch (inst->opcode) {
1624 case BRW_OPCODE_MOV:
1625 brw_MOV(p, dst, src[0]);
1626 break;
1627 case BRW_OPCODE_ADD:
1628 brw_ADD(p, dst, src[0], src[1]);
1629 break;
1630 case BRW_OPCODE_MUL:
1631 brw_MUL(p, dst, src[0], src[1]);
1632 break;
1633 case BRW_OPCODE_AVG:
1634 brw_AVG(p, dst, src[0], src[1]);
1635 break;
1636 case BRW_OPCODE_MACH:
1637 brw_MACH(p, dst, src[0], src[1]);
1638 break;
1639
1640 case BRW_OPCODE_LINE:
1641 brw_LINE(p, dst, src[0], src[1]);
1642 break;
1643
1644 case BRW_OPCODE_MAD:
1645 assert(devinfo->gen >= 6);
1646 brw_set_default_access_mode(p, BRW_ALIGN_16);
1647 brw_MAD(p, dst, src[0], src[1], src[2]);
1648 break;
1649
1650 case BRW_OPCODE_LRP:
1651 assert(devinfo->gen >= 6);
1652 brw_set_default_access_mode(p, BRW_ALIGN_16);
1653 brw_LRP(p, dst, src[0], src[1], src[2]);
1654 break;
1655
1656 case BRW_OPCODE_FRC:
1657 brw_FRC(p, dst, src[0]);
1658 break;
1659 case BRW_OPCODE_RNDD:
1660 brw_RNDD(p, dst, src[0]);
1661 break;
1662 case BRW_OPCODE_RNDE:
1663 brw_RNDE(p, dst, src[0]);
1664 break;
1665 case BRW_OPCODE_RNDZ:
1666 brw_RNDZ(p, dst, src[0]);
1667 break;
1668
1669 case BRW_OPCODE_AND:
1670 brw_AND(p, dst, src[0], src[1]);
1671 break;
1672 case BRW_OPCODE_OR:
1673 brw_OR(p, dst, src[0], src[1]);
1674 break;
1675 case BRW_OPCODE_XOR:
1676 brw_XOR(p, dst, src[0], src[1]);
1677 break;
1678 case BRW_OPCODE_NOT:
1679 brw_NOT(p, dst, src[0]);
1680 break;
1681 case BRW_OPCODE_ASR:
1682 brw_ASR(p, dst, src[0], src[1]);
1683 break;
1684 case BRW_OPCODE_SHR:
1685 brw_SHR(p, dst, src[0], src[1]);
1686 break;
1687 case BRW_OPCODE_SHL:
1688 brw_SHL(p, dst, src[0], src[1]);
1689 break;
1690 case BRW_OPCODE_F32TO16:
1691 assert(devinfo->gen >= 7);
1692 brw_F32TO16(p, dst, src[0]);
1693 break;
1694 case BRW_OPCODE_F16TO32:
1695 assert(devinfo->gen >= 7);
1696 brw_F16TO32(p, dst, src[0]);
1697 break;
1698 case BRW_OPCODE_CMP:
1699 if (inst->exec_size >= 16 && devinfo->gen == 7 && !devinfo->is_haswell &&
1700 dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1701 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1702 * implemented in the compiler is not sufficient. Overriding the
1703 * type when the destination is the null register is necessary but
1704 * not sufficient by itself.
1705 */
1706 assert(dst.nr == BRW_ARF_NULL);
1707 dst.type = BRW_REGISTER_TYPE_D;
1708 }
1709 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1710 break;
1711 case BRW_OPCODE_SEL:
1712 brw_SEL(p, dst, src[0], src[1]);
1713 break;
1714 case BRW_OPCODE_BFREV:
1715 assert(devinfo->gen >= 7);
1716 /* BFREV only supports UD type for src and dst. */
1717 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1718 retype(src[0], BRW_REGISTER_TYPE_UD));
1719 break;
1720 case BRW_OPCODE_FBH:
1721 assert(devinfo->gen >= 7);
1722 /* FBH only supports UD type for dst. */
1723 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1724 break;
1725 case BRW_OPCODE_FBL:
1726 assert(devinfo->gen >= 7);
1727 /* FBL only supports UD type for dst. */
1728 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1729 break;
1730 case BRW_OPCODE_CBIT:
1731 assert(devinfo->gen >= 7);
1732 /* CBIT only supports UD type for dst. */
1733 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1734 break;
1735 case BRW_OPCODE_ADDC:
1736 assert(devinfo->gen >= 7);
1737 brw_ADDC(p, dst, src[0], src[1]);
1738 break;
1739 case BRW_OPCODE_SUBB:
1740 assert(devinfo->gen >= 7);
1741 brw_SUBB(p, dst, src[0], src[1]);
1742 break;
1743 case BRW_OPCODE_MAC:
1744 brw_MAC(p, dst, src[0], src[1]);
1745 break;
1746
1747 case BRW_OPCODE_BFE:
1748 assert(devinfo->gen >= 7);
1749 brw_set_default_access_mode(p, BRW_ALIGN_16);
1750 brw_BFE(p, dst, src[0], src[1], src[2]);
1751 break;
1752
1753 case BRW_OPCODE_BFI1:
1754 assert(devinfo->gen >= 7);
1755 brw_BFI1(p, dst, src[0], src[1]);
1756 break;
1757 case BRW_OPCODE_BFI2:
1758 assert(devinfo->gen >= 7);
1759 brw_set_default_access_mode(p, BRW_ALIGN_16);
1760 brw_BFI2(p, dst, src[0], src[1], src[2]);
1761 break;
1762
1763 case BRW_OPCODE_IF:
1764 if (inst->src[0].file != BAD_FILE) {
1765 /* The instruction has an embedded compare (only allowed on gen6) */
1766 assert(devinfo->gen == 6);
1767 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1768 } else {
1769 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1770 }
1771 break;
1772
1773 case BRW_OPCODE_ELSE:
1774 brw_ELSE(p);
1775 break;
1776 case BRW_OPCODE_ENDIF:
1777 brw_ENDIF(p);
1778 break;
1779
1780 case BRW_OPCODE_DO:
1781 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1782 break;
1783
1784 case BRW_OPCODE_BREAK:
1785 brw_BREAK(p);
1786 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1787 break;
1788 case BRW_OPCODE_CONTINUE:
1789 brw_CONT(p);
1790 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1791 break;
1792
1793 case BRW_OPCODE_WHILE:
1794 brw_WHILE(p);
1795 loop_count++;
1796 break;
1797
1798 case SHADER_OPCODE_RCP:
1799 case SHADER_OPCODE_RSQ:
1800 case SHADER_OPCODE_SQRT:
1801 case SHADER_OPCODE_EXP2:
1802 case SHADER_OPCODE_LOG2:
1803 case SHADER_OPCODE_SIN:
1804 case SHADER_OPCODE_COS:
1805 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1806 if (devinfo->gen >= 6) {
1807 assert(inst->mlen == 0);
1808 assert(devinfo->gen >= 7 || inst->exec_size == 8);
1809 gen6_math(p, dst, brw_math_function(inst->opcode),
1810 src[0], brw_null_reg());
1811 } else {
1812 assert(inst->mlen >= 1);
1813 assert(devinfo->gen == 5 || devinfo->is_g4x || inst->exec_size == 8);
1814 gen4_math(p, dst,
1815 brw_math_function(inst->opcode),
1816 inst->base_mrf, src[0],
1817 BRW_MATH_PRECISION_FULL);
1818 }
1819 break;
1820 case SHADER_OPCODE_INT_QUOTIENT:
1821 case SHADER_OPCODE_INT_REMAINDER:
1822 case SHADER_OPCODE_POW:
1823 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1824 if (devinfo->gen >= 6) {
1825 assert(inst->mlen == 0);
1826 assert((devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) ||
1827 inst->exec_size == 8);
1828 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1829 } else {
1830 assert(inst->mlen >= 1);
1831 assert(inst->exec_size == 8);
1832 gen4_math(p, dst, brw_math_function(inst->opcode),
1833 inst->base_mrf, src[0],
1834 BRW_MATH_PRECISION_FULL);
1835 }
1836 break;
1837 case FS_OPCODE_CINTERP:
1838 brw_MOV(p, dst, src[0]);
1839 break;
1840 case FS_OPCODE_LINTERP:
1841 generate_linterp(inst, dst, src);
1842 break;
1843 case FS_OPCODE_PIXEL_X:
1844 assert(src[0].type == BRW_REGISTER_TYPE_UW);
1845 src[0].subnr = 0 * type_sz(src[0].type);
1846 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1847 break;
1848 case FS_OPCODE_PIXEL_Y:
1849 assert(src[0].type == BRW_REGISTER_TYPE_UW);
1850 src[0].subnr = 4 * type_sz(src[0].type);
1851 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1852 break;
1853 case FS_OPCODE_GET_BUFFER_SIZE:
1854 generate_get_buffer_size(inst, dst, src[0], src[1]);
1855 break;
1856 case SHADER_OPCODE_TEX:
1857 case FS_OPCODE_TXB:
1858 case SHADER_OPCODE_TXD:
1859 case SHADER_OPCODE_TXF:
1860 case SHADER_OPCODE_TXF_LZ:
1861 case SHADER_OPCODE_TXF_CMS:
1862 case SHADER_OPCODE_TXF_CMS_W:
1863 case SHADER_OPCODE_TXF_UMS:
1864 case SHADER_OPCODE_TXF_MCS:
1865 case SHADER_OPCODE_TXL:
1866 case SHADER_OPCODE_TXL_LZ:
1867 case SHADER_OPCODE_TXS:
1868 case SHADER_OPCODE_LOD:
1869 case SHADER_OPCODE_TG4:
1870 case SHADER_OPCODE_TG4_OFFSET:
1871 case SHADER_OPCODE_SAMPLEINFO:
1872 generate_tex(inst, dst, src[0], src[1], src[2]);
1873 break;
1874 case FS_OPCODE_DDX_COARSE:
1875 case FS_OPCODE_DDX_FINE:
1876 generate_ddx(inst->opcode, dst, src[0]);
1877 break;
1878 case FS_OPCODE_DDY_COARSE:
1879 case FS_OPCODE_DDY_FINE:
1880 generate_ddy(inst->opcode, dst, src[0]);
1881 break;
1882
1883 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1884 generate_scratch_write(inst, src[0]);
1885 spill_count++;
1886 break;
1887
1888 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1889 generate_scratch_read(inst, dst);
1890 fill_count++;
1891 break;
1892
1893 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1894 generate_scratch_read_gen7(inst, dst);
1895 fill_count++;
1896 break;
1897
1898 case SHADER_OPCODE_MOV_INDIRECT:
1899 generate_mov_indirect(inst, dst, src[0], src[1]);
1900 break;
1901
1902 case SHADER_OPCODE_URB_READ_SIMD8:
1903 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1904 generate_urb_read(inst, dst, src[0]);
1905 break;
1906
1907 case SHADER_OPCODE_URB_WRITE_SIMD8:
1908 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1909 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1910 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1911 generate_urb_write(inst, src[0]);
1912 break;
1913
1914 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1915 assert(inst->force_writemask_all);
1916 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1917 break;
1918
1919 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1920 assert(inst->force_writemask_all);
1921 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1922 break;
1923
1924 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
1925 generate_varying_pull_constant_load_gen4(inst, dst, src[0]);
1926 break;
1927
1928 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1929 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1930 break;
1931
1932 case FS_OPCODE_REP_FB_WRITE:
1933 case FS_OPCODE_FB_WRITE:
1934 generate_fb_write(inst, src[0]);
1935 break;
1936
1937 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1938 generate_mov_dispatch_to_flags(inst);
1939 break;
1940
1941 case FS_OPCODE_DISCARD_JUMP:
1942 generate_discard_jump(inst);
1943 break;
1944
1945 case SHADER_OPCODE_SHADER_TIME_ADD:
1946 generate_shader_time_add(inst, src[0], src[1], src[2]);
1947 break;
1948
1949 case SHADER_OPCODE_UNTYPED_ATOMIC:
1950 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1951 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
1952 inst->mlen, !inst->dst.is_null());
1953 break;
1954
1955 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1956 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1957 brw_untyped_surface_read(p, dst, src[0], src[1],
1958 inst->mlen, src[2].ud);
1959 break;
1960
1961 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1962 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1963 brw_untyped_surface_write(p, src[0], src[1],
1964 inst->mlen, src[2].ud);
1965 break;
1966
1967 case SHADER_OPCODE_TYPED_ATOMIC:
1968 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1969 brw_typed_atomic(p, dst, src[0], src[1],
1970 src[2].ud, inst->mlen, !inst->dst.is_null());
1971 break;
1972
1973 case SHADER_OPCODE_TYPED_SURFACE_READ:
1974 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1975 brw_typed_surface_read(p, dst, src[0], src[1],
1976 inst->mlen, src[2].ud);
1977 break;
1978
1979 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1980 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1981 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud);
1982 break;
1983
1984 case SHADER_OPCODE_MEMORY_FENCE:
1985 brw_memory_fence(p, dst);
1986 break;
1987
1988 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1989 generate_set_simd4x2_offset(inst, dst, src[0]);
1990 break;
1991
1992 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
1993 brw_find_live_channel(p, dst);
1994 break;
1995
1996 case SHADER_OPCODE_BROADCAST:
1997 brw_broadcast(p, dst, src[0], src[1]);
1998 break;
1999
2000 case FS_OPCODE_SET_SAMPLE_ID:
2001 generate_set_sample_id(inst, dst, src[0], src[1]);
2002 break;
2003
2004 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2005 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2006 break;
2007
2008 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2009 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2010 generate_unpack_half_2x16_split(inst, dst, src[0]);
2011 break;
2012
2013 case FS_OPCODE_PLACEHOLDER_HALT:
2014 /* This is the place where the final HALT needs to be inserted if
2015 * we've emitted any discards. If not, this will emit no code.
2016 */
2017 if (!patch_discard_jumps_to_fb_writes()) {
2018 if (unlikely(debug_flag)) {
2019 annotation.ann_count--;
2020 }
2021 }
2022 break;
2023
2024 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2025 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2026 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2027 break;
2028
2029 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2030 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2031 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2032 break;
2033
2034 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2035 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2036 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2037 break;
2038
2039 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2040 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2041 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2042 break;
2043
2044 case CS_OPCODE_CS_TERMINATE:
2045 generate_cs_terminate(inst, src[0]);
2046 break;
2047
2048 case SHADER_OPCODE_BARRIER:
2049 generate_barrier(inst, src[0]);
2050 break;
2051
2052 default:
2053 unreachable("Unsupported opcode");
2054
2055 case SHADER_OPCODE_LOAD_PAYLOAD:
2056 unreachable("Should be lowered by lower_load_payload()");
2057 }
2058
2059 if (multiple_instructions_emitted)
2060 continue;
2061
2062 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2063 assert(p->next_insn_offset == last_insn_offset + 16 ||
2064 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2065 "emitting more than 1 instruction");
2066
2067 brw_inst *last = &p->store[last_insn_offset / 16];
2068
2069 if (inst->conditional_mod)
2070 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2071 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2072 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2073 }
2074 }
2075
2076 brw_set_uip_jip(p);
2077 annotation_finalize(&annotation, p->next_insn_offset);
2078
2079 #ifndef NDEBUG
2080 bool validated = brw_validate_instructions(p, start_offset, &annotation);
2081 #else
2082 if (unlikely(debug_flag))
2083 brw_validate_instructions(p, start_offset, &annotation);
2084 #endif
2085
2086 int before_size = p->next_insn_offset - start_offset;
2087 brw_compact_instructions(p, start_offset, annotation.ann_count,
2088 annotation.ann);
2089 int after_size = p->next_insn_offset - start_offset;
2090
2091 if (unlikely(debug_flag)) {
2092 fprintf(stderr, "Native code for %s\n"
2093 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2094 " bytes (%.0f%%)\n",
2095 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2096 spill_count, fill_count, promoted_constants, before_size, after_size,
2097 100.0f * (before_size - after_size) / before_size);
2098
2099 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2100 p->devinfo);
2101 ralloc_free(annotation.mem_ctx);
2102 }
2103 assert(validated);
2104
2105 compiler->shader_debug_log(log_data,
2106 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2107 "%d:%d spills:fills, Promoted %u constants, "
2108 "compacted %d to %d bytes.",
2109 _mesa_shader_stage_to_abbrev(stage),
2110 dispatch_width, before_size / 16,
2111 loop_count, cfg->cycle_count, spill_count,
2112 fill_count, promoted_constants, before_size,
2113 after_size);
2114
2115 return start_offset;
2116 }
2117
2118 const unsigned *
2119 fs_generator::get_assembly(unsigned int *assembly_size)
2120 {
2121 return brw_get_program(p, assembly_size);
2122 }