2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
31 #include "main/macros.h"
32 #include "brw_context.h"
39 fs_generator::fs_generator(struct brw_context
*brw
,
41 const struct brw_wm_prog_key
*key
,
42 struct brw_wm_prog_data
*prog_data
,
43 struct gl_shader_program
*shader_prog
,
44 struct gl_fragment_program
*fp
,
45 bool runtime_check_aads_emit
,
48 : brw(brw
), stage(MESA_SHADER_FRAGMENT
), key(key
),
49 prog_data(&prog_data
->base
), shader_prog(shader_prog
),
50 prog(&fp
->Base
), runtime_check_aads_emit(runtime_check_aads_emit
),
51 debug_flag(debug_flag
), mem_ctx(mem_ctx
)
55 p
= rzalloc(mem_ctx
, struct brw_compile
);
56 brw_init_compile(brw
, p
, mem_ctx
);
59 fs_generator::~fs_generator()
64 fs_generator::patch_discard_jumps_to_fb_writes()
66 if (brw
->gen
< 6 || this->discard_halt_patches
.is_empty())
69 int scale
= brw_jump_scale(brw
);
71 /* There is a somewhat strange undocumented requirement of using
72 * HALT, according to the simulator. If some channel has HALTed to
73 * a particular UIP, then by the end of the program, every channel
74 * must have HALTed to that UIP. Furthermore, the tracking is a
75 * stack, so you can't do the final halt of a UIP after starting
76 * halting to a new UIP.
78 * Symptoms of not emitting this instruction on actual hardware
79 * included GPU hangs and sparkly rendering on the piglit discard
82 brw_inst
*last_halt
= gen6_HALT(p
);
83 brw_inst_set_uip(brw
, last_halt
, 1 * scale
);
84 brw_inst_set_jip(brw
, last_halt
, 1 * scale
);
88 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
89 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
91 assert(brw_inst_opcode(brw
, patch
) == BRW_OPCODE_HALT
);
92 /* HALT takes a half-instruction distance from the pre-incremented IP. */
93 brw_inst_set_uip(brw
, patch
, (ip
- patch_ip
->ip
) * scale
);
96 this->discard_halt_patches
.make_empty();
101 fs_generator::fire_fb_write(fs_inst
*inst
,
102 struct brw_reg payload
,
103 struct brw_reg implied_header
,
106 uint32_t msg_control
;
108 assert(stage
== MESA_SHADER_FRAGMENT
);
109 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
112 brw_push_insn_state(p
);
113 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
114 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
115 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
116 brw_MOV(p
, offset(payload
, 1), brw_vec8_grf(1, 0));
117 brw_pop_insn_state(p
);
120 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
)
121 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
122 else if (prog_data
->dual_src_blend
)
123 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
124 else if (dispatch_width
== 16)
125 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
127 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
129 uint32_t surf_index
=
130 prog_data
->binding_table
.render_target_start
+ inst
->target
;
141 inst
->header_present
);
143 brw_mark_surface_used(&prog_data
->base
, surf_index
);
147 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
149 assert(stage
== MESA_SHADER_FRAGMENT
);
150 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
151 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
152 struct brw_reg implied_header
;
154 if (inst
->base_mrf
>= 0)
155 payload
= brw_message_reg(inst
->base_mrf
);
157 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
160 if (inst
->header_present
) {
161 brw_push_insn_state(p
);
162 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
163 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
164 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
165 brw_set_default_flag_reg(p
, 0, 0);
167 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
170 if (prog_data
->uses_kill
|| key
->alpha_test_func
) {
171 struct brw_reg pixel_mask
;
174 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
176 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
178 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
182 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
184 retype(payload
, BRW_REGISTER_TYPE_UD
),
185 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
186 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
188 if (inst
->target
> 0 && key
->replicate_alpha
) {
189 /* Set "Source0 Alpha Present to RenderTarget" bit in message
193 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
194 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
195 brw_imm_ud(0x1 << 11));
198 if (inst
->target
> 0) {
199 /* Set the render target index for choosing BLEND_STATE. */
200 brw_MOV(p
, retype(vec1(suboffset(payload
, 2)),
201 BRW_REGISTER_TYPE_UD
),
202 brw_imm_ud(inst
->target
));
205 implied_header
= brw_null_reg();
207 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
210 brw_pop_insn_state(p
);
212 implied_header
= brw_null_reg();
215 if (!runtime_check_aads_emit
) {
216 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
218 /* This can only happen in gen < 6 */
219 assert(brw
->gen
< 6);
221 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
223 /* Check runtime bit to detect if we have to send AA data or not */
224 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
227 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
229 brw_inst_set_cond_modifier(brw
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
231 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
232 brw_inst_set_exec_size(brw
, brw_last_inst
, BRW_EXECUTE_1
);
234 /* Don't send AA data */
235 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
237 brw_land_fwd_jump(p
, jmp
);
238 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
243 fs_generator::generate_blorp_fb_write(fs_inst
*inst
)
246 16 /* dispatch_width */,
247 brw_message_reg(inst
->base_mrf
),
248 brw_reg_from_fs_reg(&inst
->src
[0]),
249 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
254 inst
->header_present
);
257 /* Computes the integer pixel x,y values from the origin.
259 * This is the basis of gl_FragCoord computation, but is also used
260 * pre-gen6 for computing the deltas from v0 for computing
264 fs_generator::generate_pixel_xy(struct brw_reg dst
, bool is_x
)
266 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
268 struct brw_reg deltas
;
271 src
= stride(suboffset(g1_uw
, 4), 2, 4, 0);
272 deltas
= brw_imm_v(0x10101010);
274 src
= stride(suboffset(g1_uw
, 5), 2, 4, 0);
275 deltas
= brw_imm_v(0x11001100);
278 if (dispatch_width
== 16) {
282 /* We do this SIMD8 or SIMD16, but since the destination is UW we
283 * don't do compression in the SIMD16 case.
285 brw_push_insn_state(p
);
286 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
287 brw_ADD(p
, dst
, src
, deltas
);
288 brw_pop_insn_state(p
);
292 fs_generator::generate_linterp(fs_inst
*inst
,
293 struct brw_reg dst
, struct brw_reg
*src
)
295 struct brw_reg delta_x
= src
[0];
296 struct brw_reg delta_y
= src
[1];
297 struct brw_reg interp
= src
[2];
300 delta_y
.nr
== delta_x
.nr
+ 1 &&
301 (brw
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
302 brw_PLN(p
, dst
, interp
, delta_x
);
304 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
305 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
310 fs_generator::generate_math_gen6(fs_inst
*inst
,
315 int op
= brw_math_function(inst
->opcode
);
316 bool binop
= src1
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
;
318 if (dispatch_width
== 8) {
319 gen6_math(p
, dst
, op
, src0
, src1
);
320 } else if (dispatch_width
== 16) {
321 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
322 gen6_math(p
, firsthalf(dst
), op
, firsthalf(src0
), firsthalf(src1
));
323 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
324 gen6_math(p
, sechalf(dst
), op
, sechalf(src0
),
325 binop
? sechalf(src1
) : brw_null_reg());
326 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
331 fs_generator::generate_math_gen4(fs_inst
*inst
,
335 int op
= brw_math_function(inst
->opcode
);
337 assert(inst
->mlen
>= 1);
339 if (dispatch_width
== 8) {
343 BRW_MATH_PRECISION_FULL
);
344 } else if (dispatch_width
== 16) {
345 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
346 gen4_math(p
, firsthalf(dst
),
348 inst
->base_mrf
, firsthalf(src
),
349 BRW_MATH_PRECISION_FULL
);
350 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
351 gen4_math(p
, sechalf(dst
),
353 inst
->base_mrf
+ 1, sechalf(src
),
354 BRW_MATH_PRECISION_FULL
);
356 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
361 fs_generator::generate_math_g45(fs_inst
*inst
,
365 if (inst
->opcode
== SHADER_OPCODE_POW
||
366 inst
->opcode
== SHADER_OPCODE_INT_QUOTIENT
||
367 inst
->opcode
== SHADER_OPCODE_INT_REMAINDER
) {
368 generate_math_gen4(inst
, dst
, src
);
372 int op
= brw_math_function(inst
->opcode
);
374 assert(inst
->mlen
>= 1);
379 BRW_MATH_PRECISION_FULL
);
383 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
384 struct brw_reg sampler_index
)
389 uint32_t return_format
;
392 case BRW_REGISTER_TYPE_D
:
393 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
395 case BRW_REGISTER_TYPE_UD
:
396 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
399 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
403 switch (inst
->exec_size
) {
405 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
408 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
411 unreachable("Invalid width for texture instruction");
415 switch (inst
->opcode
) {
416 case SHADER_OPCODE_TEX
:
417 if (inst
->shadow_compare
) {
418 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
420 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
424 if (inst
->shadow_compare
) {
425 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
427 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
430 case SHADER_OPCODE_TXL
:
431 if (inst
->shadow_compare
) {
432 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
434 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
437 case SHADER_OPCODE_TXS
:
438 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
440 case SHADER_OPCODE_TXD
:
441 if (inst
->shadow_compare
) {
442 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
443 assert(brw
->gen
>= 8 || brw
->is_haswell
);
444 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
446 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
449 case SHADER_OPCODE_TXF
:
450 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
452 case SHADER_OPCODE_TXF_CMS
:
454 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
456 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
458 case SHADER_OPCODE_TXF_UMS
:
459 assert(brw
->gen
>= 7);
460 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
462 case SHADER_OPCODE_TXF_MCS
:
463 assert(brw
->gen
>= 7);
464 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
466 case SHADER_OPCODE_LOD
:
467 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
469 case SHADER_OPCODE_TG4
:
470 if (inst
->shadow_compare
) {
471 assert(brw
->gen
>= 7);
472 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
474 assert(brw
->gen
>= 6);
475 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
478 case SHADER_OPCODE_TG4_OFFSET
:
479 assert(brw
->gen
>= 7);
480 if (inst
->shadow_compare
) {
481 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
483 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
487 unreachable("not reached");
490 switch (inst
->opcode
) {
491 case SHADER_OPCODE_TEX
:
492 /* Note that G45 and older determines shadow compare and dispatch width
493 * from message length for most messages.
495 assert(dispatch_width
== 8);
496 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
497 if (inst
->shadow_compare
) {
498 assert(inst
->mlen
== 6);
500 assert(inst
->mlen
<= 4);
504 if (inst
->shadow_compare
) {
505 assert(inst
->mlen
== 6);
506 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
508 assert(inst
->mlen
== 9);
509 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
510 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
513 case SHADER_OPCODE_TXL
:
514 if (inst
->shadow_compare
) {
515 assert(inst
->mlen
== 6);
516 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
518 assert(inst
->mlen
== 9);
519 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
520 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
523 case SHADER_OPCODE_TXD
:
524 /* There is no sample_d_c message; comparisons are done manually */
525 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
526 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
528 case SHADER_OPCODE_TXF
:
529 assert(inst
->mlen
== 9);
530 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
531 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
533 case SHADER_OPCODE_TXS
:
534 assert(inst
->mlen
== 3);
535 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
536 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
539 unreachable("not reached");
542 assert(msg_type
!= -1);
544 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
549 assert(brw
->gen
< 7 || !inst
->header_present
||
550 src
.file
== BRW_GENERAL_REGISTER_FILE
);
552 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
554 /* Load the message header if present. If there's a texture offset,
555 * we need to set it up explicitly and load the offset bitfield.
556 * Otherwise, we can use an implied move from g0 to the first message reg.
558 if (inst
->header_present
) {
559 if (brw
->gen
< 6 && !inst
->texture_offset
) {
560 /* Set up an implied move from g0 to the MRF. */
561 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
563 struct brw_reg header_reg
;
568 assert(inst
->base_mrf
!= -1);
569 header_reg
= brw_message_reg(inst
->base_mrf
);
572 brw_push_insn_state(p
);
573 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
574 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
575 /* Explicitly set up the message header by copying g0 to the MRF. */
576 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
578 if (inst
->texture_offset
) {
579 /* Set the offset bits in DWord 2. */
580 brw_MOV(p
, get_element_ud(header_reg
, 2),
581 brw_imm_ud(inst
->texture_offset
));
584 brw_adjust_sampler_state_pointer(p
, header_reg
, sampler_index
, dst
);
585 brw_pop_insn_state(p
);
589 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
590 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
591 ? prog_data
->binding_table
.gather_texture_start
592 : prog_data
->binding_table
.texture_start
;
594 if (sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
595 uint32_t sampler
= sampler_index
.dw1
.ud
;
598 retype(dst
, BRW_REGISTER_TYPE_UW
),
601 sampler
+ base_binding_table_index
,
606 inst
->header_present
,
610 brw_mark_surface_used(prog_data
, sampler
+ base_binding_table_index
);
612 /* Non-const sampler index */
613 /* Note: this clobbers `dst` as a temporary before emitting the send */
615 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
616 struct brw_reg temp
= vec1(retype(dst
, BRW_REGISTER_TYPE_UD
));
618 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
620 brw_push_insn_state(p
);
621 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
622 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
624 /* Some care required: `sampler` and `temp` may alias:
625 * addr = sampler & 0xff
626 * temp = (sampler << 8) & 0xf00
629 brw_ADD(p
, addr
, sampler_reg
, brw_imm_ud(base_binding_table_index
));
630 brw_SHL(p
, temp
, sampler_reg
, brw_imm_ud(8u));
631 brw_AND(p
, temp
, temp
, brw_imm_ud(0x0f00));
632 brw_AND(p
, addr
, addr
, brw_imm_ud(0x0ff));
633 brw_OR(p
, addr
, addr
, temp
);
635 /* a0.0 |= <descriptor> */
636 brw_inst
*insn_or
= brw_next_insn(p
, BRW_OPCODE_OR
);
637 brw_set_sampler_message(p
, insn_or
,
642 inst
->mlen
/* mlen */,
643 inst
->header_present
/* header */,
646 brw_inst_set_exec_size(p
->brw
, insn_or
, BRW_EXECUTE_1
);
647 brw_inst_set_src1_reg_type(p
->brw
, insn_or
, BRW_REGISTER_TYPE_UD
);
648 brw_set_src0(p
, insn_or
, addr
);
649 brw_set_dest(p
, insn_or
, addr
);
652 /* dst = send(offset, a0.0) */
653 brw_inst
*insn_send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
654 brw_set_dest(p
, insn_send
, dst
);
655 brw_set_src0(p
, insn_send
, src
);
656 brw_set_indirect_send_descriptor(p
, insn_send
, BRW_SFID_SAMPLER
, addr
);
658 brw_pop_insn_state(p
);
660 /* visitor knows more than we do about the surface limit required,
661 * so has already done marking.
667 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
670 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
672 * Ideally, we want to produce:
675 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
676 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
677 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
678 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
679 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
680 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
681 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
682 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
684 * and add another set of two more subspans if in 16-pixel dispatch mode.
686 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
687 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
688 * pair. But the ideal approximation may impose a huge performance cost on
689 * sample_d. On at least Haswell, sample_d instruction does some
690 * optimizations if the same LOD is used for all pixels in the subspan.
692 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
693 * appropriate swizzling.
696 fs_generator::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
697 struct brw_reg quality
)
699 unsigned vstride
, width
;
700 assert(quality
.file
== BRW_IMMEDIATE_VALUE
);
701 assert(quality
.type
== BRW_REGISTER_TYPE_D
);
703 assert(stage
== MESA_SHADER_FRAGMENT
);
704 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
706 int quality_value
= quality
.dw1
.d
;
708 if (quality_value
== BRW_DERIVATIVE_FINE
||
709 (key
->high_quality_derivatives
&& quality_value
!= BRW_DERIVATIVE_COARSE
)) {
710 /* produce accurate derivatives */
711 vstride
= BRW_VERTICAL_STRIDE_2
;
715 /* replicate the derivative at the top-left pixel to other pixels */
716 vstride
= BRW_VERTICAL_STRIDE_4
;
720 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
724 BRW_HORIZONTAL_STRIDE_0
,
725 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
726 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
730 BRW_HORIZONTAL_STRIDE_0
,
731 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
732 brw_ADD(p
, dst
, src0
, negate(src1
));
735 /* The negate_value boolean is used to negate the derivative computation for
736 * FBOs, since they place the origin at the upper left instead of the lower
740 fs_generator::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
741 struct brw_reg quality
, bool negate_value
)
743 assert(quality
.file
== BRW_IMMEDIATE_VALUE
);
744 assert(quality
.type
== BRW_REGISTER_TYPE_D
);
746 assert(stage
== MESA_SHADER_FRAGMENT
);
747 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
749 int quality_value
= quality
.dw1
.d
;
751 if (quality_value
== BRW_DERIVATIVE_FINE
||
752 (key
->high_quality_derivatives
&& quality_value
!= BRW_DERIVATIVE_COARSE
)) {
753 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
754 * Region Restrictions):
756 * In Align16 access mode, SIMD16 is not allowed for DW operations
757 * and SIMD8 is not allowed for DF operations.
759 * In this context, "DW operations" means "operations acting on 32-bit
760 * values", so it includes operations on floats.
762 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
763 * (Instruction Compression -> Rules and Restrictions):
765 * A compressed instruction must be in Align1 access mode. Align16
766 * mode instructions cannot be compressed.
768 * Similar text exists in the g45 PRM.
770 * On these platforms, if we're building a SIMD16 shader, we need to
771 * manually unroll to a pair of SIMD8 instructions.
773 bool unroll_to_simd8
=
774 (dispatch_width
== 16 &&
775 (brw
->gen
== 4 || (brw
->gen
== 7 && !brw
->is_haswell
)));
777 /* produce accurate derivatives */
778 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
780 BRW_VERTICAL_STRIDE_4
,
782 BRW_HORIZONTAL_STRIDE_1
,
783 BRW_SWIZZLE_XYXY
, WRITEMASK_XYZW
);
784 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
786 BRW_VERTICAL_STRIDE_4
,
788 BRW_HORIZONTAL_STRIDE_1
,
789 BRW_SWIZZLE_ZWZW
, WRITEMASK_XYZW
);
790 brw_push_insn_state(p
);
791 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
792 if (unroll_to_simd8
) {
793 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
795 brw_ADD(p
, firsthalf(dst
), firsthalf(src1
), negate(firsthalf(src0
)));
796 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
797 brw_ADD(p
, sechalf(dst
), sechalf(src1
), negate(sechalf(src0
)));
799 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), negate(firsthalf(src1
)));
800 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
801 brw_ADD(p
, sechalf(dst
), sechalf(src0
), negate(sechalf(src1
)));
805 brw_ADD(p
, dst
, src1
, negate(src0
));
807 brw_ADD(p
, dst
, src0
, negate(src1
));
809 brw_pop_insn_state(p
);
811 /* replicate the derivative at the top-left pixel to other pixels */
812 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
814 BRW_VERTICAL_STRIDE_4
,
816 BRW_HORIZONTAL_STRIDE_0
,
817 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
818 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
820 BRW_VERTICAL_STRIDE_4
,
822 BRW_HORIZONTAL_STRIDE_0
,
823 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
825 brw_ADD(p
, dst
, src1
, negate(src0
));
827 brw_ADD(p
, dst
, src0
, negate(src1
));
832 fs_generator::generate_discard_jump(fs_inst
*inst
)
834 assert(brw
->gen
>= 6);
836 /* This HALT will be patched up at FB write time to point UIP at the end of
837 * the program, and at brw_uip_jip() JIP will be set to the end of the
838 * current block (or the program).
840 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
842 brw_push_insn_state(p
);
843 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
845 brw_pop_insn_state(p
);
849 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
851 assert(inst
->mlen
!= 0);
854 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
855 retype(src
, BRW_REGISTER_TYPE_UD
));
856 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
857 dispatch_width
/ 8, inst
->offset
);
861 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
863 assert(inst
->mlen
!= 0);
865 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
866 dispatch_width
/ 8, inst
->offset
);
870 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
872 gen7_block_read_scratch(p
, dst
, dispatch_width
/ 8, inst
->offset
);
876 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
878 struct brw_reg index
,
879 struct brw_reg offset
)
881 assert(inst
->mlen
!= 0);
883 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
884 index
.type
== BRW_REGISTER_TYPE_UD
);
885 uint32_t surf_index
= index
.dw1
.ud
;
887 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
888 offset
.type
== BRW_REGISTER_TYPE_UD
);
889 uint32_t read_offset
= offset
.dw1
.ud
;
891 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
892 read_offset
, surf_index
);
894 brw_mark_surface_used(prog_data
, surf_index
);
898 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
900 struct brw_reg index
,
901 struct brw_reg offset
)
903 assert(inst
->mlen
== 0);
904 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
906 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
907 /* Reference just the dword we need, to avoid angering validate_reg(). */
908 offset
= brw_vec1_grf(offset
.nr
, 0);
910 /* We use the SIMD4x2 mode because we want to end up with 4 components in
911 * the destination loaded consecutively from the same offset (which appears
912 * in the first component, and the rest are ignored).
914 dst
.width
= BRW_WIDTH_4
;
916 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
918 uint32_t surf_index
= index
.dw1
.ud
;
920 brw_push_insn_state(p
);
921 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
922 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
923 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
924 brw_pop_insn_state(p
);
926 brw_set_dest(p
, send
, dst
);
927 brw_set_src0(p
, send
, offset
);
928 brw_set_sampler_message(p
, send
,
930 0, /* LD message ignores sampler unit */
931 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
934 false, /* no header */
935 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
938 brw_mark_surface_used(prog_data
, surf_index
);
942 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
944 brw_push_insn_state(p
);
945 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
946 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
948 /* a0.0 = surf_index & 0xff */
949 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
950 brw_inst_set_exec_size(p
->brw
, insn_and
, BRW_EXECUTE_1
);
951 brw_set_dest(p
, insn_and
, addr
);
952 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
953 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
956 /* a0.0 |= <descriptor> */
957 brw_inst
*insn_or
= brw_next_insn(p
, BRW_OPCODE_OR
);
958 brw_set_sampler_message(p
, insn_or
,
961 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
965 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
967 brw_inst_set_exec_size(p
->brw
, insn_or
, BRW_EXECUTE_1
);
968 brw_inst_set_src1_reg_type(p
->brw
, insn_or
, BRW_REGISTER_TYPE_UD
);
969 brw_set_src0(p
, insn_or
, addr
);
970 brw_set_dest(p
, insn_or
, addr
);
973 /* dst = send(offset, a0.0) */
974 brw_inst
*insn_send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
975 brw_set_dest(p
, insn_send
, dst
);
976 brw_set_src0(p
, insn_send
, offset
);
977 brw_set_indirect_send_descriptor(p
, insn_send
, BRW_SFID_SAMPLER
, addr
);
979 brw_pop_insn_state(p
);
981 /* visitor knows more than we do about the surface limit required,
982 * so has already done marking.
989 fs_generator::generate_varying_pull_constant_load(fs_inst
*inst
,
991 struct brw_reg index
,
992 struct brw_reg offset
)
994 assert(brw
->gen
< 7); /* Should use the gen7 variant. */
995 assert(inst
->header_present
);
998 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
999 index
.type
== BRW_REGISTER_TYPE_UD
);
1000 uint32_t surf_index
= index
.dw1
.ud
;
1002 uint32_t simd_mode
, rlen
, msg_type
;
1003 if (dispatch_width
== 16) {
1004 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1007 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1012 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1014 /* We always use the SIMD16 message so that we only have to load U, and
1017 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1018 assert(inst
->mlen
== 3);
1019 assert(inst
->regs_written
== 8);
1021 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1024 struct brw_reg offset_mrf
= retype(brw_message_reg(inst
->base_mrf
+ 1),
1025 BRW_REGISTER_TYPE_D
);
1026 brw_MOV(p
, offset_mrf
, offset
);
1028 struct brw_reg header
= brw_vec8_grf(0, 0);
1029 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1031 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1032 brw_inst_set_qtr_control(brw
, send
, BRW_COMPRESSION_NONE
);
1033 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1034 brw_set_src0(p
, send
, header
);
1036 brw_inst_set_base_mrf(brw
, send
, inst
->base_mrf
);
1038 /* Our surface is set up as floats, regardless of what actual data is
1041 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1042 brw_set_sampler_message(p
, send
,
1044 0, /* sampler (unused) */
1048 inst
->header_present
,
1052 brw_mark_surface_used(prog_data
, surf_index
);
1056 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1058 struct brw_reg index
,
1059 struct brw_reg offset
)
1061 assert(brw
->gen
>= 7);
1062 /* Varying-offset pull constant loads are treated as a normal expression on
1063 * gen7, so the fact that it's a send message is hidden at the IR level.
1065 assert(!inst
->header_present
);
1066 assert(!inst
->mlen
);
1067 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1069 uint32_t simd_mode
, rlen
, mlen
;
1070 if (dispatch_width
== 16) {
1073 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1077 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1080 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1082 uint32_t surf_index
= index
.dw1
.ud
;
1084 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1085 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1086 brw_set_src0(p
, send
, offset
);
1087 brw_set_sampler_message(p
, send
,
1089 0, /* LD message ignores sampler unit */
1090 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1093 false, /* no header */
1097 brw_mark_surface_used(prog_data
, surf_index
);
1101 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1103 brw_push_insn_state(p
);
1104 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1105 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1107 /* a0.0 = surf_index & 0xff */
1108 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1109 brw_inst_set_exec_size(p
->brw
, insn_and
, BRW_EXECUTE_1
);
1110 brw_set_dest(p
, insn_and
, addr
);
1111 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1112 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1115 /* a0.0 |= <descriptor> */
1116 brw_inst
*insn_or
= brw_next_insn(p
, BRW_OPCODE_OR
);
1117 brw_set_sampler_message(p
, insn_or
,
1120 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1126 brw_inst_set_exec_size(p
->brw
, insn_or
, BRW_EXECUTE_1
);
1127 brw_inst_set_src1_reg_type(p
->brw
, insn_or
, BRW_REGISTER_TYPE_UD
);
1128 brw_set_src0(p
, insn_or
, addr
);
1129 brw_set_dest(p
, insn_or
, addr
);
1132 /* dst = send(offset, a0.0) */
1133 brw_inst
*insn_send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1134 brw_set_dest(p
, insn_send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1135 brw_set_src0(p
, insn_send
, offset
);
1136 brw_set_indirect_send_descriptor(p
, insn_send
, BRW_SFID_SAMPLER
, addr
);
1138 brw_pop_insn_state(p
);
1140 /* visitor knows more than we do about the surface limit required,
1141 * so has already done marking.
1147 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1148 * into the flags register (f0.0).
1150 * Used only on Gen6 and above.
1153 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1155 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
1156 struct brw_reg dispatch_mask
;
1159 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1161 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1163 brw_push_insn_state(p
);
1164 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1165 brw_MOV(p
, flags
, dispatch_mask
);
1166 brw_pop_insn_state(p
);
1170 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1173 struct brw_reg msg_data
,
1176 assert(msg_data
.file
== BRW_IMMEDIATE_VALUE
&&
1177 msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1179 brw_pixel_interpolator_query(p
,
1180 retype(dst
, BRW_REGISTER_TYPE_UW
),
1182 inst
->pi_noperspective
,
1186 inst
->regs_written
);
1190 static uint32_t brw_file_from_reg(fs_reg
*reg
)
1192 switch (reg
->file
) {
1194 return BRW_GENERAL_REGISTER_FILE
;
1196 return BRW_MESSAGE_REGISTER_FILE
;
1198 return BRW_IMMEDIATE_VALUE
;
1200 unreachable("not reached");
1205 brw_reg_from_fs_reg(fs_reg
*reg
)
1207 struct brw_reg brw_reg
;
1209 switch (reg
->file
) {
1212 if (reg
->stride
== 0) {
1213 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
1215 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
1216 brw_reg
= stride(brw_reg
, 8 * reg
->stride
, 8, reg
->stride
);
1219 brw_reg
= retype(brw_reg
, reg
->type
);
1220 brw_reg
= byte_offset(brw_reg
, reg
->subreg_offset
);
1223 switch (reg
->type
) {
1224 case BRW_REGISTER_TYPE_F
:
1225 brw_reg
= brw_imm_f(reg
->fixed_hw_reg
.dw1
.f
);
1227 case BRW_REGISTER_TYPE_D
:
1228 brw_reg
= brw_imm_d(reg
->fixed_hw_reg
.dw1
.d
);
1230 case BRW_REGISTER_TYPE_UD
:
1231 brw_reg
= brw_imm_ud(reg
->fixed_hw_reg
.dw1
.ud
);
1234 unreachable("not reached");
1238 assert(reg
->type
== reg
->fixed_hw_reg
.type
);
1239 brw_reg
= reg
->fixed_hw_reg
;
1242 /* Probably unused. */
1243 brw_reg
= brw_null_reg();
1246 unreachable("not reached");
1248 unreachable("not reached");
1251 brw_reg
= brw_abs(brw_reg
);
1253 brw_reg
= negate(brw_reg
);
1259 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1260 * sampler LD messages.
1262 * We don't want to bake it into the send message's code generation because
1263 * that means we don't get a chance to schedule the instructions.
1266 fs_generator::generate_set_simd4x2_offset(fs_inst
*inst
,
1268 struct brw_reg value
)
1270 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1272 brw_push_insn_state(p
);
1273 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1274 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1275 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 0), value
.type
), value
);
1276 brw_pop_insn_state(p
);
1279 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1280 * (when mask is passed as a uniform) of register mask before moving it
1284 fs_generator::generate_set_omask(fs_inst
*inst
,
1286 struct brw_reg mask
)
1289 (mask
.vstride
== BRW_VERTICAL_STRIDE_8
&&
1290 mask
.width
== BRW_WIDTH_8
&&
1291 mask
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
1294 (mask
.vstride
== BRW_VERTICAL_STRIDE_0
&&
1295 mask
.width
== BRW_WIDTH_1
&&
1296 mask
.hstride
== BRW_HORIZONTAL_STRIDE_0
);
1298 assert(stride_8_8_1
|| stride_0_1_0
);
1299 assert(dst
.type
== BRW_REGISTER_TYPE_UW
);
1301 if (dispatch_width
== 16)
1303 brw_push_insn_state(p
);
1304 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1305 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1308 brw_MOV(p
, dst
, retype(stride(mask
, 16, 8, 2), dst
.type
));
1309 } else if (stride_0_1_0
) {
1310 brw_MOV(p
, dst
, retype(mask
, dst
.type
));
1312 brw_pop_insn_state(p
);
1315 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1316 * the ADD instruction.
1319 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1321 struct brw_reg src0
,
1322 struct brw_reg src1
)
1324 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1325 dst
.type
== BRW_REGISTER_TYPE_UD
);
1326 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1327 src0
.type
== BRW_REGISTER_TYPE_UD
);
1329 brw_push_insn_state(p
);
1330 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1331 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1332 struct brw_reg reg
= retype(stride(src1
, 1, 4, 0), BRW_REGISTER_TYPE_UW
);
1333 if (dispatch_width
== 8) {
1334 brw_ADD(p
, dst
, src0
, reg
);
1335 } else if (dispatch_width
== 16) {
1336 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), reg
);
1337 brw_ADD(p
, sechalf(dst
), sechalf(src0
), suboffset(reg
, 2));
1339 brw_pop_insn_state(p
);
1343 * Change the register's data type from UD to W, doubling the strides in order
1344 * to compensate for halving the data type width.
1346 static struct brw_reg
1347 ud_reg_to_w(struct brw_reg r
)
1349 assert(r
.type
== BRW_REGISTER_TYPE_UD
);
1350 r
.type
= BRW_REGISTER_TYPE_W
;
1352 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1353 * doubles the real stride.
1364 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
1369 assert(brw
->gen
>= 7);
1370 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1371 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1372 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1374 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1376 * Because this instruction does not have a 16-bit floating-point type,
1377 * the destination data type must be Word (W).
1379 * The destination must be DWord-aligned and specify a horizontal stride
1380 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1381 * each destination channel and the upper word is not modified.
1383 struct brw_reg dst_w
= ud_reg_to_w(dst
);
1385 /* Give each 32-bit channel of dst the form below , where "." means
1389 brw_F32TO16(p
, dst_w
, y
);
1394 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1396 /* And, finally the form of packHalf2x16's output:
1399 brw_F32TO16(p
, dst_w
, x
);
1403 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1407 assert(brw
->gen
>= 7);
1408 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1409 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1411 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1413 * Because this instruction does not have a 16-bit floating-point type,
1414 * the source data type must be Word (W). The destination type must be
1417 struct brw_reg src_w
= ud_reg_to_w(src
);
1419 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1420 * For the Y case, we wish to access only the upper word; therefore
1421 * a 16-bit subregister offset is needed.
1423 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1424 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1425 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1428 brw_F16TO32(p
, dst
, src_w
);
1432 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1433 struct brw_reg payload
,
1434 struct brw_reg offset
,
1435 struct brw_reg value
)
1437 assert(brw
->gen
>= 7);
1438 brw_push_insn_state(p
);
1439 brw_set_default_mask_control(p
, true);
1441 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1442 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1444 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1447 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1448 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1449 value
.width
= BRW_WIDTH_1
;
1450 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1451 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1453 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1456 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1457 * case, and we don't really care about squeezing every bit of performance
1458 * out of this path, so we just emit the MOVs from here.
1460 brw_MOV(p
, payload_offset
, offset
);
1461 brw_MOV(p
, payload_value
, value
);
1462 brw_shader_time_add(p
, payload
,
1463 prog_data
->binding_table
.shader_time_start
);
1464 brw_pop_insn_state(p
);
1466 brw_mark_surface_used(prog_data
,
1467 prog_data
->binding_table
.shader_time_start
);
1471 fs_generator::generate_untyped_atomic(fs_inst
*inst
, struct brw_reg dst
,
1472 struct brw_reg payload
,
1473 struct brw_reg atomic_op
,
1474 struct brw_reg surf_index
)
1476 assert(atomic_op
.file
== BRW_IMMEDIATE_VALUE
&&
1477 atomic_op
.type
== BRW_REGISTER_TYPE_UD
&&
1478 surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
1479 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
1481 brw_untyped_atomic(p
, dst
, payload
, atomic_op
.dw1
.ud
, surf_index
.dw1
.ud
,
1482 inst
->mlen
, inst
->exec_size
/ 8);
1484 brw_mark_surface_used(prog_data
, surf_index
.dw1
.ud
);
1488 fs_generator::generate_untyped_surface_read(fs_inst
*inst
, struct brw_reg dst
,
1489 struct brw_reg payload
,
1490 struct brw_reg surf_index
)
1492 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
1493 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
1495 brw_untyped_surface_read(p
, dst
, payload
,
1497 inst
->mlen
, inst
->exec_size
/ 8);
1499 brw_mark_surface_used(prog_data
, surf_index
.dw1
.ud
);
1503 fs_generator::generate_code(const cfg_t
*cfg
)
1505 int start_offset
= p
->next_insn_offset
;
1508 struct annotation_info annotation
;
1509 memset(&annotation
, 0, sizeof(annotation
));
1511 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1512 struct brw_reg src
[3], dst
;
1513 unsigned int last_insn_offset
= p
->next_insn_offset
;
1515 if (unlikely(debug_flag
))
1516 annotate(brw
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1518 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1519 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1521 /* The accumulator result appears to get used for the
1522 * conditional modifier generation. When negating a UD
1523 * value, there is a 33rd bit generated for the sign in the
1524 * accumulator value, so now you can't check, for example,
1525 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1527 assert(!inst
->conditional_mod
||
1528 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1529 !inst
->src
[i
].negate
);
1531 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1533 brw_set_default_predicate_control(p
, inst
->predicate
);
1534 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1535 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1536 brw_set_default_saturate(p
, inst
->saturate
);
1537 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1538 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1540 switch (inst
->exec_size
) {
1544 assert(inst
->force_writemask_all
);
1545 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1548 if (inst
->force_sechalf
) {
1549 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1551 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1555 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1558 unreachable(!"Invalid instruction width");
1561 switch (inst
->opcode
) {
1562 case BRW_OPCODE_MOV
:
1563 brw_MOV(p
, dst
, src
[0]);
1565 case BRW_OPCODE_ADD
:
1566 brw_ADD(p
, dst
, src
[0], src
[1]);
1568 case BRW_OPCODE_MUL
:
1569 brw_MUL(p
, dst
, src
[0], src
[1]);
1571 case BRW_OPCODE_AVG
:
1572 brw_AVG(p
, dst
, src
[0], src
[1]);
1574 case BRW_OPCODE_MACH
:
1575 brw_MACH(p
, dst
, src
[0], src
[1]);
1578 case BRW_OPCODE_MAD
:
1579 assert(brw
->gen
>= 6);
1580 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1581 if (dispatch_width
== 16 && brw
->gen
< 8 && !brw
->is_haswell
) {
1582 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1583 brw_MAD(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1584 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1585 brw_MAD(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1586 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1588 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1590 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1593 case BRW_OPCODE_LRP
:
1594 assert(brw
->gen
>= 6);
1595 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1596 if (dispatch_width
== 16 && brw
->gen
< 8 && !brw
->is_haswell
) {
1597 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1598 brw_LRP(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1599 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1600 brw_LRP(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1601 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1603 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1605 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1608 case BRW_OPCODE_FRC
:
1609 brw_FRC(p
, dst
, src
[0]);
1611 case BRW_OPCODE_RNDD
:
1612 brw_RNDD(p
, dst
, src
[0]);
1614 case BRW_OPCODE_RNDE
:
1615 brw_RNDE(p
, dst
, src
[0]);
1617 case BRW_OPCODE_RNDZ
:
1618 brw_RNDZ(p
, dst
, src
[0]);
1621 case BRW_OPCODE_AND
:
1622 brw_AND(p
, dst
, src
[0], src
[1]);
1625 brw_OR(p
, dst
, src
[0], src
[1]);
1627 case BRW_OPCODE_XOR
:
1628 brw_XOR(p
, dst
, src
[0], src
[1]);
1630 case BRW_OPCODE_NOT
:
1631 brw_NOT(p
, dst
, src
[0]);
1633 case BRW_OPCODE_ASR
:
1634 brw_ASR(p
, dst
, src
[0], src
[1]);
1636 case BRW_OPCODE_SHR
:
1637 brw_SHR(p
, dst
, src
[0], src
[1]);
1639 case BRW_OPCODE_SHL
:
1640 brw_SHL(p
, dst
, src
[0], src
[1]);
1642 case BRW_OPCODE_F32TO16
:
1643 assert(brw
->gen
>= 7);
1644 brw_F32TO16(p
, dst
, src
[0]);
1646 case BRW_OPCODE_F16TO32
:
1647 assert(brw
->gen
>= 7);
1648 brw_F16TO32(p
, dst
, src
[0]);
1650 case BRW_OPCODE_CMP
:
1651 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1653 case BRW_OPCODE_SEL
:
1654 brw_SEL(p
, dst
, src
[0], src
[1]);
1656 case BRW_OPCODE_BFREV
:
1657 assert(brw
->gen
>= 7);
1658 /* BFREV only supports UD type for src and dst. */
1659 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1660 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1662 case BRW_OPCODE_FBH
:
1663 assert(brw
->gen
>= 7);
1664 /* FBH only supports UD type for dst. */
1665 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1667 case BRW_OPCODE_FBL
:
1668 assert(brw
->gen
>= 7);
1669 /* FBL only supports UD type for dst. */
1670 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1672 case BRW_OPCODE_CBIT
:
1673 assert(brw
->gen
>= 7);
1674 /* CBIT only supports UD type for dst. */
1675 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1677 case BRW_OPCODE_ADDC
:
1678 assert(brw
->gen
>= 7);
1679 brw_ADDC(p
, dst
, src
[0], src
[1]);
1681 case BRW_OPCODE_SUBB
:
1682 assert(brw
->gen
>= 7);
1683 brw_SUBB(p
, dst
, src
[0], src
[1]);
1685 case BRW_OPCODE_MAC
:
1686 brw_MAC(p
, dst
, src
[0], src
[1]);
1689 case BRW_OPCODE_BFE
:
1690 assert(brw
->gen
>= 7);
1691 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1692 if (dispatch_width
== 16 && brw
->gen
< 8 && !brw
->is_haswell
) {
1693 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1694 brw_BFE(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1695 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1696 brw_BFE(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1697 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1699 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1701 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1704 case BRW_OPCODE_BFI1
:
1705 assert(brw
->gen
>= 7);
1706 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1709 * "Force BFI instructions to be executed always in SIMD8."
1711 if (dispatch_width
== 16 && brw
->is_haswell
) {
1712 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1713 brw_BFI1(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]));
1714 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1715 brw_BFI1(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]));
1716 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1718 brw_BFI1(p
, dst
, src
[0], src
[1]);
1721 case BRW_OPCODE_BFI2
:
1722 assert(brw
->gen
>= 7);
1723 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1724 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1727 * "Force BFI instructions to be executed always in SIMD8."
1729 * Otherwise we would be able to emit compressed instructions like we
1730 * do for the other three-source instructions.
1732 if (dispatch_width
== 16 && brw
->gen
< 8) {
1733 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1734 brw_BFI2(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1735 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1736 brw_BFI2(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1737 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1739 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1741 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1745 if (inst
->src
[0].file
!= BAD_FILE
) {
1746 /* The instruction has an embedded compare (only allowed on gen6) */
1747 assert(brw
->gen
== 6);
1748 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1750 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1754 case BRW_OPCODE_ELSE
:
1757 case BRW_OPCODE_ENDIF
:
1762 brw_DO(p
, BRW_EXECUTE_8
);
1765 case BRW_OPCODE_BREAK
:
1767 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1769 case BRW_OPCODE_CONTINUE
:
1771 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1774 case BRW_OPCODE_WHILE
:
1779 case SHADER_OPCODE_RCP
:
1780 case SHADER_OPCODE_RSQ
:
1781 case SHADER_OPCODE_SQRT
:
1782 case SHADER_OPCODE_EXP2
:
1783 case SHADER_OPCODE_LOG2
:
1784 case SHADER_OPCODE_SIN
:
1785 case SHADER_OPCODE_COS
:
1786 assert(brw
->gen
< 6 || inst
->mlen
== 0);
1787 if (brw
->gen
>= 7) {
1788 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1790 } else if (brw
->gen
== 6) {
1791 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
1792 } else if (brw
->gen
== 5 || brw
->is_g4x
) {
1793 generate_math_g45(inst
, dst
, src
[0]);
1795 generate_math_gen4(inst
, dst
, src
[0]);
1798 case SHADER_OPCODE_INT_QUOTIENT
:
1799 case SHADER_OPCODE_INT_REMAINDER
:
1800 case SHADER_OPCODE_POW
:
1801 assert(brw
->gen
< 6 || inst
->mlen
== 0);
1802 if (brw
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) {
1803 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1804 } else if (brw
->gen
>= 6) {
1805 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
1807 generate_math_gen4(inst
, dst
, src
[0]);
1810 case FS_OPCODE_PIXEL_X
:
1811 generate_pixel_xy(dst
, true);
1813 case FS_OPCODE_PIXEL_Y
:
1814 generate_pixel_xy(dst
, false);
1816 case FS_OPCODE_CINTERP
:
1817 brw_MOV(p
, dst
, src
[0]);
1819 case FS_OPCODE_LINTERP
:
1820 generate_linterp(inst
, dst
, src
);
1822 case SHADER_OPCODE_TEX
:
1824 case SHADER_OPCODE_TXD
:
1825 case SHADER_OPCODE_TXF
:
1826 case SHADER_OPCODE_TXF_CMS
:
1827 case SHADER_OPCODE_TXF_UMS
:
1828 case SHADER_OPCODE_TXF_MCS
:
1829 case SHADER_OPCODE_TXL
:
1830 case SHADER_OPCODE_TXS
:
1831 case SHADER_OPCODE_LOD
:
1832 case SHADER_OPCODE_TG4
:
1833 case SHADER_OPCODE_TG4_OFFSET
:
1834 generate_tex(inst
, dst
, src
[0], src
[1]);
1837 generate_ddx(inst
, dst
, src
[0], src
[1]);
1840 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1841 * guarantee that key->render_to_fbo is set).
1843 assert(stage
== MESA_SHADER_FRAGMENT
&&
1844 ((gl_fragment_program
*) prog
)->UsesDFdy
);
1845 generate_ddy(inst
, dst
, src
[0], src
[1],
1846 ((brw_wm_prog_key
* const) this->key
)->render_to_fbo
);
1849 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1850 generate_scratch_write(inst
, src
[0]);
1853 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1854 generate_scratch_read(inst
, dst
);
1857 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
1858 generate_scratch_read_gen7(inst
, dst
);
1861 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1862 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1865 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
1866 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1869 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
1870 generate_varying_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1873 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
1874 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1877 case FS_OPCODE_REP_FB_WRITE
:
1878 case FS_OPCODE_FB_WRITE
:
1879 generate_fb_write(inst
, src
[0]);
1882 case FS_OPCODE_BLORP_FB_WRITE
:
1883 generate_blorp_fb_write(inst
);
1886 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
1887 generate_mov_dispatch_to_flags(inst
);
1890 case FS_OPCODE_DISCARD_JUMP
:
1891 generate_discard_jump(inst
);
1894 case SHADER_OPCODE_SHADER_TIME_ADD
:
1895 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
1898 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1899 generate_untyped_atomic(inst
, dst
, src
[0], src
[1], src
[2]);
1902 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1903 generate_untyped_surface_read(inst
, dst
, src
[0], src
[1]);
1906 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
1907 generate_set_simd4x2_offset(inst
, dst
, src
[0]);
1910 case FS_OPCODE_SET_OMASK
:
1911 generate_set_omask(inst
, dst
, src
[0]);
1914 case FS_OPCODE_SET_SAMPLE_ID
:
1915 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
1918 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
1919 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
1922 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
1923 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
1924 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
1927 case FS_OPCODE_PLACEHOLDER_HALT
:
1928 /* This is the place where the final HALT needs to be inserted if
1929 * we've emitted any discards. If not, this will emit no code.
1931 if (!patch_discard_jumps_to_fb_writes()) {
1932 if (unlikely(debug_flag
)) {
1933 annotation
.ann_count
--;
1938 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
1939 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
1940 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID
);
1943 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
1944 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
1945 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
1948 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
1949 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
1950 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
1953 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
1954 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
1955 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
1959 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1960 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
1961 opcode_descs
[inst
->opcode
].name
);
1963 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
1967 case SHADER_OPCODE_LOAD_PAYLOAD
:
1968 unreachable("Should be lowered by lower_load_payload()");
1971 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
1972 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
1973 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1974 "emitting more than 1 instruction");
1976 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
1978 brw_inst_set_cond_modifier(brw
, last
, inst
->conditional_mod
);
1979 brw_inst_set_no_dd_clear(brw
, last
, inst
->no_dd_clear
);
1980 brw_inst_set_no_dd_check(brw
, last
, inst
->no_dd_check
);
1985 annotation_finalize(&annotation
, p
->next_insn_offset
);
1987 int before_size
= p
->next_insn_offset
- start_offset
;
1988 brw_compact_instructions(p
, start_offset
, annotation
.ann_count
,
1990 int after_size
= p
->next_insn_offset
- start_offset
;
1992 if (unlikely(debug_flag
)) {
1995 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
1996 shader_prog
->Label
? shader_prog
->Label
: "unnamed",
1997 shader_prog
->Name
, dispatch_width
);
2000 "Native code for fragment program %d (SIMD%d dispatch):\n",
2001 prog
->Id
, dispatch_width
);
2003 fprintf(stderr
, "Native code for blorp program (SIMD%d dispatch):\n",
2006 fprintf(stderr
, "SIMD%d shader: %d instructions. %d loops. Compacted %d to %d"
2007 " bytes (%.0f%%)\n",
2008 dispatch_width
, before_size
/ 16, loop_count
, before_size
, after_size
,
2009 100.0f
* (before_size
- after_size
) / before_size
);
2011 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
, brw
, prog
);
2012 ralloc_free(annotation
.ann
);
2017 fs_generator::generate_assembly(const cfg_t
*simd8_cfg
,
2018 const cfg_t
*simd16_cfg
,
2019 unsigned *assembly_size
)
2021 assert(simd8_cfg
|| simd16_cfg
);
2025 generate_code(simd8_cfg
);
2029 /* align to 64 byte boundary. */
2030 while (p
->next_insn_offset
% 64) {
2034 assert(stage
== MESA_SHADER_FRAGMENT
);
2035 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
2037 /* Save off the start of this SIMD16 program */
2038 prog_data
->prog_offset_16
= p
->next_insn_offset
;
2040 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
2042 dispatch_width
= 16;
2043 generate_code(simd16_cfg
);
2046 return brw_get_program(p
, assembly_size
);