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i965/fs: Add vector float immediate infrastructure.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 void *mem_ctx,
41 const struct brw_wm_prog_key *key,
42 struct brw_wm_prog_data *prog_data,
43 struct gl_shader_program *shader_prog,
44 struct gl_fragment_program *fp,
45 bool runtime_check_aads_emit,
46 bool debug_flag)
47
48 : brw(brw), stage(MESA_SHADER_FRAGMENT), key(key),
49 prog_data(&prog_data->base), shader_prog(shader_prog),
50 prog(&fp->Base), runtime_check_aads_emit(runtime_check_aads_emit),
51 debug_flag(debug_flag), mem_ctx(mem_ctx)
52 {
53 ctx = &brw->ctx;
54
55 p = rzalloc(mem_ctx, struct brw_compile);
56 brw_init_compile(brw, p, mem_ctx);
57 }
58
59 fs_generator::~fs_generator()
60 {
61 }
62
63 class ip_record : public exec_node {
64 public:
65 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
66
67 ip_record(int ip)
68 {
69 this->ip = ip;
70 }
71
72 int ip;
73 };
74
75 bool
76 fs_generator::patch_discard_jumps_to_fb_writes()
77 {
78 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
79 return false;
80
81 int scale = brw_jump_scale(brw);
82
83 /* There is a somewhat strange undocumented requirement of using
84 * HALT, according to the simulator. If some channel has HALTed to
85 * a particular UIP, then by the end of the program, every channel
86 * must have HALTed to that UIP. Furthermore, the tracking is a
87 * stack, so you can't do the final halt of a UIP after starting
88 * halting to a new UIP.
89 *
90 * Symptoms of not emitting this instruction on actual hardware
91 * included GPU hangs and sparkly rendering on the piglit discard
92 * tests.
93 */
94 brw_inst *last_halt = gen6_HALT(p);
95 brw_inst_set_uip(brw, last_halt, 1 * scale);
96 brw_inst_set_jip(brw, last_halt, 1 * scale);
97
98 int ip = p->nr_insn;
99
100 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
101 brw_inst *patch = &p->store[patch_ip->ip];
102
103 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
104 /* HALT takes a half-instruction distance from the pre-incremented IP. */
105 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
106 }
107
108 this->discard_halt_patches.make_empty();
109 return true;
110 }
111
112 void
113 fs_generator::fire_fb_write(fs_inst *inst,
114 struct brw_reg payload,
115 struct brw_reg implied_header,
116 GLuint nr)
117 {
118 uint32_t msg_control;
119
120 assert(stage == MESA_SHADER_FRAGMENT);
121 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
122
123 if (brw->gen < 6) {
124 brw_push_insn_state(p);
125 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
126 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
127 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
128 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
129 brw_pop_insn_state(p);
130 }
131
132 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
133 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
134 else if (prog_data->dual_src_blend)
135 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
136 else if (dispatch_width == 16)
137 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
138 else
139 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
140
141 uint32_t surf_index =
142 prog_data->binding_table.render_target_start + inst->target;
143
144 brw_fb_WRITE(p,
145 dispatch_width,
146 payload,
147 implied_header,
148 msg_control,
149 surf_index,
150 nr,
151 0,
152 inst->eot,
153 inst->header_present);
154
155 brw_mark_surface_used(&prog_data->base, surf_index);
156 }
157
158 void
159 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
160 {
161 assert(stage == MESA_SHADER_FRAGMENT);
162 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
163 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
164 struct brw_reg implied_header;
165
166 if (inst->base_mrf >= 0)
167 payload = brw_message_reg(inst->base_mrf);
168
169 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
170 * move, here's g1.
171 */
172 if (inst->header_present) {
173 brw_push_insn_state(p);
174 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
175 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
176 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
177 brw_set_default_flag_reg(p, 0, 0);
178
179 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
180 * present.
181 */
182 if (prog_data->uses_kill || key->alpha_test_func) {
183 struct brw_reg pixel_mask;
184
185 if (brw->gen >= 6)
186 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
187 else
188 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
189
190 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
191 }
192
193 if (brw->gen >= 6) {
194 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
195 brw_MOV(p,
196 retype(payload, BRW_REGISTER_TYPE_UD),
197 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
198 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
199
200 if (inst->target > 0 && key->replicate_alpha) {
201 /* Set "Source0 Alpha Present to RenderTarget" bit in message
202 * header.
203 */
204 brw_OR(p,
205 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
206 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
207 brw_imm_ud(0x1 << 11));
208 }
209
210 if (inst->target > 0) {
211 /* Set the render target index for choosing BLEND_STATE. */
212 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
213 BRW_REGISTER_TYPE_UD),
214 brw_imm_ud(inst->target));
215 }
216
217 implied_header = brw_null_reg();
218 } else {
219 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
220 }
221
222 brw_pop_insn_state(p);
223 } else {
224 implied_header = brw_null_reg();
225 }
226
227 if (!runtime_check_aads_emit) {
228 fire_fb_write(inst, payload, implied_header, inst->mlen);
229 } else {
230 /* This can only happen in gen < 6 */
231 assert(brw->gen < 6);
232
233 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
234
235 /* Check runtime bit to detect if we have to send AA data or not */
236 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
237 brw_AND(p,
238 v1_null_ud,
239 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
240 brw_imm_ud(1<<26));
241 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
242
243 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
244 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
245 {
246 /* Don't send AA data */
247 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
248 }
249 brw_land_fwd_jump(p, jmp);
250 fire_fb_write(inst, payload, implied_header, inst->mlen);
251 }
252 }
253
254 void
255 fs_generator::generate_blorp_fb_write(fs_inst *inst)
256 {
257 brw_fb_WRITE(p,
258 16 /* dispatch_width */,
259 brw_message_reg(inst->base_mrf),
260 brw_reg_from_fs_reg(&inst->src[0]),
261 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
262 inst->target,
263 inst->mlen,
264 0,
265 true,
266 inst->header_present);
267 }
268
269 /* Computes the integer pixel x,y values from the origin.
270 *
271 * This is the basis of gl_FragCoord computation, but is also used
272 * pre-gen6 for computing the deltas from v0 for computing
273 * interpolation.
274 */
275 void
276 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
277 {
278 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
279 struct brw_reg src;
280 struct brw_reg deltas;
281
282 if (is_x) {
283 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
284 deltas = brw_imm_v(0x10101010);
285 } else {
286 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
287 deltas = brw_imm_v(0x11001100);
288 }
289
290 if (dispatch_width == 16) {
291 dst = vec16(dst);
292 }
293
294 /* We do this SIMD8 or SIMD16, but since the destination is UW we
295 * don't do compression in the SIMD16 case.
296 */
297 brw_push_insn_state(p);
298 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
299 brw_ADD(p, dst, src, deltas);
300 brw_pop_insn_state(p);
301 }
302
303 void
304 fs_generator::generate_linterp(fs_inst *inst,
305 struct brw_reg dst, struct brw_reg *src)
306 {
307 struct brw_reg delta_x = src[0];
308 struct brw_reg delta_y = src[1];
309 struct brw_reg interp = src[2];
310
311 if (brw->has_pln &&
312 delta_y.nr == delta_x.nr + 1 &&
313 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
314 brw_PLN(p, dst, interp, delta_x);
315 } else {
316 brw_LINE(p, brw_null_reg(), interp, delta_x);
317 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
318 }
319 }
320
321 void
322 fs_generator::generate_math_gen6(fs_inst *inst,
323 struct brw_reg dst,
324 struct brw_reg src0,
325 struct brw_reg src1)
326 {
327 int op = brw_math_function(inst->opcode);
328 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
329
330 if (dispatch_width == 8) {
331 gen6_math(p, dst, op, src0, src1);
332 } else if (dispatch_width == 16) {
333 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
334 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
335 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
336 gen6_math(p, sechalf(dst), op, sechalf(src0),
337 binop ? sechalf(src1) : brw_null_reg());
338 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
339 }
340 }
341
342 void
343 fs_generator::generate_math_gen4(fs_inst *inst,
344 struct brw_reg dst,
345 struct brw_reg src)
346 {
347 int op = brw_math_function(inst->opcode);
348
349 assert(inst->mlen >= 1);
350
351 if (dispatch_width == 8) {
352 gen4_math(p, dst,
353 op,
354 inst->base_mrf, src,
355 BRW_MATH_PRECISION_FULL);
356 } else if (dispatch_width == 16) {
357 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
358 gen4_math(p, firsthalf(dst),
359 op,
360 inst->base_mrf, firsthalf(src),
361 BRW_MATH_PRECISION_FULL);
362 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
363 gen4_math(p, sechalf(dst),
364 op,
365 inst->base_mrf + 1, sechalf(src),
366 BRW_MATH_PRECISION_FULL);
367
368 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
369 }
370 }
371
372 void
373 fs_generator::generate_math_g45(fs_inst *inst,
374 struct brw_reg dst,
375 struct brw_reg src)
376 {
377 if (inst->opcode == SHADER_OPCODE_POW ||
378 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
379 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
380 generate_math_gen4(inst, dst, src);
381 return;
382 }
383
384 int op = brw_math_function(inst->opcode);
385
386 assert(inst->mlen >= 1);
387
388 gen4_math(p, dst,
389 op,
390 inst->base_mrf, src,
391 BRW_MATH_PRECISION_FULL);
392 }
393
394 void
395 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
396 struct brw_reg sampler_index)
397 {
398 int msg_type = -1;
399 int rlen = 4;
400 uint32_t simd_mode;
401 uint32_t return_format;
402
403 switch (dst.type) {
404 case BRW_REGISTER_TYPE_D:
405 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
406 break;
407 case BRW_REGISTER_TYPE_UD:
408 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
409 break;
410 default:
411 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
412 break;
413 }
414
415 switch (inst->exec_size) {
416 case 8:
417 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
418 break;
419 case 16:
420 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
421 break;
422 default:
423 unreachable("Invalid width for texture instruction");
424 }
425
426 if (brw->gen >= 5) {
427 switch (inst->opcode) {
428 case SHADER_OPCODE_TEX:
429 if (inst->shadow_compare) {
430 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
431 } else {
432 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
433 }
434 break;
435 case FS_OPCODE_TXB:
436 if (inst->shadow_compare) {
437 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
438 } else {
439 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
440 }
441 break;
442 case SHADER_OPCODE_TXL:
443 if (inst->shadow_compare) {
444 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
445 } else {
446 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
447 }
448 break;
449 case SHADER_OPCODE_TXS:
450 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
451 break;
452 case SHADER_OPCODE_TXD:
453 if (inst->shadow_compare) {
454 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
455 assert(brw->gen >= 8 || brw->is_haswell);
456 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
457 } else {
458 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
459 }
460 break;
461 case SHADER_OPCODE_TXF:
462 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
463 break;
464 case SHADER_OPCODE_TXF_CMS:
465 if (brw->gen >= 7)
466 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
467 else
468 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
469 break;
470 case SHADER_OPCODE_TXF_UMS:
471 assert(brw->gen >= 7);
472 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
473 break;
474 case SHADER_OPCODE_TXF_MCS:
475 assert(brw->gen >= 7);
476 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
477 break;
478 case SHADER_OPCODE_LOD:
479 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
480 break;
481 case SHADER_OPCODE_TG4:
482 if (inst->shadow_compare) {
483 assert(brw->gen >= 7);
484 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
485 } else {
486 assert(brw->gen >= 6);
487 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
488 }
489 break;
490 case SHADER_OPCODE_TG4_OFFSET:
491 assert(brw->gen >= 7);
492 if (inst->shadow_compare) {
493 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
494 } else {
495 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
496 }
497 break;
498 default:
499 unreachable("not reached");
500 }
501 } else {
502 switch (inst->opcode) {
503 case SHADER_OPCODE_TEX:
504 /* Note that G45 and older determines shadow compare and dispatch width
505 * from message length for most messages.
506 */
507 assert(dispatch_width == 8);
508 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
509 if (inst->shadow_compare) {
510 assert(inst->mlen == 6);
511 } else {
512 assert(inst->mlen <= 4);
513 }
514 break;
515 case FS_OPCODE_TXB:
516 if (inst->shadow_compare) {
517 assert(inst->mlen == 6);
518 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
519 } else {
520 assert(inst->mlen == 9);
521 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
522 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
523 }
524 break;
525 case SHADER_OPCODE_TXL:
526 if (inst->shadow_compare) {
527 assert(inst->mlen == 6);
528 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
529 } else {
530 assert(inst->mlen == 9);
531 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
532 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
533 }
534 break;
535 case SHADER_OPCODE_TXD:
536 /* There is no sample_d_c message; comparisons are done manually */
537 assert(inst->mlen == 7 || inst->mlen == 10);
538 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
539 break;
540 case SHADER_OPCODE_TXF:
541 assert(inst->mlen == 9);
542 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
543 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
544 break;
545 case SHADER_OPCODE_TXS:
546 assert(inst->mlen == 3);
547 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
548 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
549 break;
550 default:
551 unreachable("not reached");
552 }
553 }
554 assert(msg_type != -1);
555
556 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
557 rlen = 8;
558 dst = vec16(dst);
559 }
560
561 assert(brw->gen < 7 || !inst->header_present ||
562 src.file == BRW_GENERAL_REGISTER_FILE);
563
564 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
565
566 /* Load the message header if present. If there's a texture offset,
567 * we need to set it up explicitly and load the offset bitfield.
568 * Otherwise, we can use an implied move from g0 to the first message reg.
569 */
570 if (inst->header_present) {
571 if (brw->gen < 6 && !inst->offset) {
572 /* Set up an implied move from g0 to the MRF. */
573 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
574 } else {
575 struct brw_reg header_reg;
576
577 if (brw->gen >= 7) {
578 header_reg = src;
579 } else {
580 assert(inst->base_mrf != -1);
581 header_reg = brw_message_reg(inst->base_mrf);
582 }
583
584 brw_push_insn_state(p);
585 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
586 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
587 /* Explicitly set up the message header by copying g0 to the MRF. */
588 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
589
590 if (inst->offset) {
591 /* Set the offset bits in DWord 2. */
592 brw_MOV(p, get_element_ud(header_reg, 2),
593 brw_imm_ud(inst->offset));
594 }
595
596 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index, dst);
597 brw_pop_insn_state(p);
598 }
599 }
600
601 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
602 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
603 ? prog_data->binding_table.gather_texture_start
604 : prog_data->binding_table.texture_start;
605
606 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
607 uint32_t sampler = sampler_index.dw1.ud;
608
609 brw_SAMPLE(p,
610 retype(dst, BRW_REGISTER_TYPE_UW),
611 inst->base_mrf,
612 src,
613 sampler + base_binding_table_index,
614 sampler % 16,
615 msg_type,
616 rlen,
617 inst->mlen,
618 inst->header_present,
619 simd_mode,
620 return_format);
621
622 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
623 } else {
624 /* Non-const sampler index */
625 /* Note: this clobbers `dst` as a temporary before emitting the send */
626
627 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
628 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
629
630 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
631
632 brw_push_insn_state(p);
633 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
634 brw_set_default_access_mode(p, BRW_ALIGN_1);
635
636 /* Some care required: `sampler` and `temp` may alias:
637 * addr = sampler & 0xff
638 * temp = (sampler << 8) & 0xf00
639 * addr = addr | temp
640 */
641 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
642 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
643 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
644 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
645 brw_OR(p, addr, addr, temp);
646
647 /* a0.0 |= <descriptor> */
648 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
649 brw_set_sampler_message(p, insn_or,
650 0 /* surface */,
651 0 /* sampler */,
652 msg_type,
653 rlen,
654 inst->mlen /* mlen */,
655 inst->header_present /* header */,
656 simd_mode,
657 return_format);
658 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
659 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
660 brw_set_src0(p, insn_or, addr);
661 brw_set_dest(p, insn_or, addr);
662
663
664 /* dst = send(offset, a0.0) */
665 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
666 brw_set_dest(p, insn_send, dst);
667 brw_set_src0(p, insn_send, src);
668 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
669
670 brw_pop_insn_state(p);
671
672 /* visitor knows more than we do about the surface limit required,
673 * so has already done marking.
674 */
675 }
676 }
677
678
679 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
680 * looking like:
681 *
682 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
683 *
684 * Ideally, we want to produce:
685 *
686 * DDX DDY
687 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
688 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
689 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
690 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
691 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
692 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
693 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
694 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
695 *
696 * and add another set of two more subspans if in 16-pixel dispatch mode.
697 *
698 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
699 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
700 * pair. But the ideal approximation may impose a huge performance cost on
701 * sample_d. On at least Haswell, sample_d instruction does some
702 * optimizations if the same LOD is used for all pixels in the subspan.
703 *
704 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
705 * appropriate swizzling.
706 */
707 void
708 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
709 struct brw_reg quality)
710 {
711 unsigned vstride, width;
712 assert(quality.file == BRW_IMMEDIATE_VALUE);
713 assert(quality.type == BRW_REGISTER_TYPE_D);
714
715 assert(stage == MESA_SHADER_FRAGMENT);
716 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
717
718 int quality_value = quality.dw1.d;
719
720 if (quality_value == BRW_DERIVATIVE_FINE ||
721 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
722 /* produce accurate derivatives */
723 vstride = BRW_VERTICAL_STRIDE_2;
724 width = BRW_WIDTH_2;
725 }
726 else {
727 /* replicate the derivative at the top-left pixel to other pixels */
728 vstride = BRW_VERTICAL_STRIDE_4;
729 width = BRW_WIDTH_4;
730 }
731
732 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
733 BRW_REGISTER_TYPE_F,
734 vstride,
735 width,
736 BRW_HORIZONTAL_STRIDE_0,
737 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
738 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
739 BRW_REGISTER_TYPE_F,
740 vstride,
741 width,
742 BRW_HORIZONTAL_STRIDE_0,
743 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
744 brw_ADD(p, dst, src0, negate(src1));
745 }
746
747 /* The negate_value boolean is used to negate the derivative computation for
748 * FBOs, since they place the origin at the upper left instead of the lower
749 * left.
750 */
751 void
752 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
753 struct brw_reg quality, bool negate_value)
754 {
755 assert(quality.file == BRW_IMMEDIATE_VALUE);
756 assert(quality.type == BRW_REGISTER_TYPE_D);
757
758 assert(stage == MESA_SHADER_FRAGMENT);
759 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
760
761 int quality_value = quality.dw1.d;
762
763 if (quality_value == BRW_DERIVATIVE_FINE ||
764 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
765 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
766 * Region Restrictions):
767 *
768 * In Align16 access mode, SIMD16 is not allowed for DW operations
769 * and SIMD8 is not allowed for DF operations.
770 *
771 * In this context, "DW operations" means "operations acting on 32-bit
772 * values", so it includes operations on floats.
773 *
774 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
775 * (Instruction Compression -> Rules and Restrictions):
776 *
777 * A compressed instruction must be in Align1 access mode. Align16
778 * mode instructions cannot be compressed.
779 *
780 * Similar text exists in the g45 PRM.
781 *
782 * On these platforms, if we're building a SIMD16 shader, we need to
783 * manually unroll to a pair of SIMD8 instructions.
784 */
785 bool unroll_to_simd8 =
786 (dispatch_width == 16 &&
787 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
788
789 /* produce accurate derivatives */
790 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
791 BRW_REGISTER_TYPE_F,
792 BRW_VERTICAL_STRIDE_4,
793 BRW_WIDTH_4,
794 BRW_HORIZONTAL_STRIDE_1,
795 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
796 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
797 BRW_REGISTER_TYPE_F,
798 BRW_VERTICAL_STRIDE_4,
799 BRW_WIDTH_4,
800 BRW_HORIZONTAL_STRIDE_1,
801 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
802 brw_push_insn_state(p);
803 brw_set_default_access_mode(p, BRW_ALIGN_16);
804 if (unroll_to_simd8) {
805 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
806 if (negate_value) {
807 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
808 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
809 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
810 } else {
811 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
812 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
813 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
814 }
815 } else {
816 if (negate_value)
817 brw_ADD(p, dst, src1, negate(src0));
818 else
819 brw_ADD(p, dst, src0, negate(src1));
820 }
821 brw_pop_insn_state(p);
822 } else {
823 /* replicate the derivative at the top-left pixel to other pixels */
824 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
825 BRW_REGISTER_TYPE_F,
826 BRW_VERTICAL_STRIDE_4,
827 BRW_WIDTH_4,
828 BRW_HORIZONTAL_STRIDE_0,
829 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
830 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
831 BRW_REGISTER_TYPE_F,
832 BRW_VERTICAL_STRIDE_4,
833 BRW_WIDTH_4,
834 BRW_HORIZONTAL_STRIDE_0,
835 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
836 if (negate_value)
837 brw_ADD(p, dst, src1, negate(src0));
838 else
839 brw_ADD(p, dst, src0, negate(src1));
840 }
841 }
842
843 void
844 fs_generator::generate_discard_jump(fs_inst *inst)
845 {
846 assert(brw->gen >= 6);
847
848 /* This HALT will be patched up at FB write time to point UIP at the end of
849 * the program, and at brw_uip_jip() JIP will be set to the end of the
850 * current block (or the program).
851 */
852 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
853
854 brw_push_insn_state(p);
855 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
856 gen6_HALT(p);
857 brw_pop_insn_state(p);
858 }
859
860 void
861 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
862 {
863 assert(inst->mlen != 0);
864
865 brw_MOV(p,
866 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
867 retype(src, BRW_REGISTER_TYPE_UD));
868 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
869 inst->exec_size / 8, inst->offset);
870 }
871
872 void
873 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
874 {
875 assert(inst->mlen != 0);
876
877 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
878 inst->exec_size / 8, inst->offset);
879 }
880
881 void
882 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
883 {
884 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
885 }
886
887 void
888 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
889 struct brw_reg dst,
890 struct brw_reg index,
891 struct brw_reg offset)
892 {
893 assert(inst->mlen != 0);
894
895 assert(index.file == BRW_IMMEDIATE_VALUE &&
896 index.type == BRW_REGISTER_TYPE_UD);
897 uint32_t surf_index = index.dw1.ud;
898
899 assert(offset.file == BRW_IMMEDIATE_VALUE &&
900 offset.type == BRW_REGISTER_TYPE_UD);
901 uint32_t read_offset = offset.dw1.ud;
902
903 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
904 read_offset, surf_index);
905
906 brw_mark_surface_used(prog_data, surf_index);
907 }
908
909 void
910 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
911 struct brw_reg dst,
912 struct brw_reg index,
913 struct brw_reg offset)
914 {
915 assert(inst->mlen == 0);
916 assert(index.type == BRW_REGISTER_TYPE_UD);
917
918 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
919 /* Reference just the dword we need, to avoid angering validate_reg(). */
920 offset = brw_vec1_grf(offset.nr, 0);
921
922 /* We use the SIMD4x2 mode because we want to end up with 4 components in
923 * the destination loaded consecutively from the same offset (which appears
924 * in the first component, and the rest are ignored).
925 */
926 dst.width = BRW_WIDTH_4;
927
928 if (index.file == BRW_IMMEDIATE_VALUE) {
929
930 uint32_t surf_index = index.dw1.ud;
931
932 brw_push_insn_state(p);
933 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
934 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
935 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
936 brw_pop_insn_state(p);
937
938 brw_set_dest(p, send, dst);
939 brw_set_src0(p, send, offset);
940 brw_set_sampler_message(p, send,
941 surf_index,
942 0, /* LD message ignores sampler unit */
943 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
944 1, /* rlen */
945 1, /* mlen */
946 false, /* no header */
947 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
948 0);
949
950 brw_mark_surface_used(prog_data, surf_index);
951
952 } else {
953
954 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
955
956 brw_push_insn_state(p);
957 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
958 brw_set_default_access_mode(p, BRW_ALIGN_1);
959
960 /* a0.0 = surf_index & 0xff */
961 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
962 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
963 brw_set_dest(p, insn_and, addr);
964 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
965 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
966
967
968 /* a0.0 |= <descriptor> */
969 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
970 brw_set_sampler_message(p, insn_or,
971 0 /* surface */,
972 0 /* sampler */,
973 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
974 1 /* rlen */,
975 1 /* mlen */,
976 false /* header */,
977 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
978 0);
979 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
980 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
981 brw_set_src0(p, insn_or, addr);
982 brw_set_dest(p, insn_or, addr);
983
984
985 /* dst = send(offset, a0.0) */
986 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
987 brw_set_dest(p, insn_send, dst);
988 brw_set_src0(p, insn_send, offset);
989 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
990
991 brw_pop_insn_state(p);
992
993 /* visitor knows more than we do about the surface limit required,
994 * so has already done marking.
995 */
996
997 }
998 }
999
1000 void
1001 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1002 struct brw_reg dst,
1003 struct brw_reg index,
1004 struct brw_reg offset)
1005 {
1006 assert(brw->gen < 7); /* Should use the gen7 variant. */
1007 assert(inst->header_present);
1008 assert(inst->mlen);
1009
1010 assert(index.file == BRW_IMMEDIATE_VALUE &&
1011 index.type == BRW_REGISTER_TYPE_UD);
1012 uint32_t surf_index = index.dw1.ud;
1013
1014 uint32_t simd_mode, rlen, msg_type;
1015 if (dispatch_width == 16) {
1016 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1017 rlen = 8;
1018 } else {
1019 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1020 rlen = 4;
1021 }
1022
1023 if (brw->gen >= 5)
1024 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1025 else {
1026 /* We always use the SIMD16 message so that we only have to load U, and
1027 * not V or R.
1028 */
1029 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1030 assert(inst->mlen == 3);
1031 assert(inst->regs_written == 8);
1032 rlen = 8;
1033 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1034 }
1035
1036 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1037 BRW_REGISTER_TYPE_D);
1038 brw_MOV(p, offset_mrf, offset);
1039
1040 struct brw_reg header = brw_vec8_grf(0, 0);
1041 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1042
1043 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1044 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
1045 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1046 brw_set_src0(p, send, header);
1047 if (brw->gen < 6)
1048 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
1049
1050 /* Our surface is set up as floats, regardless of what actual data is
1051 * stored in it.
1052 */
1053 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1054 brw_set_sampler_message(p, send,
1055 surf_index,
1056 0, /* sampler (unused) */
1057 msg_type,
1058 rlen,
1059 inst->mlen,
1060 inst->header_present,
1061 simd_mode,
1062 return_format);
1063
1064 brw_mark_surface_used(prog_data, surf_index);
1065 }
1066
1067 void
1068 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1069 struct brw_reg dst,
1070 struct brw_reg index,
1071 struct brw_reg offset)
1072 {
1073 assert(brw->gen >= 7);
1074 /* Varying-offset pull constant loads are treated as a normal expression on
1075 * gen7, so the fact that it's a send message is hidden at the IR level.
1076 */
1077 assert(!inst->header_present);
1078 assert(!inst->mlen);
1079 assert(index.type == BRW_REGISTER_TYPE_UD);
1080
1081 uint32_t simd_mode, rlen, mlen;
1082 if (dispatch_width == 16) {
1083 mlen = 2;
1084 rlen = 8;
1085 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1086 } else {
1087 mlen = 1;
1088 rlen = 4;
1089 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1090 }
1091
1092 if (index.file == BRW_IMMEDIATE_VALUE) {
1093
1094 uint32_t surf_index = index.dw1.ud;
1095
1096 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1097 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1098 brw_set_src0(p, send, offset);
1099 brw_set_sampler_message(p, send,
1100 surf_index,
1101 0, /* LD message ignores sampler unit */
1102 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1103 rlen,
1104 mlen,
1105 false, /* no header */
1106 simd_mode,
1107 0);
1108
1109 brw_mark_surface_used(prog_data, surf_index);
1110
1111 } else {
1112
1113 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1114
1115 brw_push_insn_state(p);
1116 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1117 brw_set_default_access_mode(p, BRW_ALIGN_1);
1118
1119 /* a0.0 = surf_index & 0xff */
1120 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1121 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1122 brw_set_dest(p, insn_and, addr);
1123 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1124 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1125
1126
1127 /* a0.0 |= <descriptor> */
1128 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1129 brw_set_sampler_message(p, insn_or,
1130 0 /* surface */,
1131 0 /* sampler */,
1132 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1133 rlen /* rlen */,
1134 mlen /* mlen */,
1135 false /* header */,
1136 simd_mode,
1137 0);
1138 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1139 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1140 brw_set_src0(p, insn_or, addr);
1141 brw_set_dest(p, insn_or, addr);
1142
1143
1144 /* dst = send(offset, a0.0) */
1145 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1146 brw_set_dest(p, insn_send, retype(dst, BRW_REGISTER_TYPE_UW));
1147 brw_set_src0(p, insn_send, offset);
1148 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1149
1150 brw_pop_insn_state(p);
1151
1152 /* visitor knows more than we do about the surface limit required,
1153 * so has already done marking.
1154 */
1155 }
1156 }
1157
1158 /**
1159 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1160 * into the flags register (f0.0).
1161 *
1162 * Used only on Gen6 and above.
1163 */
1164 void
1165 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1166 {
1167 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1168 struct brw_reg dispatch_mask;
1169
1170 if (brw->gen >= 6)
1171 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1172 else
1173 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1174
1175 brw_push_insn_state(p);
1176 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1177 brw_MOV(p, flags, dispatch_mask);
1178 brw_pop_insn_state(p);
1179 }
1180
1181 void
1182 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1183 struct brw_reg dst,
1184 struct brw_reg src,
1185 struct brw_reg msg_data,
1186 unsigned msg_type)
1187 {
1188 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1189 msg_data.type == BRW_REGISTER_TYPE_UD);
1190
1191 brw_pixel_interpolator_query(p,
1192 retype(dst, BRW_REGISTER_TYPE_UW),
1193 src,
1194 inst->pi_noperspective,
1195 msg_type,
1196 msg_data.dw1.ud,
1197 inst->mlen,
1198 inst->regs_written);
1199 }
1200
1201
1202 static uint32_t brw_file_from_reg(fs_reg *reg)
1203 {
1204 switch (reg->file) {
1205 case GRF:
1206 return BRW_GENERAL_REGISTER_FILE;
1207 case MRF:
1208 return BRW_MESSAGE_REGISTER_FILE;
1209 case IMM:
1210 return BRW_IMMEDIATE_VALUE;
1211 default:
1212 unreachable("not reached");
1213 }
1214 }
1215
1216 struct brw_reg
1217 brw_reg_from_fs_reg(fs_reg *reg)
1218 {
1219 struct brw_reg brw_reg;
1220
1221 switch (reg->file) {
1222 case GRF:
1223 case MRF:
1224 if (reg->stride == 0) {
1225 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
1226 } else if (reg->width < 8) {
1227 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1228 brw_reg = stride(brw_reg, reg->width * reg->stride,
1229 reg->width, reg->stride);
1230 } else {
1231 /* From the Haswell PRM:
1232 *
1233 * VertStride must be used to cross GRF register boundaries. This
1234 * rule implies that elements within a 'Width' cannot cross GRF
1235 * boundaries.
1236 *
1237 * So, for registers with width > 8, we have to use a width of 8
1238 * and trust the compression state to sort out the exec size.
1239 */
1240 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1241 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1242 }
1243
1244 brw_reg = retype(brw_reg, reg->type);
1245 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1246 break;
1247 case IMM:
1248 switch (reg->type) {
1249 case BRW_REGISTER_TYPE_F:
1250 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
1251 break;
1252 case BRW_REGISTER_TYPE_D:
1253 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
1254 break;
1255 case BRW_REGISTER_TYPE_UD:
1256 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
1257 break;
1258 case BRW_REGISTER_TYPE_VF:
1259 brw_reg = brw_imm_vf(reg->fixed_hw_reg.dw1.ud);
1260 break;
1261 default:
1262 unreachable("not reached");
1263 }
1264 break;
1265 case HW_REG:
1266 assert(reg->type == reg->fixed_hw_reg.type);
1267 brw_reg = reg->fixed_hw_reg;
1268 break;
1269 case BAD_FILE:
1270 /* Probably unused. */
1271 brw_reg = brw_null_reg();
1272 break;
1273 case UNIFORM:
1274 unreachable("not reached");
1275 default:
1276 unreachable("not reached");
1277 }
1278 if (reg->abs)
1279 brw_reg = brw_abs(brw_reg);
1280 if (reg->negate)
1281 brw_reg = negate(brw_reg);
1282
1283 return brw_reg;
1284 }
1285
1286 /**
1287 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1288 * sampler LD messages.
1289 *
1290 * We don't want to bake it into the send message's code generation because
1291 * that means we don't get a chance to schedule the instructions.
1292 */
1293 void
1294 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1295 struct brw_reg dst,
1296 struct brw_reg value)
1297 {
1298 assert(value.file == BRW_IMMEDIATE_VALUE);
1299
1300 brw_push_insn_state(p);
1301 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1302 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1303 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1304 brw_pop_insn_state(p);
1305 }
1306
1307 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1308 * (when mask is passed as a uniform) of register mask before moving it
1309 * to register dst.
1310 */
1311 void
1312 fs_generator::generate_set_omask(fs_inst *inst,
1313 struct brw_reg dst,
1314 struct brw_reg mask)
1315 {
1316 bool stride_8_8_1 =
1317 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1318 mask.width == BRW_WIDTH_8 &&
1319 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1320
1321 bool stride_0_1_0 =
1322 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1323 mask.width == BRW_WIDTH_1 &&
1324 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1325
1326 assert(stride_8_8_1 || stride_0_1_0);
1327 assert(dst.type == BRW_REGISTER_TYPE_UW);
1328
1329 if (dispatch_width == 16)
1330 dst = vec16(dst);
1331 brw_push_insn_state(p);
1332 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1333 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1334
1335 if (stride_8_8_1) {
1336 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1337 } else if (stride_0_1_0) {
1338 brw_MOV(p, dst, retype(mask, dst.type));
1339 }
1340 brw_pop_insn_state(p);
1341 }
1342
1343 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1344 * the ADD instruction.
1345 */
1346 void
1347 fs_generator::generate_set_sample_id(fs_inst *inst,
1348 struct brw_reg dst,
1349 struct brw_reg src0,
1350 struct brw_reg src1)
1351 {
1352 assert(dst.type == BRW_REGISTER_TYPE_D ||
1353 dst.type == BRW_REGISTER_TYPE_UD);
1354 assert(src0.type == BRW_REGISTER_TYPE_D ||
1355 src0.type == BRW_REGISTER_TYPE_UD);
1356
1357 brw_push_insn_state(p);
1358 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1359 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1360 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1361 if (dispatch_width == 8) {
1362 brw_ADD(p, dst, src0, reg);
1363 } else if (dispatch_width == 16) {
1364 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1365 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1366 }
1367 brw_pop_insn_state(p);
1368 }
1369
1370 /**
1371 * Change the register's data type from UD to W, doubling the strides in order
1372 * to compensate for halving the data type width.
1373 */
1374 static struct brw_reg
1375 ud_reg_to_w(struct brw_reg r)
1376 {
1377 assert(r.type == BRW_REGISTER_TYPE_UD);
1378 r.type = BRW_REGISTER_TYPE_W;
1379
1380 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1381 * doubles the real stride.
1382 */
1383 if (r.hstride != 0)
1384 ++r.hstride;
1385 if (r.vstride != 0)
1386 ++r.vstride;
1387
1388 return r;
1389 }
1390
1391 void
1392 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1393 struct brw_reg dst,
1394 struct brw_reg x,
1395 struct brw_reg y)
1396 {
1397 assert(brw->gen >= 7);
1398 assert(dst.type == BRW_REGISTER_TYPE_UD);
1399 assert(x.type == BRW_REGISTER_TYPE_F);
1400 assert(y.type == BRW_REGISTER_TYPE_F);
1401
1402 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1403 *
1404 * Because this instruction does not have a 16-bit floating-point type,
1405 * the destination data type must be Word (W).
1406 *
1407 * The destination must be DWord-aligned and specify a horizontal stride
1408 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1409 * each destination channel and the upper word is not modified.
1410 */
1411 struct brw_reg dst_w = ud_reg_to_w(dst);
1412
1413 /* Give each 32-bit channel of dst the form below , where "." means
1414 * unchanged.
1415 * 0x....hhhh
1416 */
1417 brw_F32TO16(p, dst_w, y);
1418
1419 /* Now the form:
1420 * 0xhhhh0000
1421 */
1422 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1423
1424 /* And, finally the form of packHalf2x16's output:
1425 * 0xhhhhllll
1426 */
1427 brw_F32TO16(p, dst_w, x);
1428 }
1429
1430 void
1431 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1432 struct brw_reg dst,
1433 struct brw_reg src)
1434 {
1435 assert(brw->gen >= 7);
1436 assert(dst.type == BRW_REGISTER_TYPE_F);
1437 assert(src.type == BRW_REGISTER_TYPE_UD);
1438
1439 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1440 *
1441 * Because this instruction does not have a 16-bit floating-point type,
1442 * the source data type must be Word (W). The destination type must be
1443 * F (Float).
1444 */
1445 struct brw_reg src_w = ud_reg_to_w(src);
1446
1447 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1448 * For the Y case, we wish to access only the upper word; therefore
1449 * a 16-bit subregister offset is needed.
1450 */
1451 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1452 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1453 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1454 src_w.subnr += 2;
1455
1456 brw_F16TO32(p, dst, src_w);
1457 }
1458
1459 void
1460 fs_generator::generate_shader_time_add(fs_inst *inst,
1461 struct brw_reg payload,
1462 struct brw_reg offset,
1463 struct brw_reg value)
1464 {
1465 assert(brw->gen >= 7);
1466 brw_push_insn_state(p);
1467 brw_set_default_mask_control(p, true);
1468
1469 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1470 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1471 offset.type);
1472 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1473 value.type);
1474
1475 assert(offset.file == BRW_IMMEDIATE_VALUE);
1476 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1477 value.width = BRW_WIDTH_1;
1478 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1479 value.vstride = BRW_VERTICAL_STRIDE_0;
1480 } else {
1481 assert(value.file == BRW_IMMEDIATE_VALUE);
1482 }
1483
1484 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1485 * case, and we don't really care about squeezing every bit of performance
1486 * out of this path, so we just emit the MOVs from here.
1487 */
1488 brw_MOV(p, payload_offset, offset);
1489 brw_MOV(p, payload_value, value);
1490 brw_shader_time_add(p, payload,
1491 prog_data->binding_table.shader_time_start);
1492 brw_pop_insn_state(p);
1493
1494 brw_mark_surface_used(prog_data,
1495 prog_data->binding_table.shader_time_start);
1496 }
1497
1498 void
1499 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1500 struct brw_reg payload,
1501 struct brw_reg atomic_op,
1502 struct brw_reg surf_index)
1503 {
1504 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1505 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1506 surf_index.file == BRW_IMMEDIATE_VALUE &&
1507 surf_index.type == BRW_REGISTER_TYPE_UD);
1508
1509 brw_untyped_atomic(p, dst, payload, atomic_op.dw1.ud, surf_index.dw1.ud,
1510 inst->mlen, inst->exec_size / 8);
1511
1512 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1513 }
1514
1515 void
1516 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1517 struct brw_reg payload,
1518 struct brw_reg surf_index)
1519 {
1520 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1521 surf_index.type == BRW_REGISTER_TYPE_UD);
1522
1523 brw_untyped_surface_read(p, dst, payload,
1524 surf_index.dw1.ud,
1525 inst->mlen, inst->exec_size / 8);
1526
1527 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1528 }
1529
1530 int
1531 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1532 {
1533 /* align to 64 byte boundary. */
1534 while (p->next_insn_offset % 64)
1535 brw_NOP(p);
1536
1537 this->dispatch_width = dispatch_width;
1538 if (dispatch_width == 16)
1539 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1540
1541 int start_offset = p->next_insn_offset;
1542 int loop_count = 0;
1543
1544 struct annotation_info annotation;
1545 memset(&annotation, 0, sizeof(annotation));
1546
1547 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1548 struct brw_reg src[3], dst;
1549 unsigned int last_insn_offset = p->next_insn_offset;
1550
1551 if (unlikely(debug_flag))
1552 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1553
1554 for (unsigned int i = 0; i < inst->sources; i++) {
1555 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1556
1557 /* The accumulator result appears to get used for the
1558 * conditional modifier generation. When negating a UD
1559 * value, there is a 33rd bit generated for the sign in the
1560 * accumulator value, so now you can't check, for example,
1561 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1562 */
1563 assert(!inst->conditional_mod ||
1564 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1565 !inst->src[i].negate);
1566 }
1567 dst = brw_reg_from_fs_reg(&inst->dst);
1568
1569 brw_set_default_predicate_control(p, inst->predicate);
1570 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1571 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1572 brw_set_default_saturate(p, inst->saturate);
1573 brw_set_default_mask_control(p, inst->force_writemask_all);
1574 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1575
1576 switch (inst->exec_size) {
1577 case 1:
1578 case 2:
1579 case 4:
1580 assert(inst->force_writemask_all);
1581 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1582 break;
1583 case 8:
1584 if (inst->force_sechalf) {
1585 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1586 } else {
1587 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1588 }
1589 break;
1590 case 16:
1591 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1592 break;
1593 default:
1594 unreachable(!"Invalid instruction width");
1595 }
1596
1597 switch (inst->opcode) {
1598 case BRW_OPCODE_MOV:
1599 brw_MOV(p, dst, src[0]);
1600 break;
1601 case BRW_OPCODE_ADD:
1602 brw_ADD(p, dst, src[0], src[1]);
1603 break;
1604 case BRW_OPCODE_MUL:
1605 brw_MUL(p, dst, src[0], src[1]);
1606 break;
1607 case BRW_OPCODE_AVG:
1608 brw_AVG(p, dst, src[0], src[1]);
1609 break;
1610 case BRW_OPCODE_MACH:
1611 brw_MACH(p, dst, src[0], src[1]);
1612 break;
1613
1614 case BRW_OPCODE_MAD:
1615 assert(brw->gen >= 6);
1616 brw_set_default_access_mode(p, BRW_ALIGN_16);
1617 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1618 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1619 brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1620 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1621 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1622 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1623 } else {
1624 brw_MAD(p, dst, src[0], src[1], src[2]);
1625 }
1626 brw_set_default_access_mode(p, BRW_ALIGN_1);
1627 break;
1628
1629 case BRW_OPCODE_LRP:
1630 assert(brw->gen >= 6);
1631 brw_set_default_access_mode(p, BRW_ALIGN_16);
1632 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1633 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1634 brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1635 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1636 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1637 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1638 } else {
1639 brw_LRP(p, dst, src[0], src[1], src[2]);
1640 }
1641 brw_set_default_access_mode(p, BRW_ALIGN_1);
1642 break;
1643
1644 case BRW_OPCODE_FRC:
1645 brw_FRC(p, dst, src[0]);
1646 break;
1647 case BRW_OPCODE_RNDD:
1648 brw_RNDD(p, dst, src[0]);
1649 break;
1650 case BRW_OPCODE_RNDE:
1651 brw_RNDE(p, dst, src[0]);
1652 break;
1653 case BRW_OPCODE_RNDZ:
1654 brw_RNDZ(p, dst, src[0]);
1655 break;
1656
1657 case BRW_OPCODE_AND:
1658 brw_AND(p, dst, src[0], src[1]);
1659 break;
1660 case BRW_OPCODE_OR:
1661 brw_OR(p, dst, src[0], src[1]);
1662 break;
1663 case BRW_OPCODE_XOR:
1664 brw_XOR(p, dst, src[0], src[1]);
1665 break;
1666 case BRW_OPCODE_NOT:
1667 brw_NOT(p, dst, src[0]);
1668 break;
1669 case BRW_OPCODE_ASR:
1670 brw_ASR(p, dst, src[0], src[1]);
1671 break;
1672 case BRW_OPCODE_SHR:
1673 brw_SHR(p, dst, src[0], src[1]);
1674 break;
1675 case BRW_OPCODE_SHL:
1676 brw_SHL(p, dst, src[0], src[1]);
1677 break;
1678 case BRW_OPCODE_F32TO16:
1679 assert(brw->gen >= 7);
1680 brw_F32TO16(p, dst, src[0]);
1681 break;
1682 case BRW_OPCODE_F16TO32:
1683 assert(brw->gen >= 7);
1684 brw_F16TO32(p, dst, src[0]);
1685 break;
1686 case BRW_OPCODE_CMP:
1687 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1688 break;
1689 case BRW_OPCODE_SEL:
1690 brw_SEL(p, dst, src[0], src[1]);
1691 break;
1692 case BRW_OPCODE_BFREV:
1693 assert(brw->gen >= 7);
1694 /* BFREV only supports UD type for src and dst. */
1695 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1696 retype(src[0], BRW_REGISTER_TYPE_UD));
1697 break;
1698 case BRW_OPCODE_FBH:
1699 assert(brw->gen >= 7);
1700 /* FBH only supports UD type for dst. */
1701 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1702 break;
1703 case BRW_OPCODE_FBL:
1704 assert(brw->gen >= 7);
1705 /* FBL only supports UD type for dst. */
1706 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1707 break;
1708 case BRW_OPCODE_CBIT:
1709 assert(brw->gen >= 7);
1710 /* CBIT only supports UD type for dst. */
1711 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1712 break;
1713 case BRW_OPCODE_ADDC:
1714 assert(brw->gen >= 7);
1715 brw_ADDC(p, dst, src[0], src[1]);
1716 break;
1717 case BRW_OPCODE_SUBB:
1718 assert(brw->gen >= 7);
1719 brw_SUBB(p, dst, src[0], src[1]);
1720 break;
1721 case BRW_OPCODE_MAC:
1722 brw_MAC(p, dst, src[0], src[1]);
1723 break;
1724
1725 case BRW_OPCODE_BFE:
1726 assert(brw->gen >= 7);
1727 brw_set_default_access_mode(p, BRW_ALIGN_16);
1728 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1729 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1730 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1731 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1732 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1733 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1734 } else {
1735 brw_BFE(p, dst, src[0], src[1], src[2]);
1736 }
1737 brw_set_default_access_mode(p, BRW_ALIGN_1);
1738 break;
1739
1740 case BRW_OPCODE_BFI1:
1741 assert(brw->gen >= 7);
1742 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1743 * should
1744 *
1745 * "Force BFI instructions to be executed always in SIMD8."
1746 */
1747 if (dispatch_width == 16 && brw->is_haswell) {
1748 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1749 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1750 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1751 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1752 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1753 } else {
1754 brw_BFI1(p, dst, src[0], src[1]);
1755 }
1756 break;
1757 case BRW_OPCODE_BFI2:
1758 assert(brw->gen >= 7);
1759 brw_set_default_access_mode(p, BRW_ALIGN_16);
1760 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1761 * should
1762 *
1763 * "Force BFI instructions to be executed always in SIMD8."
1764 *
1765 * Otherwise we would be able to emit compressed instructions like we
1766 * do for the other three-source instructions.
1767 */
1768 if (dispatch_width == 16 && brw->gen < 8) {
1769 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1770 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1771 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1772 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1773 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1774 } else {
1775 brw_BFI2(p, dst, src[0], src[1], src[2]);
1776 }
1777 brw_set_default_access_mode(p, BRW_ALIGN_1);
1778 break;
1779
1780 case BRW_OPCODE_IF:
1781 if (inst->src[0].file != BAD_FILE) {
1782 /* The instruction has an embedded compare (only allowed on gen6) */
1783 assert(brw->gen == 6);
1784 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1785 } else {
1786 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1787 }
1788 break;
1789
1790 case BRW_OPCODE_ELSE:
1791 brw_ELSE(p);
1792 break;
1793 case BRW_OPCODE_ENDIF:
1794 brw_ENDIF(p);
1795 break;
1796
1797 case BRW_OPCODE_DO:
1798 brw_DO(p, BRW_EXECUTE_8);
1799 break;
1800
1801 case BRW_OPCODE_BREAK:
1802 brw_BREAK(p);
1803 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1804 break;
1805 case BRW_OPCODE_CONTINUE:
1806 brw_CONT(p);
1807 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1808 break;
1809
1810 case BRW_OPCODE_WHILE:
1811 brw_WHILE(p);
1812 loop_count++;
1813 break;
1814
1815 case SHADER_OPCODE_RCP:
1816 case SHADER_OPCODE_RSQ:
1817 case SHADER_OPCODE_SQRT:
1818 case SHADER_OPCODE_EXP2:
1819 case SHADER_OPCODE_LOG2:
1820 case SHADER_OPCODE_SIN:
1821 case SHADER_OPCODE_COS:
1822 assert(brw->gen < 6 || inst->mlen == 0);
1823 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1824 if (brw->gen >= 7) {
1825 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1826 brw_null_reg());
1827 } else if (brw->gen == 6) {
1828 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1829 } else if (brw->gen == 5 || brw->is_g4x) {
1830 generate_math_g45(inst, dst, src[0]);
1831 } else {
1832 generate_math_gen4(inst, dst, src[0]);
1833 }
1834 break;
1835 case SHADER_OPCODE_INT_QUOTIENT:
1836 case SHADER_OPCODE_INT_REMAINDER:
1837 case SHADER_OPCODE_POW:
1838 assert(brw->gen < 6 || inst->mlen == 0);
1839 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1840 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1841 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1842 } else if (brw->gen >= 6) {
1843 generate_math_gen6(inst, dst, src[0], src[1]);
1844 } else {
1845 generate_math_gen4(inst, dst, src[0]);
1846 }
1847 break;
1848 case FS_OPCODE_PIXEL_X:
1849 generate_pixel_xy(dst, true);
1850 break;
1851 case FS_OPCODE_PIXEL_Y:
1852 generate_pixel_xy(dst, false);
1853 break;
1854 case FS_OPCODE_CINTERP:
1855 brw_MOV(p, dst, src[0]);
1856 break;
1857 case FS_OPCODE_LINTERP:
1858 generate_linterp(inst, dst, src);
1859 break;
1860 case SHADER_OPCODE_TEX:
1861 case FS_OPCODE_TXB:
1862 case SHADER_OPCODE_TXD:
1863 case SHADER_OPCODE_TXF:
1864 case SHADER_OPCODE_TXF_CMS:
1865 case SHADER_OPCODE_TXF_UMS:
1866 case SHADER_OPCODE_TXF_MCS:
1867 case SHADER_OPCODE_TXL:
1868 case SHADER_OPCODE_TXS:
1869 case SHADER_OPCODE_LOD:
1870 case SHADER_OPCODE_TG4:
1871 case SHADER_OPCODE_TG4_OFFSET:
1872 generate_tex(inst, dst, src[0], src[1]);
1873 break;
1874 case FS_OPCODE_DDX:
1875 generate_ddx(inst, dst, src[0], src[1]);
1876 break;
1877 case FS_OPCODE_DDY:
1878 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1879 * guarantee that key->render_to_fbo is set).
1880 */
1881 assert(stage == MESA_SHADER_FRAGMENT &&
1882 ((gl_fragment_program *) prog)->UsesDFdy);
1883 generate_ddy(inst, dst, src[0], src[1],
1884 ((brw_wm_prog_key * const) this->key)->render_to_fbo);
1885 break;
1886
1887 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1888 generate_scratch_write(inst, src[0]);
1889 break;
1890
1891 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1892 generate_scratch_read(inst, dst);
1893 break;
1894
1895 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1896 generate_scratch_read_gen7(inst, dst);
1897 break;
1898
1899 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1900 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1901 break;
1902
1903 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1904 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1905 break;
1906
1907 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1908 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1909 break;
1910
1911 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1912 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1913 break;
1914
1915 case FS_OPCODE_REP_FB_WRITE:
1916 case FS_OPCODE_FB_WRITE:
1917 generate_fb_write(inst, src[0]);
1918 break;
1919
1920 case FS_OPCODE_BLORP_FB_WRITE:
1921 generate_blorp_fb_write(inst);
1922 break;
1923
1924 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1925 generate_mov_dispatch_to_flags(inst);
1926 break;
1927
1928 case FS_OPCODE_DISCARD_JUMP:
1929 generate_discard_jump(inst);
1930 break;
1931
1932 case SHADER_OPCODE_SHADER_TIME_ADD:
1933 generate_shader_time_add(inst, src[0], src[1], src[2]);
1934 break;
1935
1936 case SHADER_OPCODE_UNTYPED_ATOMIC:
1937 generate_untyped_atomic(inst, dst, src[0], src[1], src[2]);
1938 break;
1939
1940 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1941 generate_untyped_surface_read(inst, dst, src[0], src[1]);
1942 break;
1943
1944 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1945 generate_set_simd4x2_offset(inst, dst, src[0]);
1946 break;
1947
1948 case FS_OPCODE_SET_OMASK:
1949 generate_set_omask(inst, dst, src[0]);
1950 break;
1951
1952 case FS_OPCODE_SET_SAMPLE_ID:
1953 generate_set_sample_id(inst, dst, src[0], src[1]);
1954 break;
1955
1956 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1957 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1958 break;
1959
1960 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1961 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1962 generate_unpack_half_2x16_split(inst, dst, src[0]);
1963 break;
1964
1965 case FS_OPCODE_PLACEHOLDER_HALT:
1966 /* This is the place where the final HALT needs to be inserted if
1967 * we've emitted any discards. If not, this will emit no code.
1968 */
1969 if (!patch_discard_jumps_to_fb_writes()) {
1970 if (unlikely(debug_flag)) {
1971 annotation.ann_count--;
1972 }
1973 }
1974 break;
1975
1976 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
1977 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1978 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
1979 break;
1980
1981 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
1982 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1983 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
1984 break;
1985
1986 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
1987 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1988 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
1989 break;
1990
1991 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
1992 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1993 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
1994 break;
1995
1996 default:
1997 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1998 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1999 opcode_descs[inst->opcode].name);
2000 } else {
2001 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
2002 }
2003 abort();
2004
2005 case SHADER_OPCODE_LOAD_PAYLOAD:
2006 unreachable("Should be lowered by lower_load_payload()");
2007 }
2008
2009 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2010 assert(p->next_insn_offset == last_insn_offset + 16 ||
2011 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2012 "emitting more than 1 instruction");
2013
2014 brw_inst *last = &p->store[last_insn_offset / 16];
2015
2016 if (inst->conditional_mod)
2017 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
2018 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
2019 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
2020 }
2021 }
2022
2023 brw_set_uip_jip(p);
2024 annotation_finalize(&annotation, p->next_insn_offset);
2025
2026 int before_size = p->next_insn_offset - start_offset;
2027 brw_compact_instructions(p, start_offset, annotation.ann_count,
2028 annotation.ann);
2029 int after_size = p->next_insn_offset - start_offset;
2030
2031 if (unlikely(debug_flag)) {
2032 if (shader_prog) {
2033 fprintf(stderr,
2034 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
2035 shader_prog->Label ? shader_prog->Label : "unnamed",
2036 shader_prog->Name, dispatch_width);
2037 } else if (prog) {
2038 fprintf(stderr,
2039 "Native code for fragment program %d (SIMD%d dispatch):\n",
2040 prog->Id, dispatch_width);
2041 } else {
2042 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
2043 dispatch_width);
2044 }
2045 fprintf(stderr, "SIMD%d shader: %d instructions. %d loops. Compacted %d to %d"
2046 " bytes (%.0f%%)\n",
2047 dispatch_width, before_size / 16, loop_count, before_size, after_size,
2048 100.0f * (before_size - after_size) / before_size);
2049
2050 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
2051 ralloc_free(annotation.ann);
2052 }
2053
2054 return start_offset;
2055 }
2056
2057 const unsigned *
2058 fs_generator::get_assembly(unsigned int *assembly_size)
2059 {
2060 return brw_get_program(p, assembly_size);
2061 }