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i965/fs: Remove the gl_program from the generator
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "main/macros.h"
31 #include "brw_context.h"
32 #include "brw_eu.h"
33 #include "brw_fs.h"
34 #include "brw_cfg.h"
35
36 static uint32_t brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case GRF:
40 return BRW_GENERAL_REGISTER_FILE;
41 case MRF:
42 return BRW_MESSAGE_REGISTER_FILE;
43 case IMM:
44 return BRW_IMMEDIATE_VALUE;
45 default:
46 unreachable("not reached");
47 }
48 }
49
50 static struct brw_reg
51 brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
52 {
53 struct brw_reg brw_reg;
54
55 switch (reg->file) {
56 case MRF:
57 assert((reg->reg & ~(1 << 7)) < BRW_MAX_MRF(gen));
58 /* Fallthrough */
59 case GRF:
60 if (reg->stride == 0) {
61 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
62 } else if (inst->exec_size < 8) {
63 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
64 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
65 inst->exec_size, reg->stride);
66 } else {
67 /* From the Haswell PRM:
68 *
69 * VertStride must be used to cross GRF register boundaries. This
70 * rule implies that elements within a 'Width' cannot cross GRF
71 * boundaries.
72 *
73 * So, for registers with width > 8, we have to use a width of 8
74 * and trust the compression state to sort out the exec size.
75 */
76 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
77 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
78 }
79
80 brw_reg = retype(brw_reg, reg->type);
81 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
82 break;
83 case IMM:
84 assert(reg->stride == ((reg->type == BRW_REGISTER_TYPE_V ||
85 reg->type == BRW_REGISTER_TYPE_UV ||
86 reg->type == BRW_REGISTER_TYPE_VF) ? 1 : 0));
87
88 switch (reg->type) {
89 case BRW_REGISTER_TYPE_F:
90 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
91 break;
92 case BRW_REGISTER_TYPE_D:
93 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
94 break;
95 case BRW_REGISTER_TYPE_UD:
96 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
97 break;
98 case BRW_REGISTER_TYPE_W:
99 brw_reg = brw_imm_w(reg->fixed_hw_reg.dw1.d);
100 break;
101 case BRW_REGISTER_TYPE_UW:
102 brw_reg = brw_imm_uw(reg->fixed_hw_reg.dw1.ud);
103 break;
104 case BRW_REGISTER_TYPE_VF:
105 brw_reg = brw_imm_vf(reg->fixed_hw_reg.dw1.ud);
106 break;
107 default:
108 unreachable("not reached");
109 }
110 break;
111 case HW_REG:
112 assert(reg->type == reg->fixed_hw_reg.type);
113 brw_reg = reg->fixed_hw_reg;
114 break;
115 case BAD_FILE:
116 /* Probably unused. */
117 brw_reg = brw_null_reg();
118 break;
119 default:
120 unreachable("not reached");
121 }
122 if (reg->abs)
123 brw_reg = brw_abs(brw_reg);
124 if (reg->negate)
125 brw_reg = negate(brw_reg);
126
127 return brw_reg;
128 }
129
130 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
131 void *mem_ctx,
132 const void *key,
133 struct brw_stage_prog_data *prog_data,
134 unsigned promoted_constants,
135 bool runtime_check_aads_emit,
136 const char *stage_abbrev)
137
138 : compiler(compiler), log_data(log_data),
139 devinfo(compiler->devinfo), key(key),
140 prog_data(prog_data),
141 promoted_constants(promoted_constants),
142 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
143 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
144 {
145 p = rzalloc(mem_ctx, struct brw_codegen);
146 brw_init_codegen(devinfo, p, mem_ctx);
147 }
148
149 fs_generator::~fs_generator()
150 {
151 }
152
153 class ip_record : public exec_node {
154 public:
155 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
156
157 ip_record(int ip)
158 {
159 this->ip = ip;
160 }
161
162 int ip;
163 };
164
165 bool
166 fs_generator::patch_discard_jumps_to_fb_writes()
167 {
168 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
169 return false;
170
171 int scale = brw_jump_scale(p->devinfo);
172
173 /* There is a somewhat strange undocumented requirement of using
174 * HALT, according to the simulator. If some channel has HALTed to
175 * a particular UIP, then by the end of the program, every channel
176 * must have HALTed to that UIP. Furthermore, the tracking is a
177 * stack, so you can't do the final halt of a UIP after starting
178 * halting to a new UIP.
179 *
180 * Symptoms of not emitting this instruction on actual hardware
181 * included GPU hangs and sparkly rendering on the piglit discard
182 * tests.
183 */
184 brw_inst *last_halt = gen6_HALT(p);
185 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
186 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
187
188 int ip = p->nr_insn;
189
190 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
191 brw_inst *patch = &p->store[patch_ip->ip];
192
193 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
194 /* HALT takes a half-instruction distance from the pre-incremented IP. */
195 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
196 }
197
198 this->discard_halt_patches.make_empty();
199 return true;
200 }
201
202 void
203 fs_generator::fire_fb_write(fs_inst *inst,
204 struct brw_reg payload,
205 struct brw_reg implied_header,
206 GLuint nr)
207 {
208 uint32_t msg_control;
209
210 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
211
212 if (devinfo->gen < 6) {
213 brw_push_insn_state(p);
214 brw_set_default_exec_size(p, BRW_EXECUTE_8);
215 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
216 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
217 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
218 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
219 brw_pop_insn_state(p);
220 }
221
222 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
223 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
224 else if (prog_data->dual_src_blend) {
225 if (!inst->force_sechalf)
226 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
227 else
228 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
229 } else if (inst->exec_size == 16)
230 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
231 else
232 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
233
234 uint32_t surf_index =
235 prog_data->binding_table.render_target_start + inst->target;
236
237 bool last_render_target = inst->eot ||
238 (prog_data->dual_src_blend && dispatch_width == 16);
239
240
241 brw_fb_WRITE(p,
242 dispatch_width,
243 payload,
244 implied_header,
245 msg_control,
246 surf_index,
247 nr,
248 0,
249 inst->eot,
250 last_render_target,
251 inst->header_size != 0);
252
253 brw_mark_surface_used(&prog_data->base, surf_index);
254 }
255
256 void
257 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
258 {
259 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
260 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
261 struct brw_reg implied_header;
262
263 if (devinfo->gen < 8 && !devinfo->is_haswell) {
264 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
265 }
266
267 if (inst->base_mrf >= 0)
268 payload = brw_message_reg(inst->base_mrf);
269
270 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
271 * move, here's g1.
272 */
273 if (inst->header_size != 0) {
274 brw_push_insn_state(p);
275 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
276 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
277 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
278 brw_set_default_flag_reg(p, 0, 0);
279
280 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
281 * present.
282 */
283 if (prog_data->uses_kill) {
284 struct brw_reg pixel_mask;
285
286 if (devinfo->gen >= 6)
287 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
288 else
289 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
290
291 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
292 }
293
294 if (devinfo->gen >= 6) {
295 brw_push_insn_state(p);
296 brw_set_default_exec_size(p, BRW_EXECUTE_16);
297 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
298 brw_MOV(p,
299 retype(payload, BRW_REGISTER_TYPE_UD),
300 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
301 brw_pop_insn_state(p);
302
303 if (inst->target > 0 && key->replicate_alpha) {
304 /* Set "Source0 Alpha Present to RenderTarget" bit in message
305 * header.
306 */
307 brw_OR(p,
308 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
309 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
310 brw_imm_ud(0x1 << 11));
311 }
312
313 if (inst->target > 0) {
314 /* Set the render target index for choosing BLEND_STATE. */
315 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
316 BRW_REGISTER_TYPE_UD),
317 brw_imm_ud(inst->target));
318 }
319
320 implied_header = brw_null_reg();
321 } else {
322 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
323 }
324
325 brw_pop_insn_state(p);
326 } else {
327 implied_header = brw_null_reg();
328 }
329
330 if (!runtime_check_aads_emit) {
331 fire_fb_write(inst, payload, implied_header, inst->mlen);
332 } else {
333 /* This can only happen in gen < 6 */
334 assert(devinfo->gen < 6);
335
336 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
337
338 /* Check runtime bit to detect if we have to send AA data or not */
339 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
340 brw_AND(p,
341 v1_null_ud,
342 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
343 brw_imm_ud(1<<26));
344 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
345
346 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
347 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
348 {
349 /* Don't send AA data */
350 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
351 }
352 brw_land_fwd_jump(p, jmp);
353 fire_fb_write(inst, payload, implied_header, inst->mlen);
354 }
355 }
356
357 void
358 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
359 {
360 brw_inst *insn;
361
362 insn = brw_next_insn(p, BRW_OPCODE_SEND);
363
364 brw_set_dest(p, insn, brw_null_reg());
365 brw_set_src0(p, insn, payload);
366 brw_set_src1(p, insn, brw_imm_d(0));
367
368 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
369 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
370
371 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
372 brw_inst_set_rlen(p->devinfo, insn, 0);
373 brw_inst_set_eot(p->devinfo, insn, inst->eot);
374 brw_inst_set_header_present(p->devinfo, insn, true);
375 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
376 }
377
378 void
379 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
380 {
381 struct brw_inst *insn;
382
383 insn = brw_next_insn(p, BRW_OPCODE_SEND);
384
385 brw_set_dest(p, insn, brw_null_reg());
386 brw_set_src0(p, insn, payload);
387 brw_set_src1(p, insn, brw_imm_d(0));
388
389 /* Terminate a compute shader by sending a message to the thread spawner.
390 */
391 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
392 brw_inst_set_mlen(devinfo, insn, 1);
393 brw_inst_set_rlen(devinfo, insn, 0);
394 brw_inst_set_eot(devinfo, insn, inst->eot);
395 brw_inst_set_header_present(devinfo, insn, false);
396
397 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
398 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
399
400 /* Note that even though the thread has a URB resource associated with it,
401 * we set the "do not dereference URB" bit, because the URB resource is
402 * managed by the fixed-function unit, so it will free it automatically.
403 */
404 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
405
406 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
407 }
408
409 void
410 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
411 {
412 brw_barrier(p, src);
413 brw_WAIT(p);
414 }
415
416 void
417 fs_generator::generate_blorp_fb_write(fs_inst *inst)
418 {
419 brw_fb_WRITE(p,
420 16 /* dispatch_width */,
421 brw_message_reg(inst->base_mrf),
422 brw_reg_from_fs_reg(inst, &inst->src[0], devinfo->gen),
423 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
424 inst->target,
425 inst->mlen,
426 0,
427 true,
428 true,
429 inst->header_size != 0);
430 }
431
432 void
433 fs_generator::generate_linterp(fs_inst *inst,
434 struct brw_reg dst, struct brw_reg *src)
435 {
436 /* PLN reads:
437 * / in SIMD16 \
438 * -----------------------------------
439 * | src1+0 | src1+1 | src1+2 | src1+3 |
440 * |-----------------------------------|
441 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
442 * -----------------------------------
443 *
444 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
445 *
446 * -----------------------------------
447 * | src1+0 | src1+1 | src1+2 | src1+3 |
448 * |-----------------------------------|
449 * |(x0, x1)|(y0, y1)| | | in SIMD8
450 * |-----------------------------------|
451 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
452 * -----------------------------------
453 *
454 * See also: emit_interpolation_setup_gen4().
455 */
456 struct brw_reg delta_x = src[0];
457 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
458 struct brw_reg interp = src[1];
459
460 if (devinfo->has_pln &&
461 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
462 brw_PLN(p, dst, interp, delta_x);
463 } else {
464 brw_LINE(p, brw_null_reg(), interp, delta_x);
465 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
466 }
467 }
468
469 void
470 fs_generator::generate_math_gen6(fs_inst *inst,
471 struct brw_reg dst,
472 struct brw_reg src0,
473 struct brw_reg src1)
474 {
475 int op = brw_math_function(inst->opcode);
476 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
477
478 if (dispatch_width == 8) {
479 gen6_math(p, dst, op, src0, src1);
480 } else if (dispatch_width == 16) {
481 brw_push_insn_state(p);
482 brw_set_default_exec_size(p, BRW_EXECUTE_8);
483 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
484 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
485 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
486 gen6_math(p, sechalf(dst), op, sechalf(src0),
487 binop ? sechalf(src1) : brw_null_reg());
488 brw_pop_insn_state(p);
489 }
490 }
491
492 void
493 fs_generator::generate_math_gen4(fs_inst *inst,
494 struct brw_reg dst,
495 struct brw_reg src)
496 {
497 int op = brw_math_function(inst->opcode);
498
499 assert(inst->mlen >= 1);
500
501 if (dispatch_width == 8) {
502 gen4_math(p, dst,
503 op,
504 inst->base_mrf, src,
505 BRW_MATH_PRECISION_FULL);
506 } else if (dispatch_width == 16) {
507 brw_set_default_exec_size(p, BRW_EXECUTE_8);
508 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
509 gen4_math(p, firsthalf(dst),
510 op,
511 inst->base_mrf, firsthalf(src),
512 BRW_MATH_PRECISION_FULL);
513 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
514 gen4_math(p, sechalf(dst),
515 op,
516 inst->base_mrf + 1, sechalf(src),
517 BRW_MATH_PRECISION_FULL);
518
519 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
520 }
521 }
522
523 void
524 fs_generator::generate_math_g45(fs_inst *inst,
525 struct brw_reg dst,
526 struct brw_reg src)
527 {
528 if (inst->opcode == SHADER_OPCODE_POW ||
529 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
530 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
531 generate_math_gen4(inst, dst, src);
532 return;
533 }
534
535 int op = brw_math_function(inst->opcode);
536
537 assert(inst->mlen >= 1);
538
539 gen4_math(p, dst,
540 op,
541 inst->base_mrf, src,
542 BRW_MATH_PRECISION_FULL);
543 }
544
545 void
546 fs_generator::generate_get_buffer_size(fs_inst *inst,
547 struct brw_reg dst,
548 struct brw_reg src,
549 struct brw_reg surf_index)
550 {
551 assert(devinfo->gen >= 7);
552 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
553
554 uint32_t simd_mode;
555 int rlen = 4;
556
557 switch (inst->exec_size) {
558 case 8:
559 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
560 break;
561 case 16:
562 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
563 break;
564 default:
565 unreachable("Invalid width for texture instruction");
566 }
567
568 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
569 rlen = 8;
570 dst = vec16(dst);
571 }
572
573 brw_SAMPLE(p,
574 retype(dst, BRW_REGISTER_TYPE_UW),
575 inst->base_mrf,
576 src,
577 surf_index.dw1.ud,
578 0,
579 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
580 rlen, /* response length */
581 inst->mlen,
582 inst->header_size > 0,
583 simd_mode,
584 BRW_SAMPLER_RETURN_FORMAT_SINT32);
585
586 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
587 }
588
589 void
590 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
591 struct brw_reg sampler_index)
592 {
593 int msg_type = -1;
594 int rlen = 4;
595 uint32_t simd_mode;
596 uint32_t return_format;
597 bool is_combined_send = inst->eot;
598
599 switch (dst.type) {
600 case BRW_REGISTER_TYPE_D:
601 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
602 break;
603 case BRW_REGISTER_TYPE_UD:
604 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
605 break;
606 default:
607 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
608 break;
609 }
610
611 switch (inst->exec_size) {
612 case 8:
613 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
614 break;
615 case 16:
616 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
617 break;
618 default:
619 unreachable("Invalid width for texture instruction");
620 }
621
622 if (devinfo->gen >= 5) {
623 switch (inst->opcode) {
624 case SHADER_OPCODE_TEX:
625 if (inst->shadow_compare) {
626 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
627 } else {
628 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
629 }
630 break;
631 case FS_OPCODE_TXB:
632 if (inst->shadow_compare) {
633 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
634 } else {
635 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
636 }
637 break;
638 case SHADER_OPCODE_TXL:
639 if (inst->shadow_compare) {
640 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
641 } else {
642 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
643 }
644 break;
645 case SHADER_OPCODE_TXS:
646 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
647 break;
648 case SHADER_OPCODE_TXD:
649 if (inst->shadow_compare) {
650 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
651 assert(devinfo->gen >= 8 || devinfo->is_haswell);
652 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
653 } else {
654 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
655 }
656 break;
657 case SHADER_OPCODE_TXF:
658 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
659 break;
660 case SHADER_OPCODE_TXF_CMS:
661 if (devinfo->gen >= 7)
662 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
663 else
664 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
665 break;
666 case SHADER_OPCODE_TXF_UMS:
667 assert(devinfo->gen >= 7);
668 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
669 break;
670 case SHADER_OPCODE_TXF_MCS:
671 assert(devinfo->gen >= 7);
672 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
673 break;
674 case SHADER_OPCODE_LOD:
675 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
676 break;
677 case SHADER_OPCODE_TG4:
678 if (inst->shadow_compare) {
679 assert(devinfo->gen >= 7);
680 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
681 } else {
682 assert(devinfo->gen >= 6);
683 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
684 }
685 break;
686 case SHADER_OPCODE_TG4_OFFSET:
687 assert(devinfo->gen >= 7);
688 if (inst->shadow_compare) {
689 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
690 } else {
691 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
692 }
693 break;
694 case SHADER_OPCODE_SAMPLEINFO:
695 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
696 break;
697 default:
698 unreachable("not reached");
699 }
700 } else {
701 switch (inst->opcode) {
702 case SHADER_OPCODE_TEX:
703 /* Note that G45 and older determines shadow compare and dispatch width
704 * from message length for most messages.
705 */
706 if (inst->exec_size == 8) {
707 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
708 if (inst->shadow_compare) {
709 assert(inst->mlen == 6);
710 } else {
711 assert(inst->mlen <= 4);
712 }
713 } else {
714 if (inst->shadow_compare) {
715 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
716 assert(inst->mlen == 9);
717 } else {
718 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
719 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
720 }
721 }
722 break;
723 case FS_OPCODE_TXB:
724 if (inst->shadow_compare) {
725 assert(inst->exec_size == 8);
726 assert(inst->mlen == 6);
727 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
728 } else {
729 assert(inst->mlen == 9);
730 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
731 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
732 }
733 break;
734 case SHADER_OPCODE_TXL:
735 if (inst->shadow_compare) {
736 assert(inst->exec_size == 8);
737 assert(inst->mlen == 6);
738 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
739 } else {
740 assert(inst->mlen == 9);
741 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
742 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
743 }
744 break;
745 case SHADER_OPCODE_TXD:
746 /* There is no sample_d_c message; comparisons are done manually */
747 assert(inst->exec_size == 8);
748 assert(inst->mlen == 7 || inst->mlen == 10);
749 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
750 break;
751 case SHADER_OPCODE_TXF:
752 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
753 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
754 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
755 break;
756 case SHADER_OPCODE_TXS:
757 assert(inst->mlen == 3);
758 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
759 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
760 break;
761 default:
762 unreachable("not reached");
763 }
764 }
765 assert(msg_type != -1);
766
767 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
768 rlen = 8;
769 dst = vec16(dst);
770 }
771
772 if (is_combined_send) {
773 assert(devinfo->gen >= 9 || devinfo->is_cherryview);
774 rlen = 0;
775 }
776
777 assert(devinfo->gen < 7 || inst->header_size == 0 ||
778 src.file == BRW_GENERAL_REGISTER_FILE);
779
780 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
781
782 /* Load the message header if present. If there's a texture offset,
783 * we need to set it up explicitly and load the offset bitfield.
784 * Otherwise, we can use an implied move from g0 to the first message reg.
785 */
786 if (inst->header_size != 0) {
787 if (devinfo->gen < 6 && !inst->offset) {
788 /* Set up an implied move from g0 to the MRF. */
789 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
790 } else {
791 struct brw_reg header_reg;
792
793 if (devinfo->gen >= 7) {
794 header_reg = src;
795 } else {
796 assert(inst->base_mrf != -1);
797 header_reg = brw_message_reg(inst->base_mrf);
798 }
799
800 brw_push_insn_state(p);
801 brw_set_default_exec_size(p, BRW_EXECUTE_8);
802 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
803 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
804 /* Explicitly set up the message header by copying g0 to the MRF. */
805 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
806
807 if (inst->offset) {
808 /* Set the offset bits in DWord 2. */
809 brw_MOV(p, get_element_ud(header_reg, 2),
810 brw_imm_ud(inst->offset));
811 }
812
813 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
814 brw_pop_insn_state(p);
815 }
816 }
817
818 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
819 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
820 ? prog_data->binding_table.gather_texture_start
821 : prog_data->binding_table.texture_start;
822
823 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
824 uint32_t sampler = sampler_index.dw1.ud;
825
826 brw_SAMPLE(p,
827 retype(dst, BRW_REGISTER_TYPE_UW),
828 inst->base_mrf,
829 src,
830 sampler + base_binding_table_index,
831 sampler % 16,
832 msg_type,
833 rlen,
834 inst->mlen,
835 inst->header_size != 0,
836 simd_mode,
837 return_format);
838
839 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
840 } else {
841 /* Non-const sampler index */
842
843 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
844 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
845
846 brw_push_insn_state(p);
847 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
848 brw_set_default_access_mode(p, BRW_ALIGN_1);
849
850 /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
851 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
852 if (base_binding_table_index)
853 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
854 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
855
856 brw_pop_insn_state(p);
857
858 /* dst = send(offset, a0.0 | <descriptor>) */
859 brw_inst *insn = brw_send_indirect_message(
860 p, BRW_SFID_SAMPLER, dst, src, addr);
861 brw_set_sampler_message(p, insn,
862 0 /* surface */,
863 0 /* sampler */,
864 msg_type,
865 rlen,
866 inst->mlen /* mlen */,
867 inst->header_size != 0 /* header */,
868 simd_mode,
869 return_format);
870
871 /* visitor knows more than we do about the surface limit required,
872 * so has already done marking.
873 */
874 }
875
876 if (is_combined_send) {
877 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
878 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
879 }
880 }
881
882
883 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
884 * looking like:
885 *
886 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
887 *
888 * Ideally, we want to produce:
889 *
890 * DDX DDY
891 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
892 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
893 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
894 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
895 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
896 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
897 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
898 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
899 *
900 * and add another set of two more subspans if in 16-pixel dispatch mode.
901 *
902 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
903 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
904 * pair. But the ideal approximation may impose a huge performance cost on
905 * sample_d. On at least Haswell, sample_d instruction does some
906 * optimizations if the same LOD is used for all pixels in the subspan.
907 *
908 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
909 * appropriate swizzling.
910 */
911 void
912 fs_generator::generate_ddx(enum opcode opcode,
913 struct brw_reg dst, struct brw_reg src)
914 {
915 unsigned vstride, width;
916
917 if (opcode == FS_OPCODE_DDX_FINE) {
918 /* produce accurate derivatives */
919 vstride = BRW_VERTICAL_STRIDE_2;
920 width = BRW_WIDTH_2;
921 } else {
922 /* replicate the derivative at the top-left pixel to other pixels */
923 vstride = BRW_VERTICAL_STRIDE_4;
924 width = BRW_WIDTH_4;
925 }
926
927 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
928 src.negate, src.abs,
929 BRW_REGISTER_TYPE_F,
930 vstride,
931 width,
932 BRW_HORIZONTAL_STRIDE_0,
933 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
934 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
935 src.negate, src.abs,
936 BRW_REGISTER_TYPE_F,
937 vstride,
938 width,
939 BRW_HORIZONTAL_STRIDE_0,
940 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
941 brw_ADD(p, dst, src0, negate(src1));
942 }
943
944 /* The negate_value boolean is used to negate the derivative computation for
945 * FBOs, since they place the origin at the upper left instead of the lower
946 * left.
947 */
948 void
949 fs_generator::generate_ddy(enum opcode opcode,
950 struct brw_reg dst, struct brw_reg src,
951 bool negate_value)
952 {
953 if (opcode == FS_OPCODE_DDY_FINE) {
954 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
955 * Region Restrictions):
956 *
957 * In Align16 access mode, SIMD16 is not allowed for DW operations
958 * and SIMD8 is not allowed for DF operations.
959 *
960 * In this context, "DW operations" means "operations acting on 32-bit
961 * values", so it includes operations on floats.
962 *
963 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
964 * (Instruction Compression -> Rules and Restrictions):
965 *
966 * A compressed instruction must be in Align1 access mode. Align16
967 * mode instructions cannot be compressed.
968 *
969 * Similar text exists in the g45 PRM.
970 *
971 * On these platforms, if we're building a SIMD16 shader, we need to
972 * manually unroll to a pair of SIMD8 instructions.
973 */
974 bool unroll_to_simd8 =
975 (dispatch_width == 16 &&
976 (devinfo->gen == 4 || (devinfo->gen == 7 && !devinfo->is_haswell)));
977
978 /* produce accurate derivatives */
979 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
980 src.negate, src.abs,
981 BRW_REGISTER_TYPE_F,
982 BRW_VERTICAL_STRIDE_4,
983 BRW_WIDTH_4,
984 BRW_HORIZONTAL_STRIDE_1,
985 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
986 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
987 src.negate, src.abs,
988 BRW_REGISTER_TYPE_F,
989 BRW_VERTICAL_STRIDE_4,
990 BRW_WIDTH_4,
991 BRW_HORIZONTAL_STRIDE_1,
992 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
993 brw_push_insn_state(p);
994 brw_set_default_access_mode(p, BRW_ALIGN_16);
995 if (unroll_to_simd8) {
996 brw_set_default_exec_size(p, BRW_EXECUTE_8);
997 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
998 if (negate_value) {
999 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
1000 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1001 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
1002 } else {
1003 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
1004 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1005 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
1006 }
1007 } else {
1008 if (negate_value)
1009 brw_ADD(p, dst, src1, negate(src0));
1010 else
1011 brw_ADD(p, dst, src0, negate(src1));
1012 }
1013 brw_pop_insn_state(p);
1014 } else {
1015 /* replicate the derivative at the top-left pixel to other pixels */
1016 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1017 src.negate, src.abs,
1018 BRW_REGISTER_TYPE_F,
1019 BRW_VERTICAL_STRIDE_4,
1020 BRW_WIDTH_4,
1021 BRW_HORIZONTAL_STRIDE_0,
1022 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1023 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1024 src.negate, src.abs,
1025 BRW_REGISTER_TYPE_F,
1026 BRW_VERTICAL_STRIDE_4,
1027 BRW_WIDTH_4,
1028 BRW_HORIZONTAL_STRIDE_0,
1029 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1030 if (negate_value)
1031 brw_ADD(p, dst, src1, negate(src0));
1032 else
1033 brw_ADD(p, dst, src0, negate(src1));
1034 }
1035 }
1036
1037 void
1038 fs_generator::generate_discard_jump(fs_inst *inst)
1039 {
1040 assert(devinfo->gen >= 6);
1041
1042 /* This HALT will be patched up at FB write time to point UIP at the end of
1043 * the program, and at brw_uip_jip() JIP will be set to the end of the
1044 * current block (or the program).
1045 */
1046 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1047
1048 brw_push_insn_state(p);
1049 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1050 gen6_HALT(p);
1051 brw_pop_insn_state(p);
1052 }
1053
1054 void
1055 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1056 {
1057 assert(inst->mlen != 0);
1058
1059 brw_MOV(p,
1060 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1061 retype(src, BRW_REGISTER_TYPE_UD));
1062 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1063 inst->exec_size / 8, inst->offset);
1064 }
1065
1066 void
1067 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1068 {
1069 assert(inst->mlen != 0);
1070
1071 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1072 inst->exec_size / 8, inst->offset);
1073 }
1074
1075 void
1076 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1077 {
1078 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1079 }
1080
1081 void
1082 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1083 struct brw_reg dst,
1084 struct brw_reg index,
1085 struct brw_reg offset)
1086 {
1087 assert(inst->mlen != 0);
1088
1089 assert(index.file == BRW_IMMEDIATE_VALUE &&
1090 index.type == BRW_REGISTER_TYPE_UD);
1091 uint32_t surf_index = index.dw1.ud;
1092
1093 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1094 offset.type == BRW_REGISTER_TYPE_UD);
1095 uint32_t read_offset = offset.dw1.ud;
1096
1097 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1098 read_offset, surf_index);
1099
1100 brw_mark_surface_used(prog_data, surf_index);
1101 }
1102
1103 void
1104 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1105 struct brw_reg dst,
1106 struct brw_reg index,
1107 struct brw_reg offset)
1108 {
1109 assert(index.type == BRW_REGISTER_TYPE_UD);
1110
1111 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1112 /* Reference just the dword we need, to avoid angering validate_reg(). */
1113 offset = brw_vec1_grf(offset.nr, 0);
1114
1115 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1116 * the destination loaded consecutively from the same offset (which appears
1117 * in the first component, and the rest are ignored).
1118 */
1119 dst.width = BRW_WIDTH_4;
1120
1121 struct brw_reg src = offset;
1122 bool header_present = false;
1123
1124 if (devinfo->gen >= 9) {
1125 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1126 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1127 header_present = true;
1128
1129 brw_push_insn_state(p);
1130 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1131 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1132 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1133 brw_set_default_access_mode(p, BRW_ALIGN_1);
1134
1135 brw_MOV(p, get_element_ud(src, 2),
1136 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1137 brw_pop_insn_state(p);
1138 }
1139
1140 if (index.file == BRW_IMMEDIATE_VALUE) {
1141
1142 uint32_t surf_index = index.dw1.ud;
1143
1144 brw_push_insn_state(p);
1145 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1146 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1147 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1148 brw_pop_insn_state(p);
1149
1150 brw_set_dest(p, send, dst);
1151 brw_set_src0(p, send, src);
1152 brw_set_sampler_message(p, send,
1153 surf_index,
1154 0, /* LD message ignores sampler unit */
1155 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1156 1, /* rlen */
1157 inst->mlen,
1158 header_present,
1159 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1160 0);
1161
1162 brw_mark_surface_used(prog_data, surf_index);
1163
1164 } else {
1165
1166 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1167
1168 brw_push_insn_state(p);
1169 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1170 brw_set_default_access_mode(p, BRW_ALIGN_1);
1171
1172 /* a0.0 = surf_index & 0xff */
1173 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1174 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1175 brw_set_dest(p, insn_and, addr);
1176 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1177 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1178
1179 /* dst = send(payload, a0.0 | <descriptor>) */
1180 brw_inst *insn = brw_send_indirect_message(
1181 p, BRW_SFID_SAMPLER, dst, src, addr);
1182 brw_set_sampler_message(p, insn,
1183 0,
1184 0, /* LD message ignores sampler unit */
1185 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1186 1, /* rlen */
1187 inst->mlen,
1188 header_present,
1189 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1190 0);
1191
1192 brw_pop_insn_state(p);
1193
1194 /* visitor knows more than we do about the surface limit required,
1195 * so has already done marking.
1196 */
1197
1198 }
1199 }
1200
1201 void
1202 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1203 struct brw_reg dst,
1204 struct brw_reg index,
1205 struct brw_reg offset)
1206 {
1207 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1208 assert(inst->header_size != 0);
1209 assert(inst->mlen);
1210
1211 assert(index.file == BRW_IMMEDIATE_VALUE &&
1212 index.type == BRW_REGISTER_TYPE_UD);
1213 uint32_t surf_index = index.dw1.ud;
1214
1215 uint32_t simd_mode, rlen, msg_type;
1216 if (dispatch_width == 16) {
1217 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1218 rlen = 8;
1219 } else {
1220 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1221 rlen = 4;
1222 }
1223
1224 if (devinfo->gen >= 5)
1225 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1226 else {
1227 /* We always use the SIMD16 message so that we only have to load U, and
1228 * not V or R.
1229 */
1230 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1231 assert(inst->mlen == 3);
1232 assert(inst->regs_written == 8);
1233 rlen = 8;
1234 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1235 }
1236
1237 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1238 BRW_REGISTER_TYPE_D);
1239 brw_MOV(p, offset_mrf, offset);
1240
1241 struct brw_reg header = brw_vec8_grf(0, 0);
1242 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1243
1244 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1245 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1246 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1247 brw_set_src0(p, send, header);
1248 if (devinfo->gen < 6)
1249 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1250
1251 /* Our surface is set up as floats, regardless of what actual data is
1252 * stored in it.
1253 */
1254 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1255 brw_set_sampler_message(p, send,
1256 surf_index,
1257 0, /* sampler (unused) */
1258 msg_type,
1259 rlen,
1260 inst->mlen,
1261 inst->header_size != 0,
1262 simd_mode,
1263 return_format);
1264
1265 brw_mark_surface_used(prog_data, surf_index);
1266 }
1267
1268 void
1269 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1270 struct brw_reg dst,
1271 struct brw_reg index,
1272 struct brw_reg offset)
1273 {
1274 assert(devinfo->gen >= 7);
1275 /* Varying-offset pull constant loads are treated as a normal expression on
1276 * gen7, so the fact that it's a send message is hidden at the IR level.
1277 */
1278 assert(inst->header_size == 0);
1279 assert(!inst->mlen);
1280 assert(index.type == BRW_REGISTER_TYPE_UD);
1281
1282 uint32_t simd_mode, rlen, mlen;
1283 if (dispatch_width == 16) {
1284 mlen = 2;
1285 rlen = 8;
1286 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1287 } else {
1288 mlen = 1;
1289 rlen = 4;
1290 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1291 }
1292
1293 if (index.file == BRW_IMMEDIATE_VALUE) {
1294
1295 uint32_t surf_index = index.dw1.ud;
1296
1297 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1298 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1299 brw_set_src0(p, send, offset);
1300 brw_set_sampler_message(p, send,
1301 surf_index,
1302 0, /* LD message ignores sampler unit */
1303 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1304 rlen,
1305 mlen,
1306 false, /* no header */
1307 simd_mode,
1308 0);
1309
1310 brw_mark_surface_used(prog_data, surf_index);
1311
1312 } else {
1313
1314 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1315
1316 brw_push_insn_state(p);
1317 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1318 brw_set_default_access_mode(p, BRW_ALIGN_1);
1319
1320 /* a0.0 = surf_index & 0xff */
1321 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1322 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1323 brw_set_dest(p, insn_and, addr);
1324 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1325 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1326
1327 brw_pop_insn_state(p);
1328
1329 /* dst = send(offset, a0.0 | <descriptor>) */
1330 brw_inst *insn = brw_send_indirect_message(
1331 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1332 offset, addr);
1333 brw_set_sampler_message(p, insn,
1334 0 /* surface */,
1335 0 /* sampler */,
1336 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1337 rlen /* rlen */,
1338 mlen /* mlen */,
1339 false /* header */,
1340 simd_mode,
1341 0);
1342
1343 /* visitor knows more than we do about the surface limit required,
1344 * so has already done marking.
1345 */
1346 }
1347 }
1348
1349 /**
1350 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1351 * into the flags register (f0.0).
1352 *
1353 * Used only on Gen6 and above.
1354 */
1355 void
1356 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1357 {
1358 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1359 struct brw_reg dispatch_mask;
1360
1361 if (devinfo->gen >= 6)
1362 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1363 else
1364 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1365
1366 brw_push_insn_state(p);
1367 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1368 brw_MOV(p, flags, dispatch_mask);
1369 brw_pop_insn_state(p);
1370 }
1371
1372 void
1373 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1374 struct brw_reg dst,
1375 struct brw_reg src,
1376 struct brw_reg msg_data,
1377 unsigned msg_type)
1378 {
1379 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1380
1381 brw_pixel_interpolator_query(p,
1382 retype(dst, BRW_REGISTER_TYPE_UW),
1383 src,
1384 inst->pi_noperspective,
1385 msg_type,
1386 msg_data,
1387 inst->mlen,
1388 inst->regs_written);
1389 }
1390
1391
1392 /**
1393 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1394 * sampler LD messages.
1395 *
1396 * We don't want to bake it into the send message's code generation because
1397 * that means we don't get a chance to schedule the instructions.
1398 */
1399 void
1400 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1401 struct brw_reg dst,
1402 struct brw_reg value)
1403 {
1404 assert(value.file == BRW_IMMEDIATE_VALUE);
1405
1406 brw_push_insn_state(p);
1407 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1408 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1409 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1410 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1411 brw_pop_insn_state(p);
1412 }
1413
1414 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1415 * the ADD instruction.
1416 */
1417 void
1418 fs_generator::generate_set_sample_id(fs_inst *inst,
1419 struct brw_reg dst,
1420 struct brw_reg src0,
1421 struct brw_reg src1)
1422 {
1423 assert(dst.type == BRW_REGISTER_TYPE_D ||
1424 dst.type == BRW_REGISTER_TYPE_UD);
1425 assert(src0.type == BRW_REGISTER_TYPE_D ||
1426 src0.type == BRW_REGISTER_TYPE_UD);
1427
1428 brw_push_insn_state(p);
1429 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1430 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1431 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1432 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1433 if (dispatch_width == 8) {
1434 brw_ADD(p, dst, src0, reg);
1435 } else if (dispatch_width == 16) {
1436 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1437 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1438 }
1439 brw_pop_insn_state(p);
1440 }
1441
1442 void
1443 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1444 struct brw_reg dst,
1445 struct brw_reg x,
1446 struct brw_reg y)
1447 {
1448 assert(devinfo->gen >= 7);
1449 assert(dst.type == BRW_REGISTER_TYPE_UD);
1450 assert(x.type == BRW_REGISTER_TYPE_F);
1451 assert(y.type == BRW_REGISTER_TYPE_F);
1452
1453 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1454 *
1455 * Because this instruction does not have a 16-bit floating-point type,
1456 * the destination data type must be Word (W).
1457 *
1458 * The destination must be DWord-aligned and specify a horizontal stride
1459 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1460 * each destination channel and the upper word is not modified.
1461 */
1462 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1463
1464 /* Give each 32-bit channel of dst the form below, where "." means
1465 * unchanged.
1466 * 0x....hhhh
1467 */
1468 brw_F32TO16(p, dst_w, y);
1469
1470 /* Now the form:
1471 * 0xhhhh0000
1472 */
1473 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1474
1475 /* And, finally the form of packHalf2x16's output:
1476 * 0xhhhhllll
1477 */
1478 brw_F32TO16(p, dst_w, x);
1479 }
1480
1481 void
1482 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1483 struct brw_reg dst,
1484 struct brw_reg src)
1485 {
1486 assert(devinfo->gen >= 7);
1487 assert(dst.type == BRW_REGISTER_TYPE_F);
1488 assert(src.type == BRW_REGISTER_TYPE_UD);
1489
1490 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1491 *
1492 * Because this instruction does not have a 16-bit floating-point type,
1493 * the source data type must be Word (W). The destination type must be
1494 * F (Float).
1495 */
1496 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1497
1498 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1499 * For the Y case, we wish to access only the upper word; therefore
1500 * a 16-bit subregister offset is needed.
1501 */
1502 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1503 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1504 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1505 src_w.subnr += 2;
1506
1507 brw_F16TO32(p, dst, src_w);
1508 }
1509
1510 void
1511 fs_generator::generate_shader_time_add(fs_inst *inst,
1512 struct brw_reg payload,
1513 struct brw_reg offset,
1514 struct brw_reg value)
1515 {
1516 assert(devinfo->gen >= 7);
1517 brw_push_insn_state(p);
1518 brw_set_default_mask_control(p, true);
1519
1520 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1521 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1522 offset.type);
1523 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1524 value.type);
1525
1526 assert(offset.file == BRW_IMMEDIATE_VALUE);
1527 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1528 value.width = BRW_WIDTH_1;
1529 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1530 value.vstride = BRW_VERTICAL_STRIDE_0;
1531 } else {
1532 assert(value.file == BRW_IMMEDIATE_VALUE);
1533 }
1534
1535 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1536 * case, and we don't really care about squeezing every bit of performance
1537 * out of this path, so we just emit the MOVs from here.
1538 */
1539 brw_MOV(p, payload_offset, offset);
1540 brw_MOV(p, payload_value, value);
1541 brw_shader_time_add(p, payload,
1542 prog_data->binding_table.shader_time_start);
1543 brw_pop_insn_state(p);
1544
1545 brw_mark_surface_used(prog_data,
1546 prog_data->binding_table.shader_time_start);
1547 }
1548
1549 void
1550 fs_generator::enable_debug(const char *shader_name)
1551 {
1552 debug_flag = true;
1553 this->shader_name = shader_name;
1554 }
1555
1556 int
1557 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1558 {
1559 /* align to 64 byte boundary. */
1560 while (p->next_insn_offset % 64)
1561 brw_NOP(p);
1562
1563 this->dispatch_width = dispatch_width;
1564 if (dispatch_width == 16)
1565 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1566
1567 int start_offset = p->next_insn_offset;
1568 int spill_count = 0, fill_count = 0;
1569 int loop_count = 0;
1570
1571 struct annotation_info annotation;
1572 memset(&annotation, 0, sizeof(annotation));
1573
1574 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1575 struct brw_reg src[3], dst;
1576 unsigned int last_insn_offset = p->next_insn_offset;
1577 bool multiple_instructions_emitted = false;
1578
1579 if (unlikely(debug_flag))
1580 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1581
1582 for (unsigned int i = 0; i < inst->sources; i++) {
1583 src[i] = brw_reg_from_fs_reg(inst, &inst->src[i], devinfo->gen);
1584
1585 /* The accumulator result appears to get used for the
1586 * conditional modifier generation. When negating a UD
1587 * value, there is a 33rd bit generated for the sign in the
1588 * accumulator value, so now you can't check, for example,
1589 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1590 */
1591 assert(!inst->conditional_mod ||
1592 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1593 !inst->src[i].negate);
1594 }
1595 dst = brw_reg_from_fs_reg(inst, &inst->dst, devinfo->gen);
1596
1597 brw_set_default_predicate_control(p, inst->predicate);
1598 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1599 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1600 brw_set_default_saturate(p, inst->saturate);
1601 brw_set_default_mask_control(p, inst->force_writemask_all);
1602 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1603 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1604
1605 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1606 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1607
1608 switch (inst->exec_size) {
1609 case 1:
1610 case 2:
1611 case 4:
1612 assert(inst->force_writemask_all);
1613 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1614 break;
1615 case 8:
1616 if (inst->force_sechalf) {
1617 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1618 } else {
1619 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1620 }
1621 break;
1622 case 16:
1623 case 32:
1624 /* If the instruction writes to more than one register, it needs to
1625 * be a "compressed" instruction on Gen <= 5.
1626 */
1627 if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
1628 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1629 else
1630 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1631 break;
1632 default:
1633 unreachable("Invalid instruction width");
1634 }
1635
1636 switch (inst->opcode) {
1637 case BRW_OPCODE_MOV:
1638 brw_MOV(p, dst, src[0]);
1639 break;
1640 case BRW_OPCODE_ADD:
1641 brw_ADD(p, dst, src[0], src[1]);
1642 break;
1643 case BRW_OPCODE_MUL:
1644 brw_MUL(p, dst, src[0], src[1]);
1645 break;
1646 case BRW_OPCODE_AVG:
1647 brw_AVG(p, dst, src[0], src[1]);
1648 break;
1649 case BRW_OPCODE_MACH:
1650 brw_MACH(p, dst, src[0], src[1]);
1651 break;
1652
1653 case BRW_OPCODE_LINE:
1654 brw_LINE(p, dst, src[0], src[1]);
1655 break;
1656
1657 case BRW_OPCODE_MAD:
1658 assert(devinfo->gen >= 6);
1659 brw_set_default_access_mode(p, BRW_ALIGN_16);
1660 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1661 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1662 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1663 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1664 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1665 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1666 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1667
1668 if (inst->conditional_mod) {
1669 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1670 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1671 multiple_instructions_emitted = true;
1672 }
1673 } else {
1674 brw_MAD(p, dst, src[0], src[1], src[2]);
1675 }
1676 brw_set_default_access_mode(p, BRW_ALIGN_1);
1677 break;
1678
1679 case BRW_OPCODE_LRP:
1680 assert(devinfo->gen >= 6);
1681 brw_set_default_access_mode(p, BRW_ALIGN_16);
1682 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1683 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1684 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1685 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1686 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1687 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1688 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1689
1690 if (inst->conditional_mod) {
1691 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1692 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1693 multiple_instructions_emitted = true;
1694 }
1695 } else {
1696 brw_LRP(p, dst, src[0], src[1], src[2]);
1697 }
1698 brw_set_default_access_mode(p, BRW_ALIGN_1);
1699 break;
1700
1701 case BRW_OPCODE_FRC:
1702 brw_FRC(p, dst, src[0]);
1703 break;
1704 case BRW_OPCODE_RNDD:
1705 brw_RNDD(p, dst, src[0]);
1706 break;
1707 case BRW_OPCODE_RNDE:
1708 brw_RNDE(p, dst, src[0]);
1709 break;
1710 case BRW_OPCODE_RNDZ:
1711 brw_RNDZ(p, dst, src[0]);
1712 break;
1713
1714 case BRW_OPCODE_AND:
1715 brw_AND(p, dst, src[0], src[1]);
1716 break;
1717 case BRW_OPCODE_OR:
1718 brw_OR(p, dst, src[0], src[1]);
1719 break;
1720 case BRW_OPCODE_XOR:
1721 brw_XOR(p, dst, src[0], src[1]);
1722 break;
1723 case BRW_OPCODE_NOT:
1724 brw_NOT(p, dst, src[0]);
1725 break;
1726 case BRW_OPCODE_ASR:
1727 brw_ASR(p, dst, src[0], src[1]);
1728 break;
1729 case BRW_OPCODE_SHR:
1730 brw_SHR(p, dst, src[0], src[1]);
1731 break;
1732 case BRW_OPCODE_SHL:
1733 brw_SHL(p, dst, src[0], src[1]);
1734 break;
1735 case BRW_OPCODE_F32TO16:
1736 assert(devinfo->gen >= 7);
1737 brw_F32TO16(p, dst, src[0]);
1738 break;
1739 case BRW_OPCODE_F16TO32:
1740 assert(devinfo->gen >= 7);
1741 brw_F16TO32(p, dst, src[0]);
1742 break;
1743 case BRW_OPCODE_CMP:
1744 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1745 * that when the destination is a GRF that the dependency-clear bit on
1746 * the flag register is cleared early.
1747 *
1748 * Suggested workarounds are to disable coissuing CMP instructions
1749 * or to split CMP(16) instructions into two CMP(8) instructions.
1750 *
1751 * We choose to split into CMP(8) instructions since disabling
1752 * coissuing would affect CMP instructions not otherwise affected by
1753 * the errata.
1754 */
1755 if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) {
1756 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1757 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1758 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1759 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1760 firsthalf(src[0]), firsthalf(src[1]));
1761 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1762 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1763 sechalf(src[0]), sechalf(src[1]));
1764 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1765
1766 multiple_instructions_emitted = true;
1767 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1768 /* For unknown reasons, the aforementioned workaround is not
1769 * sufficient. Overriding the type when the destination is the
1770 * null register is necessary but not sufficient by itself.
1771 */
1772 assert(dst.nr == BRW_ARF_NULL);
1773 dst.type = BRW_REGISTER_TYPE_D;
1774 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1775 } else {
1776 unreachable("not reached");
1777 }
1778 } else {
1779 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1780 }
1781 break;
1782 case BRW_OPCODE_SEL:
1783 brw_SEL(p, dst, src[0], src[1]);
1784 break;
1785 case BRW_OPCODE_BFREV:
1786 assert(devinfo->gen >= 7);
1787 /* BFREV only supports UD type for src and dst. */
1788 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1789 retype(src[0], BRW_REGISTER_TYPE_UD));
1790 break;
1791 case BRW_OPCODE_FBH:
1792 assert(devinfo->gen >= 7);
1793 /* FBH only supports UD type for dst. */
1794 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1795 break;
1796 case BRW_OPCODE_FBL:
1797 assert(devinfo->gen >= 7);
1798 /* FBL only supports UD type for dst. */
1799 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1800 break;
1801 case BRW_OPCODE_CBIT:
1802 assert(devinfo->gen >= 7);
1803 /* CBIT only supports UD type for dst. */
1804 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1805 break;
1806 case BRW_OPCODE_ADDC:
1807 assert(devinfo->gen >= 7);
1808 brw_ADDC(p, dst, src[0], src[1]);
1809 break;
1810 case BRW_OPCODE_SUBB:
1811 assert(devinfo->gen >= 7);
1812 brw_SUBB(p, dst, src[0], src[1]);
1813 break;
1814 case BRW_OPCODE_MAC:
1815 brw_MAC(p, dst, src[0], src[1]);
1816 break;
1817
1818 case BRW_OPCODE_BFE:
1819 assert(devinfo->gen >= 7);
1820 brw_set_default_access_mode(p, BRW_ALIGN_16);
1821 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1822 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1823 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1824 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1825 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1826 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1827 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1828 } else {
1829 brw_BFE(p, dst, src[0], src[1], src[2]);
1830 }
1831 brw_set_default_access_mode(p, BRW_ALIGN_1);
1832 break;
1833
1834 case BRW_OPCODE_BFI1:
1835 assert(devinfo->gen >= 7);
1836 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1837 * should
1838 *
1839 * "Force BFI instructions to be executed always in SIMD8."
1840 */
1841 if (dispatch_width == 16 && devinfo->is_haswell) {
1842 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1843 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1844 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1845 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1846 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1847 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1848 } else {
1849 brw_BFI1(p, dst, src[0], src[1]);
1850 }
1851 break;
1852 case BRW_OPCODE_BFI2:
1853 assert(devinfo->gen >= 7);
1854 brw_set_default_access_mode(p, BRW_ALIGN_16);
1855 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1856 * should
1857 *
1858 * "Force BFI instructions to be executed always in SIMD8."
1859 *
1860 * Otherwise we would be able to emit compressed instructions like we
1861 * do for the other three-source instructions.
1862 */
1863 if (dispatch_width == 16 &&
1864 (devinfo->is_haswell || !devinfo->supports_simd16_3src)) {
1865 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1866 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1867 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1868 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1869 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1870 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1871 } else {
1872 brw_BFI2(p, dst, src[0], src[1], src[2]);
1873 }
1874 brw_set_default_access_mode(p, BRW_ALIGN_1);
1875 break;
1876
1877 case BRW_OPCODE_IF:
1878 if (inst->src[0].file != BAD_FILE) {
1879 /* The instruction has an embedded compare (only allowed on gen6) */
1880 assert(devinfo->gen == 6);
1881 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1882 } else {
1883 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1884 }
1885 break;
1886
1887 case BRW_OPCODE_ELSE:
1888 brw_ELSE(p);
1889 break;
1890 case BRW_OPCODE_ENDIF:
1891 brw_ENDIF(p);
1892 break;
1893
1894 case BRW_OPCODE_DO:
1895 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1896 break;
1897
1898 case BRW_OPCODE_BREAK:
1899 brw_BREAK(p);
1900 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1901 break;
1902 case BRW_OPCODE_CONTINUE:
1903 brw_CONT(p);
1904 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1905 break;
1906
1907 case BRW_OPCODE_WHILE:
1908 brw_WHILE(p);
1909 loop_count++;
1910 break;
1911
1912 case SHADER_OPCODE_RCP:
1913 case SHADER_OPCODE_RSQ:
1914 case SHADER_OPCODE_SQRT:
1915 case SHADER_OPCODE_EXP2:
1916 case SHADER_OPCODE_LOG2:
1917 case SHADER_OPCODE_SIN:
1918 case SHADER_OPCODE_COS:
1919 assert(devinfo->gen < 6 || inst->mlen == 0);
1920 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1921 if (devinfo->gen >= 7) {
1922 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1923 brw_null_reg());
1924 } else if (devinfo->gen == 6) {
1925 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1926 } else if (devinfo->gen == 5 || devinfo->is_g4x) {
1927 generate_math_g45(inst, dst, src[0]);
1928 } else {
1929 generate_math_gen4(inst, dst, src[0]);
1930 }
1931 break;
1932 case SHADER_OPCODE_INT_QUOTIENT:
1933 case SHADER_OPCODE_INT_REMAINDER:
1934 case SHADER_OPCODE_POW:
1935 assert(devinfo->gen < 6 || inst->mlen == 0);
1936 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1937 if (devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1938 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1939 } else if (devinfo->gen >= 6) {
1940 generate_math_gen6(inst, dst, src[0], src[1]);
1941 } else {
1942 generate_math_gen4(inst, dst, src[0]);
1943 }
1944 break;
1945 case FS_OPCODE_CINTERP:
1946 brw_MOV(p, dst, src[0]);
1947 break;
1948 case FS_OPCODE_LINTERP:
1949 generate_linterp(inst, dst, src);
1950 break;
1951 case FS_OPCODE_PIXEL_X:
1952 assert(src[0].type == BRW_REGISTER_TYPE_UW);
1953 src[0].subnr = 0 * type_sz(src[0].type);
1954 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1955 break;
1956 case FS_OPCODE_PIXEL_Y:
1957 assert(src[0].type == BRW_REGISTER_TYPE_UW);
1958 src[0].subnr = 4 * type_sz(src[0].type);
1959 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1960 break;
1961 case FS_OPCODE_GET_BUFFER_SIZE:
1962 generate_get_buffer_size(inst, dst, src[0], src[1]);
1963 break;
1964 case SHADER_OPCODE_TEX:
1965 case FS_OPCODE_TXB:
1966 case SHADER_OPCODE_TXD:
1967 case SHADER_OPCODE_TXF:
1968 case SHADER_OPCODE_TXF_CMS:
1969 case SHADER_OPCODE_TXF_UMS:
1970 case SHADER_OPCODE_TXF_MCS:
1971 case SHADER_OPCODE_TXL:
1972 case SHADER_OPCODE_TXS:
1973 case SHADER_OPCODE_LOD:
1974 case SHADER_OPCODE_TG4:
1975 case SHADER_OPCODE_TG4_OFFSET:
1976 case SHADER_OPCODE_SAMPLEINFO:
1977 generate_tex(inst, dst, src[0], src[1]);
1978 break;
1979 case FS_OPCODE_DDX_COARSE:
1980 case FS_OPCODE_DDX_FINE:
1981 generate_ddx(inst->opcode, dst, src[0]);
1982 break;
1983 case FS_OPCODE_DDY_COARSE:
1984 case FS_OPCODE_DDY_FINE:
1985 assert(src[1].file == BRW_IMMEDIATE_VALUE);
1986 generate_ddy(inst->opcode, dst, src[0], src[1].dw1.ud);
1987 break;
1988
1989 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1990 generate_scratch_write(inst, src[0]);
1991 spill_count++;
1992 break;
1993
1994 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1995 generate_scratch_read(inst, dst);
1996 fill_count++;
1997 break;
1998
1999 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2000 generate_scratch_read_gen7(inst, dst);
2001 fill_count++;
2002 break;
2003
2004 case SHADER_OPCODE_URB_WRITE_SIMD8:
2005 generate_urb_write(inst, src[0]);
2006 break;
2007
2008 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2009 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2010 break;
2011
2012 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2013 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2014 break;
2015
2016 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
2017 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
2018 break;
2019
2020 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2021 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2022 break;
2023
2024 case FS_OPCODE_REP_FB_WRITE:
2025 case FS_OPCODE_FB_WRITE:
2026 generate_fb_write(inst, src[0]);
2027 break;
2028
2029 case FS_OPCODE_BLORP_FB_WRITE:
2030 generate_blorp_fb_write(inst);
2031 break;
2032
2033 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2034 generate_mov_dispatch_to_flags(inst);
2035 break;
2036
2037 case FS_OPCODE_DISCARD_JUMP:
2038 generate_discard_jump(inst);
2039 break;
2040
2041 case SHADER_OPCODE_SHADER_TIME_ADD:
2042 generate_shader_time_add(inst, src[0], src[1], src[2]);
2043 break;
2044
2045 case SHADER_OPCODE_UNTYPED_ATOMIC:
2046 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2047 brw_untyped_atomic(p, dst, src[0], src[1], src[2].dw1.ud,
2048 inst->mlen, !inst->dst.is_null());
2049 break;
2050
2051 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2052 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2053 brw_untyped_surface_read(p, dst, src[0], src[1],
2054 inst->mlen, src[2].dw1.ud);
2055 break;
2056
2057 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2058 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2059 brw_untyped_surface_write(p, src[0], src[1],
2060 inst->mlen, src[2].dw1.ud);
2061 break;
2062
2063 case SHADER_OPCODE_TYPED_ATOMIC:
2064 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2065 brw_typed_atomic(p, dst, src[0], src[1],
2066 src[2].dw1.ud, inst->mlen, !inst->dst.is_null());
2067 break;
2068
2069 case SHADER_OPCODE_TYPED_SURFACE_READ:
2070 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2071 brw_typed_surface_read(p, dst, src[0], src[1],
2072 inst->mlen, src[2].dw1.ud);
2073 break;
2074
2075 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2076 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2077 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].dw1.ud);
2078 break;
2079
2080 case SHADER_OPCODE_MEMORY_FENCE:
2081 brw_memory_fence(p, dst);
2082 break;
2083
2084 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2085 generate_set_simd4x2_offset(inst, dst, src[0]);
2086 break;
2087
2088 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
2089 brw_find_live_channel(p, dst);
2090 break;
2091
2092 case SHADER_OPCODE_BROADCAST:
2093 brw_broadcast(p, dst, src[0], src[1]);
2094 break;
2095
2096 case FS_OPCODE_SET_SAMPLE_ID:
2097 generate_set_sample_id(inst, dst, src[0], src[1]);
2098 break;
2099
2100 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2101 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2102 break;
2103
2104 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2105 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2106 generate_unpack_half_2x16_split(inst, dst, src[0]);
2107 break;
2108
2109 case FS_OPCODE_PLACEHOLDER_HALT:
2110 /* This is the place where the final HALT needs to be inserted if
2111 * we've emitted any discards. If not, this will emit no code.
2112 */
2113 if (!patch_discard_jumps_to_fb_writes()) {
2114 if (unlikely(debug_flag)) {
2115 annotation.ann_count--;
2116 }
2117 }
2118 break;
2119
2120 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2121 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2122 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2123 break;
2124
2125 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2126 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2127 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2128 break;
2129
2130 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2131 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2132 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2133 break;
2134
2135 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2136 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2137 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2138 break;
2139
2140 case CS_OPCODE_CS_TERMINATE:
2141 generate_cs_terminate(inst, src[0]);
2142 break;
2143
2144 case SHADER_OPCODE_BARRIER:
2145 generate_barrier(inst, src[0]);
2146 break;
2147
2148 default:
2149 unreachable("Unsupported opcode");
2150
2151 case SHADER_OPCODE_LOAD_PAYLOAD:
2152 unreachable("Should be lowered by lower_load_payload()");
2153 }
2154
2155 if (multiple_instructions_emitted)
2156 continue;
2157
2158 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2159 assert(p->next_insn_offset == last_insn_offset + 16 ||
2160 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2161 "emitting more than 1 instruction");
2162
2163 brw_inst *last = &p->store[last_insn_offset / 16];
2164
2165 if (inst->conditional_mod)
2166 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2167 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2168 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2169 }
2170 }
2171
2172 brw_set_uip_jip(p);
2173 annotation_finalize(&annotation, p->next_insn_offset);
2174
2175 int before_size = p->next_insn_offset - start_offset;
2176 brw_compact_instructions(p, start_offset, annotation.ann_count,
2177 annotation.ann);
2178 int after_size = p->next_insn_offset - start_offset;
2179
2180 if (unlikely(debug_flag)) {
2181 fprintf(stderr, "Native code for %s\n"
2182 "SIMD%d shader: %d instructions. %d loops. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2183 " bytes (%.0f%%)\n",
2184 shader_name, dispatch_width, before_size / 16, loop_count,
2185 spill_count, fill_count, promoted_constants, before_size, after_size,
2186 100.0f * (before_size - after_size) / before_size);
2187
2188 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2189 p->devinfo);
2190 ralloc_free(annotation.ann);
2191 }
2192
2193 compiler->shader_debug_log(log_data,
2194 "%s SIMD%d shader: %d inst, %d loops, "
2195 "%d:%d spills:fills, Promoted %u constants, "
2196 "compacted %d to %d bytes.\n",
2197 stage_abbrev, dispatch_width, before_size / 16,
2198 loop_count, spill_count, fill_count,
2199 promoted_constants, before_size, after_size);
2200
2201 return start_offset;
2202 }
2203
2204 const unsigned *
2205 fs_generator::get_assembly(unsigned int *assembly_size)
2206 {
2207 return brw_get_program(p, assembly_size);
2208 }