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i965: Remove the context field from brw_compiler
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "main/macros.h"
31 #include "brw_context.h"
32 #include "brw_eu.h"
33 #include "brw_fs.h"
34 #include "brw_cfg.h"
35
36 static uint32_t brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case GRF:
40 return BRW_GENERAL_REGISTER_FILE;
41 case MRF:
42 return BRW_MESSAGE_REGISTER_FILE;
43 case IMM:
44 return BRW_IMMEDIATE_VALUE;
45 default:
46 unreachable("not reached");
47 }
48 }
49
50 static struct brw_reg
51 brw_reg_from_fs_reg(fs_reg *reg)
52 {
53 struct brw_reg brw_reg;
54
55 switch (reg->file) {
56 case GRF:
57 case MRF:
58 if (reg->stride == 0) {
59 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
60 } else if (reg->width < 8) {
61 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
62 brw_reg = stride(brw_reg, reg->width * reg->stride,
63 reg->width, reg->stride);
64 } else {
65 /* From the Haswell PRM:
66 *
67 * VertStride must be used to cross GRF register boundaries. This
68 * rule implies that elements within a 'Width' cannot cross GRF
69 * boundaries.
70 *
71 * So, for registers with width > 8, we have to use a width of 8
72 * and trust the compression state to sort out the exec size.
73 */
74 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
75 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
76 }
77
78 brw_reg = retype(brw_reg, reg->type);
79 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
80 break;
81 case IMM:
82 switch (reg->type) {
83 case BRW_REGISTER_TYPE_F:
84 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
85 break;
86 case BRW_REGISTER_TYPE_D:
87 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
88 break;
89 case BRW_REGISTER_TYPE_UD:
90 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
91 break;
92 case BRW_REGISTER_TYPE_W:
93 brw_reg = brw_imm_w(reg->fixed_hw_reg.dw1.d);
94 break;
95 case BRW_REGISTER_TYPE_UW:
96 brw_reg = brw_imm_uw(reg->fixed_hw_reg.dw1.ud);
97 break;
98 case BRW_REGISTER_TYPE_VF:
99 brw_reg = brw_imm_vf(reg->fixed_hw_reg.dw1.ud);
100 break;
101 default:
102 unreachable("not reached");
103 }
104 break;
105 case HW_REG:
106 assert(reg->type == reg->fixed_hw_reg.type);
107 brw_reg = reg->fixed_hw_reg;
108 break;
109 case BAD_FILE:
110 /* Probably unused. */
111 brw_reg = brw_null_reg();
112 break;
113 default:
114 unreachable("not reached");
115 }
116 if (reg->abs)
117 brw_reg = brw_abs(brw_reg);
118 if (reg->negate)
119 brw_reg = negate(brw_reg);
120
121 return brw_reg;
122 }
123
124 fs_generator::fs_generator(struct brw_context *brw,
125 void *mem_ctx,
126 const void *key,
127 struct brw_stage_prog_data *prog_data,
128 struct gl_program *prog,
129 unsigned promoted_constants,
130 bool runtime_check_aads_emit,
131 const char *stage_abbrev)
132
133 : brw(brw), key(key),
134 prog_data(prog_data),
135 prog(prog), promoted_constants(promoted_constants),
136 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
137 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
138 {
139 ctx = &brw->ctx;
140
141 p = rzalloc(mem_ctx, struct brw_compile);
142 brw_init_compile(brw->intelScreen->devinfo, p, mem_ctx);
143 }
144
145 fs_generator::~fs_generator()
146 {
147 }
148
149 class ip_record : public exec_node {
150 public:
151 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
152
153 ip_record(int ip)
154 {
155 this->ip = ip;
156 }
157
158 int ip;
159 };
160
161 bool
162 fs_generator::patch_discard_jumps_to_fb_writes()
163 {
164 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
165 return false;
166
167 int scale = brw_jump_scale(p->devinfo);
168
169 /* There is a somewhat strange undocumented requirement of using
170 * HALT, according to the simulator. If some channel has HALTed to
171 * a particular UIP, then by the end of the program, every channel
172 * must have HALTed to that UIP. Furthermore, the tracking is a
173 * stack, so you can't do the final halt of a UIP after starting
174 * halting to a new UIP.
175 *
176 * Symptoms of not emitting this instruction on actual hardware
177 * included GPU hangs and sparkly rendering on the piglit discard
178 * tests.
179 */
180 brw_inst *last_halt = gen6_HALT(p);
181 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
182 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
183
184 int ip = p->nr_insn;
185
186 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
187 brw_inst *patch = &p->store[patch_ip->ip];
188
189 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
190 /* HALT takes a half-instruction distance from the pre-incremented IP. */
191 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
192 }
193
194 this->discard_halt_patches.make_empty();
195 return true;
196 }
197
198 void
199 fs_generator::fire_fb_write(fs_inst *inst,
200 struct brw_reg payload,
201 struct brw_reg implied_header,
202 GLuint nr)
203 {
204 uint32_t msg_control;
205
206 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
207
208 if (brw->gen < 6) {
209 brw_push_insn_state(p);
210 brw_set_default_exec_size(p, BRW_EXECUTE_8);
211 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
212 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
213 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
214 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
215 brw_pop_insn_state(p);
216 }
217
218 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
219 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
220 else if (prog_data->dual_src_blend) {
221 if (dispatch_width == 8 || !inst->eot)
222 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
223 else
224 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
225 } else if (dispatch_width == 16)
226 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
227 else
228 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
229
230 uint32_t surf_index =
231 prog_data->binding_table.render_target_start + inst->target;
232
233 bool last_render_target = inst->eot ||
234 (prog_data->dual_src_blend && dispatch_width == 16);
235
236
237 brw_fb_WRITE(p,
238 dispatch_width,
239 payload,
240 implied_header,
241 msg_control,
242 surf_index,
243 nr,
244 0,
245 inst->eot,
246 last_render_target,
247 inst->header_present);
248
249 brw_mark_surface_used(&prog_data->base, surf_index);
250 }
251
252 void
253 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
254 {
255 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
256 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
257 struct brw_reg implied_header;
258
259 if (brw->gen < 8 && !brw->is_haswell) {
260 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
261 }
262
263 if (inst->base_mrf >= 0)
264 payload = brw_message_reg(inst->base_mrf);
265
266 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
267 * move, here's g1.
268 */
269 if (inst->header_present) {
270 brw_push_insn_state(p);
271 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
272 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
273 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
274 brw_set_default_flag_reg(p, 0, 0);
275
276 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
277 * present.
278 */
279 if (prog_data->uses_kill) {
280 struct brw_reg pixel_mask;
281
282 if (brw->gen >= 6)
283 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
284 else
285 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
286
287 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
288 }
289
290 if (brw->gen >= 6) {
291 brw_push_insn_state(p);
292 brw_set_default_exec_size(p, BRW_EXECUTE_16);
293 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
294 brw_MOV(p,
295 retype(payload, BRW_REGISTER_TYPE_UD),
296 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
297 brw_pop_insn_state(p);
298
299 if (inst->target > 0 && key->replicate_alpha) {
300 /* Set "Source0 Alpha Present to RenderTarget" bit in message
301 * header.
302 */
303 brw_OR(p,
304 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
305 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
306 brw_imm_ud(0x1 << 11));
307 }
308
309 if (inst->target > 0) {
310 /* Set the render target index for choosing BLEND_STATE. */
311 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
312 BRW_REGISTER_TYPE_UD),
313 brw_imm_ud(inst->target));
314 }
315
316 implied_header = brw_null_reg();
317 } else {
318 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
319 }
320
321 brw_pop_insn_state(p);
322 } else {
323 implied_header = brw_null_reg();
324 }
325
326 if (!runtime_check_aads_emit) {
327 fire_fb_write(inst, payload, implied_header, inst->mlen);
328 } else {
329 /* This can only happen in gen < 6 */
330 assert(brw->gen < 6);
331
332 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
333
334 /* Check runtime bit to detect if we have to send AA data or not */
335 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
336 brw_AND(p,
337 v1_null_ud,
338 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
339 brw_imm_ud(1<<26));
340 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
341
342 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
343 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
344 {
345 /* Don't send AA data */
346 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
347 }
348 brw_land_fwd_jump(p, jmp);
349 fire_fb_write(inst, payload, implied_header, inst->mlen);
350 }
351 }
352
353 void
354 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
355 {
356 brw_inst *insn;
357
358 insn = brw_next_insn(p, BRW_OPCODE_SEND);
359
360 brw_set_dest(p, insn, brw_null_reg());
361 brw_set_src0(p, insn, payload);
362 brw_set_src1(p, insn, brw_imm_d(0));
363
364 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
365 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
366
367 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
368 brw_inst_set_rlen(p->devinfo, insn, 0);
369 brw_inst_set_eot(p->devinfo, insn, inst->eot);
370 brw_inst_set_header_present(p->devinfo, insn, true);
371 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
372 }
373
374 void
375 fs_generator::generate_blorp_fb_write(fs_inst *inst)
376 {
377 brw_fb_WRITE(p,
378 16 /* dispatch_width */,
379 brw_message_reg(inst->base_mrf),
380 brw_reg_from_fs_reg(&inst->src[0]),
381 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
382 inst->target,
383 inst->mlen,
384 0,
385 true,
386 true,
387 inst->header_present);
388 }
389
390 void
391 fs_generator::generate_linterp(fs_inst *inst,
392 struct brw_reg dst, struct brw_reg *src)
393 {
394 /* PLN reads:
395 * / in SIMD16 \
396 * -----------------------------------
397 * | src1+0 | src1+1 | src1+2 | src1+3 |
398 * |-----------------------------------|
399 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
400 * -----------------------------------
401 *
402 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
403 *
404 * -----------------------------------
405 * | src1+0 | src1+1 | src1+2 | src1+3 |
406 * |-----------------------------------|
407 * |(x0, x1)|(y0, y1)| | | in SIMD8
408 * |-----------------------------------|
409 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
410 * -----------------------------------
411 *
412 * See also: emit_interpolation_setup_gen4().
413 */
414 struct brw_reg delta_x = src[0];
415 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
416 struct brw_reg interp = src[1];
417
418 if (brw->has_pln &&
419 (brw->gen >= 7 || (delta_x.nr & 1) == 0)) {
420 brw_PLN(p, dst, interp, delta_x);
421 } else {
422 brw_LINE(p, brw_null_reg(), interp, delta_x);
423 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
424 }
425 }
426
427 void
428 fs_generator::generate_math_gen6(fs_inst *inst,
429 struct brw_reg dst,
430 struct brw_reg src0,
431 struct brw_reg src1)
432 {
433 int op = brw_math_function(inst->opcode);
434 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
435
436 if (dispatch_width == 8) {
437 gen6_math(p, dst, op, src0, src1);
438 } else if (dispatch_width == 16) {
439 brw_push_insn_state(p);
440 brw_set_default_exec_size(p, BRW_EXECUTE_8);
441 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
442 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
443 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
444 gen6_math(p, sechalf(dst), op, sechalf(src0),
445 binop ? sechalf(src1) : brw_null_reg());
446 brw_pop_insn_state(p);
447 }
448 }
449
450 void
451 fs_generator::generate_math_gen4(fs_inst *inst,
452 struct brw_reg dst,
453 struct brw_reg src)
454 {
455 int op = brw_math_function(inst->opcode);
456
457 assert(inst->mlen >= 1);
458
459 if (dispatch_width == 8) {
460 gen4_math(p, dst,
461 op,
462 inst->base_mrf, src,
463 BRW_MATH_PRECISION_FULL);
464 } else if (dispatch_width == 16) {
465 brw_set_default_exec_size(p, BRW_EXECUTE_8);
466 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
467 gen4_math(p, firsthalf(dst),
468 op,
469 inst->base_mrf, firsthalf(src),
470 BRW_MATH_PRECISION_FULL);
471 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
472 gen4_math(p, sechalf(dst),
473 op,
474 inst->base_mrf + 1, sechalf(src),
475 BRW_MATH_PRECISION_FULL);
476
477 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
478 }
479 }
480
481 void
482 fs_generator::generate_math_g45(fs_inst *inst,
483 struct brw_reg dst,
484 struct brw_reg src)
485 {
486 if (inst->opcode == SHADER_OPCODE_POW ||
487 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
488 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
489 generate_math_gen4(inst, dst, src);
490 return;
491 }
492
493 int op = brw_math_function(inst->opcode);
494
495 assert(inst->mlen >= 1);
496
497 gen4_math(p, dst,
498 op,
499 inst->base_mrf, src,
500 BRW_MATH_PRECISION_FULL);
501 }
502
503 void
504 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
505 struct brw_reg sampler_index)
506 {
507 int msg_type = -1;
508 int rlen = 4;
509 uint32_t simd_mode;
510 uint32_t return_format;
511 bool is_combined_send = inst->eot;
512
513 switch (dst.type) {
514 case BRW_REGISTER_TYPE_D:
515 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
516 break;
517 case BRW_REGISTER_TYPE_UD:
518 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
519 break;
520 default:
521 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
522 break;
523 }
524
525 switch (inst->exec_size) {
526 case 8:
527 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
528 break;
529 case 16:
530 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
531 break;
532 default:
533 unreachable("Invalid width for texture instruction");
534 }
535
536 if (brw->gen >= 5) {
537 switch (inst->opcode) {
538 case SHADER_OPCODE_TEX:
539 if (inst->shadow_compare) {
540 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
541 } else {
542 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
543 }
544 break;
545 case FS_OPCODE_TXB:
546 if (inst->shadow_compare) {
547 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
548 } else {
549 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
550 }
551 break;
552 case SHADER_OPCODE_TXL:
553 if (inst->shadow_compare) {
554 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
555 } else {
556 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
557 }
558 break;
559 case SHADER_OPCODE_TXS:
560 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
561 break;
562 case SHADER_OPCODE_TXD:
563 if (inst->shadow_compare) {
564 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
565 assert(brw->gen >= 8 || brw->is_haswell);
566 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
567 } else {
568 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
569 }
570 break;
571 case SHADER_OPCODE_TXF:
572 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
573 break;
574 case SHADER_OPCODE_TXF_CMS:
575 if (brw->gen >= 7)
576 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
577 else
578 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
579 break;
580 case SHADER_OPCODE_TXF_UMS:
581 assert(brw->gen >= 7);
582 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
583 break;
584 case SHADER_OPCODE_TXF_MCS:
585 assert(brw->gen >= 7);
586 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
587 break;
588 case SHADER_OPCODE_LOD:
589 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
590 break;
591 case SHADER_OPCODE_TG4:
592 if (inst->shadow_compare) {
593 assert(brw->gen >= 7);
594 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
595 } else {
596 assert(brw->gen >= 6);
597 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
598 }
599 break;
600 case SHADER_OPCODE_TG4_OFFSET:
601 assert(brw->gen >= 7);
602 if (inst->shadow_compare) {
603 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
604 } else {
605 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
606 }
607 break;
608 default:
609 unreachable("not reached");
610 }
611 } else {
612 switch (inst->opcode) {
613 case SHADER_OPCODE_TEX:
614 /* Note that G45 and older determines shadow compare and dispatch width
615 * from message length for most messages.
616 */
617 if (dispatch_width == 8) {
618 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
619 if (inst->shadow_compare) {
620 assert(inst->mlen == 6);
621 } else {
622 assert(inst->mlen <= 4);
623 }
624 } else {
625 if (inst->shadow_compare) {
626 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
627 assert(inst->mlen == 9);
628 } else {
629 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
630 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
631 }
632 }
633 break;
634 case FS_OPCODE_TXB:
635 if (inst->shadow_compare) {
636 assert(dispatch_width == 8);
637 assert(inst->mlen == 6);
638 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
639 } else {
640 assert(inst->mlen == 9);
641 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
642 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
643 }
644 break;
645 case SHADER_OPCODE_TXL:
646 if (inst->shadow_compare) {
647 assert(dispatch_width == 8);
648 assert(inst->mlen == 6);
649 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
650 } else {
651 assert(inst->mlen == 9);
652 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
653 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
654 }
655 break;
656 case SHADER_OPCODE_TXD:
657 /* There is no sample_d_c message; comparisons are done manually */
658 assert(dispatch_width == 8);
659 assert(inst->mlen == 7 || inst->mlen == 10);
660 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
661 break;
662 case SHADER_OPCODE_TXF:
663 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
664 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
665 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
666 break;
667 case SHADER_OPCODE_TXS:
668 assert(inst->mlen == 3);
669 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
670 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
671 break;
672 default:
673 unreachable("not reached");
674 }
675 }
676 assert(msg_type != -1);
677
678 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
679 rlen = 8;
680 dst = vec16(dst);
681 }
682
683 if (is_combined_send) {
684 assert(brw->gen >= 9 || brw->is_cherryview);
685 rlen = 0;
686 }
687
688 assert(brw->gen < 7 || !inst->header_present ||
689 src.file == BRW_GENERAL_REGISTER_FILE);
690
691 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
692
693 /* Load the message header if present. If there's a texture offset,
694 * we need to set it up explicitly and load the offset bitfield.
695 * Otherwise, we can use an implied move from g0 to the first message reg.
696 */
697 if (inst->header_present) {
698 if (brw->gen < 6 && !inst->offset) {
699 /* Set up an implied move from g0 to the MRF. */
700 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
701 } else {
702 struct brw_reg header_reg;
703
704 if (brw->gen >= 7) {
705 header_reg = src;
706 } else {
707 assert(inst->base_mrf != -1);
708 header_reg = brw_message_reg(inst->base_mrf);
709 }
710
711 brw_push_insn_state(p);
712 brw_set_default_exec_size(p, BRW_EXECUTE_8);
713 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
714 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
715 /* Explicitly set up the message header by copying g0 to the MRF. */
716 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
717
718 if (inst->offset) {
719 /* Set the offset bits in DWord 2. */
720 brw_MOV(p, get_element_ud(header_reg, 2),
721 brw_imm_ud(inst->offset));
722 }
723
724 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
725 brw_pop_insn_state(p);
726 }
727 }
728
729 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
730 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
731 ? prog_data->binding_table.gather_texture_start
732 : prog_data->binding_table.texture_start;
733
734 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
735 uint32_t sampler = sampler_index.dw1.ud;
736
737 brw_SAMPLE(p,
738 retype(dst, BRW_REGISTER_TYPE_UW),
739 inst->base_mrf,
740 src,
741 sampler + base_binding_table_index,
742 sampler % 16,
743 msg_type,
744 rlen,
745 inst->mlen,
746 inst->header_present,
747 simd_mode,
748 return_format);
749
750 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
751 } else {
752 /* Non-const sampler index */
753 /* Note: this clobbers `dst` as a temporary before emitting the send */
754
755 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
756 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
757
758 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
759
760 brw_push_insn_state(p);
761 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
762 brw_set_default_access_mode(p, BRW_ALIGN_1);
763
764 /* Some care required: `sampler` and `temp` may alias:
765 * addr = sampler & 0xff
766 * temp = (sampler << 8) & 0xf00
767 * addr = addr | temp
768 */
769 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
770 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
771 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
772 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
773 brw_OR(p, addr, addr, temp);
774
775 brw_pop_insn_state(p);
776
777 /* dst = send(offset, a0.0 | <descriptor>) */
778 brw_inst *insn = brw_send_indirect_message(
779 p, BRW_SFID_SAMPLER, dst, src, addr);
780 brw_set_sampler_message(p, insn,
781 0 /* surface */,
782 0 /* sampler */,
783 msg_type,
784 rlen,
785 inst->mlen /* mlen */,
786 inst->header_present /* header */,
787 simd_mode,
788 return_format);
789
790 /* visitor knows more than we do about the surface limit required,
791 * so has already done marking.
792 */
793 }
794
795 if (is_combined_send) {
796 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
797 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
798 }
799 }
800
801
802 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
803 * looking like:
804 *
805 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
806 *
807 * Ideally, we want to produce:
808 *
809 * DDX DDY
810 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
811 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
812 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
813 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
814 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
815 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
816 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
817 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
818 *
819 * and add another set of two more subspans if in 16-pixel dispatch mode.
820 *
821 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
822 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
823 * pair. But the ideal approximation may impose a huge performance cost on
824 * sample_d. On at least Haswell, sample_d instruction does some
825 * optimizations if the same LOD is used for all pixels in the subspan.
826 *
827 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
828 * appropriate swizzling.
829 */
830 void
831 fs_generator::generate_ddx(enum opcode opcode,
832 struct brw_reg dst, struct brw_reg src)
833 {
834 unsigned vstride, width;
835
836 if (opcode == FS_OPCODE_DDX_FINE) {
837 /* produce accurate derivatives */
838 vstride = BRW_VERTICAL_STRIDE_2;
839 width = BRW_WIDTH_2;
840 } else {
841 /* replicate the derivative at the top-left pixel to other pixels */
842 vstride = BRW_VERTICAL_STRIDE_4;
843 width = BRW_WIDTH_4;
844 }
845
846 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
847 src.negate, src.abs,
848 BRW_REGISTER_TYPE_F,
849 vstride,
850 width,
851 BRW_HORIZONTAL_STRIDE_0,
852 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
853 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
854 src.negate, src.abs,
855 BRW_REGISTER_TYPE_F,
856 vstride,
857 width,
858 BRW_HORIZONTAL_STRIDE_0,
859 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
860 brw_ADD(p, dst, src0, negate(src1));
861 }
862
863 /* The negate_value boolean is used to negate the derivative computation for
864 * FBOs, since they place the origin at the upper left instead of the lower
865 * left.
866 */
867 void
868 fs_generator::generate_ddy(enum opcode opcode,
869 struct brw_reg dst, struct brw_reg src,
870 bool negate_value)
871 {
872 if (opcode == FS_OPCODE_DDY_FINE) {
873 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
874 * Region Restrictions):
875 *
876 * In Align16 access mode, SIMD16 is not allowed for DW operations
877 * and SIMD8 is not allowed for DF operations.
878 *
879 * In this context, "DW operations" means "operations acting on 32-bit
880 * values", so it includes operations on floats.
881 *
882 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
883 * (Instruction Compression -> Rules and Restrictions):
884 *
885 * A compressed instruction must be in Align1 access mode. Align16
886 * mode instructions cannot be compressed.
887 *
888 * Similar text exists in the g45 PRM.
889 *
890 * On these platforms, if we're building a SIMD16 shader, we need to
891 * manually unroll to a pair of SIMD8 instructions.
892 */
893 bool unroll_to_simd8 =
894 (dispatch_width == 16 &&
895 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
896
897 /* produce accurate derivatives */
898 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
899 src.negate, src.abs,
900 BRW_REGISTER_TYPE_F,
901 BRW_VERTICAL_STRIDE_4,
902 BRW_WIDTH_4,
903 BRW_HORIZONTAL_STRIDE_1,
904 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
905 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
906 src.negate, src.abs,
907 BRW_REGISTER_TYPE_F,
908 BRW_VERTICAL_STRIDE_4,
909 BRW_WIDTH_4,
910 BRW_HORIZONTAL_STRIDE_1,
911 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
912 brw_push_insn_state(p);
913 brw_set_default_access_mode(p, BRW_ALIGN_16);
914 if (unroll_to_simd8) {
915 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
916 if (negate_value) {
917 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
918 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
919 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
920 } else {
921 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
922 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
923 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
924 }
925 } else {
926 if (negate_value)
927 brw_ADD(p, dst, src1, negate(src0));
928 else
929 brw_ADD(p, dst, src0, negate(src1));
930 }
931 brw_pop_insn_state(p);
932 } else {
933 /* replicate the derivative at the top-left pixel to other pixels */
934 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
935 src.negate, src.abs,
936 BRW_REGISTER_TYPE_F,
937 BRW_VERTICAL_STRIDE_4,
938 BRW_WIDTH_4,
939 BRW_HORIZONTAL_STRIDE_0,
940 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
941 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
942 src.negate, src.abs,
943 BRW_REGISTER_TYPE_F,
944 BRW_VERTICAL_STRIDE_4,
945 BRW_WIDTH_4,
946 BRW_HORIZONTAL_STRIDE_0,
947 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
948 if (negate_value)
949 brw_ADD(p, dst, src1, negate(src0));
950 else
951 brw_ADD(p, dst, src0, negate(src1));
952 }
953 }
954
955 void
956 fs_generator::generate_discard_jump(fs_inst *inst)
957 {
958 assert(brw->gen >= 6);
959
960 /* This HALT will be patched up at FB write time to point UIP at the end of
961 * the program, and at brw_uip_jip() JIP will be set to the end of the
962 * current block (or the program).
963 */
964 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
965
966 brw_push_insn_state(p);
967 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
968 gen6_HALT(p);
969 brw_pop_insn_state(p);
970 }
971
972 void
973 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
974 {
975 assert(inst->mlen != 0);
976
977 brw_MOV(p,
978 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
979 retype(src, BRW_REGISTER_TYPE_UD));
980 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
981 inst->exec_size / 8, inst->offset);
982 }
983
984 void
985 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
986 {
987 assert(inst->mlen != 0);
988
989 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
990 inst->exec_size / 8, inst->offset);
991 }
992
993 void
994 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
995 {
996 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
997 }
998
999 void
1000 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1001 struct brw_reg dst,
1002 struct brw_reg index,
1003 struct brw_reg offset)
1004 {
1005 assert(inst->mlen != 0);
1006
1007 assert(index.file == BRW_IMMEDIATE_VALUE &&
1008 index.type == BRW_REGISTER_TYPE_UD);
1009 uint32_t surf_index = index.dw1.ud;
1010
1011 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1012 offset.type == BRW_REGISTER_TYPE_UD);
1013 uint32_t read_offset = offset.dw1.ud;
1014
1015 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1016 read_offset, surf_index);
1017
1018 brw_mark_surface_used(prog_data, surf_index);
1019 }
1020
1021 void
1022 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1023 struct brw_reg dst,
1024 struct brw_reg index,
1025 struct brw_reg offset)
1026 {
1027 assert(inst->mlen == 0);
1028 assert(index.type == BRW_REGISTER_TYPE_UD);
1029
1030 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1031 /* Reference just the dword we need, to avoid angering validate_reg(). */
1032 offset = brw_vec1_grf(offset.nr, 0);
1033
1034 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1035 * the destination loaded consecutively from the same offset (which appears
1036 * in the first component, and the rest are ignored).
1037 */
1038 dst.width = BRW_WIDTH_4;
1039
1040 struct brw_reg src = offset;
1041 bool header_present = false;
1042 int mlen = 1;
1043
1044 if (brw->gen >= 9) {
1045 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1046 src = retype(brw_vec4_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD);
1047 mlen = 2;
1048 header_present = true;
1049
1050 brw_push_insn_state(p);
1051 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1052 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1053 brw_set_default_access_mode(p, BRW_ALIGN_1);
1054
1055 brw_MOV(p, get_element_ud(src, 2),
1056 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1057 brw_pop_insn_state(p);
1058 }
1059
1060 if (index.file == BRW_IMMEDIATE_VALUE) {
1061
1062 uint32_t surf_index = index.dw1.ud;
1063
1064 brw_push_insn_state(p);
1065 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1066 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1067 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1068 brw_pop_insn_state(p);
1069
1070 brw_set_dest(p, send, dst);
1071 brw_set_src0(p, send, src);
1072 brw_set_sampler_message(p, send,
1073 surf_index,
1074 0, /* LD message ignores sampler unit */
1075 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1076 1, /* rlen */
1077 mlen,
1078 header_present,
1079 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1080 0);
1081
1082 brw_mark_surface_used(prog_data, surf_index);
1083
1084 } else {
1085
1086 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1087
1088 brw_push_insn_state(p);
1089 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1090 brw_set_default_access_mode(p, BRW_ALIGN_1);
1091
1092 /* a0.0 = surf_index & 0xff */
1093 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1094 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1095 brw_set_dest(p, insn_and, addr);
1096 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1097 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1098
1099 /* dst = send(payload, a0.0 | <descriptor>) */
1100 brw_inst *insn = brw_send_indirect_message(
1101 p, BRW_SFID_SAMPLER, dst, src, addr);
1102 brw_set_sampler_message(p, insn,
1103 0,
1104 0, /* LD message ignores sampler unit */
1105 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1106 1, /* rlen */
1107 mlen,
1108 header_present,
1109 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1110 0);
1111
1112 brw_pop_insn_state(p);
1113
1114 /* visitor knows more than we do about the surface limit required,
1115 * so has already done marking.
1116 */
1117
1118 }
1119 }
1120
1121 void
1122 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1123 struct brw_reg dst,
1124 struct brw_reg index,
1125 struct brw_reg offset)
1126 {
1127 assert(brw->gen < 7); /* Should use the gen7 variant. */
1128 assert(inst->header_present);
1129 assert(inst->mlen);
1130
1131 assert(index.file == BRW_IMMEDIATE_VALUE &&
1132 index.type == BRW_REGISTER_TYPE_UD);
1133 uint32_t surf_index = index.dw1.ud;
1134
1135 uint32_t simd_mode, rlen, msg_type;
1136 if (dispatch_width == 16) {
1137 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1138 rlen = 8;
1139 } else {
1140 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1141 rlen = 4;
1142 }
1143
1144 if (brw->gen >= 5)
1145 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1146 else {
1147 /* We always use the SIMD16 message so that we only have to load U, and
1148 * not V or R.
1149 */
1150 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1151 assert(inst->mlen == 3);
1152 assert(inst->regs_written == 8);
1153 rlen = 8;
1154 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1155 }
1156
1157 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1158 BRW_REGISTER_TYPE_D);
1159 brw_MOV(p, offset_mrf, offset);
1160
1161 struct brw_reg header = brw_vec8_grf(0, 0);
1162 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1163
1164 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1165 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1166 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1167 brw_set_src0(p, send, header);
1168 if (brw->gen < 6)
1169 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1170
1171 /* Our surface is set up as floats, regardless of what actual data is
1172 * stored in it.
1173 */
1174 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1175 brw_set_sampler_message(p, send,
1176 surf_index,
1177 0, /* sampler (unused) */
1178 msg_type,
1179 rlen,
1180 inst->mlen,
1181 inst->header_present,
1182 simd_mode,
1183 return_format);
1184
1185 brw_mark_surface_used(prog_data, surf_index);
1186 }
1187
1188 void
1189 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1190 struct brw_reg dst,
1191 struct brw_reg index,
1192 struct brw_reg offset)
1193 {
1194 assert(brw->gen >= 7);
1195 /* Varying-offset pull constant loads are treated as a normal expression on
1196 * gen7, so the fact that it's a send message is hidden at the IR level.
1197 */
1198 assert(!inst->header_present);
1199 assert(!inst->mlen);
1200 assert(index.type == BRW_REGISTER_TYPE_UD);
1201
1202 uint32_t simd_mode, rlen, mlen;
1203 if (dispatch_width == 16) {
1204 mlen = 2;
1205 rlen = 8;
1206 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1207 } else {
1208 mlen = 1;
1209 rlen = 4;
1210 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1211 }
1212
1213 if (index.file == BRW_IMMEDIATE_VALUE) {
1214
1215 uint32_t surf_index = index.dw1.ud;
1216
1217 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1218 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1219 brw_set_src0(p, send, offset);
1220 brw_set_sampler_message(p, send,
1221 surf_index,
1222 0, /* LD message ignores sampler unit */
1223 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1224 rlen,
1225 mlen,
1226 false, /* no header */
1227 simd_mode,
1228 0);
1229
1230 brw_mark_surface_used(prog_data, surf_index);
1231
1232 } else {
1233
1234 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1235
1236 brw_push_insn_state(p);
1237 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1238 brw_set_default_access_mode(p, BRW_ALIGN_1);
1239
1240 /* a0.0 = surf_index & 0xff */
1241 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1242 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1243 brw_set_dest(p, insn_and, addr);
1244 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1245 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1246
1247 brw_pop_insn_state(p);
1248
1249 /* dst = send(offset, a0.0 | <descriptor>) */
1250 brw_inst *insn = brw_send_indirect_message(
1251 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1252 offset, addr);
1253 brw_set_sampler_message(p, insn,
1254 0 /* surface */,
1255 0 /* sampler */,
1256 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1257 rlen /* rlen */,
1258 mlen /* mlen */,
1259 false /* header */,
1260 simd_mode,
1261 0);
1262
1263 /* visitor knows more than we do about the surface limit required,
1264 * so has already done marking.
1265 */
1266 }
1267 }
1268
1269 /**
1270 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1271 * into the flags register (f0.0).
1272 *
1273 * Used only on Gen6 and above.
1274 */
1275 void
1276 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1277 {
1278 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1279 struct brw_reg dispatch_mask;
1280
1281 if (brw->gen >= 6)
1282 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1283 else
1284 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1285
1286 brw_push_insn_state(p);
1287 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1288 brw_MOV(p, flags, dispatch_mask);
1289 brw_pop_insn_state(p);
1290 }
1291
1292 void
1293 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1294 struct brw_reg dst,
1295 struct brw_reg src,
1296 struct brw_reg msg_data,
1297 unsigned msg_type)
1298 {
1299 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1300 msg_data.type == BRW_REGISTER_TYPE_UD);
1301
1302 brw_pixel_interpolator_query(p,
1303 retype(dst, BRW_REGISTER_TYPE_UW),
1304 src,
1305 inst->pi_noperspective,
1306 msg_type,
1307 msg_data.dw1.ud,
1308 inst->mlen,
1309 inst->regs_written);
1310 }
1311
1312
1313 /**
1314 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1315 * sampler LD messages.
1316 *
1317 * We don't want to bake it into the send message's code generation because
1318 * that means we don't get a chance to schedule the instructions.
1319 */
1320 void
1321 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1322 struct brw_reg dst,
1323 struct brw_reg value)
1324 {
1325 assert(value.file == BRW_IMMEDIATE_VALUE);
1326
1327 brw_push_insn_state(p);
1328 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1329 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1330 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1331 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1332 brw_pop_insn_state(p);
1333 }
1334
1335 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1336 * (when mask is passed as a uniform) of register mask before moving it
1337 * to register dst.
1338 */
1339 void
1340 fs_generator::generate_set_omask(fs_inst *inst,
1341 struct brw_reg dst,
1342 struct brw_reg mask)
1343 {
1344 bool stride_8_8_1 =
1345 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1346 mask.width == BRW_WIDTH_8 &&
1347 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1348
1349 bool stride_0_1_0 = has_scalar_region(mask);
1350
1351 assert(stride_8_8_1 || stride_0_1_0);
1352 assert(dst.type == BRW_REGISTER_TYPE_UW);
1353
1354 brw_push_insn_state(p);
1355 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1356 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1357
1358 if (stride_8_8_1) {
1359 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1360 } else if (stride_0_1_0) {
1361 brw_MOV(p, dst, retype(mask, dst.type));
1362 }
1363 brw_pop_insn_state(p);
1364 }
1365
1366 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1367 * the ADD instruction.
1368 */
1369 void
1370 fs_generator::generate_set_sample_id(fs_inst *inst,
1371 struct brw_reg dst,
1372 struct brw_reg src0,
1373 struct brw_reg src1)
1374 {
1375 assert(dst.type == BRW_REGISTER_TYPE_D ||
1376 dst.type == BRW_REGISTER_TYPE_UD);
1377 assert(src0.type == BRW_REGISTER_TYPE_D ||
1378 src0.type == BRW_REGISTER_TYPE_UD);
1379
1380 brw_push_insn_state(p);
1381 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1382 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1383 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1384 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1385 if (dispatch_width == 8) {
1386 brw_ADD(p, dst, src0, reg);
1387 } else if (dispatch_width == 16) {
1388 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1389 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1390 }
1391 brw_pop_insn_state(p);
1392 }
1393
1394 void
1395 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1396 struct brw_reg dst,
1397 struct brw_reg x,
1398 struct brw_reg y)
1399 {
1400 assert(brw->gen >= 7);
1401 assert(dst.type == BRW_REGISTER_TYPE_UD);
1402 assert(x.type == BRW_REGISTER_TYPE_F);
1403 assert(y.type == BRW_REGISTER_TYPE_F);
1404
1405 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1406 *
1407 * Because this instruction does not have a 16-bit floating-point type,
1408 * the destination data type must be Word (W).
1409 *
1410 * The destination must be DWord-aligned and specify a horizontal stride
1411 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1412 * each destination channel and the upper word is not modified.
1413 */
1414 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1415
1416 /* Give each 32-bit channel of dst the form below, where "." means
1417 * unchanged.
1418 * 0x....hhhh
1419 */
1420 brw_F32TO16(p, dst_w, y);
1421
1422 /* Now the form:
1423 * 0xhhhh0000
1424 */
1425 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1426
1427 /* And, finally the form of packHalf2x16's output:
1428 * 0xhhhhllll
1429 */
1430 brw_F32TO16(p, dst_w, x);
1431 }
1432
1433 void
1434 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1435 struct brw_reg dst,
1436 struct brw_reg src)
1437 {
1438 assert(brw->gen >= 7);
1439 assert(dst.type == BRW_REGISTER_TYPE_F);
1440 assert(src.type == BRW_REGISTER_TYPE_UD);
1441
1442 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1443 *
1444 * Because this instruction does not have a 16-bit floating-point type,
1445 * the source data type must be Word (W). The destination type must be
1446 * F (Float).
1447 */
1448 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1449
1450 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1451 * For the Y case, we wish to access only the upper word; therefore
1452 * a 16-bit subregister offset is needed.
1453 */
1454 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1455 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1456 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1457 src_w.subnr += 2;
1458
1459 brw_F16TO32(p, dst, src_w);
1460 }
1461
1462 void
1463 fs_generator::generate_shader_time_add(fs_inst *inst,
1464 struct brw_reg payload,
1465 struct brw_reg offset,
1466 struct brw_reg value)
1467 {
1468 assert(brw->gen >= 7);
1469 brw_push_insn_state(p);
1470 brw_set_default_mask_control(p, true);
1471
1472 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1473 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1474 offset.type);
1475 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1476 value.type);
1477
1478 assert(offset.file == BRW_IMMEDIATE_VALUE);
1479 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1480 value.width = BRW_WIDTH_1;
1481 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1482 value.vstride = BRW_VERTICAL_STRIDE_0;
1483 } else {
1484 assert(value.file == BRW_IMMEDIATE_VALUE);
1485 }
1486
1487 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1488 * case, and we don't really care about squeezing every bit of performance
1489 * out of this path, so we just emit the MOVs from here.
1490 */
1491 brw_MOV(p, payload_offset, offset);
1492 brw_MOV(p, payload_value, value);
1493 brw_shader_time_add(p, payload,
1494 prog_data->binding_table.shader_time_start);
1495 brw_pop_insn_state(p);
1496
1497 brw_mark_surface_used(prog_data,
1498 prog_data->binding_table.shader_time_start);
1499 }
1500
1501 void
1502 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1503 struct brw_reg payload,
1504 struct brw_reg atomic_op,
1505 struct brw_reg surf_index)
1506 {
1507 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1508 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1509 surf_index.file == BRW_IMMEDIATE_VALUE &&
1510 surf_index.type == BRW_REGISTER_TYPE_UD);
1511
1512 brw_untyped_atomic(p, dst, payload,
1513 atomic_op.dw1.ud, surf_index.dw1.ud,
1514 inst->mlen, true);
1515
1516 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1517 }
1518
1519 void
1520 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1521 struct brw_reg payload,
1522 struct brw_reg surf_index)
1523 {
1524 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1525 surf_index.type == BRW_REGISTER_TYPE_UD);
1526
1527 brw_untyped_surface_read(p, dst, payload, surf_index.dw1.ud, inst->mlen, 1);
1528
1529 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1530 }
1531
1532 void
1533 fs_generator::enable_debug(const char *shader_name)
1534 {
1535 debug_flag = true;
1536 this->shader_name = shader_name;
1537 }
1538
1539 /**
1540 * Some hardware doesn't support SIMD16 instructions with 3 sources.
1541 */
1542 static bool
1543 brw_supports_simd16_3src(const struct brw_context *brw)
1544 {
1545 /* WaDisableSIMD16On3SrcInstr: 3-source instructions don't work in SIMD16
1546 * on a few steppings of Skylake.
1547 */
1548 if (brw->gen == 9)
1549 return brw->revision != 2 && brw->revision != 3 && brw->revision != -1;
1550
1551 return brw->is_haswell || brw->gen >= 8;
1552 }
1553
1554 int
1555 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1556 {
1557 /* align to 64 byte boundary. */
1558 while (p->next_insn_offset % 64)
1559 brw_NOP(p);
1560
1561 this->dispatch_width = dispatch_width;
1562 if (dispatch_width == 16)
1563 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1564
1565 int start_offset = p->next_insn_offset;
1566 int spill_count = 0, fill_count = 0;
1567 int loop_count = 0;
1568
1569 struct annotation_info annotation;
1570 memset(&annotation, 0, sizeof(annotation));
1571
1572 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1573 struct brw_reg src[3], dst;
1574 unsigned int last_insn_offset = p->next_insn_offset;
1575 bool multiple_instructions_emitted = false;
1576
1577 if (unlikely(debug_flag))
1578 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1579
1580 for (unsigned int i = 0; i < inst->sources; i++) {
1581 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1582
1583 /* The accumulator result appears to get used for the
1584 * conditional modifier generation. When negating a UD
1585 * value, there is a 33rd bit generated for the sign in the
1586 * accumulator value, so now you can't check, for example,
1587 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1588 */
1589 assert(!inst->conditional_mod ||
1590 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1591 !inst->src[i].negate);
1592 }
1593 dst = brw_reg_from_fs_reg(&inst->dst);
1594
1595 brw_set_default_predicate_control(p, inst->predicate);
1596 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1597 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1598 brw_set_default_saturate(p, inst->saturate);
1599 brw_set_default_mask_control(p, inst->force_writemask_all);
1600 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1601 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1602
1603 switch (inst->exec_size) {
1604 case 1:
1605 case 2:
1606 case 4:
1607 assert(inst->force_writemask_all);
1608 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1609 break;
1610 case 8:
1611 if (inst->force_sechalf) {
1612 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1613 } else {
1614 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1615 }
1616 break;
1617 case 16:
1618 case 32:
1619 if (type_sz(inst->dst.type) < sizeof(float))
1620 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1621 else
1622 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1623 break;
1624 default:
1625 unreachable("Invalid instruction width");
1626 }
1627
1628 switch (inst->opcode) {
1629 case BRW_OPCODE_MOV:
1630 brw_MOV(p, dst, src[0]);
1631 break;
1632 case BRW_OPCODE_ADD:
1633 brw_ADD(p, dst, src[0], src[1]);
1634 break;
1635 case BRW_OPCODE_MUL:
1636 brw_MUL(p, dst, src[0], src[1]);
1637 break;
1638 case BRW_OPCODE_AVG:
1639 brw_AVG(p, dst, src[0], src[1]);
1640 break;
1641 case BRW_OPCODE_MACH:
1642 brw_MACH(p, dst, src[0], src[1]);
1643 break;
1644
1645 case BRW_OPCODE_LINE:
1646 brw_LINE(p, dst, src[0], src[1]);
1647 break;
1648
1649 case BRW_OPCODE_MAD:
1650 assert(brw->gen >= 6);
1651 brw_set_default_access_mode(p, BRW_ALIGN_16);
1652 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1653 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1654 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1655 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1656 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1657 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1658 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1659
1660 if (inst->conditional_mod) {
1661 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1662 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1663 multiple_instructions_emitted = true;
1664 }
1665 } else {
1666 brw_MAD(p, dst, src[0], src[1], src[2]);
1667 }
1668 brw_set_default_access_mode(p, BRW_ALIGN_1);
1669 break;
1670
1671 case BRW_OPCODE_LRP:
1672 assert(brw->gen >= 6);
1673 brw_set_default_access_mode(p, BRW_ALIGN_16);
1674 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1675 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1676 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1677 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1678 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1679 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1680 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1681
1682 if (inst->conditional_mod) {
1683 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1684 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1685 multiple_instructions_emitted = true;
1686 }
1687 } else {
1688 brw_LRP(p, dst, src[0], src[1], src[2]);
1689 }
1690 brw_set_default_access_mode(p, BRW_ALIGN_1);
1691 break;
1692
1693 case BRW_OPCODE_FRC:
1694 brw_FRC(p, dst, src[0]);
1695 break;
1696 case BRW_OPCODE_RNDD:
1697 brw_RNDD(p, dst, src[0]);
1698 break;
1699 case BRW_OPCODE_RNDE:
1700 brw_RNDE(p, dst, src[0]);
1701 break;
1702 case BRW_OPCODE_RNDZ:
1703 brw_RNDZ(p, dst, src[0]);
1704 break;
1705
1706 case BRW_OPCODE_AND:
1707 brw_AND(p, dst, src[0], src[1]);
1708 break;
1709 case BRW_OPCODE_OR:
1710 brw_OR(p, dst, src[0], src[1]);
1711 break;
1712 case BRW_OPCODE_XOR:
1713 brw_XOR(p, dst, src[0], src[1]);
1714 break;
1715 case BRW_OPCODE_NOT:
1716 brw_NOT(p, dst, src[0]);
1717 break;
1718 case BRW_OPCODE_ASR:
1719 brw_ASR(p, dst, src[0], src[1]);
1720 break;
1721 case BRW_OPCODE_SHR:
1722 brw_SHR(p, dst, src[0], src[1]);
1723 break;
1724 case BRW_OPCODE_SHL:
1725 brw_SHL(p, dst, src[0], src[1]);
1726 break;
1727 case BRW_OPCODE_F32TO16:
1728 assert(brw->gen >= 7);
1729 brw_F32TO16(p, dst, src[0]);
1730 break;
1731 case BRW_OPCODE_F16TO32:
1732 assert(brw->gen >= 7);
1733 brw_F16TO32(p, dst, src[0]);
1734 break;
1735 case BRW_OPCODE_CMP:
1736 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1737 * that when the destination is a GRF that the dependency-clear bit on
1738 * the flag register is cleared early.
1739 *
1740 * Suggested workarounds are to disable coissuing CMP instructions
1741 * or to split CMP(16) instructions into two CMP(8) instructions.
1742 *
1743 * We choose to split into CMP(8) instructions since disabling
1744 * coissuing would affect CMP instructions not otherwise affected by
1745 * the errata.
1746 */
1747 if (dispatch_width == 16 && brw->gen == 7 && !brw->is_haswell) {
1748 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1749 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1750 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1751 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1752 firsthalf(src[0]), firsthalf(src[1]));
1753 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1754 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1755 sechalf(src[0]), sechalf(src[1]));
1756 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1757
1758 multiple_instructions_emitted = true;
1759 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1760 /* For unknown reasons, the aforementioned workaround is not
1761 * sufficient. Overriding the type when the destination is the
1762 * null register is necessary but not sufficient by itself.
1763 */
1764 assert(dst.nr == BRW_ARF_NULL);
1765 dst.type = BRW_REGISTER_TYPE_D;
1766 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1767 } else {
1768 unreachable("not reached");
1769 }
1770 } else {
1771 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1772 }
1773 break;
1774 case BRW_OPCODE_SEL:
1775 brw_SEL(p, dst, src[0], src[1]);
1776 break;
1777 case BRW_OPCODE_BFREV:
1778 assert(brw->gen >= 7);
1779 /* BFREV only supports UD type for src and dst. */
1780 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1781 retype(src[0], BRW_REGISTER_TYPE_UD));
1782 break;
1783 case BRW_OPCODE_FBH:
1784 assert(brw->gen >= 7);
1785 /* FBH only supports UD type for dst. */
1786 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1787 break;
1788 case BRW_OPCODE_FBL:
1789 assert(brw->gen >= 7);
1790 /* FBL only supports UD type for dst. */
1791 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1792 break;
1793 case BRW_OPCODE_CBIT:
1794 assert(brw->gen >= 7);
1795 /* CBIT only supports UD type for dst. */
1796 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1797 break;
1798 case BRW_OPCODE_ADDC:
1799 assert(brw->gen >= 7);
1800 brw_ADDC(p, dst, src[0], src[1]);
1801 break;
1802 case BRW_OPCODE_SUBB:
1803 assert(brw->gen >= 7);
1804 brw_SUBB(p, dst, src[0], src[1]);
1805 break;
1806 case BRW_OPCODE_MAC:
1807 brw_MAC(p, dst, src[0], src[1]);
1808 break;
1809
1810 case BRW_OPCODE_BFE:
1811 assert(brw->gen >= 7);
1812 brw_set_default_access_mode(p, BRW_ALIGN_16);
1813 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1814 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1815 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1816 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1817 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1818 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1819 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1820 } else {
1821 brw_BFE(p, dst, src[0], src[1], src[2]);
1822 }
1823 brw_set_default_access_mode(p, BRW_ALIGN_1);
1824 break;
1825
1826 case BRW_OPCODE_BFI1:
1827 assert(brw->gen >= 7);
1828 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1829 * should
1830 *
1831 * "Force BFI instructions to be executed always in SIMD8."
1832 */
1833 if (dispatch_width == 16 && brw->is_haswell) {
1834 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1835 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1836 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1837 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1838 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1839 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1840 } else {
1841 brw_BFI1(p, dst, src[0], src[1]);
1842 }
1843 break;
1844 case BRW_OPCODE_BFI2:
1845 assert(brw->gen >= 7);
1846 brw_set_default_access_mode(p, BRW_ALIGN_16);
1847 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1848 * should
1849 *
1850 * "Force BFI instructions to be executed always in SIMD8."
1851 *
1852 * Otherwise we would be able to emit compressed instructions like we
1853 * do for the other three-source instructions.
1854 */
1855 if (dispatch_width == 16 &&
1856 (brw->is_haswell || !brw_supports_simd16_3src(brw))) {
1857 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1858 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1859 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1860 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1861 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1862 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1863 } else {
1864 brw_BFI2(p, dst, src[0], src[1], src[2]);
1865 }
1866 brw_set_default_access_mode(p, BRW_ALIGN_1);
1867 break;
1868
1869 case BRW_OPCODE_IF:
1870 if (inst->src[0].file != BAD_FILE) {
1871 /* The instruction has an embedded compare (only allowed on gen6) */
1872 assert(brw->gen == 6);
1873 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1874 } else {
1875 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1876 }
1877 break;
1878
1879 case BRW_OPCODE_ELSE:
1880 brw_ELSE(p);
1881 break;
1882 case BRW_OPCODE_ENDIF:
1883 brw_ENDIF(p);
1884 break;
1885
1886 case BRW_OPCODE_DO:
1887 brw_DO(p, BRW_EXECUTE_8);
1888 break;
1889
1890 case BRW_OPCODE_BREAK:
1891 brw_BREAK(p);
1892 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1893 break;
1894 case BRW_OPCODE_CONTINUE:
1895 brw_CONT(p);
1896 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1897 break;
1898
1899 case BRW_OPCODE_WHILE:
1900 brw_WHILE(p);
1901 loop_count++;
1902 break;
1903
1904 case SHADER_OPCODE_RCP:
1905 case SHADER_OPCODE_RSQ:
1906 case SHADER_OPCODE_SQRT:
1907 case SHADER_OPCODE_EXP2:
1908 case SHADER_OPCODE_LOG2:
1909 case SHADER_OPCODE_SIN:
1910 case SHADER_OPCODE_COS:
1911 assert(brw->gen < 6 || inst->mlen == 0);
1912 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1913 if (brw->gen >= 7) {
1914 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1915 brw_null_reg());
1916 } else if (brw->gen == 6) {
1917 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1918 } else if (brw->gen == 5 || brw->is_g4x) {
1919 generate_math_g45(inst, dst, src[0]);
1920 } else {
1921 generate_math_gen4(inst, dst, src[0]);
1922 }
1923 break;
1924 case SHADER_OPCODE_INT_QUOTIENT:
1925 case SHADER_OPCODE_INT_REMAINDER:
1926 case SHADER_OPCODE_POW:
1927 assert(brw->gen < 6 || inst->mlen == 0);
1928 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1929 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1930 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1931 } else if (brw->gen >= 6) {
1932 generate_math_gen6(inst, dst, src[0], src[1]);
1933 } else {
1934 generate_math_gen4(inst, dst, src[0]);
1935 }
1936 break;
1937 case FS_OPCODE_CINTERP:
1938 brw_MOV(p, dst, src[0]);
1939 break;
1940 case FS_OPCODE_LINTERP:
1941 generate_linterp(inst, dst, src);
1942 break;
1943 case FS_OPCODE_PIXEL_X:
1944 assert(src[0].type == BRW_REGISTER_TYPE_UW);
1945 src[0].subnr = 0 * type_sz(src[0].type);
1946 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1947 break;
1948 case FS_OPCODE_PIXEL_Y:
1949 assert(src[0].type == BRW_REGISTER_TYPE_UW);
1950 src[0].subnr = 4 * type_sz(src[0].type);
1951 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1952 break;
1953 case SHADER_OPCODE_TEX:
1954 case FS_OPCODE_TXB:
1955 case SHADER_OPCODE_TXD:
1956 case SHADER_OPCODE_TXF:
1957 case SHADER_OPCODE_TXF_CMS:
1958 case SHADER_OPCODE_TXF_UMS:
1959 case SHADER_OPCODE_TXF_MCS:
1960 case SHADER_OPCODE_TXL:
1961 case SHADER_OPCODE_TXS:
1962 case SHADER_OPCODE_LOD:
1963 case SHADER_OPCODE_TG4:
1964 case SHADER_OPCODE_TG4_OFFSET:
1965 generate_tex(inst, dst, src[0], src[1]);
1966 break;
1967 case FS_OPCODE_DDX_COARSE:
1968 case FS_OPCODE_DDX_FINE:
1969 generate_ddx(inst->opcode, dst, src[0]);
1970 break;
1971 case FS_OPCODE_DDY_COARSE:
1972 case FS_OPCODE_DDY_FINE:
1973 assert(src[1].file == BRW_IMMEDIATE_VALUE);
1974 generate_ddy(inst->opcode, dst, src[0], src[1].dw1.ud);
1975 break;
1976
1977 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1978 generate_scratch_write(inst, src[0]);
1979 spill_count++;
1980 break;
1981
1982 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1983 generate_scratch_read(inst, dst);
1984 fill_count++;
1985 break;
1986
1987 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1988 generate_scratch_read_gen7(inst, dst);
1989 fill_count++;
1990 break;
1991
1992 case SHADER_OPCODE_URB_WRITE_SIMD8:
1993 generate_urb_write(inst, src[0]);
1994 break;
1995
1996 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1997 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1998 break;
1999
2000 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2001 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2002 break;
2003
2004 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
2005 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
2006 break;
2007
2008 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2009 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2010 break;
2011
2012 case FS_OPCODE_REP_FB_WRITE:
2013 case FS_OPCODE_FB_WRITE:
2014 generate_fb_write(inst, src[0]);
2015 break;
2016
2017 case FS_OPCODE_BLORP_FB_WRITE:
2018 generate_blorp_fb_write(inst);
2019 break;
2020
2021 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2022 generate_mov_dispatch_to_flags(inst);
2023 break;
2024
2025 case FS_OPCODE_DISCARD_JUMP:
2026 generate_discard_jump(inst);
2027 break;
2028
2029 case SHADER_OPCODE_SHADER_TIME_ADD:
2030 generate_shader_time_add(inst, src[0], src[1], src[2]);
2031 break;
2032
2033 case SHADER_OPCODE_UNTYPED_ATOMIC:
2034 generate_untyped_atomic(inst, dst, src[0], src[1], src[2]);
2035 break;
2036
2037 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2038 generate_untyped_surface_read(inst, dst, src[0], src[1]);
2039 break;
2040
2041 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2042 generate_set_simd4x2_offset(inst, dst, src[0]);
2043 break;
2044
2045 case FS_OPCODE_SET_OMASK:
2046 generate_set_omask(inst, dst, src[0]);
2047 break;
2048
2049 case FS_OPCODE_SET_SAMPLE_ID:
2050 generate_set_sample_id(inst, dst, src[0], src[1]);
2051 break;
2052
2053 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2054 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2055 break;
2056
2057 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2058 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2059 generate_unpack_half_2x16_split(inst, dst, src[0]);
2060 break;
2061
2062 case FS_OPCODE_PLACEHOLDER_HALT:
2063 /* This is the place where the final HALT needs to be inserted if
2064 * we've emitted any discards. If not, this will emit no code.
2065 */
2066 if (!patch_discard_jumps_to_fb_writes()) {
2067 if (unlikely(debug_flag)) {
2068 annotation.ann_count--;
2069 }
2070 }
2071 break;
2072
2073 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2074 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2075 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2076 break;
2077
2078 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2079 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2080 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2081 break;
2082
2083 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2084 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2085 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2086 break;
2087
2088 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2089 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2090 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2091 break;
2092
2093 default:
2094 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
2095 _mesa_problem(ctx, "Unsupported opcode `%s' in %s",
2096 opcode_descs[inst->opcode].name, stage_abbrev);
2097 } else {
2098 _mesa_problem(ctx, "Unsupported opcode %d in %s", inst->opcode,
2099 stage_abbrev);
2100 }
2101 abort();
2102
2103 case SHADER_OPCODE_LOAD_PAYLOAD:
2104 unreachable("Should be lowered by lower_load_payload()");
2105 }
2106
2107 if (multiple_instructions_emitted)
2108 continue;
2109
2110 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2111 assert(p->next_insn_offset == last_insn_offset + 16 ||
2112 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2113 "emitting more than 1 instruction");
2114
2115 brw_inst *last = &p->store[last_insn_offset / 16];
2116
2117 if (inst->conditional_mod)
2118 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2119 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2120 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2121 }
2122 }
2123
2124 brw_set_uip_jip(p);
2125 annotation_finalize(&annotation, p->next_insn_offset);
2126
2127 int before_size = p->next_insn_offset - start_offset;
2128 brw_compact_instructions(p, start_offset, annotation.ann_count,
2129 annotation.ann);
2130 int after_size = p->next_insn_offset - start_offset;
2131
2132 if (unlikely(debug_flag)) {
2133 fprintf(stderr, "Native code for %s\n"
2134 "SIMD%d shader: %d instructions. %d loops. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2135 " bytes (%.0f%%)\n",
2136 shader_name, dispatch_width, before_size / 16, loop_count,
2137 spill_count, fill_count, promoted_constants, before_size, after_size,
2138 100.0f * (before_size - after_size) / before_size);
2139
2140 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
2141 ralloc_free(annotation.ann);
2142 }
2143
2144 static GLuint msg_id = 0;
2145 _mesa_gl_debug(&brw->ctx, &msg_id,
2146 MESA_DEBUG_SOURCE_SHADER_COMPILER,
2147 MESA_DEBUG_TYPE_OTHER,
2148 MESA_DEBUG_SEVERITY_NOTIFICATION,
2149 "%s SIMD%d shader: %d inst, %d loops, %d:%d spills:fills, "
2150 "Promoted %u constants, compacted %d to %d bytes.\n",
2151 stage_abbrev, dispatch_width, before_size / 16, loop_count,
2152 spill_count, fill_count, promoted_constants, before_size, after_size);
2153
2154 return start_offset;
2155 }
2156
2157 const unsigned *
2158 fs_generator::get_assembly(unsigned int *assembly_size)
2159 {
2160 return brw_get_program(p, assembly_size);
2161 }