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i965/fs: Always set hannel 2 of texture headers in some stages
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "brw_eu.h"
31 #include "brw_fs.h"
32 #include "brw_cfg.h"
33 #include "brw_program.h"
34
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case ARF:
40 return BRW_ARCHITECTURE_REGISTER_FILE;
41 case FIXED_GRF:
42 case VGRF:
43 return BRW_GENERAL_REGISTER_FILE;
44 case MRF:
45 return BRW_MESSAGE_REGISTER_FILE;
46 case IMM:
47 return BRW_IMMEDIATE_VALUE;
48 case BAD_FILE:
49 case ATTR:
50 case UNIFORM:
51 unreachable("not reached");
52 }
53 return BRW_ARCHITECTURE_REGISTER_FILE;
54 }
55
56 static struct brw_reg
57 brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
58 {
59 struct brw_reg brw_reg;
60
61 switch (reg->file) {
62 case MRF:
63 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(gen));
64 /* Fallthrough */
65 case VGRF:
66 if (reg->stride == 0) {
67 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
68 } else if (inst->exec_size < 8) {
69 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
70 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
71 inst->exec_size, reg->stride);
72 } else {
73 /* From the Haswell PRM:
74 *
75 * VertStride must be used to cross GRF register boundaries. This
76 * rule implies that elements within a 'Width' cannot cross GRF
77 * boundaries.
78 *
79 * So, for registers with width > 8, we have to use a width of 8
80 * and trust the compression state to sort out the exec size.
81 */
82 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
83 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
84 }
85
86 brw_reg = retype(brw_reg, reg->type);
87 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
88 brw_reg.abs = reg->abs;
89 brw_reg.negate = reg->negate;
90 break;
91 case ARF:
92 case FIXED_GRF:
93 case IMM:
94 brw_reg = reg->as_brw_reg();
95 break;
96 case BAD_FILE:
97 /* Probably unused. */
98 brw_reg = brw_null_reg();
99 break;
100 case ATTR:
101 case UNIFORM:
102 unreachable("not reached");
103 }
104
105 return brw_reg;
106 }
107
108 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
109 void *mem_ctx,
110 const void *key,
111 struct brw_stage_prog_data *prog_data,
112 unsigned promoted_constants,
113 bool runtime_check_aads_emit,
114 gl_shader_stage stage)
115
116 : compiler(compiler), log_data(log_data),
117 devinfo(compiler->devinfo), key(key),
118 prog_data(prog_data),
119 promoted_constants(promoted_constants),
120 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
121 stage(stage), mem_ctx(mem_ctx)
122 {
123 p = rzalloc(mem_ctx, struct brw_codegen);
124 brw_init_codegen(devinfo, p, mem_ctx);
125 }
126
127 fs_generator::~fs_generator()
128 {
129 }
130
131 class ip_record : public exec_node {
132 public:
133 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
134
135 ip_record(int ip)
136 {
137 this->ip = ip;
138 }
139
140 int ip;
141 };
142
143 bool
144 fs_generator::patch_discard_jumps_to_fb_writes()
145 {
146 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
147 return false;
148
149 int scale = brw_jump_scale(p->devinfo);
150
151 /* There is a somewhat strange undocumented requirement of using
152 * HALT, according to the simulator. If some channel has HALTed to
153 * a particular UIP, then by the end of the program, every channel
154 * must have HALTed to that UIP. Furthermore, the tracking is a
155 * stack, so you can't do the final halt of a UIP after starting
156 * halting to a new UIP.
157 *
158 * Symptoms of not emitting this instruction on actual hardware
159 * included GPU hangs and sparkly rendering on the piglit discard
160 * tests.
161 */
162 brw_inst *last_halt = gen6_HALT(p);
163 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
164 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
165
166 int ip = p->nr_insn;
167
168 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
169 brw_inst *patch = &p->store[patch_ip->ip];
170
171 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
172 /* HALT takes a half-instruction distance from the pre-incremented IP. */
173 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
174 }
175
176 this->discard_halt_patches.make_empty();
177 return true;
178 }
179
180 void
181 fs_generator::fire_fb_write(fs_inst *inst,
182 struct brw_reg payload,
183 struct brw_reg implied_header,
184 GLuint nr)
185 {
186 uint32_t msg_control;
187
188 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
189
190 if (devinfo->gen < 6) {
191 brw_push_insn_state(p);
192 brw_set_default_exec_size(p, BRW_EXECUTE_8);
193 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
194 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
195 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
196 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
197 brw_pop_insn_state(p);
198 }
199
200 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
201 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
202 else if (prog_data->dual_src_blend) {
203 if (!inst->force_sechalf)
204 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
205 else
206 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
207 } else if (inst->exec_size == 16)
208 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
209 else
210 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
211
212 uint32_t surf_index =
213 prog_data->binding_table.render_target_start + inst->target;
214
215 bool last_render_target = inst->eot ||
216 (prog_data->dual_src_blend && dispatch_width == 16);
217
218
219 brw_fb_WRITE(p,
220 dispatch_width,
221 payload,
222 implied_header,
223 msg_control,
224 surf_index,
225 nr,
226 0,
227 inst->eot,
228 last_render_target,
229 inst->header_size != 0);
230
231 brw_mark_surface_used(&prog_data->base, surf_index);
232 }
233
234 void
235 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
236 {
237 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
238 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
239 struct brw_reg implied_header;
240
241 if (devinfo->gen < 8 && !devinfo->is_haswell) {
242 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
243 }
244
245 if (inst->base_mrf >= 0)
246 payload = brw_message_reg(inst->base_mrf);
247
248 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
249 * move, here's g1.
250 */
251 if (inst->header_size != 0) {
252 brw_push_insn_state(p);
253 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
254 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
255 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
256 brw_set_default_flag_reg(p, 0, 0);
257
258 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
259 * present.
260 */
261 if (prog_data->uses_kill) {
262 struct brw_reg pixel_mask;
263
264 if (devinfo->gen >= 6)
265 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
266 else
267 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
268
269 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
270 }
271
272 if (devinfo->gen >= 6) {
273 brw_push_insn_state(p);
274 brw_set_default_exec_size(p, BRW_EXECUTE_16);
275 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
276 brw_MOV(p,
277 retype(payload, BRW_REGISTER_TYPE_UD),
278 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
279 brw_pop_insn_state(p);
280
281 if (inst->target > 0 && key->replicate_alpha) {
282 /* Set "Source0 Alpha Present to RenderTarget" bit in message
283 * header.
284 */
285 brw_OR(p,
286 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
287 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
288 brw_imm_ud(0x1 << 11));
289 }
290
291 if (inst->target > 0) {
292 /* Set the render target index for choosing BLEND_STATE. */
293 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
294 BRW_REGISTER_TYPE_UD),
295 brw_imm_ud(inst->target));
296 }
297
298 /* Set computes stencil to render target */
299 if (prog_data->computed_stencil) {
300 brw_OR(p,
301 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
302 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
303 brw_imm_ud(0x1 << 14));
304 }
305
306 implied_header = brw_null_reg();
307 } else {
308 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
309 }
310
311 brw_pop_insn_state(p);
312 } else {
313 implied_header = brw_null_reg();
314 }
315
316 if (!runtime_check_aads_emit) {
317 fire_fb_write(inst, payload, implied_header, inst->mlen);
318 } else {
319 /* This can only happen in gen < 6 */
320 assert(devinfo->gen < 6);
321
322 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
323
324 /* Check runtime bit to detect if we have to send AA data or not */
325 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
326 brw_AND(p,
327 v1_null_ud,
328 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
329 brw_imm_ud(1<<26));
330 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
331
332 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
333 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
334 {
335 /* Don't send AA data */
336 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
337 }
338 brw_land_fwd_jump(p, jmp);
339 fire_fb_write(inst, payload, implied_header, inst->mlen);
340 }
341 }
342
343 void
344 fs_generator::generate_mov_indirect(fs_inst *inst,
345 struct brw_reg dst,
346 struct brw_reg reg,
347 struct brw_reg indirect_byte_offset)
348 {
349 assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
350 assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
351
352 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
353
354 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
355 struct brw_reg addr = vec8(brw_address_reg(0));
356
357 /* The destination stride of an instruction (in bytes) must be greater
358 * than or equal to the size of the rest of the instruction. Since the
359 * address register is of type UW, we can't use a D-type instruction.
360 * In order to get around this, re re-type to UW and use a stride.
361 */
362 indirect_byte_offset =
363 retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
364
365 /* Prior to Broadwell, there are only 8 address registers. */
366 assert(inst->exec_size == 8 || devinfo->gen >= 8);
367
368 brw_MOV(p, addr, indirect_byte_offset);
369 brw_inst_set_mask_control(devinfo, brw_last_inst, BRW_MASK_DISABLE);
370 brw_MOV(p, dst, retype(brw_VxH_indirect(0, imm_byte_offset), dst.type));
371 }
372
373 void
374 fs_generator::generate_urb_read(fs_inst *inst,
375 struct brw_reg dst,
376 struct brw_reg header)
377 {
378 assert(header.file == BRW_GENERAL_REGISTER_FILE);
379 assert(header.type == BRW_REGISTER_TYPE_UD);
380
381 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
382 brw_set_dest(p, send, dst);
383 brw_set_src0(p, send, header);
384 brw_set_src1(p, send, brw_imm_ud(0u));
385
386 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
387 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
388
389 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
390 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
391
392 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
393 brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
394 brw_inst_set_header_present(p->devinfo, send, true);
395 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
396 }
397
398 void
399 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
400 {
401 brw_inst *insn;
402
403 insn = brw_next_insn(p, BRW_OPCODE_SEND);
404
405 brw_set_dest(p, insn, brw_null_reg());
406 brw_set_src0(p, insn, payload);
407 brw_set_src1(p, insn, brw_imm_d(0));
408
409 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
410 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
411
412 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
413 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
414 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
415
416 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
417 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
418 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
419
420 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
421 brw_inst_set_rlen(p->devinfo, insn, 0);
422 brw_inst_set_eot(p->devinfo, insn, inst->eot);
423 brw_inst_set_header_present(p->devinfo, insn, true);
424 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
425 }
426
427 void
428 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
429 {
430 struct brw_inst *insn;
431
432 insn = brw_next_insn(p, BRW_OPCODE_SEND);
433
434 brw_set_dest(p, insn, brw_null_reg());
435 brw_set_src0(p, insn, payload);
436 brw_set_src1(p, insn, brw_imm_d(0));
437
438 /* Terminate a compute shader by sending a message to the thread spawner.
439 */
440 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
441 brw_inst_set_mlen(devinfo, insn, 1);
442 brw_inst_set_rlen(devinfo, insn, 0);
443 brw_inst_set_eot(devinfo, insn, inst->eot);
444 brw_inst_set_header_present(devinfo, insn, false);
445
446 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
447 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
448
449 /* Note that even though the thread has a URB resource associated with it,
450 * we set the "do not dereference URB" bit, because the URB resource is
451 * managed by the fixed-function unit, so it will free it automatically.
452 */
453 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
454
455 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
456 }
457
458 void
459 fs_generator::generate_stencil_ref_packing(fs_inst *inst,
460 struct brw_reg dst,
461 struct brw_reg src)
462 {
463 assert(dispatch_width == 8);
464 assert(devinfo->gen >= 9);
465
466 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
467 * Presumably, in order to save memory bandwidth, the stencil reference
468 * values written from the FS need to be packed into 2 dwords (this makes
469 * sense because the stencil values are limited to 1 byte each and a SIMD8
470 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
471 *
472 * The spec is confusing here because in the payload definition of MDP_RTW_S8
473 * (Message Data Payload for Render Target Writes with Stencil 8b) the
474 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
475 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
476 * packed values specified above and diagrammed below:
477 *
478 * 31 0
479 * --------------------------------
480 * DW | |
481 * 2-7 | IGNORED |
482 * | |
483 * --------------------------------
484 * DW1 | STC | STC | STC | STC |
485 * | slot7 | slot6 | slot5 | slot4|
486 * --------------------------------
487 * DW0 | STC | STC | STC | STC |
488 * | slot3 | slot2 | slot1 | slot0|
489 * --------------------------------
490 */
491
492 src.vstride = BRW_VERTICAL_STRIDE_4;
493 src.width = BRW_WIDTH_1;
494 src.hstride = BRW_HORIZONTAL_STRIDE_0;
495 assert(src.type == BRW_REGISTER_TYPE_UB);
496 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UB), src);
497 }
498
499 void
500 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
501 {
502 brw_barrier(p, src);
503 brw_WAIT(p);
504 }
505
506 void
507 fs_generator::generate_blorp_fb_write(fs_inst *inst)
508 {
509 brw_fb_WRITE(p,
510 16 /* dispatch_width */,
511 brw_message_reg(inst->base_mrf),
512 brw_reg_from_fs_reg(inst, &inst->src[0], devinfo->gen),
513 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
514 inst->target,
515 inst->mlen,
516 0,
517 true,
518 true,
519 inst->header_size != 0);
520 }
521
522 void
523 fs_generator::generate_linterp(fs_inst *inst,
524 struct brw_reg dst, struct brw_reg *src)
525 {
526 /* PLN reads:
527 * / in SIMD16 \
528 * -----------------------------------
529 * | src1+0 | src1+1 | src1+2 | src1+3 |
530 * |-----------------------------------|
531 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
532 * -----------------------------------
533 *
534 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
535 *
536 * -----------------------------------
537 * | src1+0 | src1+1 | src1+2 | src1+3 |
538 * |-----------------------------------|
539 * |(x0, x1)|(y0, y1)| | | in SIMD8
540 * |-----------------------------------|
541 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
542 * -----------------------------------
543 *
544 * See also: emit_interpolation_setup_gen4().
545 */
546 struct brw_reg delta_x = src[0];
547 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
548 struct brw_reg interp = src[1];
549
550 if (devinfo->has_pln &&
551 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
552 brw_PLN(p, dst, interp, delta_x);
553 } else {
554 brw_LINE(p, brw_null_reg(), interp, delta_x);
555 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
556 }
557 }
558
559 void
560 fs_generator::generate_math_gen6(fs_inst *inst,
561 struct brw_reg dst,
562 struct brw_reg src0,
563 struct brw_reg src1)
564 {
565 int op = brw_math_function(inst->opcode);
566 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
567
568 if (dispatch_width == 8) {
569 gen6_math(p, dst, op, src0, src1);
570 } else if (dispatch_width == 16) {
571 brw_push_insn_state(p);
572 brw_set_default_exec_size(p, BRW_EXECUTE_8);
573 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
574 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
575 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
576 gen6_math(p, sechalf(dst), op, sechalf(src0),
577 binop ? sechalf(src1) : brw_null_reg());
578 brw_pop_insn_state(p);
579 }
580 }
581
582 void
583 fs_generator::generate_math_gen4(fs_inst *inst,
584 struct brw_reg dst,
585 struct brw_reg src)
586 {
587 int op = brw_math_function(inst->opcode);
588
589 assert(inst->mlen >= 1);
590
591 if (dispatch_width == 8) {
592 gen4_math(p, dst,
593 op,
594 inst->base_mrf, src,
595 BRW_MATH_PRECISION_FULL);
596 } else if (dispatch_width == 16) {
597 brw_set_default_exec_size(p, BRW_EXECUTE_8);
598 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
599 gen4_math(p, firsthalf(dst),
600 op,
601 inst->base_mrf, firsthalf(src),
602 BRW_MATH_PRECISION_FULL);
603 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
604 gen4_math(p, sechalf(dst),
605 op,
606 inst->base_mrf + 1, sechalf(src),
607 BRW_MATH_PRECISION_FULL);
608
609 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
610 }
611 }
612
613 void
614 fs_generator::generate_math_g45(fs_inst *inst,
615 struct brw_reg dst,
616 struct brw_reg src)
617 {
618 if (inst->opcode == SHADER_OPCODE_POW ||
619 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
620 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
621 generate_math_gen4(inst, dst, src);
622 return;
623 }
624
625 int op = brw_math_function(inst->opcode);
626
627 assert(inst->mlen >= 1);
628
629 gen4_math(p, dst,
630 op,
631 inst->base_mrf, src,
632 BRW_MATH_PRECISION_FULL);
633 }
634
635 void
636 fs_generator::generate_get_buffer_size(fs_inst *inst,
637 struct brw_reg dst,
638 struct brw_reg src,
639 struct brw_reg surf_index)
640 {
641 assert(devinfo->gen >= 7);
642 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
643
644 uint32_t simd_mode;
645 int rlen = 4;
646
647 switch (inst->exec_size) {
648 case 8:
649 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
650 break;
651 case 16:
652 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
653 break;
654 default:
655 unreachable("Invalid width for texture instruction");
656 }
657
658 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
659 rlen = 8;
660 dst = vec16(dst);
661 }
662
663 brw_SAMPLE(p,
664 retype(dst, BRW_REGISTER_TYPE_UW),
665 inst->base_mrf,
666 src,
667 surf_index.ud,
668 0,
669 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
670 rlen, /* response length */
671 inst->mlen,
672 inst->header_size > 0,
673 simd_mode,
674 BRW_SAMPLER_RETURN_FORMAT_SINT32);
675
676 brw_mark_surface_used(prog_data, surf_index.ud);
677 }
678
679 void
680 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
681 struct brw_reg surface_index,
682 struct brw_reg sampler_index)
683 {
684 int msg_type = -1;
685 int rlen = 4;
686 uint32_t simd_mode;
687 uint32_t return_format;
688 bool is_combined_send = inst->eot;
689
690 switch (dst.type) {
691 case BRW_REGISTER_TYPE_D:
692 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
693 break;
694 case BRW_REGISTER_TYPE_UD:
695 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
696 break;
697 default:
698 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
699 break;
700 }
701
702 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
703 * is set as part of the message descriptor. On gen4, the PRM seems to
704 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
705 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
706 * gone from the message descriptor entirely and you just get UINT32 all
707 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
708 * just stomp it to UINT32 all the time.
709 */
710 if (inst->opcode == SHADER_OPCODE_TXS)
711 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
712
713 switch (inst->exec_size) {
714 case 8:
715 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
716 break;
717 case 16:
718 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
719 break;
720 default:
721 unreachable("Invalid width for texture instruction");
722 }
723
724 if (devinfo->gen >= 5) {
725 switch (inst->opcode) {
726 case SHADER_OPCODE_TEX:
727 if (inst->shadow_compare) {
728 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
729 } else {
730 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
731 }
732 break;
733 case FS_OPCODE_TXB:
734 if (inst->shadow_compare) {
735 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
736 } else {
737 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
738 }
739 break;
740 case SHADER_OPCODE_TXL:
741 if (inst->shadow_compare) {
742 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
743 } else {
744 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
745 }
746 break;
747 case SHADER_OPCODE_TXS:
748 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
749 break;
750 case SHADER_OPCODE_TXD:
751 if (inst->shadow_compare) {
752 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
753 assert(devinfo->gen >= 8 || devinfo->is_haswell);
754 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
755 } else {
756 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
757 }
758 break;
759 case SHADER_OPCODE_TXF:
760 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
761 break;
762 case SHADER_OPCODE_TXF_CMS_W:
763 assert(devinfo->gen >= 9);
764 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
765 break;
766 case SHADER_OPCODE_TXF_CMS:
767 if (devinfo->gen >= 7)
768 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
769 else
770 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
771 break;
772 case SHADER_OPCODE_TXF_UMS:
773 assert(devinfo->gen >= 7);
774 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
775 break;
776 case SHADER_OPCODE_TXF_MCS:
777 assert(devinfo->gen >= 7);
778 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
779 break;
780 case SHADER_OPCODE_LOD:
781 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
782 break;
783 case SHADER_OPCODE_TG4:
784 if (inst->shadow_compare) {
785 assert(devinfo->gen >= 7);
786 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
787 } else {
788 assert(devinfo->gen >= 6);
789 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
790 }
791 break;
792 case SHADER_OPCODE_TG4_OFFSET:
793 assert(devinfo->gen >= 7);
794 if (inst->shadow_compare) {
795 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
796 } else {
797 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
798 }
799 break;
800 case SHADER_OPCODE_SAMPLEINFO:
801 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
802 break;
803 default:
804 unreachable("not reached");
805 }
806 } else {
807 switch (inst->opcode) {
808 case SHADER_OPCODE_TEX:
809 /* Note that G45 and older determines shadow compare and dispatch width
810 * from message length for most messages.
811 */
812 if (inst->exec_size == 8) {
813 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
814 if (inst->shadow_compare) {
815 assert(inst->mlen == 6);
816 } else {
817 assert(inst->mlen <= 4);
818 }
819 } else {
820 if (inst->shadow_compare) {
821 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
822 assert(inst->mlen == 9);
823 } else {
824 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
825 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
826 }
827 }
828 break;
829 case FS_OPCODE_TXB:
830 if (inst->shadow_compare) {
831 assert(inst->exec_size == 8);
832 assert(inst->mlen == 6);
833 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
834 } else {
835 assert(inst->mlen == 9);
836 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
837 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
838 }
839 break;
840 case SHADER_OPCODE_TXL:
841 if (inst->shadow_compare) {
842 assert(inst->exec_size == 8);
843 assert(inst->mlen == 6);
844 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
845 } else {
846 assert(inst->mlen == 9);
847 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
848 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
849 }
850 break;
851 case SHADER_OPCODE_TXD:
852 /* There is no sample_d_c message; comparisons are done manually */
853 assert(inst->exec_size == 8);
854 assert(inst->mlen == 7 || inst->mlen == 10);
855 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
856 break;
857 case SHADER_OPCODE_TXF:
858 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
859 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
860 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
861 break;
862 case SHADER_OPCODE_TXS:
863 assert(inst->mlen == 3);
864 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
865 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
866 break;
867 default:
868 unreachable("not reached");
869 }
870 }
871 assert(msg_type != -1);
872
873 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
874 rlen = 8;
875 dst = vec16(dst);
876 }
877
878 if (is_combined_send) {
879 assert(devinfo->gen >= 9 || devinfo->is_cherryview);
880 rlen = 0;
881 }
882
883 assert(devinfo->gen < 7 || inst->header_size == 0 ||
884 src.file == BRW_GENERAL_REGISTER_FILE);
885
886 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
887
888 /* Load the message header if present. If there's a texture offset,
889 * we need to set it up explicitly and load the offset bitfield.
890 * Otherwise, we can use an implied move from g0 to the first message reg.
891 */
892 if (inst->header_size != 0) {
893 if (devinfo->gen < 6 && !inst->offset) {
894 /* Set up an implied move from g0 to the MRF. */
895 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
896 } else {
897 struct brw_reg header_reg;
898
899 if (devinfo->gen >= 7) {
900 header_reg = src;
901 } else {
902 assert(inst->base_mrf != -1);
903 header_reg = brw_message_reg(inst->base_mrf);
904 }
905
906 brw_push_insn_state(p);
907 brw_set_default_exec_size(p, BRW_EXECUTE_8);
908 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
909 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
910 /* Explicitly set up the message header by copying g0 to the MRF. */
911 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
912
913 if (inst->offset) {
914 /* Set the offset bits in DWord 2. */
915 brw_MOV(p, get_element_ud(header_reg, 2),
916 brw_imm_ud(inst->offset));
917 } else if (stage != MESA_SHADER_VERTEX &&
918 stage != MESA_SHADER_FRAGMENT) {
919 /* In the vertex and fragment stages, the hardware is nice to us
920 * and leaves g0.2 zerod out for us so we can use it for headers.
921 * However, in compute, geometry, and tessellation stages, the
922 * hardware is not so nice. In particular, for compute shaders on
923 * BDW, the hardware places some debug bits in 23:15. As it
924 * happens, bit 15 is the alpha channel mask. This means that if
925 * you use a texturing instruction with a header in a compute
926 * shader, you may randomly get the alpha channel randomly
927 * disabled. Since channel masks affect the return length of the
928 * sampler message, this can lead the GPU to expect a different
929 * mlen to the one you specified in the shader (probably 4 or 8)
930 * and this, in turn, hangs your GPU.
931 */
932 brw_MOV(p, get_element_ud(header_reg, 2), brw_imm_ud(0));
933 }
934
935 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
936 brw_pop_insn_state(p);
937 }
938 }
939
940 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
941 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
942 ? prog_data->binding_table.gather_texture_start
943 : prog_data->binding_table.texture_start;
944
945 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
946 sampler_index.file == BRW_IMMEDIATE_VALUE) {
947 uint32_t surface = surface_index.ud;
948 uint32_t sampler = sampler_index.ud;
949
950 brw_SAMPLE(p,
951 retype(dst, BRW_REGISTER_TYPE_UW),
952 inst->base_mrf,
953 src,
954 surface + base_binding_table_index,
955 sampler % 16,
956 msg_type,
957 rlen,
958 inst->mlen,
959 inst->header_size != 0,
960 simd_mode,
961 return_format);
962
963 brw_mark_surface_used(prog_data, surface + base_binding_table_index);
964 } else {
965 /* Non-const sampler index */
966
967 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
968 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
969 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
970
971 brw_push_insn_state(p);
972 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
973 brw_set_default_access_mode(p, BRW_ALIGN_1);
974
975 if (memcmp(&surface_reg, &sampler_reg, sizeof(surface_reg)) == 0) {
976 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
977 } else {
978 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
979 brw_OR(p, addr, addr, surface_reg);
980 }
981 if (base_binding_table_index)
982 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
983 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
984
985 brw_pop_insn_state(p);
986
987 /* dst = send(offset, a0.0 | <descriptor>) */
988 brw_inst *insn = brw_send_indirect_message(
989 p, BRW_SFID_SAMPLER, dst, src, addr);
990 brw_set_sampler_message(p, insn,
991 0 /* surface */,
992 0 /* sampler */,
993 msg_type,
994 rlen,
995 inst->mlen /* mlen */,
996 inst->header_size != 0 /* header */,
997 simd_mode,
998 return_format);
999
1000 /* visitor knows more than we do about the surface limit required,
1001 * so has already done marking.
1002 */
1003 }
1004
1005 if (is_combined_send) {
1006 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
1007 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
1008 }
1009 }
1010
1011
1012 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1013 * looking like:
1014 *
1015 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1016 *
1017 * Ideally, we want to produce:
1018 *
1019 * DDX DDY
1020 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1021 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1022 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1023 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1024 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1025 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1026 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1027 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1028 *
1029 * and add another set of two more subspans if in 16-pixel dispatch mode.
1030 *
1031 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1032 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1033 * pair. But the ideal approximation may impose a huge performance cost on
1034 * sample_d. On at least Haswell, sample_d instruction does some
1035 * optimizations if the same LOD is used for all pixels in the subspan.
1036 *
1037 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1038 * appropriate swizzling.
1039 */
1040 void
1041 fs_generator::generate_ddx(enum opcode opcode,
1042 struct brw_reg dst, struct brw_reg src)
1043 {
1044 unsigned vstride, width;
1045
1046 if (opcode == FS_OPCODE_DDX_FINE) {
1047 /* produce accurate derivatives */
1048 vstride = BRW_VERTICAL_STRIDE_2;
1049 width = BRW_WIDTH_2;
1050 } else {
1051 /* replicate the derivative at the top-left pixel to other pixels */
1052 vstride = BRW_VERTICAL_STRIDE_4;
1053 width = BRW_WIDTH_4;
1054 }
1055
1056 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
1057 src.negate, src.abs,
1058 BRW_REGISTER_TYPE_F,
1059 vstride,
1060 width,
1061 BRW_HORIZONTAL_STRIDE_0,
1062 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1063 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1064 src.negate, src.abs,
1065 BRW_REGISTER_TYPE_F,
1066 vstride,
1067 width,
1068 BRW_HORIZONTAL_STRIDE_0,
1069 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1070 brw_ADD(p, dst, src0, negate(src1));
1071 }
1072
1073 /* The negate_value boolean is used to negate the derivative computation for
1074 * FBOs, since they place the origin at the upper left instead of the lower
1075 * left.
1076 */
1077 void
1078 fs_generator::generate_ddy(enum opcode opcode,
1079 struct brw_reg dst, struct brw_reg src,
1080 bool negate_value)
1081 {
1082 if (opcode == FS_OPCODE_DDY_FINE) {
1083 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1084 * Region Restrictions):
1085 *
1086 * In Align16 access mode, SIMD16 is not allowed for DW operations
1087 * and SIMD8 is not allowed for DF operations.
1088 *
1089 * In this context, "DW operations" means "operations acting on 32-bit
1090 * values", so it includes operations on floats.
1091 *
1092 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1093 * (Instruction Compression -> Rules and Restrictions):
1094 *
1095 * A compressed instruction must be in Align1 access mode. Align16
1096 * mode instructions cannot be compressed.
1097 *
1098 * Similar text exists in the g45 PRM.
1099 *
1100 * On these platforms, if we're building a SIMD16 shader, we need to
1101 * manually unroll to a pair of SIMD8 instructions.
1102 */
1103 bool unroll_to_simd8 =
1104 (dispatch_width == 16 &&
1105 (devinfo->gen == 4 || (devinfo->gen == 7 && !devinfo->is_haswell)));
1106
1107 /* produce accurate derivatives */
1108 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1109 src.negate, src.abs,
1110 BRW_REGISTER_TYPE_F,
1111 BRW_VERTICAL_STRIDE_4,
1112 BRW_WIDTH_4,
1113 BRW_HORIZONTAL_STRIDE_1,
1114 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
1115 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1116 src.negate, src.abs,
1117 BRW_REGISTER_TYPE_F,
1118 BRW_VERTICAL_STRIDE_4,
1119 BRW_WIDTH_4,
1120 BRW_HORIZONTAL_STRIDE_1,
1121 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
1122 brw_push_insn_state(p);
1123 brw_set_default_access_mode(p, BRW_ALIGN_16);
1124 if (unroll_to_simd8) {
1125 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1126 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1127 if (negate_value) {
1128 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
1129 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1130 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
1131 } else {
1132 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
1133 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1134 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
1135 }
1136 } else {
1137 if (negate_value)
1138 brw_ADD(p, dst, src1, negate(src0));
1139 else
1140 brw_ADD(p, dst, src0, negate(src1));
1141 }
1142 brw_pop_insn_state(p);
1143 } else {
1144 /* replicate the derivative at the top-left pixel to other pixels */
1145 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1146 src.negate, src.abs,
1147 BRW_REGISTER_TYPE_F,
1148 BRW_VERTICAL_STRIDE_4,
1149 BRW_WIDTH_4,
1150 BRW_HORIZONTAL_STRIDE_0,
1151 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1152 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1153 src.negate, src.abs,
1154 BRW_REGISTER_TYPE_F,
1155 BRW_VERTICAL_STRIDE_4,
1156 BRW_WIDTH_4,
1157 BRW_HORIZONTAL_STRIDE_0,
1158 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1159 if (negate_value)
1160 brw_ADD(p, dst, src1, negate(src0));
1161 else
1162 brw_ADD(p, dst, src0, negate(src1));
1163 }
1164 }
1165
1166 void
1167 fs_generator::generate_discard_jump(fs_inst *inst)
1168 {
1169 assert(devinfo->gen >= 6);
1170
1171 /* This HALT will be patched up at FB write time to point UIP at the end of
1172 * the program, and at brw_uip_jip() JIP will be set to the end of the
1173 * current block (or the program).
1174 */
1175 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1176
1177 brw_push_insn_state(p);
1178 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1179 gen6_HALT(p);
1180 brw_pop_insn_state(p);
1181 }
1182
1183 void
1184 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1185 {
1186 assert(inst->mlen != 0);
1187
1188 brw_MOV(p,
1189 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1190 retype(src, BRW_REGISTER_TYPE_UD));
1191 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1192 inst->exec_size / 8, inst->offset);
1193 }
1194
1195 void
1196 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1197 {
1198 assert(inst->mlen != 0);
1199
1200 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1201 inst->exec_size / 8, inst->offset);
1202 }
1203
1204 void
1205 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1206 {
1207 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1208 }
1209
1210 void
1211 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1212 struct brw_reg dst,
1213 struct brw_reg index,
1214 struct brw_reg offset)
1215 {
1216 assert(inst->mlen != 0);
1217
1218 assert(index.file == BRW_IMMEDIATE_VALUE &&
1219 index.type == BRW_REGISTER_TYPE_UD);
1220 uint32_t surf_index = index.ud;
1221
1222 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1223 offset.type == BRW_REGISTER_TYPE_UD);
1224 uint32_t read_offset = offset.ud;
1225
1226 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1227 read_offset, surf_index);
1228 }
1229
1230 void
1231 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1232 struct brw_reg dst,
1233 struct brw_reg index,
1234 struct brw_reg offset)
1235 {
1236 assert(index.type == BRW_REGISTER_TYPE_UD);
1237
1238 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1239 /* Reference just the dword we need, to avoid angering validate_reg(). */
1240 offset = brw_vec1_grf(offset.nr, 0);
1241
1242 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1243 * the destination loaded consecutively from the same offset (which appears
1244 * in the first component, and the rest are ignored).
1245 */
1246 dst.width = BRW_WIDTH_4;
1247
1248 struct brw_reg src = offset;
1249 bool header_present = false;
1250
1251 if (devinfo->gen >= 9) {
1252 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1253 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1254 header_present = true;
1255
1256 brw_push_insn_state(p);
1257 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1258 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1259 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1260 brw_set_default_access_mode(p, BRW_ALIGN_1);
1261
1262 brw_MOV(p, get_element_ud(src, 2),
1263 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1264 brw_pop_insn_state(p);
1265 }
1266
1267 if (index.file == BRW_IMMEDIATE_VALUE) {
1268
1269 uint32_t surf_index = index.ud;
1270
1271 brw_push_insn_state(p);
1272 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1273 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1274 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1275 brw_pop_insn_state(p);
1276
1277 brw_set_dest(p, send, dst);
1278 brw_set_src0(p, send, src);
1279 brw_set_sampler_message(p, send,
1280 surf_index,
1281 0, /* LD message ignores sampler unit */
1282 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1283 1, /* rlen */
1284 inst->mlen,
1285 header_present,
1286 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1287 0);
1288 } else {
1289
1290 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1291
1292 brw_push_insn_state(p);
1293 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1294 brw_set_default_access_mode(p, BRW_ALIGN_1);
1295
1296 /* a0.0 = surf_index & 0xff */
1297 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1298 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1299 brw_set_dest(p, insn_and, addr);
1300 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1301 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1302
1303 /* dst = send(payload, a0.0 | <descriptor>) */
1304 brw_inst *insn = brw_send_indirect_message(
1305 p, BRW_SFID_SAMPLER, dst, src, addr);
1306 brw_set_sampler_message(p, insn,
1307 0,
1308 0, /* LD message ignores sampler unit */
1309 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1310 1, /* rlen */
1311 inst->mlen,
1312 header_present,
1313 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1314 0);
1315
1316 brw_pop_insn_state(p);
1317 }
1318 }
1319
1320 void
1321 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1322 struct brw_reg dst,
1323 struct brw_reg index,
1324 struct brw_reg offset)
1325 {
1326 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1327 assert(inst->header_size != 0);
1328 assert(inst->mlen);
1329
1330 assert(index.file == BRW_IMMEDIATE_VALUE &&
1331 index.type == BRW_REGISTER_TYPE_UD);
1332 uint32_t surf_index = index.ud;
1333
1334 uint32_t simd_mode, rlen, msg_type;
1335 if (dispatch_width == 16) {
1336 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1337 rlen = 8;
1338 } else {
1339 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1340 rlen = 4;
1341 }
1342
1343 if (devinfo->gen >= 5)
1344 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1345 else {
1346 /* We always use the SIMD16 message so that we only have to load U, and
1347 * not V or R.
1348 */
1349 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1350 assert(inst->mlen == 3);
1351 assert(inst->regs_written == 8);
1352 rlen = 8;
1353 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1354 }
1355
1356 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1357 BRW_REGISTER_TYPE_D);
1358 brw_MOV(p, offset_mrf, offset);
1359
1360 struct brw_reg header = brw_vec8_grf(0, 0);
1361 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1362
1363 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1364 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1365 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1366 brw_set_src0(p, send, header);
1367 if (devinfo->gen < 6)
1368 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1369
1370 /* Our surface is set up as floats, regardless of what actual data is
1371 * stored in it.
1372 */
1373 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1374 brw_set_sampler_message(p, send,
1375 surf_index,
1376 0, /* sampler (unused) */
1377 msg_type,
1378 rlen,
1379 inst->mlen,
1380 inst->header_size != 0,
1381 simd_mode,
1382 return_format);
1383 }
1384
1385 void
1386 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1387 struct brw_reg dst,
1388 struct brw_reg index,
1389 struct brw_reg offset)
1390 {
1391 assert(devinfo->gen >= 7);
1392 /* Varying-offset pull constant loads are treated as a normal expression on
1393 * gen7, so the fact that it's a send message is hidden at the IR level.
1394 */
1395 assert(inst->header_size == 0);
1396 assert(!inst->mlen);
1397 assert(index.type == BRW_REGISTER_TYPE_UD);
1398
1399 uint32_t simd_mode, rlen, mlen;
1400 if (dispatch_width == 16) {
1401 mlen = 2;
1402 rlen = 8;
1403 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1404 } else {
1405 mlen = 1;
1406 rlen = 4;
1407 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1408 }
1409
1410 if (index.file == BRW_IMMEDIATE_VALUE) {
1411
1412 uint32_t surf_index = index.ud;
1413
1414 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1415 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1416 brw_set_src0(p, send, offset);
1417 brw_set_sampler_message(p, send,
1418 surf_index,
1419 0, /* LD message ignores sampler unit */
1420 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1421 rlen,
1422 mlen,
1423 false, /* no header */
1424 simd_mode,
1425 0);
1426
1427 } else {
1428
1429 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1430
1431 brw_push_insn_state(p);
1432 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1433 brw_set_default_access_mode(p, BRW_ALIGN_1);
1434
1435 /* a0.0 = surf_index & 0xff */
1436 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1437 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1438 brw_set_dest(p, insn_and, addr);
1439 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1440 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1441
1442 brw_pop_insn_state(p);
1443
1444 /* dst = send(offset, a0.0 | <descriptor>) */
1445 brw_inst *insn = brw_send_indirect_message(
1446 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1447 offset, addr);
1448 brw_set_sampler_message(p, insn,
1449 0 /* surface */,
1450 0 /* sampler */,
1451 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1452 rlen /* rlen */,
1453 mlen /* mlen */,
1454 false /* header */,
1455 simd_mode,
1456 0);
1457 }
1458 }
1459
1460 /**
1461 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1462 * into the flags register (f0.0).
1463 *
1464 * Used only on Gen6 and above.
1465 */
1466 void
1467 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1468 {
1469 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1470 struct brw_reg dispatch_mask;
1471
1472 if (devinfo->gen >= 6)
1473 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1474 else
1475 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1476
1477 brw_push_insn_state(p);
1478 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1479 brw_MOV(p, flags, dispatch_mask);
1480 brw_pop_insn_state(p);
1481 }
1482
1483 void
1484 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1485 struct brw_reg dst,
1486 struct brw_reg src,
1487 struct brw_reg msg_data,
1488 unsigned msg_type)
1489 {
1490 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1491
1492 brw_pixel_interpolator_query(p,
1493 retype(dst, BRW_REGISTER_TYPE_UW),
1494 src,
1495 inst->pi_noperspective,
1496 msg_type,
1497 msg_data,
1498 inst->mlen,
1499 inst->regs_written);
1500 }
1501
1502
1503 /**
1504 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1505 * sampler LD messages.
1506 *
1507 * We don't want to bake it into the send message's code generation because
1508 * that means we don't get a chance to schedule the instructions.
1509 */
1510 void
1511 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1512 struct brw_reg dst,
1513 struct brw_reg value)
1514 {
1515 assert(value.file == BRW_IMMEDIATE_VALUE);
1516
1517 brw_push_insn_state(p);
1518 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1519 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1520 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1521 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1522 brw_pop_insn_state(p);
1523 }
1524
1525 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1526 * the ADD instruction.
1527 */
1528 void
1529 fs_generator::generate_set_sample_id(fs_inst *inst,
1530 struct brw_reg dst,
1531 struct brw_reg src0,
1532 struct brw_reg src1)
1533 {
1534 assert(dst.type == BRW_REGISTER_TYPE_D ||
1535 dst.type == BRW_REGISTER_TYPE_UD);
1536 assert(src0.type == BRW_REGISTER_TYPE_D ||
1537 src0.type == BRW_REGISTER_TYPE_UD);
1538
1539 struct brw_reg reg = stride(src1, 1, 4, 0);
1540 if (devinfo->gen >= 8 || dispatch_width == 8) {
1541 brw_ADD(p, dst, src0, reg);
1542 } else if (dispatch_width == 16) {
1543 brw_push_insn_state(p);
1544 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1545 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1546 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1547 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1548 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1549 brw_pop_insn_state(p);
1550 }
1551 }
1552
1553 void
1554 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1555 struct brw_reg dst,
1556 struct brw_reg x,
1557 struct brw_reg y)
1558 {
1559 assert(devinfo->gen >= 7);
1560 assert(dst.type == BRW_REGISTER_TYPE_UD);
1561 assert(x.type == BRW_REGISTER_TYPE_F);
1562 assert(y.type == BRW_REGISTER_TYPE_F);
1563
1564 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1565 *
1566 * Because this instruction does not have a 16-bit floating-point type,
1567 * the destination data type must be Word (W).
1568 *
1569 * The destination must be DWord-aligned and specify a horizontal stride
1570 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1571 * each destination channel and the upper word is not modified.
1572 */
1573 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1574
1575 /* Give each 32-bit channel of dst the form below, where "." means
1576 * unchanged.
1577 * 0x....hhhh
1578 */
1579 brw_F32TO16(p, dst_w, y);
1580
1581 /* Now the form:
1582 * 0xhhhh0000
1583 */
1584 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1585
1586 /* And, finally the form of packHalf2x16's output:
1587 * 0xhhhhllll
1588 */
1589 brw_F32TO16(p, dst_w, x);
1590 }
1591
1592 void
1593 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1594 struct brw_reg dst,
1595 struct brw_reg src)
1596 {
1597 assert(devinfo->gen >= 7);
1598 assert(dst.type == BRW_REGISTER_TYPE_F);
1599 assert(src.type == BRW_REGISTER_TYPE_UD);
1600
1601 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1602 *
1603 * Because this instruction does not have a 16-bit floating-point type,
1604 * the source data type must be Word (W). The destination type must be
1605 * F (Float).
1606 */
1607 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1608
1609 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1610 * For the Y case, we wish to access only the upper word; therefore
1611 * a 16-bit subregister offset is needed.
1612 */
1613 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1614 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1615 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1616 src_w.subnr += 2;
1617
1618 brw_F16TO32(p, dst, src_w);
1619 }
1620
1621 void
1622 fs_generator::generate_shader_time_add(fs_inst *inst,
1623 struct brw_reg payload,
1624 struct brw_reg offset,
1625 struct brw_reg value)
1626 {
1627 assert(devinfo->gen >= 7);
1628 brw_push_insn_state(p);
1629 brw_set_default_mask_control(p, true);
1630
1631 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1632 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1633 offset.type);
1634 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1635 value.type);
1636
1637 assert(offset.file == BRW_IMMEDIATE_VALUE);
1638 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1639 value.width = BRW_WIDTH_1;
1640 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1641 value.vstride = BRW_VERTICAL_STRIDE_0;
1642 } else {
1643 assert(value.file == BRW_IMMEDIATE_VALUE);
1644 }
1645
1646 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1647 * case, and we don't really care about squeezing every bit of performance
1648 * out of this path, so we just emit the MOVs from here.
1649 */
1650 brw_MOV(p, payload_offset, offset);
1651 brw_MOV(p, payload_value, value);
1652 brw_shader_time_add(p, payload,
1653 prog_data->binding_table.shader_time_start);
1654 brw_pop_insn_state(p);
1655
1656 brw_mark_surface_used(prog_data,
1657 prog_data->binding_table.shader_time_start);
1658 }
1659
1660 void
1661 fs_generator::enable_debug(const char *shader_name)
1662 {
1663 debug_flag = true;
1664 this->shader_name = shader_name;
1665 }
1666
1667 int
1668 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1669 {
1670 /* align to 64 byte boundary. */
1671 while (p->next_insn_offset % 64)
1672 brw_NOP(p);
1673
1674 this->dispatch_width = dispatch_width;
1675 if (dispatch_width == 16)
1676 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1677
1678 int start_offset = p->next_insn_offset;
1679 int spill_count = 0, fill_count = 0;
1680 int loop_count = 0;
1681
1682 struct annotation_info annotation;
1683 memset(&annotation, 0, sizeof(annotation));
1684
1685 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1686 struct brw_reg src[3], dst;
1687 unsigned int last_insn_offset = p->next_insn_offset;
1688 bool multiple_instructions_emitted = false;
1689
1690 if (unlikely(debug_flag))
1691 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1692
1693 for (unsigned int i = 0; i < inst->sources; i++) {
1694 src[i] = brw_reg_from_fs_reg(inst, &inst->src[i], devinfo->gen);
1695
1696 /* The accumulator result appears to get used for the
1697 * conditional modifier generation. When negating a UD
1698 * value, there is a 33rd bit generated for the sign in the
1699 * accumulator value, so now you can't check, for example,
1700 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1701 */
1702 assert(!inst->conditional_mod ||
1703 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1704 !inst->src[i].negate);
1705 }
1706 dst = brw_reg_from_fs_reg(inst, &inst->dst, devinfo->gen);
1707
1708 brw_set_default_predicate_control(p, inst->predicate);
1709 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1710 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1711 brw_set_default_saturate(p, inst->saturate);
1712 brw_set_default_mask_control(p, inst->force_writemask_all);
1713 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1714 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1715
1716 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1717 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1718
1719 switch (inst->exec_size) {
1720 case 1:
1721 case 2:
1722 case 4:
1723 assert(inst->force_writemask_all);
1724 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1725 break;
1726 case 8:
1727 if (inst->force_sechalf) {
1728 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1729 } else {
1730 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1731 }
1732 break;
1733 case 16:
1734 case 32:
1735 /* If the instruction writes to more than one register, it needs to
1736 * be a "compressed" instruction on Gen <= 5.
1737 */
1738 if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
1739 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1740 else
1741 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1742 break;
1743 default:
1744 unreachable("Invalid instruction width");
1745 }
1746
1747 switch (inst->opcode) {
1748 case BRW_OPCODE_MOV:
1749 brw_MOV(p, dst, src[0]);
1750 break;
1751 case BRW_OPCODE_ADD:
1752 brw_ADD(p, dst, src[0], src[1]);
1753 break;
1754 case BRW_OPCODE_MUL:
1755 brw_MUL(p, dst, src[0], src[1]);
1756 break;
1757 case BRW_OPCODE_AVG:
1758 brw_AVG(p, dst, src[0], src[1]);
1759 break;
1760 case BRW_OPCODE_MACH:
1761 brw_MACH(p, dst, src[0], src[1]);
1762 break;
1763
1764 case BRW_OPCODE_LINE:
1765 brw_LINE(p, dst, src[0], src[1]);
1766 break;
1767
1768 case BRW_OPCODE_MAD:
1769 assert(devinfo->gen >= 6);
1770 brw_set_default_access_mode(p, BRW_ALIGN_16);
1771 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1772 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1773 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1774 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1775 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1776 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1777 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1778
1779 if (inst->conditional_mod) {
1780 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1781 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1782 multiple_instructions_emitted = true;
1783 }
1784 } else {
1785 brw_MAD(p, dst, src[0], src[1], src[2]);
1786 }
1787 brw_set_default_access_mode(p, BRW_ALIGN_1);
1788 break;
1789
1790 case BRW_OPCODE_LRP:
1791 assert(devinfo->gen >= 6);
1792 brw_set_default_access_mode(p, BRW_ALIGN_16);
1793 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1794 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1795 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1796 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1797 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1798 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1799 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1800
1801 if (inst->conditional_mod) {
1802 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1803 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1804 multiple_instructions_emitted = true;
1805 }
1806 } else {
1807 brw_LRP(p, dst, src[0], src[1], src[2]);
1808 }
1809 brw_set_default_access_mode(p, BRW_ALIGN_1);
1810 break;
1811
1812 case BRW_OPCODE_FRC:
1813 brw_FRC(p, dst, src[0]);
1814 break;
1815 case BRW_OPCODE_RNDD:
1816 brw_RNDD(p, dst, src[0]);
1817 break;
1818 case BRW_OPCODE_RNDE:
1819 brw_RNDE(p, dst, src[0]);
1820 break;
1821 case BRW_OPCODE_RNDZ:
1822 brw_RNDZ(p, dst, src[0]);
1823 break;
1824
1825 case BRW_OPCODE_AND:
1826 brw_AND(p, dst, src[0], src[1]);
1827 break;
1828 case BRW_OPCODE_OR:
1829 brw_OR(p, dst, src[0], src[1]);
1830 break;
1831 case BRW_OPCODE_XOR:
1832 brw_XOR(p, dst, src[0], src[1]);
1833 break;
1834 case BRW_OPCODE_NOT:
1835 brw_NOT(p, dst, src[0]);
1836 break;
1837 case BRW_OPCODE_ASR:
1838 brw_ASR(p, dst, src[0], src[1]);
1839 break;
1840 case BRW_OPCODE_SHR:
1841 brw_SHR(p, dst, src[0], src[1]);
1842 break;
1843 case BRW_OPCODE_SHL:
1844 brw_SHL(p, dst, src[0], src[1]);
1845 break;
1846 case BRW_OPCODE_F32TO16:
1847 assert(devinfo->gen >= 7);
1848 brw_F32TO16(p, dst, src[0]);
1849 break;
1850 case BRW_OPCODE_F16TO32:
1851 assert(devinfo->gen >= 7);
1852 brw_F16TO32(p, dst, src[0]);
1853 break;
1854 case BRW_OPCODE_CMP:
1855 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1856 * that when the destination is a GRF that the dependency-clear bit on
1857 * the flag register is cleared early.
1858 *
1859 * Suggested workarounds are to disable coissuing CMP instructions
1860 * or to split CMP(16) instructions into two CMP(8) instructions.
1861 *
1862 * We choose to split into CMP(8) instructions since disabling
1863 * coissuing would affect CMP instructions not otherwise affected by
1864 * the errata.
1865 */
1866 if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) {
1867 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1868 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1869 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1870 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1871 firsthalf(src[0]), firsthalf(src[1]));
1872 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1873 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1874 sechalf(src[0]), sechalf(src[1]));
1875 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1876
1877 multiple_instructions_emitted = true;
1878 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1879 /* For unknown reasons, the aforementioned workaround is not
1880 * sufficient. Overriding the type when the destination is the
1881 * null register is necessary but not sufficient by itself.
1882 */
1883 assert(dst.nr == BRW_ARF_NULL);
1884 dst.type = BRW_REGISTER_TYPE_D;
1885 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1886 } else {
1887 unreachable("not reached");
1888 }
1889 } else {
1890 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1891 }
1892 break;
1893 case BRW_OPCODE_SEL:
1894 brw_SEL(p, dst, src[0], src[1]);
1895 break;
1896 case BRW_OPCODE_BFREV:
1897 assert(devinfo->gen >= 7);
1898 /* BFREV only supports UD type for src and dst. */
1899 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1900 retype(src[0], BRW_REGISTER_TYPE_UD));
1901 break;
1902 case BRW_OPCODE_FBH:
1903 assert(devinfo->gen >= 7);
1904 /* FBH only supports UD type for dst. */
1905 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1906 break;
1907 case BRW_OPCODE_FBL:
1908 assert(devinfo->gen >= 7);
1909 /* FBL only supports UD type for dst. */
1910 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1911 break;
1912 case BRW_OPCODE_CBIT:
1913 assert(devinfo->gen >= 7);
1914 /* CBIT only supports UD type for dst. */
1915 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1916 break;
1917 case BRW_OPCODE_ADDC:
1918 assert(devinfo->gen >= 7);
1919 brw_ADDC(p, dst, src[0], src[1]);
1920 break;
1921 case BRW_OPCODE_SUBB:
1922 assert(devinfo->gen >= 7);
1923 brw_SUBB(p, dst, src[0], src[1]);
1924 break;
1925 case BRW_OPCODE_MAC:
1926 brw_MAC(p, dst, src[0], src[1]);
1927 break;
1928
1929 case BRW_OPCODE_BFE:
1930 assert(devinfo->gen >= 7);
1931 brw_set_default_access_mode(p, BRW_ALIGN_16);
1932 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1933 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1934 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1935 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1936 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1937 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1938 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1939 } else {
1940 brw_BFE(p, dst, src[0], src[1], src[2]);
1941 }
1942 brw_set_default_access_mode(p, BRW_ALIGN_1);
1943 break;
1944
1945 case BRW_OPCODE_BFI1:
1946 assert(devinfo->gen >= 7);
1947 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1948 * should
1949 *
1950 * "Force BFI instructions to be executed always in SIMD8."
1951 */
1952 if (dispatch_width == 16 && devinfo->is_haswell) {
1953 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1954 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1955 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1956 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1957 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1958 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1959 } else {
1960 brw_BFI1(p, dst, src[0], src[1]);
1961 }
1962 break;
1963 case BRW_OPCODE_BFI2:
1964 assert(devinfo->gen >= 7);
1965 brw_set_default_access_mode(p, BRW_ALIGN_16);
1966 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1967 * should
1968 *
1969 * "Force BFI instructions to be executed always in SIMD8."
1970 *
1971 * Otherwise we would be able to emit compressed instructions like we
1972 * do for the other three-source instructions.
1973 */
1974 if (dispatch_width == 16 &&
1975 (devinfo->is_haswell || !devinfo->supports_simd16_3src)) {
1976 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1977 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1978 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1979 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1980 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1981 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1982 } else {
1983 brw_BFI2(p, dst, src[0], src[1], src[2]);
1984 }
1985 brw_set_default_access_mode(p, BRW_ALIGN_1);
1986 break;
1987
1988 case BRW_OPCODE_IF:
1989 if (inst->src[0].file != BAD_FILE) {
1990 /* The instruction has an embedded compare (only allowed on gen6) */
1991 assert(devinfo->gen == 6);
1992 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1993 } else {
1994 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1995 }
1996 break;
1997
1998 case BRW_OPCODE_ELSE:
1999 brw_ELSE(p);
2000 break;
2001 case BRW_OPCODE_ENDIF:
2002 brw_ENDIF(p);
2003 break;
2004
2005 case BRW_OPCODE_DO:
2006 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
2007 break;
2008
2009 case BRW_OPCODE_BREAK:
2010 brw_BREAK(p);
2011 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2012 break;
2013 case BRW_OPCODE_CONTINUE:
2014 brw_CONT(p);
2015 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2016 break;
2017
2018 case BRW_OPCODE_WHILE:
2019 brw_WHILE(p);
2020 loop_count++;
2021 break;
2022
2023 case SHADER_OPCODE_RCP:
2024 case SHADER_OPCODE_RSQ:
2025 case SHADER_OPCODE_SQRT:
2026 case SHADER_OPCODE_EXP2:
2027 case SHADER_OPCODE_LOG2:
2028 case SHADER_OPCODE_SIN:
2029 case SHADER_OPCODE_COS:
2030 assert(devinfo->gen < 6 || inst->mlen == 0);
2031 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2032 if (devinfo->gen >= 7) {
2033 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
2034 brw_null_reg());
2035 } else if (devinfo->gen == 6) {
2036 generate_math_gen6(inst, dst, src[0], brw_null_reg());
2037 } else if (devinfo->gen == 5 || devinfo->is_g4x) {
2038 generate_math_g45(inst, dst, src[0]);
2039 } else {
2040 generate_math_gen4(inst, dst, src[0]);
2041 }
2042 break;
2043 case SHADER_OPCODE_INT_QUOTIENT:
2044 case SHADER_OPCODE_INT_REMAINDER:
2045 case SHADER_OPCODE_POW:
2046 assert(devinfo->gen < 6 || inst->mlen == 0);
2047 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2048 if (devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
2049 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
2050 } else if (devinfo->gen >= 6) {
2051 generate_math_gen6(inst, dst, src[0], src[1]);
2052 } else {
2053 generate_math_gen4(inst, dst, src[0]);
2054 }
2055 break;
2056 case FS_OPCODE_CINTERP:
2057 brw_MOV(p, dst, src[0]);
2058 break;
2059 case FS_OPCODE_LINTERP:
2060 generate_linterp(inst, dst, src);
2061 break;
2062 case FS_OPCODE_PIXEL_X:
2063 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2064 src[0].subnr = 0 * type_sz(src[0].type);
2065 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2066 break;
2067 case FS_OPCODE_PIXEL_Y:
2068 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2069 src[0].subnr = 4 * type_sz(src[0].type);
2070 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2071 break;
2072 case FS_OPCODE_GET_BUFFER_SIZE:
2073 generate_get_buffer_size(inst, dst, src[0], src[1]);
2074 break;
2075 case SHADER_OPCODE_TEX:
2076 case FS_OPCODE_TXB:
2077 case SHADER_OPCODE_TXD:
2078 case SHADER_OPCODE_TXF:
2079 case SHADER_OPCODE_TXF_CMS:
2080 case SHADER_OPCODE_TXF_CMS_W:
2081 case SHADER_OPCODE_TXF_UMS:
2082 case SHADER_OPCODE_TXF_MCS:
2083 case SHADER_OPCODE_TXL:
2084 case SHADER_OPCODE_TXS:
2085 case SHADER_OPCODE_LOD:
2086 case SHADER_OPCODE_TG4:
2087 case SHADER_OPCODE_TG4_OFFSET:
2088 case SHADER_OPCODE_SAMPLEINFO:
2089 generate_tex(inst, dst, src[0], src[1], src[2]);
2090 break;
2091 case FS_OPCODE_DDX_COARSE:
2092 case FS_OPCODE_DDX_FINE:
2093 generate_ddx(inst->opcode, dst, src[0]);
2094 break;
2095 case FS_OPCODE_DDY_COARSE:
2096 case FS_OPCODE_DDY_FINE:
2097 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2098 generate_ddy(inst->opcode, dst, src[0], src[1].ud);
2099 break;
2100
2101 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
2102 generate_scratch_write(inst, src[0]);
2103 spill_count++;
2104 break;
2105
2106 case SHADER_OPCODE_GEN4_SCRATCH_READ:
2107 generate_scratch_read(inst, dst);
2108 fill_count++;
2109 break;
2110
2111 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2112 generate_scratch_read_gen7(inst, dst);
2113 fill_count++;
2114 break;
2115
2116 case SHADER_OPCODE_MOV_INDIRECT:
2117 generate_mov_indirect(inst, dst, src[0], src[1]);
2118 break;
2119
2120 case SHADER_OPCODE_URB_READ_SIMD8:
2121 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
2122 generate_urb_read(inst, dst, src[0]);
2123 break;
2124
2125 case SHADER_OPCODE_URB_WRITE_SIMD8:
2126 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
2127 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
2128 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
2129 generate_urb_write(inst, src[0]);
2130 break;
2131
2132 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2133 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2134 break;
2135
2136 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2137 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2138 break;
2139
2140 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
2141 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
2142 break;
2143
2144 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2145 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2146 break;
2147
2148 case FS_OPCODE_REP_FB_WRITE:
2149 case FS_OPCODE_FB_WRITE:
2150 generate_fb_write(inst, src[0]);
2151 break;
2152
2153 case FS_OPCODE_BLORP_FB_WRITE:
2154 generate_blorp_fb_write(inst);
2155 break;
2156
2157 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2158 generate_mov_dispatch_to_flags(inst);
2159 break;
2160
2161 case FS_OPCODE_DISCARD_JUMP:
2162 generate_discard_jump(inst);
2163 break;
2164
2165 case SHADER_OPCODE_SHADER_TIME_ADD:
2166 generate_shader_time_add(inst, src[0], src[1], src[2]);
2167 break;
2168
2169 case SHADER_OPCODE_UNTYPED_ATOMIC:
2170 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2171 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
2172 inst->mlen, !inst->dst.is_null());
2173 break;
2174
2175 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2176 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2177 brw_untyped_surface_read(p, dst, src[0], src[1],
2178 inst->mlen, src[2].ud);
2179 break;
2180
2181 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2182 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2183 brw_untyped_surface_write(p, src[0], src[1],
2184 inst->mlen, src[2].ud);
2185 break;
2186
2187 case SHADER_OPCODE_TYPED_ATOMIC:
2188 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2189 brw_typed_atomic(p, dst, src[0], src[1],
2190 src[2].ud, inst->mlen, !inst->dst.is_null());
2191 break;
2192
2193 case SHADER_OPCODE_TYPED_SURFACE_READ:
2194 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2195 brw_typed_surface_read(p, dst, src[0], src[1],
2196 inst->mlen, src[2].ud);
2197 break;
2198
2199 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2200 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2201 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud);
2202 break;
2203
2204 case SHADER_OPCODE_MEMORY_FENCE:
2205 brw_memory_fence(p, dst);
2206 break;
2207
2208 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2209 generate_set_simd4x2_offset(inst, dst, src[0]);
2210 break;
2211
2212 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
2213 brw_find_live_channel(p, dst);
2214 break;
2215
2216 case SHADER_OPCODE_BROADCAST:
2217 brw_broadcast(p, dst, src[0], src[1]);
2218 break;
2219
2220 case FS_OPCODE_SET_SAMPLE_ID:
2221 generate_set_sample_id(inst, dst, src[0], src[1]);
2222 break;
2223
2224 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2225 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2226 break;
2227
2228 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2229 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2230 generate_unpack_half_2x16_split(inst, dst, src[0]);
2231 break;
2232
2233 case FS_OPCODE_PLACEHOLDER_HALT:
2234 /* This is the place where the final HALT needs to be inserted if
2235 * we've emitted any discards. If not, this will emit no code.
2236 */
2237 if (!patch_discard_jumps_to_fb_writes()) {
2238 if (unlikely(debug_flag)) {
2239 annotation.ann_count--;
2240 }
2241 }
2242 break;
2243
2244 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2245 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2246 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2247 break;
2248
2249 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2250 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2251 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2252 break;
2253
2254 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2255 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2256 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2257 break;
2258
2259 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2260 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2261 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2262 break;
2263
2264 case CS_OPCODE_CS_TERMINATE:
2265 generate_cs_terminate(inst, src[0]);
2266 break;
2267
2268 case SHADER_OPCODE_BARRIER:
2269 generate_barrier(inst, src[0]);
2270 break;
2271
2272 case FS_OPCODE_PACK_STENCIL_REF:
2273 generate_stencil_ref_packing(inst, dst, src[0]);
2274 break;
2275
2276 default:
2277 unreachable("Unsupported opcode");
2278
2279 case SHADER_OPCODE_LOAD_PAYLOAD:
2280 unreachable("Should be lowered by lower_load_payload()");
2281 }
2282
2283 if (multiple_instructions_emitted)
2284 continue;
2285
2286 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2287 assert(p->next_insn_offset == last_insn_offset + 16 ||
2288 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2289 "emitting more than 1 instruction");
2290
2291 brw_inst *last = &p->store[last_insn_offset / 16];
2292
2293 if (inst->conditional_mod)
2294 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2295 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2296 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2297 }
2298 }
2299
2300 brw_set_uip_jip(p);
2301 annotation_finalize(&annotation, p->next_insn_offset);
2302
2303 #ifndef NDEBUG
2304 bool validated = brw_validate_instructions(p, start_offset, &annotation);
2305 #else
2306 if (unlikely(debug_flag))
2307 brw_validate_instructions(p, start_offset, &annotation);
2308 #endif
2309
2310 int before_size = p->next_insn_offset - start_offset;
2311 brw_compact_instructions(p, start_offset, annotation.ann_count,
2312 annotation.ann);
2313 int after_size = p->next_insn_offset - start_offset;
2314
2315 if (unlikely(debug_flag)) {
2316 fprintf(stderr, "Native code for %s\n"
2317 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2318 " bytes (%.0f%%)\n",
2319 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2320 spill_count, fill_count, promoted_constants, before_size, after_size,
2321 100.0f * (before_size - after_size) / before_size);
2322
2323 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2324 p->devinfo);
2325 ralloc_free(annotation.mem_ctx);
2326 }
2327 assert(validated);
2328
2329 compiler->shader_debug_log(log_data,
2330 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2331 "%d:%d spills:fills, Promoted %u constants, "
2332 "compacted %d to %d bytes.",
2333 _mesa_shader_stage_to_abbrev(stage),
2334 dispatch_width, before_size / 16,
2335 loop_count, cfg->cycle_count, spill_count,
2336 fill_count, promoted_constants, before_size,
2337 after_size);
2338
2339 return start_offset;
2340 }
2341
2342 const unsigned *
2343 fs_generator::get_assembly(unsigned int *assembly_size)
2344 {
2345 return brw_get_program(p, assembly_size);
2346 }