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i965/skl: Break down SIMD16 3-source instructions when required.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "main/macros.h"
31 #include "brw_context.h"
32 #include "brw_eu.h"
33 #include "brw_fs.h"
34 #include "brw_cfg.h"
35
36 static uint32_t brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case GRF:
40 return BRW_GENERAL_REGISTER_FILE;
41 case MRF:
42 return BRW_MESSAGE_REGISTER_FILE;
43 case IMM:
44 return BRW_IMMEDIATE_VALUE;
45 default:
46 unreachable("not reached");
47 }
48 }
49
50 static struct brw_reg
51 brw_reg_from_fs_reg(fs_reg *reg)
52 {
53 struct brw_reg brw_reg;
54
55 switch (reg->file) {
56 case GRF:
57 case MRF:
58 if (reg->stride == 0) {
59 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
60 } else if (reg->width < 8) {
61 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
62 brw_reg = stride(brw_reg, reg->width * reg->stride,
63 reg->width, reg->stride);
64 } else {
65 /* From the Haswell PRM:
66 *
67 * VertStride must be used to cross GRF register boundaries. This
68 * rule implies that elements within a 'Width' cannot cross GRF
69 * boundaries.
70 *
71 * So, for registers with width > 8, we have to use a width of 8
72 * and trust the compression state to sort out the exec size.
73 */
74 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
75 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
76 }
77
78 brw_reg = retype(brw_reg, reg->type);
79 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
80 break;
81 case IMM:
82 switch (reg->type) {
83 case BRW_REGISTER_TYPE_F:
84 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
85 break;
86 case BRW_REGISTER_TYPE_D:
87 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
88 break;
89 case BRW_REGISTER_TYPE_UD:
90 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
91 break;
92 case BRW_REGISTER_TYPE_W:
93 brw_reg = brw_imm_w(reg->fixed_hw_reg.dw1.d);
94 break;
95 case BRW_REGISTER_TYPE_UW:
96 brw_reg = brw_imm_uw(reg->fixed_hw_reg.dw1.ud);
97 break;
98 case BRW_REGISTER_TYPE_VF:
99 brw_reg = brw_imm_vf(reg->fixed_hw_reg.dw1.ud);
100 break;
101 default:
102 unreachable("not reached");
103 }
104 break;
105 case HW_REG:
106 assert(reg->type == reg->fixed_hw_reg.type);
107 brw_reg = reg->fixed_hw_reg;
108 break;
109 case BAD_FILE:
110 /* Probably unused. */
111 brw_reg = brw_null_reg();
112 break;
113 default:
114 unreachable("not reached");
115 }
116 if (reg->abs)
117 brw_reg = brw_abs(brw_reg);
118 if (reg->negate)
119 brw_reg = negate(brw_reg);
120
121 return brw_reg;
122 }
123
124 fs_generator::fs_generator(struct brw_context *brw,
125 void *mem_ctx,
126 const void *key,
127 struct brw_stage_prog_data *prog_data,
128 struct gl_program *prog,
129 unsigned promoted_constants,
130 bool runtime_check_aads_emit,
131 const char *stage_abbrev)
132
133 : brw(brw), key(key),
134 prog_data(prog_data),
135 prog(prog), promoted_constants(promoted_constants),
136 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
137 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
138 {
139 ctx = &brw->ctx;
140
141 p = rzalloc(mem_ctx, struct brw_compile);
142 brw_init_compile(brw, p, mem_ctx);
143 }
144
145 fs_generator::~fs_generator()
146 {
147 }
148
149 class ip_record : public exec_node {
150 public:
151 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
152
153 ip_record(int ip)
154 {
155 this->ip = ip;
156 }
157
158 int ip;
159 };
160
161 bool
162 fs_generator::patch_discard_jumps_to_fb_writes()
163 {
164 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
165 return false;
166
167 int scale = brw_jump_scale(brw);
168
169 /* There is a somewhat strange undocumented requirement of using
170 * HALT, according to the simulator. If some channel has HALTed to
171 * a particular UIP, then by the end of the program, every channel
172 * must have HALTed to that UIP. Furthermore, the tracking is a
173 * stack, so you can't do the final halt of a UIP after starting
174 * halting to a new UIP.
175 *
176 * Symptoms of not emitting this instruction on actual hardware
177 * included GPU hangs and sparkly rendering on the piglit discard
178 * tests.
179 */
180 brw_inst *last_halt = gen6_HALT(p);
181 brw_inst_set_uip(brw, last_halt, 1 * scale);
182 brw_inst_set_jip(brw, last_halt, 1 * scale);
183
184 int ip = p->nr_insn;
185
186 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
187 brw_inst *patch = &p->store[patch_ip->ip];
188
189 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
190 /* HALT takes a half-instruction distance from the pre-incremented IP. */
191 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
192 }
193
194 this->discard_halt_patches.make_empty();
195 return true;
196 }
197
198 void
199 fs_generator::fire_fb_write(fs_inst *inst,
200 struct brw_reg payload,
201 struct brw_reg implied_header,
202 GLuint nr)
203 {
204 uint32_t msg_control;
205
206 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
207
208 if (brw->gen < 6) {
209 brw_push_insn_state(p);
210 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
211 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
212 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
213 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
214 brw_pop_insn_state(p);
215 }
216
217 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
218 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
219 else if (prog_data->dual_src_blend) {
220 if (dispatch_width == 8 || !inst->eot)
221 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
222 else
223 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
224 } else if (dispatch_width == 16)
225 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
226 else
227 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
228
229 uint32_t surf_index =
230 prog_data->binding_table.render_target_start + inst->target;
231
232 bool last_render_target = inst->eot ||
233 (prog_data->dual_src_blend && dispatch_width == 16);
234
235
236 brw_fb_WRITE(p,
237 dispatch_width,
238 payload,
239 implied_header,
240 msg_control,
241 surf_index,
242 nr,
243 0,
244 inst->eot,
245 last_render_target,
246 inst->header_present);
247
248 brw_mark_surface_used(&prog_data->base, surf_index);
249 }
250
251 void
252 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
253 {
254 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
255 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
256 struct brw_reg implied_header;
257
258 if (brw->gen < 8 && !brw->is_haswell) {
259 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
260 }
261
262 if (inst->base_mrf >= 0)
263 payload = brw_message_reg(inst->base_mrf);
264
265 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
266 * move, here's g1.
267 */
268 if (inst->header_present) {
269 brw_push_insn_state(p);
270 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
271 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
272 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
273 brw_set_default_flag_reg(p, 0, 0);
274
275 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
276 * present.
277 */
278 if (prog_data->uses_kill) {
279 struct brw_reg pixel_mask;
280
281 if (brw->gen >= 6)
282 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
283 else
284 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
285
286 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
287 }
288
289 if (brw->gen >= 6) {
290 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
291 brw_MOV(p,
292 retype(payload, BRW_REGISTER_TYPE_UD),
293 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
294 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
295
296 if (inst->target > 0 && key->replicate_alpha) {
297 /* Set "Source0 Alpha Present to RenderTarget" bit in message
298 * header.
299 */
300 brw_OR(p,
301 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
302 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
303 brw_imm_ud(0x1 << 11));
304 }
305
306 if (inst->target > 0) {
307 /* Set the render target index for choosing BLEND_STATE. */
308 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
309 BRW_REGISTER_TYPE_UD),
310 brw_imm_ud(inst->target));
311 }
312
313 implied_header = brw_null_reg();
314 } else {
315 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
316 }
317
318 brw_pop_insn_state(p);
319 } else {
320 implied_header = brw_null_reg();
321 }
322
323 if (!runtime_check_aads_emit) {
324 fire_fb_write(inst, payload, implied_header, inst->mlen);
325 } else {
326 /* This can only happen in gen < 6 */
327 assert(brw->gen < 6);
328
329 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
330
331 /* Check runtime bit to detect if we have to send AA data or not */
332 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
333 brw_AND(p,
334 v1_null_ud,
335 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
336 brw_imm_ud(1<<26));
337 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
338
339 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
340 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
341 {
342 /* Don't send AA data */
343 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
344 }
345 brw_land_fwd_jump(p, jmp);
346 fire_fb_write(inst, payload, implied_header, inst->mlen);
347 }
348 }
349
350 void
351 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
352 {
353 brw_inst *insn;
354
355 insn = brw_next_insn(p, BRW_OPCODE_SEND);
356
357 brw_set_dest(p, insn, brw_null_reg());
358 brw_set_src0(p, insn, payload);
359 brw_set_src1(p, insn, brw_imm_d(0));
360
361 brw_inst_set_sfid(brw, insn, BRW_SFID_URB);
362 brw_inst_set_urb_opcode(brw, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
363
364 brw_inst_set_mlen(brw, insn, inst->mlen);
365 brw_inst_set_rlen(brw, insn, 0);
366 brw_inst_set_eot(brw, insn, inst->eot);
367 brw_inst_set_header_present(brw, insn, true);
368 brw_inst_set_urb_global_offset(brw, insn, inst->offset);
369 }
370
371 void
372 fs_generator::generate_blorp_fb_write(fs_inst *inst)
373 {
374 brw_fb_WRITE(p,
375 16 /* dispatch_width */,
376 brw_message_reg(inst->base_mrf),
377 brw_reg_from_fs_reg(&inst->src[0]),
378 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
379 inst->target,
380 inst->mlen,
381 0,
382 true,
383 true,
384 inst->header_present);
385 }
386
387 /* Computes the integer pixel x,y values from the origin.
388 *
389 * This is the basis of gl_FragCoord computation, but is also used
390 * pre-gen6 for computing the deltas from v0 for computing
391 * interpolation.
392 */
393 void
394 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
395 {
396 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
397 struct brw_reg src;
398 struct brw_reg deltas;
399
400 if (is_x) {
401 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
402 deltas = brw_imm_v(0x10101010);
403 } else {
404 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
405 deltas = brw_imm_v(0x11001100);
406 }
407
408 if (dispatch_width == 16) {
409 dst = vec16(dst);
410 }
411
412 /* We do this SIMD8 or SIMD16, but since the destination is UW we
413 * don't do compression in the SIMD16 case.
414 */
415 brw_push_insn_state(p);
416 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
417 brw_ADD(p, dst, src, deltas);
418 brw_pop_insn_state(p);
419 }
420
421 void
422 fs_generator::generate_linterp(fs_inst *inst,
423 struct brw_reg dst, struct brw_reg *src)
424 {
425 struct brw_reg delta_x = src[0];
426 struct brw_reg delta_y = src[1];
427 struct brw_reg interp = src[2];
428
429 if (brw->has_pln &&
430 delta_y.nr == delta_x.nr + 1 &&
431 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
432 brw_PLN(p, dst, interp, delta_x);
433 } else {
434 brw_LINE(p, brw_null_reg(), interp, delta_x);
435 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
436 }
437 }
438
439 void
440 fs_generator::generate_math_gen6(fs_inst *inst,
441 struct brw_reg dst,
442 struct brw_reg src0,
443 struct brw_reg src1)
444 {
445 int op = brw_math_function(inst->opcode);
446 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
447
448 if (dispatch_width == 8) {
449 gen6_math(p, dst, op, src0, src1);
450 } else if (dispatch_width == 16) {
451 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
452 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
453 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
454 gen6_math(p, sechalf(dst), op, sechalf(src0),
455 binop ? sechalf(src1) : brw_null_reg());
456 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
457 }
458 }
459
460 void
461 fs_generator::generate_math_gen4(fs_inst *inst,
462 struct brw_reg dst,
463 struct brw_reg src)
464 {
465 int op = brw_math_function(inst->opcode);
466
467 assert(inst->mlen >= 1);
468
469 if (dispatch_width == 8) {
470 gen4_math(p, dst,
471 op,
472 inst->base_mrf, src,
473 BRW_MATH_PRECISION_FULL);
474 } else if (dispatch_width == 16) {
475 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
476 gen4_math(p, firsthalf(dst),
477 op,
478 inst->base_mrf, firsthalf(src),
479 BRW_MATH_PRECISION_FULL);
480 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
481 gen4_math(p, sechalf(dst),
482 op,
483 inst->base_mrf + 1, sechalf(src),
484 BRW_MATH_PRECISION_FULL);
485
486 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
487 }
488 }
489
490 void
491 fs_generator::generate_math_g45(fs_inst *inst,
492 struct brw_reg dst,
493 struct brw_reg src)
494 {
495 if (inst->opcode == SHADER_OPCODE_POW ||
496 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
497 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
498 generate_math_gen4(inst, dst, src);
499 return;
500 }
501
502 int op = brw_math_function(inst->opcode);
503
504 assert(inst->mlen >= 1);
505
506 gen4_math(p, dst,
507 op,
508 inst->base_mrf, src,
509 BRW_MATH_PRECISION_FULL);
510 }
511
512 void
513 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
514 struct brw_reg sampler_index)
515 {
516 int msg_type = -1;
517 int rlen = 4;
518 uint32_t simd_mode;
519 uint32_t return_format;
520
521 switch (dst.type) {
522 case BRW_REGISTER_TYPE_D:
523 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
524 break;
525 case BRW_REGISTER_TYPE_UD:
526 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
527 break;
528 default:
529 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
530 break;
531 }
532
533 switch (inst->exec_size) {
534 case 8:
535 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
536 break;
537 case 16:
538 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
539 break;
540 default:
541 unreachable("Invalid width for texture instruction");
542 }
543
544 if (brw->gen >= 5) {
545 switch (inst->opcode) {
546 case SHADER_OPCODE_TEX:
547 if (inst->shadow_compare) {
548 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
549 } else {
550 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
551 }
552 break;
553 case FS_OPCODE_TXB:
554 if (inst->shadow_compare) {
555 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
556 } else {
557 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
558 }
559 break;
560 case SHADER_OPCODE_TXL:
561 if (inst->shadow_compare) {
562 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
563 } else {
564 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
565 }
566 break;
567 case SHADER_OPCODE_TXS:
568 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
569 break;
570 case SHADER_OPCODE_TXD:
571 if (inst->shadow_compare) {
572 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
573 assert(brw->gen >= 8 || brw->is_haswell);
574 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
575 } else {
576 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
577 }
578 break;
579 case SHADER_OPCODE_TXF:
580 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
581 break;
582 case SHADER_OPCODE_TXF_CMS:
583 if (brw->gen >= 7)
584 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
585 else
586 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
587 break;
588 case SHADER_OPCODE_TXF_UMS:
589 assert(brw->gen >= 7);
590 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
591 break;
592 case SHADER_OPCODE_TXF_MCS:
593 assert(brw->gen >= 7);
594 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
595 break;
596 case SHADER_OPCODE_LOD:
597 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
598 break;
599 case SHADER_OPCODE_TG4:
600 if (inst->shadow_compare) {
601 assert(brw->gen >= 7);
602 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
603 } else {
604 assert(brw->gen >= 6);
605 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
606 }
607 break;
608 case SHADER_OPCODE_TG4_OFFSET:
609 assert(brw->gen >= 7);
610 if (inst->shadow_compare) {
611 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
612 } else {
613 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
614 }
615 break;
616 default:
617 unreachable("not reached");
618 }
619 } else {
620 switch (inst->opcode) {
621 case SHADER_OPCODE_TEX:
622 /* Note that G45 and older determines shadow compare and dispatch width
623 * from message length for most messages.
624 */
625 assert(dispatch_width == 8);
626 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
627 if (inst->shadow_compare) {
628 assert(inst->mlen == 6);
629 } else {
630 assert(inst->mlen <= 4);
631 }
632 break;
633 case FS_OPCODE_TXB:
634 if (inst->shadow_compare) {
635 assert(inst->mlen == 6);
636 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
637 } else {
638 assert(inst->mlen == 9);
639 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
640 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
641 }
642 break;
643 case SHADER_OPCODE_TXL:
644 if (inst->shadow_compare) {
645 assert(inst->mlen == 6);
646 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
647 } else {
648 assert(inst->mlen == 9);
649 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
650 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
651 }
652 break;
653 case SHADER_OPCODE_TXD:
654 /* There is no sample_d_c message; comparisons are done manually */
655 assert(inst->mlen == 7 || inst->mlen == 10);
656 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
657 break;
658 case SHADER_OPCODE_TXF:
659 assert(inst->mlen == 9);
660 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
661 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
662 break;
663 case SHADER_OPCODE_TXS:
664 assert(inst->mlen == 3);
665 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
666 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
667 break;
668 default:
669 unreachable("not reached");
670 }
671 }
672 assert(msg_type != -1);
673
674 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
675 rlen = 8;
676 dst = vec16(dst);
677 }
678
679 assert(brw->gen < 7 || !inst->header_present ||
680 src.file == BRW_GENERAL_REGISTER_FILE);
681
682 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
683
684 /* Load the message header if present. If there's a texture offset,
685 * we need to set it up explicitly and load the offset bitfield.
686 * Otherwise, we can use an implied move from g0 to the first message reg.
687 */
688 if (inst->header_present) {
689 if (brw->gen < 6 && !inst->offset) {
690 /* Set up an implied move from g0 to the MRF. */
691 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
692 } else {
693 struct brw_reg header_reg;
694
695 if (brw->gen >= 7) {
696 header_reg = src;
697 } else {
698 assert(inst->base_mrf != -1);
699 header_reg = brw_message_reg(inst->base_mrf);
700 }
701
702 brw_push_insn_state(p);
703 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
704 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
705 /* Explicitly set up the message header by copying g0 to the MRF. */
706 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
707
708 if (inst->offset) {
709 /* Set the offset bits in DWord 2. */
710 brw_MOV(p, get_element_ud(header_reg, 2),
711 brw_imm_ud(inst->offset));
712 }
713
714 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
715 brw_pop_insn_state(p);
716 }
717 }
718
719 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
720 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
721 ? prog_data->binding_table.gather_texture_start
722 : prog_data->binding_table.texture_start;
723
724 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
725 uint32_t sampler = sampler_index.dw1.ud;
726
727 brw_SAMPLE(p,
728 retype(dst, BRW_REGISTER_TYPE_UW),
729 inst->base_mrf,
730 src,
731 sampler + base_binding_table_index,
732 sampler % 16,
733 msg_type,
734 rlen,
735 inst->mlen,
736 inst->header_present,
737 simd_mode,
738 return_format);
739
740 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
741 } else {
742 /* Non-const sampler index */
743 /* Note: this clobbers `dst` as a temporary before emitting the send */
744
745 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
746 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
747
748 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
749
750 brw_push_insn_state(p);
751 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
752 brw_set_default_access_mode(p, BRW_ALIGN_1);
753
754 /* Some care required: `sampler` and `temp` may alias:
755 * addr = sampler & 0xff
756 * temp = (sampler << 8) & 0xf00
757 * addr = addr | temp
758 */
759 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
760 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
761 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
762 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
763 brw_OR(p, addr, addr, temp);
764
765 /* a0.0 |= <descriptor> */
766 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
767 brw_set_sampler_message(p, insn_or,
768 0 /* surface */,
769 0 /* sampler */,
770 msg_type,
771 rlen,
772 inst->mlen /* mlen */,
773 inst->header_present /* header */,
774 simd_mode,
775 return_format);
776 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
777 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
778 brw_set_src0(p, insn_or, addr);
779 brw_set_dest(p, insn_or, addr);
780
781
782 /* dst = send(offset, a0.0) */
783 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
784 brw_set_dest(p, insn_send, dst);
785 brw_set_src0(p, insn_send, src);
786 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
787
788 brw_pop_insn_state(p);
789
790 /* visitor knows more than we do about the surface limit required,
791 * so has already done marking.
792 */
793 }
794 }
795
796
797 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
798 * looking like:
799 *
800 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
801 *
802 * Ideally, we want to produce:
803 *
804 * DDX DDY
805 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
806 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
807 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
808 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
809 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
810 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
811 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
812 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
813 *
814 * and add another set of two more subspans if in 16-pixel dispatch mode.
815 *
816 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
817 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
818 * pair. But the ideal approximation may impose a huge performance cost on
819 * sample_d. On at least Haswell, sample_d instruction does some
820 * optimizations if the same LOD is used for all pixels in the subspan.
821 *
822 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
823 * appropriate swizzling.
824 */
825 void
826 fs_generator::generate_ddx(enum opcode opcode,
827 struct brw_reg dst, struct brw_reg src)
828 {
829 unsigned vstride, width;
830
831 if (opcode == FS_OPCODE_DDX_FINE) {
832 /* produce accurate derivatives */
833 vstride = BRW_VERTICAL_STRIDE_2;
834 width = BRW_WIDTH_2;
835 } else {
836 /* replicate the derivative at the top-left pixel to other pixels */
837 vstride = BRW_VERTICAL_STRIDE_4;
838 width = BRW_WIDTH_4;
839 }
840
841 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
842 src.negate, src.abs,
843 BRW_REGISTER_TYPE_F,
844 vstride,
845 width,
846 BRW_HORIZONTAL_STRIDE_0,
847 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
848 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
849 src.negate, src.abs,
850 BRW_REGISTER_TYPE_F,
851 vstride,
852 width,
853 BRW_HORIZONTAL_STRIDE_0,
854 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
855 brw_ADD(p, dst, src0, negate(src1));
856 }
857
858 /* The negate_value boolean is used to negate the derivative computation for
859 * FBOs, since they place the origin at the upper left instead of the lower
860 * left.
861 */
862 void
863 fs_generator::generate_ddy(enum opcode opcode,
864 struct brw_reg dst, struct brw_reg src,
865 bool negate_value)
866 {
867 if (opcode == FS_OPCODE_DDY_FINE) {
868 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
869 * Region Restrictions):
870 *
871 * In Align16 access mode, SIMD16 is not allowed for DW operations
872 * and SIMD8 is not allowed for DF operations.
873 *
874 * In this context, "DW operations" means "operations acting on 32-bit
875 * values", so it includes operations on floats.
876 *
877 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
878 * (Instruction Compression -> Rules and Restrictions):
879 *
880 * A compressed instruction must be in Align1 access mode. Align16
881 * mode instructions cannot be compressed.
882 *
883 * Similar text exists in the g45 PRM.
884 *
885 * On these platforms, if we're building a SIMD16 shader, we need to
886 * manually unroll to a pair of SIMD8 instructions.
887 */
888 bool unroll_to_simd8 =
889 (dispatch_width == 16 &&
890 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
891
892 /* produce accurate derivatives */
893 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
894 src.negate, src.abs,
895 BRW_REGISTER_TYPE_F,
896 BRW_VERTICAL_STRIDE_4,
897 BRW_WIDTH_4,
898 BRW_HORIZONTAL_STRIDE_1,
899 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
900 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
901 src.negate, src.abs,
902 BRW_REGISTER_TYPE_F,
903 BRW_VERTICAL_STRIDE_4,
904 BRW_WIDTH_4,
905 BRW_HORIZONTAL_STRIDE_1,
906 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
907 brw_push_insn_state(p);
908 brw_set_default_access_mode(p, BRW_ALIGN_16);
909 if (unroll_to_simd8) {
910 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
911 if (negate_value) {
912 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
913 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
914 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
915 } else {
916 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
917 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
918 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
919 }
920 } else {
921 if (negate_value)
922 brw_ADD(p, dst, src1, negate(src0));
923 else
924 brw_ADD(p, dst, src0, negate(src1));
925 }
926 brw_pop_insn_state(p);
927 } else {
928 /* replicate the derivative at the top-left pixel to other pixels */
929 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
930 src.negate, src.abs,
931 BRW_REGISTER_TYPE_F,
932 BRW_VERTICAL_STRIDE_4,
933 BRW_WIDTH_4,
934 BRW_HORIZONTAL_STRIDE_0,
935 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
936 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
937 src.negate, src.abs,
938 BRW_REGISTER_TYPE_F,
939 BRW_VERTICAL_STRIDE_4,
940 BRW_WIDTH_4,
941 BRW_HORIZONTAL_STRIDE_0,
942 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
943 if (negate_value)
944 brw_ADD(p, dst, src1, negate(src0));
945 else
946 brw_ADD(p, dst, src0, negate(src1));
947 }
948 }
949
950 void
951 fs_generator::generate_discard_jump(fs_inst *inst)
952 {
953 assert(brw->gen >= 6);
954
955 /* This HALT will be patched up at FB write time to point UIP at the end of
956 * the program, and at brw_uip_jip() JIP will be set to the end of the
957 * current block (or the program).
958 */
959 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
960
961 brw_push_insn_state(p);
962 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
963 gen6_HALT(p);
964 brw_pop_insn_state(p);
965 }
966
967 void
968 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
969 {
970 assert(inst->mlen != 0);
971
972 brw_MOV(p,
973 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
974 retype(src, BRW_REGISTER_TYPE_UD));
975 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
976 inst->exec_size / 8, inst->offset);
977 }
978
979 void
980 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
981 {
982 assert(inst->mlen != 0);
983
984 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
985 inst->exec_size / 8, inst->offset);
986 }
987
988 void
989 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
990 {
991 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
992 }
993
994 void
995 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
996 struct brw_reg dst,
997 struct brw_reg index,
998 struct brw_reg offset)
999 {
1000 assert(inst->mlen != 0);
1001
1002 assert(index.file == BRW_IMMEDIATE_VALUE &&
1003 index.type == BRW_REGISTER_TYPE_UD);
1004 uint32_t surf_index = index.dw1.ud;
1005
1006 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1007 offset.type == BRW_REGISTER_TYPE_UD);
1008 uint32_t read_offset = offset.dw1.ud;
1009
1010 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1011 read_offset, surf_index);
1012
1013 brw_mark_surface_used(prog_data, surf_index);
1014 }
1015
1016 void
1017 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1018 struct brw_reg dst,
1019 struct brw_reg index,
1020 struct brw_reg offset)
1021 {
1022 assert(inst->mlen == 0);
1023 assert(index.type == BRW_REGISTER_TYPE_UD);
1024
1025 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1026 /* Reference just the dword we need, to avoid angering validate_reg(). */
1027 offset = brw_vec1_grf(offset.nr, 0);
1028
1029 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1030 * the destination loaded consecutively from the same offset (which appears
1031 * in the first component, and the rest are ignored).
1032 */
1033 dst.width = BRW_WIDTH_4;
1034
1035 struct brw_reg src = offset;
1036 bool header_present = false;
1037 int mlen = 1;
1038
1039 if (brw->gen >= 9) {
1040 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1041 src = retype(brw_vec4_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD);
1042 mlen = 2;
1043 header_present = true;
1044
1045 brw_push_insn_state(p);
1046 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1047 brw_MOV(p, src, retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD));
1048 brw_set_default_access_mode(p, BRW_ALIGN_1);
1049
1050 brw_MOV(p, get_element_ud(src, 2),
1051 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1052 brw_pop_insn_state(p);
1053 }
1054
1055 if (index.file == BRW_IMMEDIATE_VALUE) {
1056
1057 uint32_t surf_index = index.dw1.ud;
1058
1059 brw_push_insn_state(p);
1060 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1061 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1062 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1063 brw_pop_insn_state(p);
1064
1065 brw_set_dest(p, send, dst);
1066 brw_set_src0(p, send, src);
1067 brw_set_sampler_message(p, send,
1068 surf_index,
1069 0, /* LD message ignores sampler unit */
1070 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1071 1, /* rlen */
1072 mlen,
1073 header_present,
1074 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1075 0);
1076
1077 brw_mark_surface_used(prog_data, surf_index);
1078
1079 } else {
1080
1081 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1082
1083 brw_push_insn_state(p);
1084 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1085 brw_set_default_access_mode(p, BRW_ALIGN_1);
1086
1087 /* a0.0 = surf_index & 0xff */
1088 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1089 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1090 brw_set_dest(p, insn_and, addr);
1091 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1092 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1093
1094
1095 /* a0.0 |= <descriptor> */
1096 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1097 brw_set_sampler_message(p, insn_or,
1098 0 /* surface */,
1099 0 /* sampler */,
1100 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1101 1 /* rlen */,
1102 mlen,
1103 header_present,
1104 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1105 0);
1106 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1107 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1108 brw_set_src0(p, insn_or, addr);
1109 brw_set_dest(p, insn_or, addr);
1110
1111
1112 /* dst = send(offset, a0.0) */
1113 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1114 brw_set_dest(p, insn_send, dst);
1115 brw_set_src0(p, insn_send, src);
1116 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1117
1118 brw_pop_insn_state(p);
1119
1120 /* visitor knows more than we do about the surface limit required,
1121 * so has already done marking.
1122 */
1123
1124 }
1125 }
1126
1127 void
1128 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1129 struct brw_reg dst,
1130 struct brw_reg index,
1131 struct brw_reg offset)
1132 {
1133 assert(brw->gen < 7); /* Should use the gen7 variant. */
1134 assert(inst->header_present);
1135 assert(inst->mlen);
1136
1137 assert(index.file == BRW_IMMEDIATE_VALUE &&
1138 index.type == BRW_REGISTER_TYPE_UD);
1139 uint32_t surf_index = index.dw1.ud;
1140
1141 uint32_t simd_mode, rlen, msg_type;
1142 if (dispatch_width == 16) {
1143 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1144 rlen = 8;
1145 } else {
1146 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1147 rlen = 4;
1148 }
1149
1150 if (brw->gen >= 5)
1151 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1152 else {
1153 /* We always use the SIMD16 message so that we only have to load U, and
1154 * not V or R.
1155 */
1156 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1157 assert(inst->mlen == 3);
1158 assert(inst->regs_written == 8);
1159 rlen = 8;
1160 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1161 }
1162
1163 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1164 BRW_REGISTER_TYPE_D);
1165 brw_MOV(p, offset_mrf, offset);
1166
1167 struct brw_reg header = brw_vec8_grf(0, 0);
1168 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1169
1170 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1171 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
1172 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1173 brw_set_src0(p, send, header);
1174 if (brw->gen < 6)
1175 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
1176
1177 /* Our surface is set up as floats, regardless of what actual data is
1178 * stored in it.
1179 */
1180 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1181 brw_set_sampler_message(p, send,
1182 surf_index,
1183 0, /* sampler (unused) */
1184 msg_type,
1185 rlen,
1186 inst->mlen,
1187 inst->header_present,
1188 simd_mode,
1189 return_format);
1190
1191 brw_mark_surface_used(prog_data, surf_index);
1192 }
1193
1194 void
1195 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1196 struct brw_reg dst,
1197 struct brw_reg index,
1198 struct brw_reg offset)
1199 {
1200 assert(brw->gen >= 7);
1201 /* Varying-offset pull constant loads are treated as a normal expression on
1202 * gen7, so the fact that it's a send message is hidden at the IR level.
1203 */
1204 assert(!inst->header_present);
1205 assert(!inst->mlen);
1206 assert(index.type == BRW_REGISTER_TYPE_UD);
1207
1208 uint32_t simd_mode, rlen, mlen;
1209 if (dispatch_width == 16) {
1210 mlen = 2;
1211 rlen = 8;
1212 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1213 } else {
1214 mlen = 1;
1215 rlen = 4;
1216 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1217 }
1218
1219 if (index.file == BRW_IMMEDIATE_VALUE) {
1220
1221 uint32_t surf_index = index.dw1.ud;
1222
1223 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1224 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1225 brw_set_src0(p, send, offset);
1226 brw_set_sampler_message(p, send,
1227 surf_index,
1228 0, /* LD message ignores sampler unit */
1229 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1230 rlen,
1231 mlen,
1232 false, /* no header */
1233 simd_mode,
1234 0);
1235
1236 brw_mark_surface_used(prog_data, surf_index);
1237
1238 } else {
1239
1240 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1241
1242 brw_push_insn_state(p);
1243 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1244 brw_set_default_access_mode(p, BRW_ALIGN_1);
1245
1246 /* a0.0 = surf_index & 0xff */
1247 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1248 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1249 brw_set_dest(p, insn_and, addr);
1250 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1251 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1252
1253
1254 /* a0.0 |= <descriptor> */
1255 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1256 brw_set_sampler_message(p, insn_or,
1257 0 /* surface */,
1258 0 /* sampler */,
1259 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1260 rlen /* rlen */,
1261 mlen /* mlen */,
1262 false /* header */,
1263 simd_mode,
1264 0);
1265 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1266 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1267 brw_set_src0(p, insn_or, addr);
1268 brw_set_dest(p, insn_or, addr);
1269
1270
1271 /* dst = send(offset, a0.0) */
1272 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1273 brw_set_dest(p, insn_send, retype(dst, BRW_REGISTER_TYPE_UW));
1274 brw_set_src0(p, insn_send, offset);
1275 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1276
1277 brw_pop_insn_state(p);
1278
1279 /* visitor knows more than we do about the surface limit required,
1280 * so has already done marking.
1281 */
1282 }
1283 }
1284
1285 /**
1286 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1287 * into the flags register (f0.0).
1288 *
1289 * Used only on Gen6 and above.
1290 */
1291 void
1292 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1293 {
1294 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1295 struct brw_reg dispatch_mask;
1296
1297 if (brw->gen >= 6)
1298 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1299 else
1300 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1301
1302 brw_push_insn_state(p);
1303 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1304 brw_MOV(p, flags, dispatch_mask);
1305 brw_pop_insn_state(p);
1306 }
1307
1308 void
1309 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1310 struct brw_reg dst,
1311 struct brw_reg src,
1312 struct brw_reg msg_data,
1313 unsigned msg_type)
1314 {
1315 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1316 msg_data.type == BRW_REGISTER_TYPE_UD);
1317
1318 brw_pixel_interpolator_query(p,
1319 retype(dst, BRW_REGISTER_TYPE_UW),
1320 src,
1321 inst->pi_noperspective,
1322 msg_type,
1323 msg_data.dw1.ud,
1324 inst->mlen,
1325 inst->regs_written);
1326 }
1327
1328
1329 /**
1330 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1331 * sampler LD messages.
1332 *
1333 * We don't want to bake it into the send message's code generation because
1334 * that means we don't get a chance to schedule the instructions.
1335 */
1336 void
1337 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1338 struct brw_reg dst,
1339 struct brw_reg value)
1340 {
1341 assert(value.file == BRW_IMMEDIATE_VALUE);
1342
1343 brw_push_insn_state(p);
1344 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1345 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1346 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1347 brw_pop_insn_state(p);
1348 }
1349
1350 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1351 * (when mask is passed as a uniform) of register mask before moving it
1352 * to register dst.
1353 */
1354 void
1355 fs_generator::generate_set_omask(fs_inst *inst,
1356 struct brw_reg dst,
1357 struct brw_reg mask)
1358 {
1359 bool stride_8_8_1 =
1360 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1361 mask.width == BRW_WIDTH_8 &&
1362 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1363
1364 bool stride_0_1_0 = has_scalar_region(mask);
1365
1366 assert(stride_8_8_1 || stride_0_1_0);
1367 assert(dst.type == BRW_REGISTER_TYPE_UW);
1368
1369 if (dispatch_width == 16)
1370 dst = vec16(dst);
1371 brw_push_insn_state(p);
1372 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1373 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1374
1375 if (stride_8_8_1) {
1376 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1377 } else if (stride_0_1_0) {
1378 brw_MOV(p, dst, retype(mask, dst.type));
1379 }
1380 brw_pop_insn_state(p);
1381 }
1382
1383 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1384 * the ADD instruction.
1385 */
1386 void
1387 fs_generator::generate_set_sample_id(fs_inst *inst,
1388 struct brw_reg dst,
1389 struct brw_reg src0,
1390 struct brw_reg src1)
1391 {
1392 assert(dst.type == BRW_REGISTER_TYPE_D ||
1393 dst.type == BRW_REGISTER_TYPE_UD);
1394 assert(src0.type == BRW_REGISTER_TYPE_D ||
1395 src0.type == BRW_REGISTER_TYPE_UD);
1396
1397 brw_push_insn_state(p);
1398 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1399 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1400 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1401 if (dispatch_width == 8) {
1402 brw_ADD(p, dst, src0, reg);
1403 } else if (dispatch_width == 16) {
1404 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1405 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1406 }
1407 brw_pop_insn_state(p);
1408 }
1409
1410 void
1411 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1412 struct brw_reg dst,
1413 struct brw_reg x,
1414 struct brw_reg y)
1415 {
1416 assert(brw->gen >= 7);
1417 assert(dst.type == BRW_REGISTER_TYPE_UD);
1418 assert(x.type == BRW_REGISTER_TYPE_F);
1419 assert(y.type == BRW_REGISTER_TYPE_F);
1420
1421 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1422 *
1423 * Because this instruction does not have a 16-bit floating-point type,
1424 * the destination data type must be Word (W).
1425 *
1426 * The destination must be DWord-aligned and specify a horizontal stride
1427 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1428 * each destination channel and the upper word is not modified.
1429 */
1430 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1431
1432 /* Give each 32-bit channel of dst the form below, where "." means
1433 * unchanged.
1434 * 0x....hhhh
1435 */
1436 brw_F32TO16(p, dst_w, y);
1437
1438 /* Now the form:
1439 * 0xhhhh0000
1440 */
1441 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1442
1443 /* And, finally the form of packHalf2x16's output:
1444 * 0xhhhhllll
1445 */
1446 brw_F32TO16(p, dst_w, x);
1447 }
1448
1449 void
1450 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1451 struct brw_reg dst,
1452 struct brw_reg src)
1453 {
1454 assert(brw->gen >= 7);
1455 assert(dst.type == BRW_REGISTER_TYPE_F);
1456 assert(src.type == BRW_REGISTER_TYPE_UD);
1457
1458 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1459 *
1460 * Because this instruction does not have a 16-bit floating-point type,
1461 * the source data type must be Word (W). The destination type must be
1462 * F (Float).
1463 */
1464 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1465
1466 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1467 * For the Y case, we wish to access only the upper word; therefore
1468 * a 16-bit subregister offset is needed.
1469 */
1470 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1471 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1472 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1473 src_w.subnr += 2;
1474
1475 brw_F16TO32(p, dst, src_w);
1476 }
1477
1478 void
1479 fs_generator::generate_shader_time_add(fs_inst *inst,
1480 struct brw_reg payload,
1481 struct brw_reg offset,
1482 struct brw_reg value)
1483 {
1484 assert(brw->gen >= 7);
1485 brw_push_insn_state(p);
1486 brw_set_default_mask_control(p, true);
1487
1488 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1489 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1490 offset.type);
1491 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1492 value.type);
1493
1494 assert(offset.file == BRW_IMMEDIATE_VALUE);
1495 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1496 value.width = BRW_WIDTH_1;
1497 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1498 value.vstride = BRW_VERTICAL_STRIDE_0;
1499 } else {
1500 assert(value.file == BRW_IMMEDIATE_VALUE);
1501 }
1502
1503 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1504 * case, and we don't really care about squeezing every bit of performance
1505 * out of this path, so we just emit the MOVs from here.
1506 */
1507 brw_MOV(p, payload_offset, offset);
1508 brw_MOV(p, payload_value, value);
1509 brw_shader_time_add(p, payload,
1510 prog_data->binding_table.shader_time_start);
1511 brw_pop_insn_state(p);
1512
1513 brw_mark_surface_used(prog_data,
1514 prog_data->binding_table.shader_time_start);
1515 }
1516
1517 void
1518 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1519 struct brw_reg payload,
1520 struct brw_reg atomic_op,
1521 struct brw_reg surf_index)
1522 {
1523 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1524 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1525 surf_index.file == BRW_IMMEDIATE_VALUE &&
1526 surf_index.type == BRW_REGISTER_TYPE_UD);
1527
1528 brw_untyped_atomic(p, dst, payload, atomic_op.dw1.ud, surf_index.dw1.ud,
1529 inst->mlen, inst->exec_size / 8);
1530
1531 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1532 }
1533
1534 void
1535 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1536 struct brw_reg payload,
1537 struct brw_reg surf_index)
1538 {
1539 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1540 surf_index.type == BRW_REGISTER_TYPE_UD);
1541
1542 brw_untyped_surface_read(p, dst, payload,
1543 surf_index.dw1.ud,
1544 inst->mlen, inst->exec_size / 8);
1545
1546 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1547 }
1548
1549 void
1550 fs_generator::enable_debug(const char *shader_name)
1551 {
1552 debug_flag = true;
1553 this->shader_name = shader_name;
1554 }
1555
1556 /**
1557 * Some hardware doesn't support SIMD16 instructions with 3 sources.
1558 */
1559 static bool
1560 brw_supports_simd16_3src(const struct brw_context *brw)
1561 {
1562 /* WaDisableSIMD16On3SrcInstr: 3-source instructions don't work in SIMD16
1563 * on a few steppings of Skylake.
1564 */
1565 if (brw->gen == 9)
1566 return brw->revision != 2 && brw->revision != 3 && brw->revision != -1;
1567
1568 return brw->is_haswell || brw->gen >= 8;
1569 }
1570
1571 int
1572 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1573 {
1574 /* align to 64 byte boundary. */
1575 while (p->next_insn_offset % 64)
1576 brw_NOP(p);
1577
1578 this->dispatch_width = dispatch_width;
1579 if (dispatch_width == 16)
1580 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1581
1582 int start_offset = p->next_insn_offset;
1583 int spill_count = 0, fill_count = 0;
1584 int loop_count = 0;
1585
1586 struct annotation_info annotation;
1587 memset(&annotation, 0, sizeof(annotation));
1588
1589 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1590 struct brw_reg src[3], dst;
1591 unsigned int last_insn_offset = p->next_insn_offset;
1592 bool multiple_instructions_emitted = false;
1593
1594 if (unlikely(debug_flag))
1595 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1596
1597 for (unsigned int i = 0; i < inst->sources; i++) {
1598 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1599
1600 /* The accumulator result appears to get used for the
1601 * conditional modifier generation. When negating a UD
1602 * value, there is a 33rd bit generated for the sign in the
1603 * accumulator value, so now you can't check, for example,
1604 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1605 */
1606 assert(!inst->conditional_mod ||
1607 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1608 !inst->src[i].negate);
1609 }
1610 dst = brw_reg_from_fs_reg(&inst->dst);
1611
1612 brw_set_default_predicate_control(p, inst->predicate);
1613 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1614 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1615 brw_set_default_saturate(p, inst->saturate);
1616 brw_set_default_mask_control(p, inst->force_writemask_all);
1617 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1618
1619 switch (inst->exec_size) {
1620 case 1:
1621 case 2:
1622 case 4:
1623 assert(inst->force_writemask_all);
1624 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1625 break;
1626 case 8:
1627 if (inst->force_sechalf) {
1628 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1629 } else {
1630 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1631 }
1632 break;
1633 case 16:
1634 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1635 break;
1636 default:
1637 unreachable(!"Invalid instruction width");
1638 }
1639
1640 switch (inst->opcode) {
1641 case BRW_OPCODE_MOV:
1642 brw_MOV(p, dst, src[0]);
1643 break;
1644 case BRW_OPCODE_ADD:
1645 brw_ADD(p, dst, src[0], src[1]);
1646 break;
1647 case BRW_OPCODE_MUL:
1648 brw_MUL(p, dst, src[0], src[1]);
1649 break;
1650 case BRW_OPCODE_AVG:
1651 brw_AVG(p, dst, src[0], src[1]);
1652 break;
1653 case BRW_OPCODE_MACH:
1654 brw_MACH(p, dst, src[0], src[1]);
1655 break;
1656
1657 case BRW_OPCODE_LINE:
1658 brw_LINE(p, dst, src[0], src[1]);
1659 break;
1660
1661 case BRW_OPCODE_MAD:
1662 assert(brw->gen >= 6);
1663 brw_set_default_access_mode(p, BRW_ALIGN_16);
1664 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1665 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1666 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1667 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1668 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1669 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1670
1671 if (inst->conditional_mod) {
1672 brw_inst_set_cond_modifier(brw, f, inst->conditional_mod);
1673 brw_inst_set_cond_modifier(brw, s, inst->conditional_mod);
1674 multiple_instructions_emitted = true;
1675 }
1676 } else {
1677 brw_MAD(p, dst, src[0], src[1], src[2]);
1678 }
1679 brw_set_default_access_mode(p, BRW_ALIGN_1);
1680 break;
1681
1682 case BRW_OPCODE_LRP:
1683 assert(brw->gen >= 6);
1684 brw_set_default_access_mode(p, BRW_ALIGN_16);
1685 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1686 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1687 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1688 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1689 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1690 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1691
1692 if (inst->conditional_mod) {
1693 brw_inst_set_cond_modifier(brw, f, inst->conditional_mod);
1694 brw_inst_set_cond_modifier(brw, s, inst->conditional_mod);
1695 multiple_instructions_emitted = true;
1696 }
1697 } else {
1698 brw_LRP(p, dst, src[0], src[1], src[2]);
1699 }
1700 brw_set_default_access_mode(p, BRW_ALIGN_1);
1701 break;
1702
1703 case BRW_OPCODE_FRC:
1704 brw_FRC(p, dst, src[0]);
1705 break;
1706 case BRW_OPCODE_RNDD:
1707 brw_RNDD(p, dst, src[0]);
1708 break;
1709 case BRW_OPCODE_RNDE:
1710 brw_RNDE(p, dst, src[0]);
1711 break;
1712 case BRW_OPCODE_RNDZ:
1713 brw_RNDZ(p, dst, src[0]);
1714 break;
1715
1716 case BRW_OPCODE_AND:
1717 brw_AND(p, dst, src[0], src[1]);
1718 break;
1719 case BRW_OPCODE_OR:
1720 brw_OR(p, dst, src[0], src[1]);
1721 break;
1722 case BRW_OPCODE_XOR:
1723 brw_XOR(p, dst, src[0], src[1]);
1724 break;
1725 case BRW_OPCODE_NOT:
1726 brw_NOT(p, dst, src[0]);
1727 break;
1728 case BRW_OPCODE_ASR:
1729 brw_ASR(p, dst, src[0], src[1]);
1730 break;
1731 case BRW_OPCODE_SHR:
1732 brw_SHR(p, dst, src[0], src[1]);
1733 break;
1734 case BRW_OPCODE_SHL:
1735 brw_SHL(p, dst, src[0], src[1]);
1736 break;
1737 case BRW_OPCODE_F32TO16:
1738 assert(brw->gen >= 7);
1739 brw_F32TO16(p, dst, src[0]);
1740 break;
1741 case BRW_OPCODE_F16TO32:
1742 assert(brw->gen >= 7);
1743 brw_F16TO32(p, dst, src[0]);
1744 break;
1745 case BRW_OPCODE_CMP:
1746 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1747 * that when the destination is a GRF that the dependency-clear bit on
1748 * the flag register is cleared early.
1749 *
1750 * Suggested workarounds are to disable coissuing CMP instructions
1751 * or to split CMP(16) instructions into two CMP(8) instructions.
1752 *
1753 * We choose to split into CMP(8) instructions since disabling
1754 * coissuing would affect CMP instructions not otherwise affected by
1755 * the errata.
1756 */
1757 if (dispatch_width == 16 && brw->gen == 7 && !brw->is_haswell) {
1758 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1759 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1760 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1761 firsthalf(src[0]), firsthalf(src[1]));
1762 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1763 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1764 sechalf(src[0]), sechalf(src[1]));
1765 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1766
1767 multiple_instructions_emitted = true;
1768 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1769 /* For unknown reasons, the aforementioned workaround is not
1770 * sufficient. Overriding the type when the destination is the
1771 * null register is necessary but not sufficient by itself.
1772 */
1773 assert(dst.nr == BRW_ARF_NULL);
1774 dst.type = BRW_REGISTER_TYPE_D;
1775 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1776 } else {
1777 unreachable("not reached");
1778 }
1779 } else {
1780 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1781 }
1782 break;
1783 case BRW_OPCODE_SEL:
1784 brw_SEL(p, dst, src[0], src[1]);
1785 break;
1786 case BRW_OPCODE_BFREV:
1787 assert(brw->gen >= 7);
1788 /* BFREV only supports UD type for src and dst. */
1789 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1790 retype(src[0], BRW_REGISTER_TYPE_UD));
1791 break;
1792 case BRW_OPCODE_FBH:
1793 assert(brw->gen >= 7);
1794 /* FBH only supports UD type for dst. */
1795 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1796 break;
1797 case BRW_OPCODE_FBL:
1798 assert(brw->gen >= 7);
1799 /* FBL only supports UD type for dst. */
1800 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1801 break;
1802 case BRW_OPCODE_CBIT:
1803 assert(brw->gen >= 7);
1804 /* CBIT only supports UD type for dst. */
1805 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1806 break;
1807 case BRW_OPCODE_ADDC:
1808 assert(brw->gen >= 7);
1809 brw_ADDC(p, dst, src[0], src[1]);
1810 break;
1811 case BRW_OPCODE_SUBB:
1812 assert(brw->gen >= 7);
1813 brw_SUBB(p, dst, src[0], src[1]);
1814 break;
1815 case BRW_OPCODE_MAC:
1816 brw_MAC(p, dst, src[0], src[1]);
1817 break;
1818
1819 case BRW_OPCODE_BFE:
1820 assert(brw->gen >= 7);
1821 brw_set_default_access_mode(p, BRW_ALIGN_16);
1822 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1823 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1824 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1825 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1826 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1827 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1828 } else {
1829 brw_BFE(p, dst, src[0], src[1], src[2]);
1830 }
1831 brw_set_default_access_mode(p, BRW_ALIGN_1);
1832 break;
1833
1834 case BRW_OPCODE_BFI1:
1835 assert(brw->gen >= 7);
1836 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1837 * should
1838 *
1839 * "Force BFI instructions to be executed always in SIMD8."
1840 */
1841 if (dispatch_width == 16 && brw->is_haswell) {
1842 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1843 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1844 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1845 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1846 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1847 } else {
1848 brw_BFI1(p, dst, src[0], src[1]);
1849 }
1850 break;
1851 case BRW_OPCODE_BFI2:
1852 assert(brw->gen >= 7);
1853 brw_set_default_access_mode(p, BRW_ALIGN_16);
1854 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1855 * should
1856 *
1857 * "Force BFI instructions to be executed always in SIMD8."
1858 *
1859 * Otherwise we would be able to emit compressed instructions like we
1860 * do for the other three-source instructions.
1861 */
1862 if (dispatch_width == 16 &&
1863 (brw->is_haswell || !brw_supports_simd16_3src(brw))) {
1864 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1865 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1866 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1867 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1868 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1869 } else {
1870 brw_BFI2(p, dst, src[0], src[1], src[2]);
1871 }
1872 brw_set_default_access_mode(p, BRW_ALIGN_1);
1873 break;
1874
1875 case BRW_OPCODE_IF:
1876 if (inst->src[0].file != BAD_FILE) {
1877 /* The instruction has an embedded compare (only allowed on gen6) */
1878 assert(brw->gen == 6);
1879 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1880 } else {
1881 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1882 }
1883 break;
1884
1885 case BRW_OPCODE_ELSE:
1886 brw_ELSE(p);
1887 break;
1888 case BRW_OPCODE_ENDIF:
1889 brw_ENDIF(p);
1890 break;
1891
1892 case BRW_OPCODE_DO:
1893 brw_DO(p, BRW_EXECUTE_8);
1894 break;
1895
1896 case BRW_OPCODE_BREAK:
1897 brw_BREAK(p);
1898 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1899 break;
1900 case BRW_OPCODE_CONTINUE:
1901 brw_CONT(p);
1902 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1903 break;
1904
1905 case BRW_OPCODE_WHILE:
1906 brw_WHILE(p);
1907 loop_count++;
1908 break;
1909
1910 case SHADER_OPCODE_RCP:
1911 case SHADER_OPCODE_RSQ:
1912 case SHADER_OPCODE_SQRT:
1913 case SHADER_OPCODE_EXP2:
1914 case SHADER_OPCODE_LOG2:
1915 case SHADER_OPCODE_SIN:
1916 case SHADER_OPCODE_COS:
1917 assert(brw->gen < 6 || inst->mlen == 0);
1918 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1919 if (brw->gen >= 7) {
1920 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1921 brw_null_reg());
1922 } else if (brw->gen == 6) {
1923 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1924 } else if (brw->gen == 5 || brw->is_g4x) {
1925 generate_math_g45(inst, dst, src[0]);
1926 } else {
1927 generate_math_gen4(inst, dst, src[0]);
1928 }
1929 break;
1930 case SHADER_OPCODE_INT_QUOTIENT:
1931 case SHADER_OPCODE_INT_REMAINDER:
1932 case SHADER_OPCODE_POW:
1933 assert(brw->gen < 6 || inst->mlen == 0);
1934 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1935 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1936 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1937 } else if (brw->gen >= 6) {
1938 generate_math_gen6(inst, dst, src[0], src[1]);
1939 } else {
1940 generate_math_gen4(inst, dst, src[0]);
1941 }
1942 break;
1943 case FS_OPCODE_PIXEL_X:
1944 generate_pixel_xy(dst, true);
1945 break;
1946 case FS_OPCODE_PIXEL_Y:
1947 generate_pixel_xy(dst, false);
1948 break;
1949 case FS_OPCODE_CINTERP:
1950 brw_MOV(p, dst, src[0]);
1951 break;
1952 case FS_OPCODE_LINTERP:
1953 generate_linterp(inst, dst, src);
1954 break;
1955 case SHADER_OPCODE_TEX:
1956 case FS_OPCODE_TXB:
1957 case SHADER_OPCODE_TXD:
1958 case SHADER_OPCODE_TXF:
1959 case SHADER_OPCODE_TXF_CMS:
1960 case SHADER_OPCODE_TXF_UMS:
1961 case SHADER_OPCODE_TXF_MCS:
1962 case SHADER_OPCODE_TXL:
1963 case SHADER_OPCODE_TXS:
1964 case SHADER_OPCODE_LOD:
1965 case SHADER_OPCODE_TG4:
1966 case SHADER_OPCODE_TG4_OFFSET:
1967 generate_tex(inst, dst, src[0], src[1]);
1968 break;
1969 case FS_OPCODE_DDX_COARSE:
1970 case FS_OPCODE_DDX_FINE:
1971 generate_ddx(inst->opcode, dst, src[0]);
1972 break;
1973 case FS_OPCODE_DDY_COARSE:
1974 case FS_OPCODE_DDY_FINE:
1975 assert(src[1].file == BRW_IMMEDIATE_VALUE);
1976 generate_ddy(inst->opcode, dst, src[0], src[1].dw1.ud);
1977 break;
1978
1979 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1980 generate_scratch_write(inst, src[0]);
1981 spill_count++;
1982 break;
1983
1984 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1985 generate_scratch_read(inst, dst);
1986 fill_count++;
1987 break;
1988
1989 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1990 generate_scratch_read_gen7(inst, dst);
1991 fill_count++;
1992 break;
1993
1994 case SHADER_OPCODE_URB_WRITE_SIMD8:
1995 generate_urb_write(inst, src[0]);
1996 break;
1997
1998 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1999 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2000 break;
2001
2002 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2003 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2004 break;
2005
2006 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
2007 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
2008 break;
2009
2010 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2011 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2012 break;
2013
2014 case FS_OPCODE_REP_FB_WRITE:
2015 case FS_OPCODE_FB_WRITE:
2016 generate_fb_write(inst, src[0]);
2017 break;
2018
2019 case FS_OPCODE_BLORP_FB_WRITE:
2020 generate_blorp_fb_write(inst);
2021 break;
2022
2023 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2024 generate_mov_dispatch_to_flags(inst);
2025 break;
2026
2027 case FS_OPCODE_DISCARD_JUMP:
2028 generate_discard_jump(inst);
2029 break;
2030
2031 case SHADER_OPCODE_SHADER_TIME_ADD:
2032 generate_shader_time_add(inst, src[0], src[1], src[2]);
2033 break;
2034
2035 case SHADER_OPCODE_UNTYPED_ATOMIC:
2036 generate_untyped_atomic(inst, dst, src[0], src[1], src[2]);
2037 break;
2038
2039 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2040 generate_untyped_surface_read(inst, dst, src[0], src[1]);
2041 break;
2042
2043 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2044 generate_set_simd4x2_offset(inst, dst, src[0]);
2045 break;
2046
2047 case FS_OPCODE_SET_OMASK:
2048 generate_set_omask(inst, dst, src[0]);
2049 break;
2050
2051 case FS_OPCODE_SET_SAMPLE_ID:
2052 generate_set_sample_id(inst, dst, src[0], src[1]);
2053 break;
2054
2055 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2056 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2057 break;
2058
2059 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2060 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2061 generate_unpack_half_2x16_split(inst, dst, src[0]);
2062 break;
2063
2064 case FS_OPCODE_PLACEHOLDER_HALT:
2065 /* This is the place where the final HALT needs to be inserted if
2066 * we've emitted any discards. If not, this will emit no code.
2067 */
2068 if (!patch_discard_jumps_to_fb_writes()) {
2069 if (unlikely(debug_flag)) {
2070 annotation.ann_count--;
2071 }
2072 }
2073 break;
2074
2075 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2076 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2077 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2078 break;
2079
2080 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2081 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2082 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2083 break;
2084
2085 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2086 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2087 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2088 break;
2089
2090 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2091 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2092 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2093 break;
2094
2095 default:
2096 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
2097 _mesa_problem(ctx, "Unsupported opcode `%s' in %s",
2098 opcode_descs[inst->opcode].name, stage_abbrev);
2099 } else {
2100 _mesa_problem(ctx, "Unsupported opcode %d in %s", inst->opcode,
2101 stage_abbrev);
2102 }
2103 abort();
2104
2105 case SHADER_OPCODE_LOAD_PAYLOAD:
2106 unreachable("Should be lowered by lower_load_payload()");
2107 }
2108
2109 if (multiple_instructions_emitted)
2110 continue;
2111
2112 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2113 assert(p->next_insn_offset == last_insn_offset + 16 ||
2114 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2115 "emitting more than 1 instruction");
2116
2117 brw_inst *last = &p->store[last_insn_offset / 16];
2118
2119 if (inst->conditional_mod)
2120 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
2121 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
2122 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
2123 }
2124 }
2125
2126 brw_set_uip_jip(p);
2127 annotation_finalize(&annotation, p->next_insn_offset);
2128
2129 int before_size = p->next_insn_offset - start_offset;
2130 brw_compact_instructions(p, start_offset, annotation.ann_count,
2131 annotation.ann);
2132 int after_size = p->next_insn_offset - start_offset;
2133
2134 if (unlikely(debug_flag)) {
2135 fprintf(stderr, "Native code for %s\n"
2136 "SIMD%d shader: %d instructions. %d loops. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2137 " bytes (%.0f%%)\n",
2138 shader_name, dispatch_width, before_size / 16, loop_count,
2139 spill_count, fill_count, promoted_constants, before_size, after_size,
2140 100.0f * (before_size - after_size) / before_size);
2141
2142 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
2143 ralloc_free(annotation.ann);
2144 }
2145
2146 static GLuint msg_id = 0;
2147 _mesa_gl_debug(&brw->ctx, &msg_id,
2148 MESA_DEBUG_SOURCE_SHADER_COMPILER,
2149 MESA_DEBUG_TYPE_OTHER,
2150 MESA_DEBUG_SEVERITY_NOTIFICATION,
2151 "%s SIMD%d shader: %d inst, %d loops, %d:%d spills:fills, "
2152 "Promoted %u constants, compacted %d to %d bytes.\n",
2153 stage_abbrev, dispatch_width, before_size / 16, loop_count,
2154 spill_count, fill_count, promoted_constants, before_size, after_size);
2155
2156 return start_offset;
2157 }
2158
2159 const unsigned *
2160 fs_generator::get_assembly(unsigned int *assembly_size)
2161 {
2162 return brw_get_program(p, assembly_size);
2163 }