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i965: Emit compaction stats without walking the assembly.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 void *mem_ctx,
41 const struct brw_wm_prog_key *key,
42 struct brw_wm_prog_data *prog_data,
43 struct gl_shader_program *prog,
44 struct gl_fragment_program *fp,
45 bool dual_source_output,
46 bool debug_flag)
47
48 : brw(brw), key(key), prog_data(prog_data), prog(prog), fp(fp),
49 dual_source_output(dual_source_output), debug_flag(debug_flag),
50 mem_ctx(mem_ctx)
51 {
52 ctx = &brw->ctx;
53
54 p = rzalloc(mem_ctx, struct brw_compile);
55 brw_init_compile(brw, p, mem_ctx);
56 }
57
58 fs_generator::~fs_generator()
59 {
60 }
61
62 bool
63 fs_generator::patch_discard_jumps_to_fb_writes()
64 {
65 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
66 return false;
67
68 /* There is a somewhat strange undocumented requirement of using
69 * HALT, according to the simulator. If some channel has HALTed to
70 * a particular UIP, then by the end of the program, every channel
71 * must have HALTed to that UIP. Furthermore, the tracking is a
72 * stack, so you can't do the final halt of a UIP after starting
73 * halting to a new UIP.
74 *
75 * Symptoms of not emitting this instruction on actual hardware
76 * included GPU hangs and sparkly rendering on the piglit discard
77 * tests.
78 */
79 struct brw_instruction *last_halt = gen6_HALT(p);
80 last_halt->bits3.break_cont.uip = 2;
81 last_halt->bits3.break_cont.jip = 2;
82
83 int ip = p->nr_insn;
84
85 foreach_list(node, &this->discard_halt_patches) {
86 ip_record *patch_ip = (ip_record *)node;
87 struct brw_instruction *patch = &p->store[patch_ip->ip];
88
89 assert(patch->header.opcode == BRW_OPCODE_HALT);
90 /* HALT takes a half-instruction distance from the pre-incremented IP. */
91 patch->bits3.break_cont.uip = (ip - patch_ip->ip) * 2;
92 }
93
94 this->discard_halt_patches.make_empty();
95 return true;
96 }
97
98 void
99 fs_generator::generate_fb_write(fs_inst *inst)
100 {
101 bool eot = inst->eot;
102 struct brw_reg implied_header;
103 uint32_t msg_control;
104
105 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
106 * move, here's g1.
107 */
108 brw_push_insn_state(p);
109 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
110 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
111 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
112
113 if (inst->header_present) {
114 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
115 * present.
116 */
117 if ((fp && fp->UsesKill) || key->alpha_test_func) {
118 struct brw_reg pixel_mask;
119
120 if (brw->gen >= 6)
121 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
122 else
123 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
124
125 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
126 }
127
128 if (brw->gen >= 6) {
129 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
130 brw_MOV(p,
131 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
132 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
133 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
134
135 if (inst->target > 0 && key->replicate_alpha) {
136 /* Set "Source0 Alpha Present to RenderTarget" bit in message
137 * header.
138 */
139 brw_OR(p,
140 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
141 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
142 brw_imm_ud(0x1 << 11));
143 }
144
145 if (inst->target > 0) {
146 /* Set the render target index for choosing BLEND_STATE. */
147 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
148 inst->base_mrf, 2),
149 BRW_REGISTER_TYPE_UD),
150 brw_imm_ud(inst->target));
151 }
152
153 implied_header = brw_null_reg();
154 } else {
155 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
156
157 brw_MOV(p,
158 brw_message_reg(inst->base_mrf + 1),
159 brw_vec8_grf(1, 0));
160 }
161 } else {
162 implied_header = brw_null_reg();
163 }
164
165 if (this->dual_source_output)
166 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
167 else if (dispatch_width == 16)
168 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
169 else
170 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
171
172 brw_pop_insn_state(p);
173
174 uint32_t surf_index =
175 prog_data->binding_table.render_target_start + inst->target;
176 brw_fb_WRITE(p,
177 dispatch_width,
178 inst->base_mrf,
179 implied_header,
180 msg_control,
181 surf_index,
182 inst->mlen,
183 0,
184 eot,
185 inst->header_present);
186
187 brw_mark_surface_used(&prog_data->base, surf_index);
188 }
189
190 void
191 fs_generator::generate_blorp_fb_write(fs_inst *inst)
192 {
193 brw_fb_WRITE(p,
194 16 /* dispatch_width */,
195 inst->base_mrf,
196 brw_reg_from_fs_reg(&inst->src[0]),
197 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
198 inst->target,
199 inst->mlen,
200 0,
201 true,
202 inst->header_present);
203 }
204
205 /* Computes the integer pixel x,y values from the origin.
206 *
207 * This is the basis of gl_FragCoord computation, but is also used
208 * pre-gen6 for computing the deltas from v0 for computing
209 * interpolation.
210 */
211 void
212 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
213 {
214 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
215 struct brw_reg src;
216 struct brw_reg deltas;
217
218 if (is_x) {
219 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
220 deltas = brw_imm_v(0x10101010);
221 } else {
222 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
223 deltas = brw_imm_v(0x11001100);
224 }
225
226 if (dispatch_width == 16) {
227 dst = vec16(dst);
228 }
229
230 /* We do this SIMD8 or SIMD16, but since the destination is UW we
231 * don't do compression in the SIMD16 case.
232 */
233 brw_push_insn_state(p);
234 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
235 brw_ADD(p, dst, src, deltas);
236 brw_pop_insn_state(p);
237 }
238
239 void
240 fs_generator::generate_linterp(fs_inst *inst,
241 struct brw_reg dst, struct brw_reg *src)
242 {
243 struct brw_reg delta_x = src[0];
244 struct brw_reg delta_y = src[1];
245 struct brw_reg interp = src[2];
246
247 if (brw->has_pln &&
248 delta_y.nr == delta_x.nr + 1 &&
249 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
250 brw_PLN(p, dst, interp, delta_x);
251 } else {
252 brw_LINE(p, brw_null_reg(), interp, delta_x);
253 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
254 }
255 }
256
257 void
258 fs_generator::generate_math1_gen7(fs_inst *inst,
259 struct brw_reg dst,
260 struct brw_reg src0)
261 {
262 assert(inst->mlen == 0);
263 brw_math(p, dst,
264 brw_math_function(inst->opcode),
265 0, src0,
266 BRW_MATH_DATA_VECTOR,
267 BRW_MATH_PRECISION_FULL);
268 }
269
270 void
271 fs_generator::generate_math2_gen7(fs_inst *inst,
272 struct brw_reg dst,
273 struct brw_reg src0,
274 struct brw_reg src1)
275 {
276 assert(inst->mlen == 0);
277 brw_math2(p, dst, brw_math_function(inst->opcode), src0, src1);
278 }
279
280 void
281 fs_generator::generate_math1_gen6(fs_inst *inst,
282 struct brw_reg dst,
283 struct brw_reg src0)
284 {
285 int op = brw_math_function(inst->opcode);
286
287 assert(inst->mlen == 0);
288
289 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
290 brw_math(p, dst,
291 op,
292 0, src0,
293 BRW_MATH_DATA_VECTOR,
294 BRW_MATH_PRECISION_FULL);
295
296 if (dispatch_width == 16) {
297 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
298 brw_math(p, sechalf(dst),
299 op,
300 0, sechalf(src0),
301 BRW_MATH_DATA_VECTOR,
302 BRW_MATH_PRECISION_FULL);
303 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
304 }
305 }
306
307 void
308 fs_generator::generate_math2_gen6(fs_inst *inst,
309 struct brw_reg dst,
310 struct brw_reg src0,
311 struct brw_reg src1)
312 {
313 int op = brw_math_function(inst->opcode);
314
315 assert(inst->mlen == 0);
316
317 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
318 brw_math2(p, dst, op, src0, src1);
319
320 if (dispatch_width == 16) {
321 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
322 brw_math2(p, sechalf(dst), op, sechalf(src0), sechalf(src1));
323 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
324 }
325 }
326
327 void
328 fs_generator::generate_math_gen4(fs_inst *inst,
329 struct brw_reg dst,
330 struct brw_reg src)
331 {
332 int op = brw_math_function(inst->opcode);
333
334 assert(inst->mlen >= 1);
335
336 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
337 brw_math(p, dst,
338 op,
339 inst->base_mrf, src,
340 BRW_MATH_DATA_VECTOR,
341 BRW_MATH_PRECISION_FULL);
342
343 if (dispatch_width == 16) {
344 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
345 brw_math(p, sechalf(dst),
346 op,
347 inst->base_mrf + 1, sechalf(src),
348 BRW_MATH_DATA_VECTOR,
349 BRW_MATH_PRECISION_FULL);
350
351 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
352 }
353 }
354
355 void
356 fs_generator::generate_math_g45(fs_inst *inst,
357 struct brw_reg dst,
358 struct brw_reg src)
359 {
360 if (inst->opcode == SHADER_OPCODE_POW ||
361 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
362 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
363 generate_math_gen4(inst, dst, src);
364 return;
365 }
366
367 int op = brw_math_function(inst->opcode);
368
369 assert(inst->mlen >= 1);
370
371 brw_math(p, dst,
372 op,
373 inst->base_mrf, src,
374 BRW_MATH_DATA_VECTOR,
375 BRW_MATH_PRECISION_FULL);
376 }
377
378 void
379 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
380 {
381 int msg_type = -1;
382 int rlen = 4;
383 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
384 uint32_t return_format;
385
386 switch (dst.type) {
387 case BRW_REGISTER_TYPE_D:
388 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
389 break;
390 case BRW_REGISTER_TYPE_UD:
391 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
392 break;
393 default:
394 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
395 break;
396 }
397
398 if (dispatch_width == 16 &&
399 !inst->force_uncompressed && !inst->force_sechalf)
400 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
401
402 if (brw->gen >= 5) {
403 switch (inst->opcode) {
404 case SHADER_OPCODE_TEX:
405 if (inst->shadow_compare) {
406 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
407 } else {
408 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
409 }
410 break;
411 case FS_OPCODE_TXB:
412 if (inst->shadow_compare) {
413 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
414 } else {
415 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
416 }
417 break;
418 case SHADER_OPCODE_TXL:
419 if (inst->shadow_compare) {
420 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
421 } else {
422 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
423 }
424 break;
425 case SHADER_OPCODE_TXS:
426 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
427 break;
428 case SHADER_OPCODE_TXD:
429 if (inst->shadow_compare) {
430 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
431 assert(brw->is_haswell);
432 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
433 } else {
434 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
435 }
436 break;
437 case SHADER_OPCODE_TXF:
438 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
439 break;
440 case SHADER_OPCODE_TXF_CMS:
441 if (brw->gen >= 7)
442 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
443 else
444 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
445 break;
446 case SHADER_OPCODE_TXF_UMS:
447 assert(brw->gen >= 7);
448 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
449 break;
450 case SHADER_OPCODE_TXF_MCS:
451 assert(brw->gen >= 7);
452 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
453 break;
454 case SHADER_OPCODE_LOD:
455 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
456 break;
457 case SHADER_OPCODE_TG4:
458 if (inst->shadow_compare) {
459 assert(brw->gen >= 7);
460 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
461 } else {
462 assert(brw->gen >= 6);
463 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
464 }
465 break;
466 case SHADER_OPCODE_TG4_OFFSET:
467 assert(brw->gen >= 7);
468 if (inst->shadow_compare) {
469 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
470 } else {
471 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
472 }
473 break;
474 default:
475 assert(!"not reached");
476 break;
477 }
478 } else {
479 switch (inst->opcode) {
480 case SHADER_OPCODE_TEX:
481 /* Note that G45 and older determines shadow compare and dispatch width
482 * from message length for most messages.
483 */
484 assert(dispatch_width == 8);
485 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
486 if (inst->shadow_compare) {
487 assert(inst->mlen == 6);
488 } else {
489 assert(inst->mlen <= 4);
490 }
491 break;
492 case FS_OPCODE_TXB:
493 if (inst->shadow_compare) {
494 assert(inst->mlen == 6);
495 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
496 } else {
497 assert(inst->mlen == 9);
498 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
499 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
500 }
501 break;
502 case SHADER_OPCODE_TXL:
503 if (inst->shadow_compare) {
504 assert(inst->mlen == 6);
505 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
506 } else {
507 assert(inst->mlen == 9);
508 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
509 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
510 }
511 break;
512 case SHADER_OPCODE_TXD:
513 /* There is no sample_d_c message; comparisons are done manually */
514 assert(inst->mlen == 7 || inst->mlen == 10);
515 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
516 break;
517 case SHADER_OPCODE_TXF:
518 assert(inst->mlen == 9);
519 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
520 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
521 break;
522 case SHADER_OPCODE_TXS:
523 assert(inst->mlen == 3);
524 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
525 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
526 break;
527 default:
528 assert(!"not reached");
529 break;
530 }
531 }
532 assert(msg_type != -1);
533
534 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
535 rlen = 8;
536 dst = vec16(dst);
537 }
538
539 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
540 /* The send-from-GRF for SIMD16 texturing with a header has an extra
541 * hardware register allocated to it, which we need to skip over (since
542 * our coordinates in the payload are in the even-numbered registers,
543 * and the header comes right before the first one).
544 */
545 assert(src.file == BRW_GENERAL_REGISTER_FILE);
546 src.nr++;
547 }
548
549 /* Load the message header if present. If there's a texture offset,
550 * we need to set it up explicitly and load the offset bitfield.
551 * Otherwise, we can use an implied move from g0 to the first message reg.
552 */
553 if (inst->header_present) {
554 if (brw->gen < 6 && !inst->texture_offset) {
555 /* Set up an implied move from g0 to the MRF. */
556 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
557 } else {
558 struct brw_reg header_reg;
559
560 if (brw->gen >= 7) {
561 header_reg = src;
562 } else {
563 assert(inst->base_mrf != -1);
564 header_reg = brw_message_reg(inst->base_mrf);
565 }
566
567 brw_push_insn_state(p);
568 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
569 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
570 /* Explicitly set up the message header by copying g0 to the MRF. */
571 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
572
573 if (inst->texture_offset) {
574 /* Set the offset bits in DWord 2. */
575 brw_MOV(p, get_element_ud(header_reg, 2),
576 brw_imm_ud(inst->texture_offset));
577 }
578
579 if (inst->sampler >= 16) {
580 /* The "Sampler Index" field can only store values between 0 and 15.
581 * However, we can add an offset to the "Sampler State Pointer"
582 * field, effectively selecting a different set of 16 samplers.
583 *
584 * The "Sampler State Pointer" needs to be aligned to a 32-byte
585 * offset, and each sampler state is only 16-bytes, so we can't
586 * exclusively use the offset - we have to use both.
587 */
588 assert(brw->is_haswell); /* field only exists on Haswell */
589 brw_ADD(p,
590 get_element_ud(header_reg, 3),
591 get_element_ud(brw_vec8_grf(0, 0), 3),
592 brw_imm_ud(16 * (inst->sampler / 16) *
593 sizeof(gen7_sampler_state)));
594 }
595 brw_pop_insn_state(p);
596 }
597 }
598
599 uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
600 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
601 ? prog_data->base.binding_table.gather_texture_start
602 : prog_data->base.binding_table.texture_start) + inst->sampler;
603
604 brw_SAMPLE(p,
605 retype(dst, BRW_REGISTER_TYPE_UW),
606 inst->base_mrf,
607 src,
608 surface_index,
609 inst->sampler % 16,
610 msg_type,
611 rlen,
612 inst->mlen,
613 inst->header_present,
614 simd_mode,
615 return_format);
616
617 brw_mark_surface_used(&prog_data->base, surface_index);
618 }
619
620
621 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
622 * looking like:
623 *
624 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
625 *
626 * Ideally, we want to produce:
627 *
628 * DDX DDY
629 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
630 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
631 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
632 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
633 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
634 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
635 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
636 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
637 *
638 * and add another set of two more subspans if in 16-pixel dispatch mode.
639 *
640 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
641 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
642 * pair. But the ideal approximation may impose a huge performance cost on
643 * sample_d. On at least Haswell, sample_d instruction does some
644 * optimizations if the same LOD is used for all pixels in the subspan.
645 *
646 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
647 * appropriate swizzling.
648 */
649 void
650 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
651 {
652 unsigned vstride, width;
653
654 if (key->high_quality_derivatives) {
655 /* produce accurate derivatives */
656 vstride = BRW_VERTICAL_STRIDE_2;
657 width = BRW_WIDTH_2;
658 }
659 else {
660 /* replicate the derivative at the top-left pixel to other pixels */
661 vstride = BRW_VERTICAL_STRIDE_4;
662 width = BRW_WIDTH_4;
663 }
664
665 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
666 BRW_REGISTER_TYPE_F,
667 vstride,
668 width,
669 BRW_HORIZONTAL_STRIDE_0,
670 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
671 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
672 BRW_REGISTER_TYPE_F,
673 vstride,
674 width,
675 BRW_HORIZONTAL_STRIDE_0,
676 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
677 brw_ADD(p, dst, src0, negate(src1));
678 }
679
680 /* The negate_value boolean is used to negate the derivative computation for
681 * FBOs, since they place the origin at the upper left instead of the lower
682 * left.
683 */
684 void
685 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
686 bool negate_value)
687 {
688 if (key->high_quality_derivatives) {
689 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
690 * Region Restrictions):
691 *
692 * In Align16 access mode, SIMD16 is not allowed for DW operations
693 * and SIMD8 is not allowed for DF operations.
694 *
695 * In this context, "DW operations" means "operations acting on 32-bit
696 * values", so it includes operations on floats.
697 *
698 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
699 * (Instruction Compression -> Rules and Restrictions):
700 *
701 * A compressed instruction must be in Align1 access mode. Align16
702 * mode instructions cannot be compressed.
703 *
704 * Similar text exists in the g45 PRM.
705 *
706 * On these platforms, if we're building a SIMD16 shader, we need to
707 * manually unroll to a pair of SIMD8 instructions.
708 */
709 bool unroll_to_simd8 =
710 (dispatch_width == 16 &&
711 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
712
713 /* produce accurate derivatives */
714 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
715 BRW_REGISTER_TYPE_F,
716 BRW_VERTICAL_STRIDE_4,
717 BRW_WIDTH_4,
718 BRW_HORIZONTAL_STRIDE_1,
719 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
720 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
721 BRW_REGISTER_TYPE_F,
722 BRW_VERTICAL_STRIDE_4,
723 BRW_WIDTH_4,
724 BRW_HORIZONTAL_STRIDE_1,
725 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
726 brw_push_insn_state(p);
727 brw_set_default_access_mode(p, BRW_ALIGN_16);
728 if (unroll_to_simd8)
729 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
730 if (negate_value)
731 brw_ADD(p, dst, src1, negate(src0));
732 else
733 brw_ADD(p, dst, src0, negate(src1));
734 if (unroll_to_simd8) {
735 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
736 src0 = sechalf(src0);
737 src1 = sechalf(src1);
738 dst = sechalf(dst);
739 if (negate_value)
740 brw_ADD(p, dst, src1, negate(src0));
741 else
742 brw_ADD(p, dst, src0, negate(src1));
743 }
744 brw_pop_insn_state(p);
745 } else {
746 /* replicate the derivative at the top-left pixel to other pixels */
747 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
748 BRW_REGISTER_TYPE_F,
749 BRW_VERTICAL_STRIDE_4,
750 BRW_WIDTH_4,
751 BRW_HORIZONTAL_STRIDE_0,
752 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
753 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
754 BRW_REGISTER_TYPE_F,
755 BRW_VERTICAL_STRIDE_4,
756 BRW_WIDTH_4,
757 BRW_HORIZONTAL_STRIDE_0,
758 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
759 if (negate_value)
760 brw_ADD(p, dst, src1, negate(src0));
761 else
762 brw_ADD(p, dst, src0, negate(src1));
763 }
764 }
765
766 void
767 fs_generator::generate_discard_jump(fs_inst *inst)
768 {
769 assert(brw->gen >= 6);
770
771 /* This HALT will be patched up at FB write time to point UIP at the end of
772 * the program, and at brw_uip_jip() JIP will be set to the end of the
773 * current block (or the program).
774 */
775 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
776
777 brw_push_insn_state(p);
778 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
779 gen6_HALT(p);
780 brw_pop_insn_state(p);
781 }
782
783 void
784 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
785 {
786 assert(inst->mlen != 0);
787
788 brw_MOV(p,
789 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
790 retype(src, BRW_REGISTER_TYPE_UD));
791 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
792 dispatch_width / 8, inst->offset);
793 }
794
795 void
796 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
797 {
798 assert(inst->mlen != 0);
799
800 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
801 dispatch_width / 8, inst->offset);
802 }
803
804 void
805 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
806 {
807 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
808 }
809
810 void
811 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
812 struct brw_reg dst,
813 struct brw_reg index,
814 struct brw_reg offset)
815 {
816 assert(inst->mlen != 0);
817
818 assert(index.file == BRW_IMMEDIATE_VALUE &&
819 index.type == BRW_REGISTER_TYPE_UD);
820 uint32_t surf_index = index.dw1.ud;
821
822 assert(offset.file == BRW_IMMEDIATE_VALUE &&
823 offset.type == BRW_REGISTER_TYPE_UD);
824 uint32_t read_offset = offset.dw1.ud;
825
826 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
827 read_offset, surf_index);
828
829 brw_mark_surface_used(&prog_data->base, surf_index);
830 }
831
832 void
833 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
834 struct brw_reg dst,
835 struct brw_reg index,
836 struct brw_reg offset)
837 {
838 assert(inst->mlen == 0);
839
840 assert(index.file == BRW_IMMEDIATE_VALUE &&
841 index.type == BRW_REGISTER_TYPE_UD);
842 uint32_t surf_index = index.dw1.ud;
843
844 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
845 /* Reference just the dword we need, to avoid angering validate_reg(). */
846 offset = brw_vec1_grf(offset.nr, 0);
847
848 brw_push_insn_state(p);
849 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
850 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
851 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
852 brw_pop_insn_state(p);
853
854 /* We use the SIMD4x2 mode because we want to end up with 4 components in
855 * the destination loaded consecutively from the same offset (which appears
856 * in the first component, and the rest are ignored).
857 */
858 dst.width = BRW_WIDTH_4;
859 brw_set_dest(p, send, dst);
860 brw_set_src0(p, send, offset);
861 brw_set_sampler_message(p, send,
862 surf_index,
863 0, /* LD message ignores sampler unit */
864 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
865 1, /* rlen */
866 1, /* mlen */
867 false, /* no header */
868 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
869 0);
870
871 brw_mark_surface_used(&prog_data->base, surf_index);
872 }
873
874 void
875 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
876 struct brw_reg dst,
877 struct brw_reg index,
878 struct brw_reg offset)
879 {
880 assert(brw->gen < 7); /* Should use the gen7 variant. */
881 assert(inst->header_present);
882 assert(inst->mlen);
883
884 assert(index.file == BRW_IMMEDIATE_VALUE &&
885 index.type == BRW_REGISTER_TYPE_UD);
886 uint32_t surf_index = index.dw1.ud;
887
888 uint32_t simd_mode, rlen, msg_type;
889 if (dispatch_width == 16) {
890 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
891 rlen = 8;
892 } else {
893 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
894 rlen = 4;
895 }
896
897 if (brw->gen >= 5)
898 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
899 else {
900 /* We always use the SIMD16 message so that we only have to load U, and
901 * not V or R.
902 */
903 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
904 assert(inst->mlen == 3);
905 assert(inst->regs_written == 8);
906 rlen = 8;
907 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
908 }
909
910 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
911 BRW_REGISTER_TYPE_D);
912 brw_MOV(p, offset_mrf, offset);
913
914 struct brw_reg header = brw_vec8_grf(0, 0);
915 gen6_resolve_implied_move(p, &header, inst->base_mrf);
916
917 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
918 send->header.compression_control = BRW_COMPRESSION_NONE;
919 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
920 brw_set_src0(p, send, header);
921 if (brw->gen < 6)
922 send->header.destreg__conditionalmod = inst->base_mrf;
923
924 /* Our surface is set up as floats, regardless of what actual data is
925 * stored in it.
926 */
927 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
928 brw_set_sampler_message(p, send,
929 surf_index,
930 0, /* sampler (unused) */
931 msg_type,
932 rlen,
933 inst->mlen,
934 inst->header_present,
935 simd_mode,
936 return_format);
937
938 brw_mark_surface_used(&prog_data->base, surf_index);
939 }
940
941 void
942 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
943 struct brw_reg dst,
944 struct brw_reg index,
945 struct brw_reg offset)
946 {
947 assert(brw->gen >= 7);
948 /* Varying-offset pull constant loads are treated as a normal expression on
949 * gen7, so the fact that it's a send message is hidden at the IR level.
950 */
951 assert(!inst->header_present);
952 assert(!inst->mlen);
953
954 assert(index.file == BRW_IMMEDIATE_VALUE &&
955 index.type == BRW_REGISTER_TYPE_UD);
956 uint32_t surf_index = index.dw1.ud;
957
958 uint32_t simd_mode, rlen, mlen;
959 if (dispatch_width == 16) {
960 mlen = 2;
961 rlen = 8;
962 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
963 } else {
964 mlen = 1;
965 rlen = 4;
966 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
967 }
968
969 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
970 brw_set_dest(p, send, dst);
971 brw_set_src0(p, send, offset);
972 brw_set_sampler_message(p, send,
973 surf_index,
974 0, /* LD message ignores sampler unit */
975 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
976 rlen,
977 mlen,
978 false, /* no header */
979 simd_mode,
980 0);
981
982 brw_mark_surface_used(&prog_data->base, surf_index);
983 }
984
985 /**
986 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
987 * into the flags register (f0.0).
988 *
989 * Used only on Gen6 and above.
990 */
991 void
992 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
993 {
994 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
995 struct brw_reg dispatch_mask;
996
997 if (brw->gen >= 6)
998 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
999 else
1000 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1001
1002 brw_push_insn_state(p);
1003 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1004 brw_MOV(p, flags, dispatch_mask);
1005 brw_pop_insn_state(p);
1006 }
1007
1008
1009 static uint32_t brw_file_from_reg(fs_reg *reg)
1010 {
1011 switch (reg->file) {
1012 case GRF:
1013 return BRW_GENERAL_REGISTER_FILE;
1014 case MRF:
1015 return BRW_MESSAGE_REGISTER_FILE;
1016 case IMM:
1017 return BRW_IMMEDIATE_VALUE;
1018 default:
1019 assert(!"not reached");
1020 return BRW_GENERAL_REGISTER_FILE;
1021 }
1022 }
1023
1024 struct brw_reg
1025 brw_reg_from_fs_reg(fs_reg *reg)
1026 {
1027 struct brw_reg brw_reg;
1028
1029 switch (reg->file) {
1030 case GRF:
1031 case MRF:
1032 if (reg->stride == 0) {
1033 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
1034 } else {
1035 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1036 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1037 }
1038
1039 brw_reg = retype(brw_reg, reg->type);
1040 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1041 break;
1042 case IMM:
1043 switch (reg->type) {
1044 case BRW_REGISTER_TYPE_F:
1045 brw_reg = brw_imm_f(reg->imm.f);
1046 break;
1047 case BRW_REGISTER_TYPE_D:
1048 brw_reg = brw_imm_d(reg->imm.i);
1049 break;
1050 case BRW_REGISTER_TYPE_UD:
1051 brw_reg = brw_imm_ud(reg->imm.u);
1052 break;
1053 default:
1054 assert(!"not reached");
1055 brw_reg = brw_null_reg();
1056 break;
1057 }
1058 break;
1059 case HW_REG:
1060 assert(reg->type == reg->fixed_hw_reg.type);
1061 brw_reg = reg->fixed_hw_reg;
1062 break;
1063 case BAD_FILE:
1064 /* Probably unused. */
1065 brw_reg = brw_null_reg();
1066 break;
1067 case UNIFORM:
1068 assert(!"not reached");
1069 brw_reg = brw_null_reg();
1070 break;
1071 default:
1072 assert(!"not reached");
1073 brw_reg = brw_null_reg();
1074 break;
1075 }
1076 if (reg->abs)
1077 brw_reg = brw_abs(brw_reg);
1078 if (reg->negate)
1079 brw_reg = negate(brw_reg);
1080
1081 return brw_reg;
1082 }
1083
1084 /**
1085 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1086 * sampler LD messages.
1087 *
1088 * We don't want to bake it into the send message's code generation because
1089 * that means we don't get a chance to schedule the instructions.
1090 */
1091 void
1092 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1093 struct brw_reg dst,
1094 struct brw_reg value)
1095 {
1096 assert(value.file == BRW_IMMEDIATE_VALUE);
1097
1098 brw_push_insn_state(p);
1099 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1100 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1101 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1102 brw_pop_insn_state(p);
1103 }
1104
1105 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1106 * (when mask is passed as a uniform) of register mask before moving it
1107 * to register dst.
1108 */
1109 void
1110 fs_generator::generate_set_omask(fs_inst *inst,
1111 struct brw_reg dst,
1112 struct brw_reg mask)
1113 {
1114 bool stride_8_8_1 =
1115 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1116 mask.width == BRW_WIDTH_8 &&
1117 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1118
1119 bool stride_0_1_0 =
1120 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1121 mask.width == BRW_WIDTH_1 &&
1122 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1123
1124 assert(stride_8_8_1 || stride_0_1_0);
1125 assert(dst.type == BRW_REGISTER_TYPE_UW);
1126
1127 if (dispatch_width == 16)
1128 dst = vec16(dst);
1129 brw_push_insn_state(p);
1130 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1131 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1132
1133 if (stride_8_8_1) {
1134 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1135 } else if (stride_0_1_0) {
1136 brw_MOV(p, dst, retype(mask, dst.type));
1137 }
1138 brw_pop_insn_state(p);
1139 }
1140
1141 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1142 * the ADD instruction.
1143 */
1144 void
1145 fs_generator::generate_set_sample_id(fs_inst *inst,
1146 struct brw_reg dst,
1147 struct brw_reg src0,
1148 struct brw_reg src1)
1149 {
1150 assert(dst.type == BRW_REGISTER_TYPE_D ||
1151 dst.type == BRW_REGISTER_TYPE_UD);
1152 assert(src0.type == BRW_REGISTER_TYPE_D ||
1153 src0.type == BRW_REGISTER_TYPE_UD);
1154
1155 brw_push_insn_state(p);
1156 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1157 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1158 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1159 brw_ADD(p, dst, src0, reg);
1160 if (dispatch_width == 16)
1161 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1162 brw_pop_insn_state(p);
1163 }
1164
1165 /**
1166 * Change the register's data type from UD to W, doubling the strides in order
1167 * to compensate for halving the data type width.
1168 */
1169 static struct brw_reg
1170 ud_reg_to_w(struct brw_reg r)
1171 {
1172 assert(r.type == BRW_REGISTER_TYPE_UD);
1173 r.type = BRW_REGISTER_TYPE_W;
1174
1175 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1176 * doubles the real stride.
1177 */
1178 if (r.hstride != 0)
1179 ++r.hstride;
1180 if (r.vstride != 0)
1181 ++r.vstride;
1182
1183 return r;
1184 }
1185
1186 void
1187 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1188 struct brw_reg dst,
1189 struct brw_reg x,
1190 struct brw_reg y)
1191 {
1192 assert(brw->gen >= 7);
1193 assert(dst.type == BRW_REGISTER_TYPE_UD);
1194 assert(x.type == BRW_REGISTER_TYPE_F);
1195 assert(y.type == BRW_REGISTER_TYPE_F);
1196
1197 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1198 *
1199 * Because this instruction does not have a 16-bit floating-point type,
1200 * the destination data type must be Word (W).
1201 *
1202 * The destination must be DWord-aligned and specify a horizontal stride
1203 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1204 * each destination channel and the upper word is not modified.
1205 */
1206 struct brw_reg dst_w = ud_reg_to_w(dst);
1207
1208 /* Give each 32-bit channel of dst the form below , where "." means
1209 * unchanged.
1210 * 0x....hhhh
1211 */
1212 brw_F32TO16(p, dst_w, y);
1213
1214 /* Now the form:
1215 * 0xhhhh0000
1216 */
1217 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1218
1219 /* And, finally the form of packHalf2x16's output:
1220 * 0xhhhhllll
1221 */
1222 brw_F32TO16(p, dst_w, x);
1223 }
1224
1225 void
1226 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1227 struct brw_reg dst,
1228 struct brw_reg src)
1229 {
1230 assert(brw->gen >= 7);
1231 assert(dst.type == BRW_REGISTER_TYPE_F);
1232 assert(src.type == BRW_REGISTER_TYPE_UD);
1233
1234 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1235 *
1236 * Because this instruction does not have a 16-bit floating-point type,
1237 * the source data type must be Word (W). The destination type must be
1238 * F (Float).
1239 */
1240 struct brw_reg src_w = ud_reg_to_w(src);
1241
1242 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1243 * For the Y case, we wish to access only the upper word; therefore
1244 * a 16-bit subregister offset is needed.
1245 */
1246 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1247 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1248 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1249 src_w.subnr += 2;
1250
1251 brw_F16TO32(p, dst, src_w);
1252 }
1253
1254 void
1255 fs_generator::generate_shader_time_add(fs_inst *inst,
1256 struct brw_reg payload,
1257 struct brw_reg offset,
1258 struct brw_reg value)
1259 {
1260 assert(brw->gen >= 7);
1261 brw_push_insn_state(p);
1262 brw_set_default_mask_control(p, true);
1263
1264 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1265 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1266 offset.type);
1267 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1268 value.type);
1269
1270 assert(offset.file == BRW_IMMEDIATE_VALUE);
1271 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1272 value.width = BRW_WIDTH_1;
1273 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1274 value.vstride = BRW_VERTICAL_STRIDE_0;
1275 } else {
1276 assert(value.file == BRW_IMMEDIATE_VALUE);
1277 }
1278
1279 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1280 * case, and we don't really care about squeezing every bit of performance
1281 * out of this path, so we just emit the MOVs from here.
1282 */
1283 brw_MOV(p, payload_offset, offset);
1284 brw_MOV(p, payload_value, value);
1285 brw_shader_time_add(p, payload,
1286 prog_data->base.binding_table.shader_time_start);
1287 brw_pop_insn_state(p);
1288
1289 brw_mark_surface_used(&prog_data->base,
1290 prog_data->base.binding_table.shader_time_start);
1291 }
1292
1293 void
1294 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1295 struct brw_reg atomic_op,
1296 struct brw_reg surf_index)
1297 {
1298 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1299 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1300 surf_index.file == BRW_IMMEDIATE_VALUE &&
1301 surf_index.type == BRW_REGISTER_TYPE_UD);
1302
1303 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1304 atomic_op.dw1.ud, surf_index.dw1.ud,
1305 inst->mlen, dispatch_width / 8);
1306
1307 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1308 }
1309
1310 void
1311 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1312 struct brw_reg surf_index)
1313 {
1314 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1315 surf_index.type == BRW_REGISTER_TYPE_UD);
1316
1317 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1318 surf_index.dw1.ud,
1319 inst->mlen, dispatch_width / 8);
1320
1321 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1322 }
1323
1324 void
1325 fs_generator::generate_code(exec_list *instructions)
1326 {
1327 int start_offset = p->next_insn_offset;
1328
1329 struct annotation_info annotation;
1330 memset(&annotation, 0, sizeof(annotation));
1331
1332 cfg_t *cfg = NULL;
1333 if (unlikely(debug_flag))
1334 cfg = new(mem_ctx) cfg_t(instructions);
1335
1336 foreach_list(node, instructions) {
1337 fs_inst *inst = (fs_inst *)node;
1338 struct brw_reg src[3], dst;
1339 unsigned int last_insn_offset = p->next_insn_offset;
1340
1341 if (unlikely(debug_flag))
1342 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1343
1344 for (unsigned int i = 0; i < inst->sources; i++) {
1345 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1346
1347 /* The accumulator result appears to get used for the
1348 * conditional modifier generation. When negating a UD
1349 * value, there is a 33rd bit generated for the sign in the
1350 * accumulator value, so now you can't check, for example,
1351 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1352 */
1353 assert(!inst->conditional_mod ||
1354 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1355 !inst->src[i].negate);
1356 }
1357 dst = brw_reg_from_fs_reg(&inst->dst);
1358
1359 brw_set_default_predicate_control(p, inst->predicate);
1360 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1361 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1362 brw_set_default_saturate(p, inst->saturate);
1363 brw_set_default_mask_control(p, inst->force_writemask_all);
1364 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1365
1366 if (inst->force_uncompressed || dispatch_width == 8) {
1367 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1368 } else if (inst->force_sechalf) {
1369 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1370 } else {
1371 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1372 }
1373
1374 switch (inst->opcode) {
1375 case BRW_OPCODE_MOV:
1376 brw_MOV(p, dst, src[0]);
1377 break;
1378 case BRW_OPCODE_ADD:
1379 brw_ADD(p, dst, src[0], src[1]);
1380 break;
1381 case BRW_OPCODE_MUL:
1382 brw_MUL(p, dst, src[0], src[1]);
1383 break;
1384 case BRW_OPCODE_AVG:
1385 brw_AVG(p, dst, src[0], src[1]);
1386 break;
1387 case BRW_OPCODE_MACH:
1388 brw_MACH(p, dst, src[0], src[1]);
1389 break;
1390
1391 case BRW_OPCODE_MAD:
1392 assert(brw->gen >= 6);
1393 brw_set_default_access_mode(p, BRW_ALIGN_16);
1394 if (dispatch_width == 16 && !brw->is_haswell) {
1395 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1396 brw_MAD(p, dst, src[0], src[1], src[2]);
1397 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1398 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1399 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1400 } else {
1401 brw_MAD(p, dst, src[0], src[1], src[2]);
1402 }
1403 brw_set_default_access_mode(p, BRW_ALIGN_1);
1404 break;
1405
1406 case BRW_OPCODE_LRP:
1407 assert(brw->gen >= 6);
1408 brw_set_default_access_mode(p, BRW_ALIGN_16);
1409 if (dispatch_width == 16 && !brw->is_haswell) {
1410 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1411 brw_LRP(p, dst, src[0], src[1], src[2]);
1412 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1413 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1414 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1415 } else {
1416 brw_LRP(p, dst, src[0], src[1], src[2]);
1417 }
1418 brw_set_default_access_mode(p, BRW_ALIGN_1);
1419 break;
1420
1421 case BRW_OPCODE_FRC:
1422 brw_FRC(p, dst, src[0]);
1423 break;
1424 case BRW_OPCODE_RNDD:
1425 brw_RNDD(p, dst, src[0]);
1426 break;
1427 case BRW_OPCODE_RNDE:
1428 brw_RNDE(p, dst, src[0]);
1429 break;
1430 case BRW_OPCODE_RNDZ:
1431 brw_RNDZ(p, dst, src[0]);
1432 break;
1433
1434 case BRW_OPCODE_AND:
1435 brw_AND(p, dst, src[0], src[1]);
1436 break;
1437 case BRW_OPCODE_OR:
1438 brw_OR(p, dst, src[0], src[1]);
1439 break;
1440 case BRW_OPCODE_XOR:
1441 brw_XOR(p, dst, src[0], src[1]);
1442 break;
1443 case BRW_OPCODE_NOT:
1444 brw_NOT(p, dst, src[0]);
1445 break;
1446 case BRW_OPCODE_ASR:
1447 brw_ASR(p, dst, src[0], src[1]);
1448 break;
1449 case BRW_OPCODE_SHR:
1450 brw_SHR(p, dst, src[0], src[1]);
1451 break;
1452 case BRW_OPCODE_SHL:
1453 brw_SHL(p, dst, src[0], src[1]);
1454 break;
1455 case BRW_OPCODE_F32TO16:
1456 assert(brw->gen >= 7);
1457 brw_F32TO16(p, dst, src[0]);
1458 break;
1459 case BRW_OPCODE_F16TO32:
1460 assert(brw->gen >= 7);
1461 brw_F16TO32(p, dst, src[0]);
1462 break;
1463 case BRW_OPCODE_CMP:
1464 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1465 break;
1466 case BRW_OPCODE_SEL:
1467 brw_SEL(p, dst, src[0], src[1]);
1468 break;
1469 case BRW_OPCODE_BFREV:
1470 assert(brw->gen >= 7);
1471 /* BFREV only supports UD type for src and dst. */
1472 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1473 retype(src[0], BRW_REGISTER_TYPE_UD));
1474 break;
1475 case BRW_OPCODE_FBH:
1476 assert(brw->gen >= 7);
1477 /* FBH only supports UD type for dst. */
1478 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1479 break;
1480 case BRW_OPCODE_FBL:
1481 assert(brw->gen >= 7);
1482 /* FBL only supports UD type for dst. */
1483 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1484 break;
1485 case BRW_OPCODE_CBIT:
1486 assert(brw->gen >= 7);
1487 /* CBIT only supports UD type for dst. */
1488 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1489 break;
1490 case BRW_OPCODE_ADDC:
1491 assert(brw->gen >= 7);
1492 brw_ADDC(p, dst, src[0], src[1]);
1493 break;
1494 case BRW_OPCODE_SUBB:
1495 assert(brw->gen >= 7);
1496 brw_SUBB(p, dst, src[0], src[1]);
1497 break;
1498 case BRW_OPCODE_MAC:
1499 brw_MAC(p, dst, src[0], src[1]);
1500 break;
1501
1502 case BRW_OPCODE_BFE:
1503 assert(brw->gen >= 7);
1504 brw_set_default_access_mode(p, BRW_ALIGN_16);
1505 if (dispatch_width == 16 && !brw->is_haswell) {
1506 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1507 brw_BFE(p, dst, src[0], src[1], src[2]);
1508 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1509 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1510 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1511 } else {
1512 brw_BFE(p, dst, src[0], src[1], src[2]);
1513 }
1514 brw_set_default_access_mode(p, BRW_ALIGN_1);
1515 break;
1516
1517 case BRW_OPCODE_BFI1:
1518 assert(brw->gen >= 7);
1519 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1520 * should
1521 *
1522 * "Force BFI instructions to be executed always in SIMD8."
1523 */
1524 if (dispatch_width == 16 && brw->is_haswell) {
1525 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1526 brw_BFI1(p, dst, src[0], src[1]);
1527 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1528 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1529 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1530 } else {
1531 brw_BFI1(p, dst, src[0], src[1]);
1532 }
1533 break;
1534 case BRW_OPCODE_BFI2:
1535 assert(brw->gen >= 7);
1536 brw_set_default_access_mode(p, BRW_ALIGN_16);
1537 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1538 * should
1539 *
1540 * "Force BFI instructions to be executed always in SIMD8."
1541 *
1542 * Otherwise we would be able to emit compressed instructions like we
1543 * do for the other three-source instructions.
1544 */
1545 if (dispatch_width == 16) {
1546 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1547 brw_BFI2(p, dst, src[0], src[1], src[2]);
1548 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1549 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1550 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1551 } else {
1552 brw_BFI2(p, dst, src[0], src[1], src[2]);
1553 }
1554 brw_set_default_access_mode(p, BRW_ALIGN_1);
1555 break;
1556
1557 case BRW_OPCODE_IF:
1558 if (inst->src[0].file != BAD_FILE) {
1559 /* The instruction has an embedded compare (only allowed on gen6) */
1560 assert(brw->gen == 6);
1561 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1562 } else {
1563 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1564 }
1565 break;
1566
1567 case BRW_OPCODE_ELSE:
1568 brw_ELSE(p);
1569 break;
1570 case BRW_OPCODE_ENDIF:
1571 brw_ENDIF(p);
1572 break;
1573
1574 case BRW_OPCODE_DO:
1575 brw_DO(p, BRW_EXECUTE_8);
1576 break;
1577
1578 case BRW_OPCODE_BREAK:
1579 brw_BREAK(p);
1580 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1581 break;
1582 case BRW_OPCODE_CONTINUE:
1583 /* FINISHME: We need to write the loop instruction support still. */
1584 if (brw->gen >= 6)
1585 gen6_CONT(p);
1586 else
1587 brw_CONT(p);
1588 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1589 break;
1590
1591 case BRW_OPCODE_WHILE:
1592 brw_WHILE(p);
1593 break;
1594
1595 case SHADER_OPCODE_RCP:
1596 case SHADER_OPCODE_RSQ:
1597 case SHADER_OPCODE_SQRT:
1598 case SHADER_OPCODE_EXP2:
1599 case SHADER_OPCODE_LOG2:
1600 case SHADER_OPCODE_SIN:
1601 case SHADER_OPCODE_COS:
1602 if (brw->gen >= 7) {
1603 generate_math1_gen7(inst, dst, src[0]);
1604 } else if (brw->gen == 6) {
1605 generate_math1_gen6(inst, dst, src[0]);
1606 } else if (brw->gen == 5 || brw->is_g4x) {
1607 generate_math_g45(inst, dst, src[0]);
1608 } else {
1609 generate_math_gen4(inst, dst, src[0]);
1610 }
1611 break;
1612 case SHADER_OPCODE_INT_QUOTIENT:
1613 case SHADER_OPCODE_INT_REMAINDER:
1614 case SHADER_OPCODE_POW:
1615 if (brw->gen >= 7) {
1616 generate_math2_gen7(inst, dst, src[0], src[1]);
1617 } else if (brw->gen == 6) {
1618 generate_math2_gen6(inst, dst, src[0], src[1]);
1619 } else {
1620 generate_math_gen4(inst, dst, src[0]);
1621 }
1622 break;
1623 case FS_OPCODE_PIXEL_X:
1624 generate_pixel_xy(dst, true);
1625 break;
1626 case FS_OPCODE_PIXEL_Y:
1627 generate_pixel_xy(dst, false);
1628 break;
1629 case FS_OPCODE_CINTERP:
1630 brw_MOV(p, dst, src[0]);
1631 break;
1632 case FS_OPCODE_LINTERP:
1633 generate_linterp(inst, dst, src);
1634 break;
1635 case SHADER_OPCODE_TEX:
1636 case FS_OPCODE_TXB:
1637 case SHADER_OPCODE_TXD:
1638 case SHADER_OPCODE_TXF:
1639 case SHADER_OPCODE_TXF_CMS:
1640 case SHADER_OPCODE_TXF_UMS:
1641 case SHADER_OPCODE_TXF_MCS:
1642 case SHADER_OPCODE_TXL:
1643 case SHADER_OPCODE_TXS:
1644 case SHADER_OPCODE_LOD:
1645 case SHADER_OPCODE_TG4:
1646 case SHADER_OPCODE_TG4_OFFSET:
1647 generate_tex(inst, dst, src[0]);
1648 break;
1649 case FS_OPCODE_DDX:
1650 generate_ddx(inst, dst, src[0]);
1651 break;
1652 case FS_OPCODE_DDY:
1653 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1654 * guarantee that key->render_to_fbo is set).
1655 */
1656 assert(fp->UsesDFdy);
1657 generate_ddy(inst, dst, src[0], key->render_to_fbo);
1658 break;
1659
1660 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1661 generate_scratch_write(inst, src[0]);
1662 break;
1663
1664 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1665 generate_scratch_read(inst, dst);
1666 break;
1667
1668 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1669 generate_scratch_read_gen7(inst, dst);
1670 break;
1671
1672 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1673 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1674 break;
1675
1676 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1677 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1678 break;
1679
1680 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1681 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1682 break;
1683
1684 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1685 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1686 break;
1687
1688 case FS_OPCODE_FB_WRITE:
1689 generate_fb_write(inst);
1690 break;
1691
1692 case FS_OPCODE_BLORP_FB_WRITE:
1693 generate_blorp_fb_write(inst);
1694 break;
1695
1696 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1697 generate_mov_dispatch_to_flags(inst);
1698 break;
1699
1700 case FS_OPCODE_DISCARD_JUMP:
1701 generate_discard_jump(inst);
1702 break;
1703
1704 case SHADER_OPCODE_SHADER_TIME_ADD:
1705 generate_shader_time_add(inst, src[0], src[1], src[2]);
1706 break;
1707
1708 case SHADER_OPCODE_UNTYPED_ATOMIC:
1709 generate_untyped_atomic(inst, dst, src[0], src[1]);
1710 break;
1711
1712 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1713 generate_untyped_surface_read(inst, dst, src[0]);
1714 break;
1715
1716 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1717 generate_set_simd4x2_offset(inst, dst, src[0]);
1718 break;
1719
1720 case FS_OPCODE_SET_OMASK:
1721 generate_set_omask(inst, dst, src[0]);
1722 break;
1723
1724 case FS_OPCODE_SET_SAMPLE_ID:
1725 generate_set_sample_id(inst, dst, src[0], src[1]);
1726 break;
1727
1728 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1729 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1730 break;
1731
1732 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1733 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1734 generate_unpack_half_2x16_split(inst, dst, src[0]);
1735 break;
1736
1737 case FS_OPCODE_PLACEHOLDER_HALT:
1738 /* This is the place where the final HALT needs to be inserted if
1739 * we've emitted any discards. If not, this will emit no code.
1740 */
1741 if (!patch_discard_jumps_to_fb_writes()) {
1742 if (unlikely(debug_flag)) {
1743 annotation.ann_count--;
1744 }
1745 }
1746 break;
1747
1748 default:
1749 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1750 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1751 opcode_descs[inst->opcode].name);
1752 } else {
1753 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1754 }
1755 abort();
1756 }
1757
1758 if (inst->conditional_mod) {
1759 /* Set the conditional modifier on the last instruction we generated.
1760 * Also, make sure we only emitted one instruction - anything else
1761 * doesn't make sense.
1762 */
1763 assert(p->next_insn_offset == last_insn_offset + 16);
1764 struct brw_instruction *last = &p->store[last_insn_offset / 16];
1765 last->header.destreg__conditionalmod = inst->conditional_mod;
1766 }
1767 }
1768
1769 brw_set_uip_jip(p);
1770 annotation_finalize(&annotation, p->next_insn_offset);
1771
1772 int before_size = p->next_insn_offset - start_offset;
1773 brw_compact_instructions(p, start_offset, annotation.ann_count,
1774 annotation.ann);
1775 int after_size = p->next_insn_offset - start_offset;
1776
1777 if (unlikely(debug_flag)) {
1778 if (prog) {
1779 fprintf(stderr,
1780 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
1781 prog->Label ? prog->Label : "unnamed",
1782 prog->Name, dispatch_width);
1783 } else if (fp) {
1784 fprintf(stderr,
1785 "Native code for fragment program %d (SIMD%d dispatch):\n",
1786 fp->Base.Id, dispatch_width);
1787 } else {
1788 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
1789 dispatch_width);
1790 }
1791 fprintf(stderr, "SIMD%d shader: %d instructions. Compacted %d to %d"
1792 " bytes (%.0f%%)\n",
1793 dispatch_width, before_size / 16, before_size, after_size,
1794 100.0f * (before_size - after_size) / before_size);
1795
1796 const struct gl_program *prog = fp ? &fp->Base : NULL;
1797
1798 dump_assembly(p->store, annotation.ann_count, annotation.ann,
1799 brw, prog, brw_disassemble);
1800 ralloc_free(annotation.ann);
1801 }
1802 }
1803
1804 const unsigned *
1805 fs_generator::generate_assembly(exec_list *simd8_instructions,
1806 exec_list *simd16_instructions,
1807 unsigned *assembly_size)
1808 {
1809 assert(simd8_instructions || simd16_instructions);
1810
1811 if (simd8_instructions) {
1812 dispatch_width = 8;
1813 generate_code(simd8_instructions);
1814 }
1815
1816 if (simd16_instructions) {
1817 /* align to 64 byte boundary. */
1818 while (p->next_insn_offset % 64) {
1819 brw_NOP(p);
1820 }
1821
1822 /* Save off the start of this SIMD16 program */
1823 prog_data->prog_offset_16 = p->next_insn_offset;
1824
1825 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1826
1827 dispatch_width = 16;
1828 generate_code(simd16_instructions);
1829 }
1830
1831 return brw_get_program(p, assembly_size);
1832 }