2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
30 #include "main/macros.h"
31 #include "brw_context.h"
36 static uint32_t brw_file_from_reg(fs_reg
*reg
)
40 return BRW_GENERAL_REGISTER_FILE
;
42 return BRW_MESSAGE_REGISTER_FILE
;
44 return BRW_IMMEDIATE_VALUE
;
46 unreachable("not reached");
51 brw_reg_from_fs_reg(fs_reg
*reg
)
53 struct brw_reg brw_reg
;
58 if (reg
->stride
== 0) {
59 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
60 } else if (reg
->width
< 8) {
61 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
62 brw_reg
= stride(brw_reg
, reg
->width
* reg
->stride
,
63 reg
->width
, reg
->stride
);
65 /* From the Haswell PRM:
67 * VertStride must be used to cross GRF register boundaries. This
68 * rule implies that elements within a 'Width' cannot cross GRF
71 * So, for registers with width > 8, we have to use a width of 8
72 * and trust the compression state to sort out the exec size.
74 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
75 brw_reg
= stride(brw_reg
, 8 * reg
->stride
, 8, reg
->stride
);
78 brw_reg
= retype(brw_reg
, reg
->type
);
79 brw_reg
= byte_offset(brw_reg
, reg
->subreg_offset
);
83 case BRW_REGISTER_TYPE_F
:
84 brw_reg
= brw_imm_f(reg
->fixed_hw_reg
.dw1
.f
);
86 case BRW_REGISTER_TYPE_D
:
87 brw_reg
= brw_imm_d(reg
->fixed_hw_reg
.dw1
.d
);
89 case BRW_REGISTER_TYPE_UD
:
90 brw_reg
= brw_imm_ud(reg
->fixed_hw_reg
.dw1
.ud
);
92 case BRW_REGISTER_TYPE_W
:
93 brw_reg
= brw_imm_w(reg
->fixed_hw_reg
.dw1
.d
);
95 case BRW_REGISTER_TYPE_UW
:
96 brw_reg
= brw_imm_uw(reg
->fixed_hw_reg
.dw1
.ud
);
98 case BRW_REGISTER_TYPE_VF
:
99 brw_reg
= brw_imm_vf(reg
->fixed_hw_reg
.dw1
.ud
);
102 unreachable("not reached");
106 assert(reg
->type
== reg
->fixed_hw_reg
.type
);
107 brw_reg
= reg
->fixed_hw_reg
;
110 /* Probably unused. */
111 brw_reg
= brw_null_reg();
114 unreachable("not reached");
117 brw_reg
= brw_abs(brw_reg
);
119 brw_reg
= negate(brw_reg
);
124 fs_generator::fs_generator(struct brw_context
*brw
,
127 struct brw_stage_prog_data
*prog_data
,
128 struct gl_program
*prog
,
129 unsigned promoted_constants
,
130 bool runtime_check_aads_emit
,
131 const char *stage_abbrev
)
133 : brw(brw
), devinfo(brw
->intelScreen
->devinfo
), key(key
),
134 prog_data(prog_data
),
135 prog(prog
), promoted_constants(promoted_constants
),
136 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
137 stage_abbrev(stage_abbrev
), mem_ctx(mem_ctx
)
139 p
= rzalloc(mem_ctx
, struct brw_codegen
);
140 brw_init_codegen(devinfo
, p
, mem_ctx
);
143 fs_generator::~fs_generator()
147 class ip_record
: public exec_node
{
149 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
160 fs_generator::patch_discard_jumps_to_fb_writes()
162 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
165 int scale
= brw_jump_scale(p
->devinfo
);
167 /* There is a somewhat strange undocumented requirement of using
168 * HALT, according to the simulator. If some channel has HALTed to
169 * a particular UIP, then by the end of the program, every channel
170 * must have HALTed to that UIP. Furthermore, the tracking is a
171 * stack, so you can't do the final halt of a UIP after starting
172 * halting to a new UIP.
174 * Symptoms of not emitting this instruction on actual hardware
175 * included GPU hangs and sparkly rendering on the piglit discard
178 brw_inst
*last_halt
= gen6_HALT(p
);
179 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
180 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
184 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
185 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
187 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
188 /* HALT takes a half-instruction distance from the pre-incremented IP. */
189 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
192 this->discard_halt_patches
.make_empty();
197 fs_generator::fire_fb_write(fs_inst
*inst
,
198 struct brw_reg payload
,
199 struct brw_reg implied_header
,
202 uint32_t msg_control
;
204 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
206 if (devinfo
->gen
< 6) {
207 brw_push_insn_state(p
);
208 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
209 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
210 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
211 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
212 brw_MOV(p
, offset(payload
, 1), brw_vec8_grf(1, 0));
213 brw_pop_insn_state(p
);
216 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
)
217 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
218 else if (prog_data
->dual_src_blend
) {
219 if (dispatch_width
== 8 || !inst
->eot
)
220 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
222 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
223 } else if (dispatch_width
== 16)
224 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
226 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
228 uint32_t surf_index
=
229 prog_data
->binding_table
.render_target_start
+ inst
->target
;
231 bool last_render_target
= inst
->eot
||
232 (prog_data
->dual_src_blend
&& dispatch_width
== 16);
245 inst
->header_size
!= 0);
247 brw_mark_surface_used(&prog_data
->base
, surf_index
);
251 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
253 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
254 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
255 struct brw_reg implied_header
;
257 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
258 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
261 if (inst
->base_mrf
>= 0)
262 payload
= brw_message_reg(inst
->base_mrf
);
264 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
267 if (inst
->header_size
!= 0) {
268 brw_push_insn_state(p
);
269 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
270 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
271 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
272 brw_set_default_flag_reg(p
, 0, 0);
274 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
277 if (prog_data
->uses_kill
) {
278 struct brw_reg pixel_mask
;
280 if (devinfo
->gen
>= 6)
281 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
283 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
285 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
288 if (devinfo
->gen
>= 6) {
289 brw_push_insn_state(p
);
290 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
291 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
293 retype(payload
, BRW_REGISTER_TYPE_UD
),
294 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
295 brw_pop_insn_state(p
);
297 if (inst
->target
> 0 && key
->replicate_alpha
) {
298 /* Set "Source0 Alpha Present to RenderTarget" bit in message
302 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
303 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
304 brw_imm_ud(0x1 << 11));
307 if (inst
->target
> 0) {
308 /* Set the render target index for choosing BLEND_STATE. */
309 brw_MOV(p
, retype(vec1(suboffset(payload
, 2)),
310 BRW_REGISTER_TYPE_UD
),
311 brw_imm_ud(inst
->target
));
314 implied_header
= brw_null_reg();
316 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
319 brw_pop_insn_state(p
);
321 implied_header
= brw_null_reg();
324 if (!runtime_check_aads_emit
) {
325 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
327 /* This can only happen in gen < 6 */
328 assert(devinfo
->gen
< 6);
330 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
332 /* Check runtime bit to detect if we have to send AA data or not */
333 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
336 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
338 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
340 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
341 brw_inst_set_exec_size(p
->devinfo
, brw_last_inst
, BRW_EXECUTE_1
);
343 /* Don't send AA data */
344 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
346 brw_land_fwd_jump(p
, jmp
);
347 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
352 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
356 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
358 brw_set_dest(p
, insn
, brw_null_reg());
359 brw_set_src0(p
, insn
, payload
);
360 brw_set_src1(p
, insn
, brw_imm_d(0));
362 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
363 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
365 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
366 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
367 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
368 brw_inst_set_header_present(p
->devinfo
, insn
, true);
369 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
373 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
375 struct brw_inst
*insn
;
377 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
379 brw_set_dest(p
, insn
, brw_null_reg());
380 brw_set_src0(p
, insn
, payload
);
381 brw_set_src1(p
, insn
, brw_imm_d(0));
383 /* Terminate a compute shader by sending a message to the thread spawner.
385 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
386 brw_inst_set_mlen(devinfo
, insn
, 1);
387 brw_inst_set_rlen(devinfo
, insn
, 0);
388 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
389 brw_inst_set_header_present(devinfo
, insn
, false);
391 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
392 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
394 /* Note that even though the thread has a URB resource associated with it,
395 * we set the "do not dereference URB" bit, because the URB resource is
396 * managed by the fixed-function unit, so it will free it automatically.
398 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
400 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
404 fs_generator::generate_blorp_fb_write(fs_inst
*inst
)
407 16 /* dispatch_width */,
408 brw_message_reg(inst
->base_mrf
),
409 brw_reg_from_fs_reg(&inst
->src
[0]),
410 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
416 inst
->header_size
!= 0);
420 fs_generator::generate_linterp(fs_inst
*inst
,
421 struct brw_reg dst
, struct brw_reg
*src
)
425 * -----------------------------------
426 * | src1+0 | src1+1 | src1+2 | src1+3 |
427 * |-----------------------------------|
428 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
429 * -----------------------------------
431 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
433 * -----------------------------------
434 * | src1+0 | src1+1 | src1+2 | src1+3 |
435 * |-----------------------------------|
436 * |(x0, x1)|(y0, y1)| | | in SIMD8
437 * |-----------------------------------|
438 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
439 * -----------------------------------
441 * See also: emit_interpolation_setup_gen4().
443 struct brw_reg delta_x
= src
[0];
444 struct brw_reg delta_y
= offset(src
[0], dispatch_width
/ 8);
445 struct brw_reg interp
= src
[1];
447 if (devinfo
->has_pln
&&
448 (devinfo
->gen
>= 7 || (delta_x
.nr
& 1) == 0)) {
449 brw_PLN(p
, dst
, interp
, delta_x
);
451 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
452 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
457 fs_generator::generate_math_gen6(fs_inst
*inst
,
462 int op
= brw_math_function(inst
->opcode
);
463 bool binop
= src1
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
;
465 if (dispatch_width
== 8) {
466 gen6_math(p
, dst
, op
, src0
, src1
);
467 } else if (dispatch_width
== 16) {
468 brw_push_insn_state(p
);
469 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
470 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
471 gen6_math(p
, firsthalf(dst
), op
, firsthalf(src0
), firsthalf(src1
));
472 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
473 gen6_math(p
, sechalf(dst
), op
, sechalf(src0
),
474 binop
? sechalf(src1
) : brw_null_reg());
475 brw_pop_insn_state(p
);
480 fs_generator::generate_math_gen4(fs_inst
*inst
,
484 int op
= brw_math_function(inst
->opcode
);
486 assert(inst
->mlen
>= 1);
488 if (dispatch_width
== 8) {
492 BRW_MATH_PRECISION_FULL
);
493 } else if (dispatch_width
== 16) {
494 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
495 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
496 gen4_math(p
, firsthalf(dst
),
498 inst
->base_mrf
, firsthalf(src
),
499 BRW_MATH_PRECISION_FULL
);
500 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
501 gen4_math(p
, sechalf(dst
),
503 inst
->base_mrf
+ 1, sechalf(src
),
504 BRW_MATH_PRECISION_FULL
);
506 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
511 fs_generator::generate_math_g45(fs_inst
*inst
,
515 if (inst
->opcode
== SHADER_OPCODE_POW
||
516 inst
->opcode
== SHADER_OPCODE_INT_QUOTIENT
||
517 inst
->opcode
== SHADER_OPCODE_INT_REMAINDER
) {
518 generate_math_gen4(inst
, dst
, src
);
522 int op
= brw_math_function(inst
->opcode
);
524 assert(inst
->mlen
>= 1);
529 BRW_MATH_PRECISION_FULL
);
533 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
534 struct brw_reg sampler_index
)
539 uint32_t return_format
;
540 bool is_combined_send
= inst
->eot
;
543 case BRW_REGISTER_TYPE_D
:
544 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
546 case BRW_REGISTER_TYPE_UD
:
547 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
550 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
554 switch (inst
->exec_size
) {
556 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
559 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
562 unreachable("Invalid width for texture instruction");
565 if (devinfo
->gen
>= 5) {
566 switch (inst
->opcode
) {
567 case SHADER_OPCODE_TEX
:
568 if (inst
->shadow_compare
) {
569 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
571 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
575 if (inst
->shadow_compare
) {
576 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
578 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
581 case SHADER_OPCODE_TXL
:
582 if (inst
->shadow_compare
) {
583 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
585 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
588 case SHADER_OPCODE_TXS
:
589 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
591 case SHADER_OPCODE_TXD
:
592 if (inst
->shadow_compare
) {
593 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
594 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
595 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
597 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
600 case SHADER_OPCODE_TXF
:
601 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
603 case SHADER_OPCODE_TXF_CMS
:
604 if (devinfo
->gen
>= 7)
605 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
607 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
609 case SHADER_OPCODE_TXF_UMS
:
610 assert(devinfo
->gen
>= 7);
611 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
613 case SHADER_OPCODE_TXF_MCS
:
614 assert(devinfo
->gen
>= 7);
615 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
617 case SHADER_OPCODE_LOD
:
618 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
620 case SHADER_OPCODE_TG4
:
621 if (inst
->shadow_compare
) {
622 assert(devinfo
->gen
>= 7);
623 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
625 assert(devinfo
->gen
>= 6);
626 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
629 case SHADER_OPCODE_TG4_OFFSET
:
630 assert(devinfo
->gen
>= 7);
631 if (inst
->shadow_compare
) {
632 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
634 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
638 unreachable("not reached");
641 switch (inst
->opcode
) {
642 case SHADER_OPCODE_TEX
:
643 /* Note that G45 and older determines shadow compare and dispatch width
644 * from message length for most messages.
646 if (dispatch_width
== 8) {
647 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
648 if (inst
->shadow_compare
) {
649 assert(inst
->mlen
== 6);
651 assert(inst
->mlen
<= 4);
654 if (inst
->shadow_compare
) {
655 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
656 assert(inst
->mlen
== 9);
658 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
659 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
664 if (inst
->shadow_compare
) {
665 assert(dispatch_width
== 8);
666 assert(inst
->mlen
== 6);
667 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
669 assert(inst
->mlen
== 9);
670 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
671 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
674 case SHADER_OPCODE_TXL
:
675 if (inst
->shadow_compare
) {
676 assert(dispatch_width
== 8);
677 assert(inst
->mlen
== 6);
678 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
680 assert(inst
->mlen
== 9);
681 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
682 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
685 case SHADER_OPCODE_TXD
:
686 /* There is no sample_d_c message; comparisons are done manually */
687 assert(dispatch_width
== 8);
688 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
689 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
691 case SHADER_OPCODE_TXF
:
692 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
693 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
694 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
696 case SHADER_OPCODE_TXS
:
697 assert(inst
->mlen
== 3);
698 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
699 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
702 unreachable("not reached");
705 assert(msg_type
!= -1);
707 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
712 if (is_combined_send
) {
713 assert(devinfo
->gen
>= 9 || devinfo
->is_cherryview
);
717 assert(devinfo
->gen
< 7 || inst
->header_size
== 0 ||
718 src
.file
== BRW_GENERAL_REGISTER_FILE
);
720 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
722 /* Load the message header if present. If there's a texture offset,
723 * we need to set it up explicitly and load the offset bitfield.
724 * Otherwise, we can use an implied move from g0 to the first message reg.
726 if (inst
->header_size
!= 0) {
727 if (devinfo
->gen
< 6 && !inst
->offset
) {
728 /* Set up an implied move from g0 to the MRF. */
729 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
731 struct brw_reg header_reg
;
733 if (devinfo
->gen
>= 7) {
736 assert(inst
->base_mrf
!= -1);
737 header_reg
= brw_message_reg(inst
->base_mrf
);
740 brw_push_insn_state(p
);
741 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
742 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
743 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
744 /* Explicitly set up the message header by copying g0 to the MRF. */
745 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
748 /* Set the offset bits in DWord 2. */
749 brw_MOV(p
, get_element_ud(header_reg
, 2),
750 brw_imm_ud(inst
->offset
));
753 brw_adjust_sampler_state_pointer(p
, header_reg
, sampler_index
);
754 brw_pop_insn_state(p
);
758 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
759 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
760 ? prog_data
->binding_table
.gather_texture_start
761 : prog_data
->binding_table
.texture_start
;
763 if (sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
764 uint32_t sampler
= sampler_index
.dw1
.ud
;
767 retype(dst
, BRW_REGISTER_TYPE_UW
),
770 sampler
+ base_binding_table_index
,
775 inst
->header_size
!= 0,
779 brw_mark_surface_used(prog_data
, sampler
+ base_binding_table_index
);
781 /* Non-const sampler index */
782 /* Note: this clobbers `dst` as a temporary before emitting the send */
784 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
785 struct brw_reg temp
= vec1(retype(dst
, BRW_REGISTER_TYPE_UD
));
787 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
789 brw_push_insn_state(p
);
790 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
791 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
793 /* Some care required: `sampler` and `temp` may alias:
794 * addr = sampler & 0xff
795 * temp = (sampler << 8) & 0xf00
798 brw_ADD(p
, addr
, sampler_reg
, brw_imm_ud(base_binding_table_index
));
799 brw_SHL(p
, temp
, sampler_reg
, brw_imm_ud(8u));
800 brw_AND(p
, temp
, temp
, brw_imm_ud(0x0f00));
801 brw_AND(p
, addr
, addr
, brw_imm_ud(0x0ff));
802 brw_OR(p
, addr
, addr
, temp
);
804 brw_pop_insn_state(p
);
806 /* dst = send(offset, a0.0 | <descriptor>) */
807 brw_inst
*insn
= brw_send_indirect_message(
808 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
809 brw_set_sampler_message(p
, insn
,
814 inst
->mlen
/* mlen */,
815 inst
->header_size
!= 0 /* header */,
819 /* visitor knows more than we do about the surface limit required,
820 * so has already done marking.
824 if (is_combined_send
) {
825 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, true);
826 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
831 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
834 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
836 * Ideally, we want to produce:
839 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
840 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
841 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
842 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
843 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
844 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
845 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
846 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
848 * and add another set of two more subspans if in 16-pixel dispatch mode.
850 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
851 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
852 * pair. But the ideal approximation may impose a huge performance cost on
853 * sample_d. On at least Haswell, sample_d instruction does some
854 * optimizations if the same LOD is used for all pixels in the subspan.
856 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
857 * appropriate swizzling.
860 fs_generator::generate_ddx(enum opcode opcode
,
861 struct brw_reg dst
, struct brw_reg src
)
863 unsigned vstride
, width
;
865 if (opcode
== FS_OPCODE_DDX_FINE
) {
866 /* produce accurate derivatives */
867 vstride
= BRW_VERTICAL_STRIDE_2
;
870 /* replicate the derivative at the top-left pixel to other pixels */
871 vstride
= BRW_VERTICAL_STRIDE_4
;
875 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
880 BRW_HORIZONTAL_STRIDE_0
,
881 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
882 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
887 BRW_HORIZONTAL_STRIDE_0
,
888 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
889 brw_ADD(p
, dst
, src0
, negate(src1
));
892 /* The negate_value boolean is used to negate the derivative computation for
893 * FBOs, since they place the origin at the upper left instead of the lower
897 fs_generator::generate_ddy(enum opcode opcode
,
898 struct brw_reg dst
, struct brw_reg src
,
901 if (opcode
== FS_OPCODE_DDY_FINE
) {
902 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
903 * Region Restrictions):
905 * In Align16 access mode, SIMD16 is not allowed for DW operations
906 * and SIMD8 is not allowed for DF operations.
908 * In this context, "DW operations" means "operations acting on 32-bit
909 * values", so it includes operations on floats.
911 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
912 * (Instruction Compression -> Rules and Restrictions):
914 * A compressed instruction must be in Align1 access mode. Align16
915 * mode instructions cannot be compressed.
917 * Similar text exists in the g45 PRM.
919 * On these platforms, if we're building a SIMD16 shader, we need to
920 * manually unroll to a pair of SIMD8 instructions.
922 bool unroll_to_simd8
=
923 (dispatch_width
== 16 &&
924 (devinfo
->gen
== 4 || (devinfo
->gen
== 7 && !devinfo
->is_haswell
)));
926 /* produce accurate derivatives */
927 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
930 BRW_VERTICAL_STRIDE_4
,
932 BRW_HORIZONTAL_STRIDE_1
,
933 BRW_SWIZZLE_XYXY
, WRITEMASK_XYZW
);
934 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
937 BRW_VERTICAL_STRIDE_4
,
939 BRW_HORIZONTAL_STRIDE_1
,
940 BRW_SWIZZLE_ZWZW
, WRITEMASK_XYZW
);
941 brw_push_insn_state(p
);
942 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
943 if (unroll_to_simd8
) {
944 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
946 brw_ADD(p
, firsthalf(dst
), firsthalf(src1
), negate(firsthalf(src0
)));
947 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
948 brw_ADD(p
, sechalf(dst
), sechalf(src1
), negate(sechalf(src0
)));
950 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), negate(firsthalf(src1
)));
951 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
952 brw_ADD(p
, sechalf(dst
), sechalf(src0
), negate(sechalf(src1
)));
956 brw_ADD(p
, dst
, src1
, negate(src0
));
958 brw_ADD(p
, dst
, src0
, negate(src1
));
960 brw_pop_insn_state(p
);
962 /* replicate the derivative at the top-left pixel to other pixels */
963 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
966 BRW_VERTICAL_STRIDE_4
,
968 BRW_HORIZONTAL_STRIDE_0
,
969 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
970 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
973 BRW_VERTICAL_STRIDE_4
,
975 BRW_HORIZONTAL_STRIDE_0
,
976 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
978 brw_ADD(p
, dst
, src1
, negate(src0
));
980 brw_ADD(p
, dst
, src0
, negate(src1
));
985 fs_generator::generate_discard_jump(fs_inst
*inst
)
987 assert(devinfo
->gen
>= 6);
989 /* This HALT will be patched up at FB write time to point UIP at the end of
990 * the program, and at brw_uip_jip() JIP will be set to the end of the
991 * current block (or the program).
993 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
995 brw_push_insn_state(p
);
996 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
998 brw_pop_insn_state(p
);
1002 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1004 assert(inst
->mlen
!= 0);
1007 brw_uvec_mrf(inst
->exec_size
, (inst
->base_mrf
+ 1), 0),
1008 retype(src
, BRW_REGISTER_TYPE_UD
));
1009 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1010 inst
->exec_size
/ 8, inst
->offset
);
1014 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1016 assert(inst
->mlen
!= 0);
1018 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1019 inst
->exec_size
/ 8, inst
->offset
);
1023 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1025 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1029 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1031 struct brw_reg index
,
1032 struct brw_reg offset
)
1034 assert(inst
->mlen
!= 0);
1036 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1037 index
.type
== BRW_REGISTER_TYPE_UD
);
1038 uint32_t surf_index
= index
.dw1
.ud
;
1040 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1041 offset
.type
== BRW_REGISTER_TYPE_UD
);
1042 uint32_t read_offset
= offset
.dw1
.ud
;
1044 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1045 read_offset
, surf_index
);
1047 brw_mark_surface_used(prog_data
, surf_index
);
1051 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1053 struct brw_reg index
,
1054 struct brw_reg offset
)
1056 assert(inst
->mlen
== 0);
1057 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1059 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
1060 /* Reference just the dword we need, to avoid angering validate_reg(). */
1061 offset
= brw_vec1_grf(offset
.nr
, 0);
1063 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1064 * the destination loaded consecutively from the same offset (which appears
1065 * in the first component, and the rest are ignored).
1067 dst
.width
= BRW_WIDTH_4
;
1069 struct brw_reg src
= offset
;
1070 bool header_present
= false;
1073 if (devinfo
->gen
>= 9) {
1074 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1075 src
= retype(brw_vec4_grf(offset
.nr
- 1, 0), BRW_REGISTER_TYPE_UD
);
1077 header_present
= true;
1079 brw_push_insn_state(p
);
1080 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1081 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1082 brw_MOV(p
, vec8(src
), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1083 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1085 brw_MOV(p
, get_element_ud(src
, 2),
1086 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
));
1087 brw_pop_insn_state(p
);
1090 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1092 uint32_t surf_index
= index
.dw1
.ud
;
1094 brw_push_insn_state(p
);
1095 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1096 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1097 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1098 brw_pop_insn_state(p
);
1100 brw_set_dest(p
, send
, dst
);
1101 brw_set_src0(p
, send
, src
);
1102 brw_set_sampler_message(p
, send
,
1104 0, /* LD message ignores sampler unit */
1105 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1109 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1112 brw_mark_surface_used(prog_data
, surf_index
);
1116 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1118 brw_push_insn_state(p
);
1119 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1120 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1122 /* a0.0 = surf_index & 0xff */
1123 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1124 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1125 brw_set_dest(p
, insn_and
, addr
);
1126 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1127 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1129 /* dst = send(payload, a0.0 | <descriptor>) */
1130 brw_inst
*insn
= brw_send_indirect_message(
1131 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1132 brw_set_sampler_message(p
, insn
,
1134 0, /* LD message ignores sampler unit */
1135 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1139 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1142 brw_pop_insn_state(p
);
1144 /* visitor knows more than we do about the surface limit required,
1145 * so has already done marking.
1152 fs_generator::generate_varying_pull_constant_load(fs_inst
*inst
,
1154 struct brw_reg index
,
1155 struct brw_reg offset
)
1157 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1158 assert(inst
->header_size
!= 0);
1161 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1162 index
.type
== BRW_REGISTER_TYPE_UD
);
1163 uint32_t surf_index
= index
.dw1
.ud
;
1165 uint32_t simd_mode
, rlen
, msg_type
;
1166 if (dispatch_width
== 16) {
1167 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1170 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1174 if (devinfo
->gen
>= 5)
1175 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1177 /* We always use the SIMD16 message so that we only have to load U, and
1180 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1181 assert(inst
->mlen
== 3);
1182 assert(inst
->regs_written
== 8);
1184 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1187 struct brw_reg offset_mrf
= retype(brw_message_reg(inst
->base_mrf
+ 1),
1188 BRW_REGISTER_TYPE_D
);
1189 brw_MOV(p
, offset_mrf
, offset
);
1191 struct brw_reg header
= brw_vec8_grf(0, 0);
1192 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1194 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1195 brw_inst_set_qtr_control(p
->devinfo
, send
, BRW_COMPRESSION_NONE
);
1196 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1197 brw_set_src0(p
, send
, header
);
1198 if (devinfo
->gen
< 6)
1199 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1201 /* Our surface is set up as floats, regardless of what actual data is
1204 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1205 brw_set_sampler_message(p
, send
,
1207 0, /* sampler (unused) */
1211 inst
->header_size
!= 0,
1215 brw_mark_surface_used(prog_data
, surf_index
);
1219 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1221 struct brw_reg index
,
1222 struct brw_reg offset
)
1224 assert(devinfo
->gen
>= 7);
1225 /* Varying-offset pull constant loads are treated as a normal expression on
1226 * gen7, so the fact that it's a send message is hidden at the IR level.
1228 assert(inst
->header_size
== 0);
1229 assert(!inst
->mlen
);
1230 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1232 uint32_t simd_mode
, rlen
, mlen
;
1233 if (dispatch_width
== 16) {
1236 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1240 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1243 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1245 uint32_t surf_index
= index
.dw1
.ud
;
1247 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1248 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1249 brw_set_src0(p
, send
, offset
);
1250 brw_set_sampler_message(p
, send
,
1252 0, /* LD message ignores sampler unit */
1253 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1256 false, /* no header */
1260 brw_mark_surface_used(prog_data
, surf_index
);
1264 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1266 brw_push_insn_state(p
);
1267 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1268 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1270 /* a0.0 = surf_index & 0xff */
1271 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1272 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1273 brw_set_dest(p
, insn_and
, addr
);
1274 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1275 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1277 brw_pop_insn_state(p
);
1279 /* dst = send(offset, a0.0 | <descriptor>) */
1280 brw_inst
*insn
= brw_send_indirect_message(
1281 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1283 brw_set_sampler_message(p
, insn
,
1286 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1293 /* visitor knows more than we do about the surface limit required,
1294 * so has already done marking.
1300 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1301 * into the flags register (f0.0).
1303 * Used only on Gen6 and above.
1306 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1308 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
1309 struct brw_reg dispatch_mask
;
1311 if (devinfo
->gen
>= 6)
1312 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1314 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1316 brw_push_insn_state(p
);
1317 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1318 brw_MOV(p
, flags
, dispatch_mask
);
1319 brw_pop_insn_state(p
);
1323 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1326 struct brw_reg msg_data
,
1329 assert(msg_data
.file
== BRW_IMMEDIATE_VALUE
&&
1330 msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1332 brw_pixel_interpolator_query(p
,
1333 retype(dst
, BRW_REGISTER_TYPE_UW
),
1335 inst
->pi_noperspective
,
1339 inst
->regs_written
);
1344 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1345 * sampler LD messages.
1347 * We don't want to bake it into the send message's code generation because
1348 * that means we don't get a chance to schedule the instructions.
1351 fs_generator::generate_set_simd4x2_offset(fs_inst
*inst
,
1353 struct brw_reg value
)
1355 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1357 brw_push_insn_state(p
);
1358 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1359 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1360 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1361 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 0), value
.type
), value
);
1362 brw_pop_insn_state(p
);
1365 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1366 * (when mask is passed as a uniform) of register mask before moving it
1370 fs_generator::generate_set_omask(fs_inst
*inst
,
1372 struct brw_reg mask
)
1375 (mask
.vstride
== BRW_VERTICAL_STRIDE_8
&&
1376 mask
.width
== BRW_WIDTH_8
&&
1377 mask
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
1379 bool stride_0_1_0
= has_scalar_region(mask
);
1381 assert(stride_8_8_1
|| stride_0_1_0
);
1382 assert(dst
.type
== BRW_REGISTER_TYPE_UW
);
1384 brw_push_insn_state(p
);
1385 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1386 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1389 brw_MOV(p
, dst
, retype(stride(mask
, 16, 8, 2), dst
.type
));
1390 } else if (stride_0_1_0
) {
1391 brw_MOV(p
, dst
, retype(mask
, dst
.type
));
1393 brw_pop_insn_state(p
);
1396 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1397 * the ADD instruction.
1400 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1402 struct brw_reg src0
,
1403 struct brw_reg src1
)
1405 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1406 dst
.type
== BRW_REGISTER_TYPE_UD
);
1407 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1408 src0
.type
== BRW_REGISTER_TYPE_UD
);
1410 brw_push_insn_state(p
);
1411 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1412 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1413 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1414 struct brw_reg reg
= retype(stride(src1
, 1, 4, 0), BRW_REGISTER_TYPE_UW
);
1415 if (dispatch_width
== 8) {
1416 brw_ADD(p
, dst
, src0
, reg
);
1417 } else if (dispatch_width
== 16) {
1418 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), reg
);
1419 brw_ADD(p
, sechalf(dst
), sechalf(src0
), suboffset(reg
, 2));
1421 brw_pop_insn_state(p
);
1425 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
1430 assert(devinfo
->gen
>= 7);
1431 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1432 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1433 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1435 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1437 * Because this instruction does not have a 16-bit floating-point type,
1438 * the destination data type must be Word (W).
1440 * The destination must be DWord-aligned and specify a horizontal stride
1441 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1442 * each destination channel and the upper word is not modified.
1444 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1446 /* Give each 32-bit channel of dst the form below, where "." means
1450 brw_F32TO16(p
, dst_w
, y
);
1455 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1457 /* And, finally the form of packHalf2x16's output:
1460 brw_F32TO16(p
, dst_w
, x
);
1464 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1468 assert(devinfo
->gen
>= 7);
1469 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1470 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1472 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1474 * Because this instruction does not have a 16-bit floating-point type,
1475 * the source data type must be Word (W). The destination type must be
1478 struct brw_reg src_w
= spread(retype(src
, BRW_REGISTER_TYPE_W
), 2);
1480 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1481 * For the Y case, we wish to access only the upper word; therefore
1482 * a 16-bit subregister offset is needed.
1484 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1485 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1486 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1489 brw_F16TO32(p
, dst
, src_w
);
1493 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1494 struct brw_reg payload
,
1495 struct brw_reg offset
,
1496 struct brw_reg value
)
1498 assert(devinfo
->gen
>= 7);
1499 brw_push_insn_state(p
);
1500 brw_set_default_mask_control(p
, true);
1502 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1503 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1505 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1508 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1509 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1510 value
.width
= BRW_WIDTH_1
;
1511 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1512 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1514 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1517 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1518 * case, and we don't really care about squeezing every bit of performance
1519 * out of this path, so we just emit the MOVs from here.
1521 brw_MOV(p
, payload_offset
, offset
);
1522 brw_MOV(p
, payload_value
, value
);
1523 brw_shader_time_add(p
, payload
,
1524 prog_data
->binding_table
.shader_time_start
);
1525 brw_pop_insn_state(p
);
1527 brw_mark_surface_used(prog_data
,
1528 prog_data
->binding_table
.shader_time_start
);
1532 fs_generator::enable_debug(const char *shader_name
)
1535 this->shader_name
= shader_name
;
1539 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1541 /* align to 64 byte boundary. */
1542 while (p
->next_insn_offset
% 64)
1545 this->dispatch_width
= dispatch_width
;
1546 if (dispatch_width
== 16)
1547 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1549 int start_offset
= p
->next_insn_offset
;
1550 int spill_count
= 0, fill_count
= 0;
1553 struct annotation_info annotation
;
1554 memset(&annotation
, 0, sizeof(annotation
));
1556 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1557 struct brw_reg src
[3], dst
;
1558 unsigned int last_insn_offset
= p
->next_insn_offset
;
1559 bool multiple_instructions_emitted
= false;
1561 if (unlikely(debug_flag
))
1562 annotate(p
->devinfo
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1564 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1565 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1567 /* The accumulator result appears to get used for the
1568 * conditional modifier generation. When negating a UD
1569 * value, there is a 33rd bit generated for the sign in the
1570 * accumulator value, so now you can't check, for example,
1571 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1573 assert(!inst
->conditional_mod
||
1574 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1575 !inst
->src
[i
].negate
);
1577 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1579 brw_set_default_predicate_control(p
, inst
->predicate
);
1580 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1581 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1582 brw_set_default_saturate(p
, inst
->saturate
);
1583 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1584 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1585 brw_set_default_exec_size(p
, cvt(inst
->exec_size
) - 1);
1587 switch (inst
->exec_size
) {
1591 assert(inst
->force_writemask_all
);
1592 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1595 if (inst
->force_sechalf
) {
1596 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1598 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1603 if (type_sz(inst
->dst
.type
) < sizeof(float))
1604 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1606 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1609 unreachable("Invalid instruction width");
1612 switch (inst
->opcode
) {
1613 case BRW_OPCODE_MOV
:
1614 brw_MOV(p
, dst
, src
[0]);
1616 case BRW_OPCODE_ADD
:
1617 brw_ADD(p
, dst
, src
[0], src
[1]);
1619 case BRW_OPCODE_MUL
:
1620 brw_MUL(p
, dst
, src
[0], src
[1]);
1622 case BRW_OPCODE_AVG
:
1623 brw_AVG(p
, dst
, src
[0], src
[1]);
1625 case BRW_OPCODE_MACH
:
1626 brw_MACH(p
, dst
, src
[0], src
[1]);
1629 case BRW_OPCODE_LINE
:
1630 brw_LINE(p
, dst
, src
[0], src
[1]);
1633 case BRW_OPCODE_MAD
:
1634 assert(devinfo
->gen
>= 6);
1635 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1636 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1637 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1638 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1639 brw_inst
*f
= brw_MAD(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1640 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1641 brw_inst
*s
= brw_MAD(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1642 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1644 if (inst
->conditional_mod
) {
1645 brw_inst_set_cond_modifier(p
->devinfo
, f
, inst
->conditional_mod
);
1646 brw_inst_set_cond_modifier(p
->devinfo
, s
, inst
->conditional_mod
);
1647 multiple_instructions_emitted
= true;
1650 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1652 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1655 case BRW_OPCODE_LRP
:
1656 assert(devinfo
->gen
>= 6);
1657 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1658 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1659 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1660 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1661 brw_inst
*f
= brw_LRP(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1662 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1663 brw_inst
*s
= brw_LRP(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1664 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1666 if (inst
->conditional_mod
) {
1667 brw_inst_set_cond_modifier(p
->devinfo
, f
, inst
->conditional_mod
);
1668 brw_inst_set_cond_modifier(p
->devinfo
, s
, inst
->conditional_mod
);
1669 multiple_instructions_emitted
= true;
1672 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1674 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1677 case BRW_OPCODE_FRC
:
1678 brw_FRC(p
, dst
, src
[0]);
1680 case BRW_OPCODE_RNDD
:
1681 brw_RNDD(p
, dst
, src
[0]);
1683 case BRW_OPCODE_RNDE
:
1684 brw_RNDE(p
, dst
, src
[0]);
1686 case BRW_OPCODE_RNDZ
:
1687 brw_RNDZ(p
, dst
, src
[0]);
1690 case BRW_OPCODE_AND
:
1691 brw_AND(p
, dst
, src
[0], src
[1]);
1694 brw_OR(p
, dst
, src
[0], src
[1]);
1696 case BRW_OPCODE_XOR
:
1697 brw_XOR(p
, dst
, src
[0], src
[1]);
1699 case BRW_OPCODE_NOT
:
1700 brw_NOT(p
, dst
, src
[0]);
1702 case BRW_OPCODE_ASR
:
1703 brw_ASR(p
, dst
, src
[0], src
[1]);
1705 case BRW_OPCODE_SHR
:
1706 brw_SHR(p
, dst
, src
[0], src
[1]);
1708 case BRW_OPCODE_SHL
:
1709 brw_SHL(p
, dst
, src
[0], src
[1]);
1711 case BRW_OPCODE_F32TO16
:
1712 assert(devinfo
->gen
>= 7);
1713 brw_F32TO16(p
, dst
, src
[0]);
1715 case BRW_OPCODE_F16TO32
:
1716 assert(devinfo
->gen
>= 7);
1717 brw_F16TO32(p
, dst
, src
[0]);
1719 case BRW_OPCODE_CMP
:
1720 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1721 * that when the destination is a GRF that the dependency-clear bit on
1722 * the flag register is cleared early.
1724 * Suggested workarounds are to disable coissuing CMP instructions
1725 * or to split CMP(16) instructions into two CMP(8) instructions.
1727 * We choose to split into CMP(8) instructions since disabling
1728 * coissuing would affect CMP instructions not otherwise affected by
1731 if (dispatch_width
== 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1732 if (dst
.file
== BRW_GENERAL_REGISTER_FILE
) {
1733 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1734 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1735 brw_CMP(p
, firsthalf(dst
), inst
->conditional_mod
,
1736 firsthalf(src
[0]), firsthalf(src
[1]));
1737 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1738 brw_CMP(p
, sechalf(dst
), inst
->conditional_mod
,
1739 sechalf(src
[0]), sechalf(src
[1]));
1740 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1742 multiple_instructions_emitted
= true;
1743 } else if (dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1744 /* For unknown reasons, the aforementioned workaround is not
1745 * sufficient. Overriding the type when the destination is the
1746 * null register is necessary but not sufficient by itself.
1748 assert(dst
.nr
== BRW_ARF_NULL
);
1749 dst
.type
= BRW_REGISTER_TYPE_D
;
1750 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1752 unreachable("not reached");
1755 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1758 case BRW_OPCODE_SEL
:
1759 brw_SEL(p
, dst
, src
[0], src
[1]);
1761 case BRW_OPCODE_BFREV
:
1762 assert(devinfo
->gen
>= 7);
1763 /* BFREV only supports UD type for src and dst. */
1764 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1765 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1767 case BRW_OPCODE_FBH
:
1768 assert(devinfo
->gen
>= 7);
1769 /* FBH only supports UD type for dst. */
1770 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1772 case BRW_OPCODE_FBL
:
1773 assert(devinfo
->gen
>= 7);
1774 /* FBL only supports UD type for dst. */
1775 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1777 case BRW_OPCODE_CBIT
:
1778 assert(devinfo
->gen
>= 7);
1779 /* CBIT only supports UD type for dst. */
1780 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1782 case BRW_OPCODE_ADDC
:
1783 assert(devinfo
->gen
>= 7);
1784 brw_ADDC(p
, dst
, src
[0], src
[1]);
1786 case BRW_OPCODE_SUBB
:
1787 assert(devinfo
->gen
>= 7);
1788 brw_SUBB(p
, dst
, src
[0], src
[1]);
1790 case BRW_OPCODE_MAC
:
1791 brw_MAC(p
, dst
, src
[0], src
[1]);
1794 case BRW_OPCODE_BFE
:
1795 assert(devinfo
->gen
>= 7);
1796 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1797 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1798 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1799 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1800 brw_BFE(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1801 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1802 brw_BFE(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1803 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1805 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1807 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1810 case BRW_OPCODE_BFI1
:
1811 assert(devinfo
->gen
>= 7);
1812 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1815 * "Force BFI instructions to be executed always in SIMD8."
1817 if (dispatch_width
== 16 && devinfo
->is_haswell
) {
1818 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1819 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1820 brw_BFI1(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]));
1821 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1822 brw_BFI1(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]));
1823 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1825 brw_BFI1(p
, dst
, src
[0], src
[1]);
1828 case BRW_OPCODE_BFI2
:
1829 assert(devinfo
->gen
>= 7);
1830 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1831 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1834 * "Force BFI instructions to be executed always in SIMD8."
1836 * Otherwise we would be able to emit compressed instructions like we
1837 * do for the other three-source instructions.
1839 if (dispatch_width
== 16 &&
1840 (devinfo
->is_haswell
|| !devinfo
->supports_simd16_3src
)) {
1841 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1842 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1843 brw_BFI2(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1844 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1845 brw_BFI2(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1846 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1848 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1850 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1854 if (inst
->src
[0].file
!= BAD_FILE
) {
1855 /* The instruction has an embedded compare (only allowed on gen6) */
1856 assert(devinfo
->gen
== 6);
1857 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1859 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1863 case BRW_OPCODE_ELSE
:
1866 case BRW_OPCODE_ENDIF
:
1871 brw_DO(p
, BRW_EXECUTE_8
);
1874 case BRW_OPCODE_BREAK
:
1876 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1878 case BRW_OPCODE_CONTINUE
:
1880 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1883 case BRW_OPCODE_WHILE
:
1888 case SHADER_OPCODE_RCP
:
1889 case SHADER_OPCODE_RSQ
:
1890 case SHADER_OPCODE_SQRT
:
1891 case SHADER_OPCODE_EXP2
:
1892 case SHADER_OPCODE_LOG2
:
1893 case SHADER_OPCODE_SIN
:
1894 case SHADER_OPCODE_COS
:
1895 assert(devinfo
->gen
< 6 || inst
->mlen
== 0);
1896 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1897 if (devinfo
->gen
>= 7) {
1898 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1900 } else if (devinfo
->gen
== 6) {
1901 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
1902 } else if (devinfo
->gen
== 5 || devinfo
->is_g4x
) {
1903 generate_math_g45(inst
, dst
, src
[0]);
1905 generate_math_gen4(inst
, dst
, src
[0]);
1908 case SHADER_OPCODE_INT_QUOTIENT
:
1909 case SHADER_OPCODE_INT_REMAINDER
:
1910 case SHADER_OPCODE_POW
:
1911 assert(devinfo
->gen
< 6 || inst
->mlen
== 0);
1912 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1913 if (devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) {
1914 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1915 } else if (devinfo
->gen
>= 6) {
1916 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
1918 generate_math_gen4(inst
, dst
, src
[0]);
1921 case FS_OPCODE_CINTERP
:
1922 brw_MOV(p
, dst
, src
[0]);
1924 case FS_OPCODE_LINTERP
:
1925 generate_linterp(inst
, dst
, src
);
1927 case FS_OPCODE_PIXEL_X
:
1928 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1929 src
[0].subnr
= 0 * type_sz(src
[0].type
);
1930 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1932 case FS_OPCODE_PIXEL_Y
:
1933 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1934 src
[0].subnr
= 4 * type_sz(src
[0].type
);
1935 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1937 case SHADER_OPCODE_TEX
:
1939 case SHADER_OPCODE_TXD
:
1940 case SHADER_OPCODE_TXF
:
1941 case SHADER_OPCODE_TXF_CMS
:
1942 case SHADER_OPCODE_TXF_UMS
:
1943 case SHADER_OPCODE_TXF_MCS
:
1944 case SHADER_OPCODE_TXL
:
1945 case SHADER_OPCODE_TXS
:
1946 case SHADER_OPCODE_LOD
:
1947 case SHADER_OPCODE_TG4
:
1948 case SHADER_OPCODE_TG4_OFFSET
:
1949 generate_tex(inst
, dst
, src
[0], src
[1]);
1951 case FS_OPCODE_DDX_COARSE
:
1952 case FS_OPCODE_DDX_FINE
:
1953 generate_ddx(inst
->opcode
, dst
, src
[0]);
1955 case FS_OPCODE_DDY_COARSE
:
1956 case FS_OPCODE_DDY_FINE
:
1957 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
1958 generate_ddy(inst
->opcode
, dst
, src
[0], src
[1].dw1
.ud
);
1961 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1962 generate_scratch_write(inst
, src
[0]);
1966 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1967 generate_scratch_read(inst
, dst
);
1971 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
1972 generate_scratch_read_gen7(inst
, dst
);
1976 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1977 generate_urb_write(inst
, src
[0]);
1980 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1981 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1984 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
1985 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1988 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
1989 generate_varying_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1992 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
1993 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1996 case FS_OPCODE_REP_FB_WRITE
:
1997 case FS_OPCODE_FB_WRITE
:
1998 generate_fb_write(inst
, src
[0]);
2001 case FS_OPCODE_BLORP_FB_WRITE
:
2002 generate_blorp_fb_write(inst
);
2005 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
2006 generate_mov_dispatch_to_flags(inst
);
2009 case FS_OPCODE_DISCARD_JUMP
:
2010 generate_discard_jump(inst
);
2013 case SHADER_OPCODE_SHADER_TIME_ADD
:
2014 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2017 case SHADER_OPCODE_UNTYPED_ATOMIC
:
2018 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
&&
2019 src
[2].file
== BRW_IMMEDIATE_VALUE
);
2020 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].dw1
.ud
,
2021 inst
->mlen
, !inst
->dst
.is_null());
2022 brw_mark_surface_used(prog_data
, src
[1].dw1
.ud
);
2025 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
2026 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
&&
2027 src
[2].file
== BRW_IMMEDIATE_VALUE
);
2028 brw_untyped_surface_read(p
, dst
, src
[0], src
[1],
2029 inst
->mlen
, src
[2].dw1
.ud
);
2030 brw_mark_surface_used(prog_data
, src
[1].dw1
.ud
);
2033 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
2034 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2035 brw_untyped_surface_write(p
, src
[0], src
[1],
2036 inst
->mlen
, src
[2].dw1
.ud
);
2039 case SHADER_OPCODE_TYPED_ATOMIC
:
2040 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2041 brw_typed_atomic(p
, dst
, src
[0], src
[1],
2042 src
[2].dw1
.ud
, inst
->mlen
, !inst
->dst
.is_null());
2045 case SHADER_OPCODE_TYPED_SURFACE_READ
:
2046 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2047 brw_typed_surface_read(p
, dst
, src
[0], src
[1],
2048 inst
->mlen
, src
[2].dw1
.ud
);
2051 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
2052 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2053 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
, src
[2].dw1
.ud
);
2056 case SHADER_OPCODE_MEMORY_FENCE
:
2057 brw_memory_fence(p
, dst
);
2060 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
2061 generate_set_simd4x2_offset(inst
, dst
, src
[0]);
2064 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2065 brw_find_live_channel(p
, dst
);
2068 case SHADER_OPCODE_BROADCAST
:
2069 brw_broadcast(p
, dst
, src
[0], src
[1]);
2072 case FS_OPCODE_SET_OMASK
:
2073 generate_set_omask(inst
, dst
, src
[0]);
2076 case FS_OPCODE_SET_SAMPLE_ID
:
2077 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2080 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2081 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2084 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
2085 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
2086 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
2089 case FS_OPCODE_PLACEHOLDER_HALT
:
2090 /* This is the place where the final HALT needs to be inserted if
2091 * we've emitted any discards. If not, this will emit no code.
2093 if (!patch_discard_jumps_to_fb_writes()) {
2094 if (unlikely(debug_flag
)) {
2095 annotation
.ann_count
--;
2100 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
2101 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2102 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID
);
2105 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2106 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2107 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2110 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2111 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2112 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2115 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2116 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2117 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2120 case CS_OPCODE_CS_TERMINATE
:
2121 generate_cs_terminate(inst
, src
[0]);
2125 unreachable("Unsupported opcode");
2127 case SHADER_OPCODE_LOAD_PAYLOAD
:
2128 unreachable("Should be lowered by lower_load_payload()");
2131 if (multiple_instructions_emitted
)
2134 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2135 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2136 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2137 "emitting more than 1 instruction");
2139 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2141 if (inst
->conditional_mod
)
2142 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2143 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2144 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2149 annotation_finalize(&annotation
, p
->next_insn_offset
);
2151 int before_size
= p
->next_insn_offset
- start_offset
;
2152 brw_compact_instructions(p
, start_offset
, annotation
.ann_count
,
2154 int after_size
= p
->next_insn_offset
- start_offset
;
2156 if (unlikely(debug_flag
)) {
2157 fprintf(stderr
, "Native code for %s\n"
2158 "SIMD%d shader: %d instructions. %d loops. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2159 " bytes (%.0f%%)\n",
2160 shader_name
, dispatch_width
, before_size
/ 16, loop_count
,
2161 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2162 100.0f
* (before_size
- after_size
) / before_size
);
2164 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
,
2166 ralloc_free(annotation
.ann
);
2169 static GLuint msg_id
= 0;
2170 _mesa_gl_debug(&brw
->ctx
, &msg_id
,
2171 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2172 MESA_DEBUG_TYPE_OTHER
,
2173 MESA_DEBUG_SEVERITY_NOTIFICATION
,
2174 "%s SIMD%d shader: %d inst, %d loops, %d:%d spills:fills, "
2175 "Promoted %u constants, compacted %d to %d bytes.\n",
2176 stage_abbrev
, dispatch_width
, before_size
/ 16, loop_count
,
2177 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
);
2179 return start_offset
;
2183 fs_generator::get_assembly(unsigned int *assembly_size
)
2185 return brw_get_program(p
, assembly_size
);