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i965/emit: Do the sampler index adjustment directly in header.0.3
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 static uint32_t brw_file_from_reg(fs_reg *reg)
40 {
41 switch (reg->file) {
42 case GRF:
43 return BRW_GENERAL_REGISTER_FILE;
44 case MRF:
45 return BRW_MESSAGE_REGISTER_FILE;
46 case IMM:
47 return BRW_IMMEDIATE_VALUE;
48 default:
49 unreachable("not reached");
50 }
51 }
52
53 static struct brw_reg
54 brw_reg_from_fs_reg(fs_reg *reg)
55 {
56 struct brw_reg brw_reg;
57
58 switch (reg->file) {
59 case GRF:
60 case MRF:
61 if (reg->stride == 0) {
62 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
63 } else if (reg->width < 8) {
64 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
65 brw_reg = stride(brw_reg, reg->width * reg->stride,
66 reg->width, reg->stride);
67 } else {
68 /* From the Haswell PRM:
69 *
70 * VertStride must be used to cross GRF register boundaries. This
71 * rule implies that elements within a 'Width' cannot cross GRF
72 * boundaries.
73 *
74 * So, for registers with width > 8, we have to use a width of 8
75 * and trust the compression state to sort out the exec size.
76 */
77 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
78 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
79 }
80
81 brw_reg = retype(brw_reg, reg->type);
82 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
83 break;
84 case IMM:
85 switch (reg->type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
94 break;
95 case BRW_REGISTER_TYPE_VF:
96 brw_reg = brw_imm_vf(reg->fixed_hw_reg.dw1.ud);
97 break;
98 default:
99 unreachable("not reached");
100 }
101 break;
102 case HW_REG:
103 assert(reg->type == reg->fixed_hw_reg.type);
104 brw_reg = reg->fixed_hw_reg;
105 break;
106 case BAD_FILE:
107 /* Probably unused. */
108 brw_reg = brw_null_reg();
109 break;
110 default:
111 unreachable("not reached");
112 }
113 if (reg->abs)
114 brw_reg = brw_abs(brw_reg);
115 if (reg->negate)
116 brw_reg = negate(brw_reg);
117
118 return brw_reg;
119 }
120
121 fs_generator::fs_generator(struct brw_context *brw,
122 void *mem_ctx,
123 const void *key,
124 struct brw_stage_prog_data *prog_data,
125 struct gl_program *prog,
126 bool runtime_check_aads_emit,
127 const char *stage_abbrev)
128
129 : brw(brw), key(key),
130 prog_data(prog_data),
131 prog(prog), runtime_check_aads_emit(runtime_check_aads_emit),
132 debug_flag(false), stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
133 {
134 ctx = &brw->ctx;
135
136 p = rzalloc(mem_ctx, struct brw_compile);
137 brw_init_compile(brw, p, mem_ctx);
138 }
139
140 fs_generator::~fs_generator()
141 {
142 }
143
144 class ip_record : public exec_node {
145 public:
146 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
147
148 ip_record(int ip)
149 {
150 this->ip = ip;
151 }
152
153 int ip;
154 };
155
156 bool
157 fs_generator::patch_discard_jumps_to_fb_writes()
158 {
159 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
160 return false;
161
162 int scale = brw_jump_scale(brw);
163
164 /* There is a somewhat strange undocumented requirement of using
165 * HALT, according to the simulator. If some channel has HALTed to
166 * a particular UIP, then by the end of the program, every channel
167 * must have HALTed to that UIP. Furthermore, the tracking is a
168 * stack, so you can't do the final halt of a UIP after starting
169 * halting to a new UIP.
170 *
171 * Symptoms of not emitting this instruction on actual hardware
172 * included GPU hangs and sparkly rendering on the piglit discard
173 * tests.
174 */
175 brw_inst *last_halt = gen6_HALT(p);
176 brw_inst_set_uip(brw, last_halt, 1 * scale);
177 brw_inst_set_jip(brw, last_halt, 1 * scale);
178
179 int ip = p->nr_insn;
180
181 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
182 brw_inst *patch = &p->store[patch_ip->ip];
183
184 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
185 /* HALT takes a half-instruction distance from the pre-incremented IP. */
186 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
187 }
188
189 this->discard_halt_patches.make_empty();
190 return true;
191 }
192
193 void
194 fs_generator::fire_fb_write(fs_inst *inst,
195 struct brw_reg payload,
196 struct brw_reg implied_header,
197 GLuint nr)
198 {
199 uint32_t msg_control;
200
201 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
202
203 if (brw->gen < 6) {
204 brw_push_insn_state(p);
205 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
206 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
207 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
208 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
209 brw_pop_insn_state(p);
210 }
211
212 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
213 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
214 else if (prog_data->dual_src_blend)
215 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
216 else if (dispatch_width == 16)
217 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
218 else
219 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
220
221 uint32_t surf_index =
222 prog_data->binding_table.render_target_start + inst->target;
223
224 brw_fb_WRITE(p,
225 dispatch_width,
226 payload,
227 implied_header,
228 msg_control,
229 surf_index,
230 nr,
231 0,
232 inst->eot,
233 inst->header_present);
234
235 brw_mark_surface_used(&prog_data->base, surf_index);
236 }
237
238 void
239 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
240 {
241 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
242 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
243 struct brw_reg implied_header;
244
245 if (brw->gen < 8 && !brw->is_haswell) {
246 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
247 }
248
249 if (inst->base_mrf >= 0)
250 payload = brw_message_reg(inst->base_mrf);
251
252 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
253 * move, here's g1.
254 */
255 if (inst->header_present) {
256 brw_push_insn_state(p);
257 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
258 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
259 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
260 brw_set_default_flag_reg(p, 0, 0);
261
262 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
263 * present.
264 */
265 if (prog_data->uses_kill) {
266 struct brw_reg pixel_mask;
267
268 if (brw->gen >= 6)
269 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
270 else
271 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
272
273 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
274 }
275
276 if (brw->gen >= 6) {
277 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
278 brw_MOV(p,
279 retype(payload, BRW_REGISTER_TYPE_UD),
280 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
281 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
282
283 if (inst->target > 0 && key->replicate_alpha) {
284 /* Set "Source0 Alpha Present to RenderTarget" bit in message
285 * header.
286 */
287 brw_OR(p,
288 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
289 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
290 brw_imm_ud(0x1 << 11));
291 }
292
293 if (inst->target > 0) {
294 /* Set the render target index for choosing BLEND_STATE. */
295 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
296 BRW_REGISTER_TYPE_UD),
297 brw_imm_ud(inst->target));
298 }
299
300 implied_header = brw_null_reg();
301 } else {
302 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
303 }
304
305 brw_pop_insn_state(p);
306 } else {
307 implied_header = brw_null_reg();
308 }
309
310 if (!runtime_check_aads_emit) {
311 fire_fb_write(inst, payload, implied_header, inst->mlen);
312 } else {
313 /* This can only happen in gen < 6 */
314 assert(brw->gen < 6);
315
316 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
317
318 /* Check runtime bit to detect if we have to send AA data or not */
319 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
320 brw_AND(p,
321 v1_null_ud,
322 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
323 brw_imm_ud(1<<26));
324 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
325
326 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
327 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
328 {
329 /* Don't send AA data */
330 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
331 }
332 brw_land_fwd_jump(p, jmp);
333 fire_fb_write(inst, payload, implied_header, inst->mlen);
334 }
335 }
336
337 void
338 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
339 {
340 brw_inst *insn;
341
342 insn = brw_next_insn(p, BRW_OPCODE_SEND);
343
344 brw_set_dest(p, insn, brw_null_reg());
345 brw_set_src0(p, insn, payload);
346 brw_set_src1(p, insn, brw_imm_d(0));
347
348 brw_inst_set_sfid(brw, insn, BRW_SFID_URB);
349 brw_inst_set_urb_opcode(brw, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
350
351 brw_inst_set_mlen(brw, insn, inst->mlen);
352 brw_inst_set_rlen(brw, insn, 0);
353 brw_inst_set_eot(brw, insn, inst->eot);
354 brw_inst_set_header_present(brw, insn, true);
355 brw_inst_set_urb_global_offset(brw, insn, inst->offset);
356 }
357
358 void
359 fs_generator::generate_blorp_fb_write(fs_inst *inst)
360 {
361 brw_fb_WRITE(p,
362 16 /* dispatch_width */,
363 brw_message_reg(inst->base_mrf),
364 brw_reg_from_fs_reg(&inst->src[0]),
365 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
366 inst->target,
367 inst->mlen,
368 0,
369 true,
370 inst->header_present);
371 }
372
373 /* Computes the integer pixel x,y values from the origin.
374 *
375 * This is the basis of gl_FragCoord computation, but is also used
376 * pre-gen6 for computing the deltas from v0 for computing
377 * interpolation.
378 */
379 void
380 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
381 {
382 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
383 struct brw_reg src;
384 struct brw_reg deltas;
385
386 if (is_x) {
387 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
388 deltas = brw_imm_v(0x10101010);
389 } else {
390 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
391 deltas = brw_imm_v(0x11001100);
392 }
393
394 if (dispatch_width == 16) {
395 dst = vec16(dst);
396 }
397
398 /* We do this SIMD8 or SIMD16, but since the destination is UW we
399 * don't do compression in the SIMD16 case.
400 */
401 brw_push_insn_state(p);
402 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
403 brw_ADD(p, dst, src, deltas);
404 brw_pop_insn_state(p);
405 }
406
407 void
408 fs_generator::generate_linterp(fs_inst *inst,
409 struct brw_reg dst, struct brw_reg *src)
410 {
411 struct brw_reg delta_x = src[0];
412 struct brw_reg delta_y = src[1];
413 struct brw_reg interp = src[2];
414
415 if (brw->has_pln &&
416 delta_y.nr == delta_x.nr + 1 &&
417 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
418 brw_PLN(p, dst, interp, delta_x);
419 } else {
420 brw_LINE(p, brw_null_reg(), interp, delta_x);
421 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
422 }
423 }
424
425 void
426 fs_generator::generate_math_gen6(fs_inst *inst,
427 struct brw_reg dst,
428 struct brw_reg src0,
429 struct brw_reg src1)
430 {
431 int op = brw_math_function(inst->opcode);
432 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
433
434 if (dispatch_width == 8) {
435 gen6_math(p, dst, op, src0, src1);
436 } else if (dispatch_width == 16) {
437 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
438 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
439 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
440 gen6_math(p, sechalf(dst), op, sechalf(src0),
441 binop ? sechalf(src1) : brw_null_reg());
442 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
443 }
444 }
445
446 void
447 fs_generator::generate_math_gen4(fs_inst *inst,
448 struct brw_reg dst,
449 struct brw_reg src)
450 {
451 int op = brw_math_function(inst->opcode);
452
453 assert(inst->mlen >= 1);
454
455 if (dispatch_width == 8) {
456 gen4_math(p, dst,
457 op,
458 inst->base_mrf, src,
459 BRW_MATH_PRECISION_FULL);
460 } else if (dispatch_width == 16) {
461 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
462 gen4_math(p, firsthalf(dst),
463 op,
464 inst->base_mrf, firsthalf(src),
465 BRW_MATH_PRECISION_FULL);
466 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
467 gen4_math(p, sechalf(dst),
468 op,
469 inst->base_mrf + 1, sechalf(src),
470 BRW_MATH_PRECISION_FULL);
471
472 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
473 }
474 }
475
476 void
477 fs_generator::generate_math_g45(fs_inst *inst,
478 struct brw_reg dst,
479 struct brw_reg src)
480 {
481 if (inst->opcode == SHADER_OPCODE_POW ||
482 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
483 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
484 generate_math_gen4(inst, dst, src);
485 return;
486 }
487
488 int op = brw_math_function(inst->opcode);
489
490 assert(inst->mlen >= 1);
491
492 gen4_math(p, dst,
493 op,
494 inst->base_mrf, src,
495 BRW_MATH_PRECISION_FULL);
496 }
497
498 void
499 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
500 struct brw_reg sampler_index)
501 {
502 int msg_type = -1;
503 int rlen = 4;
504 uint32_t simd_mode;
505 uint32_t return_format;
506
507 switch (dst.type) {
508 case BRW_REGISTER_TYPE_D:
509 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
510 break;
511 case BRW_REGISTER_TYPE_UD:
512 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
513 break;
514 default:
515 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
516 break;
517 }
518
519 switch (inst->exec_size) {
520 case 8:
521 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
522 break;
523 case 16:
524 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
525 break;
526 default:
527 unreachable("Invalid width for texture instruction");
528 }
529
530 if (brw->gen >= 5) {
531 switch (inst->opcode) {
532 case SHADER_OPCODE_TEX:
533 if (inst->shadow_compare) {
534 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
535 } else {
536 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
537 }
538 break;
539 case FS_OPCODE_TXB:
540 if (inst->shadow_compare) {
541 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
542 } else {
543 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
544 }
545 break;
546 case SHADER_OPCODE_TXL:
547 if (inst->shadow_compare) {
548 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
549 } else {
550 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
551 }
552 break;
553 case SHADER_OPCODE_TXS:
554 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
555 break;
556 case SHADER_OPCODE_TXD:
557 if (inst->shadow_compare) {
558 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
559 assert(brw->gen >= 8 || brw->is_haswell);
560 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
561 } else {
562 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
563 }
564 break;
565 case SHADER_OPCODE_TXF:
566 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
567 break;
568 case SHADER_OPCODE_TXF_CMS:
569 if (brw->gen >= 7)
570 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
571 else
572 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
573 break;
574 case SHADER_OPCODE_TXF_UMS:
575 assert(brw->gen >= 7);
576 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
577 break;
578 case SHADER_OPCODE_TXF_MCS:
579 assert(brw->gen >= 7);
580 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
581 break;
582 case SHADER_OPCODE_LOD:
583 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
584 break;
585 case SHADER_OPCODE_TG4:
586 if (inst->shadow_compare) {
587 assert(brw->gen >= 7);
588 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
589 } else {
590 assert(brw->gen >= 6);
591 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
592 }
593 break;
594 case SHADER_OPCODE_TG4_OFFSET:
595 assert(brw->gen >= 7);
596 if (inst->shadow_compare) {
597 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
598 } else {
599 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
600 }
601 break;
602 default:
603 unreachable("not reached");
604 }
605 } else {
606 switch (inst->opcode) {
607 case SHADER_OPCODE_TEX:
608 /* Note that G45 and older determines shadow compare and dispatch width
609 * from message length for most messages.
610 */
611 assert(dispatch_width == 8);
612 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
613 if (inst->shadow_compare) {
614 assert(inst->mlen == 6);
615 } else {
616 assert(inst->mlen <= 4);
617 }
618 break;
619 case FS_OPCODE_TXB:
620 if (inst->shadow_compare) {
621 assert(inst->mlen == 6);
622 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
623 } else {
624 assert(inst->mlen == 9);
625 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
626 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
627 }
628 break;
629 case SHADER_OPCODE_TXL:
630 if (inst->shadow_compare) {
631 assert(inst->mlen == 6);
632 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
633 } else {
634 assert(inst->mlen == 9);
635 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
636 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
637 }
638 break;
639 case SHADER_OPCODE_TXD:
640 /* There is no sample_d_c message; comparisons are done manually */
641 assert(inst->mlen == 7 || inst->mlen == 10);
642 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
643 break;
644 case SHADER_OPCODE_TXF:
645 assert(inst->mlen == 9);
646 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
647 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
648 break;
649 case SHADER_OPCODE_TXS:
650 assert(inst->mlen == 3);
651 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
652 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
653 break;
654 default:
655 unreachable("not reached");
656 }
657 }
658 assert(msg_type != -1);
659
660 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
661 rlen = 8;
662 dst = vec16(dst);
663 }
664
665 assert(brw->gen < 7 || !inst->header_present ||
666 src.file == BRW_GENERAL_REGISTER_FILE);
667
668 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
669
670 /* Load the message header if present. If there's a texture offset,
671 * we need to set it up explicitly and load the offset bitfield.
672 * Otherwise, we can use an implied move from g0 to the first message reg.
673 */
674 if (inst->header_present) {
675 if (brw->gen < 6 && !inst->offset) {
676 /* Set up an implied move from g0 to the MRF. */
677 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
678 } else {
679 struct brw_reg header_reg;
680
681 if (brw->gen >= 7) {
682 header_reg = src;
683 } else {
684 assert(inst->base_mrf != -1);
685 header_reg = brw_message_reg(inst->base_mrf);
686 }
687
688 brw_push_insn_state(p);
689 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
690 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
691 /* Explicitly set up the message header by copying g0 to the MRF. */
692 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
693
694 if (inst->offset) {
695 /* Set the offset bits in DWord 2. */
696 brw_MOV(p, get_element_ud(header_reg, 2),
697 brw_imm_ud(inst->offset));
698 }
699
700 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
701 brw_pop_insn_state(p);
702 }
703 }
704
705 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
706 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
707 ? prog_data->binding_table.gather_texture_start
708 : prog_data->binding_table.texture_start;
709
710 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
711 uint32_t sampler = sampler_index.dw1.ud;
712
713 brw_SAMPLE(p,
714 retype(dst, BRW_REGISTER_TYPE_UW),
715 inst->base_mrf,
716 src,
717 sampler + base_binding_table_index,
718 sampler % 16,
719 msg_type,
720 rlen,
721 inst->mlen,
722 inst->header_present,
723 simd_mode,
724 return_format);
725
726 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
727 } else {
728 /* Non-const sampler index */
729 /* Note: this clobbers `dst` as a temporary before emitting the send */
730
731 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
732 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
733
734 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
735
736 brw_push_insn_state(p);
737 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
738 brw_set_default_access_mode(p, BRW_ALIGN_1);
739
740 /* Some care required: `sampler` and `temp` may alias:
741 * addr = sampler & 0xff
742 * temp = (sampler << 8) & 0xf00
743 * addr = addr | temp
744 */
745 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
746 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
747 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
748 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
749 brw_OR(p, addr, addr, temp);
750
751 /* a0.0 |= <descriptor> */
752 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
753 brw_set_sampler_message(p, insn_or,
754 0 /* surface */,
755 0 /* sampler */,
756 msg_type,
757 rlen,
758 inst->mlen /* mlen */,
759 inst->header_present /* header */,
760 simd_mode,
761 return_format);
762 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
763 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
764 brw_set_src0(p, insn_or, addr);
765 brw_set_dest(p, insn_or, addr);
766
767
768 /* dst = send(offset, a0.0) */
769 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
770 brw_set_dest(p, insn_send, dst);
771 brw_set_src0(p, insn_send, src);
772 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
773
774 brw_pop_insn_state(p);
775
776 /* visitor knows more than we do about the surface limit required,
777 * so has already done marking.
778 */
779 }
780 }
781
782
783 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
784 * looking like:
785 *
786 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
787 *
788 * Ideally, we want to produce:
789 *
790 * DDX DDY
791 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
792 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
793 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
794 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
795 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
796 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
797 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
798 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
799 *
800 * and add another set of two more subspans if in 16-pixel dispatch mode.
801 *
802 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
803 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
804 * pair. But the ideal approximation may impose a huge performance cost on
805 * sample_d. On at least Haswell, sample_d instruction does some
806 * optimizations if the same LOD is used for all pixels in the subspan.
807 *
808 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
809 * appropriate swizzling.
810 */
811 void
812 fs_generator::generate_ddx(enum opcode opcode,
813 struct brw_reg dst, struct brw_reg src)
814 {
815 unsigned vstride, width;
816
817 if (opcode == FS_OPCODE_DDX_FINE) {
818 /* produce accurate derivatives */
819 vstride = BRW_VERTICAL_STRIDE_2;
820 width = BRW_WIDTH_2;
821 } else {
822 /* replicate the derivative at the top-left pixel to other pixels */
823 vstride = BRW_VERTICAL_STRIDE_4;
824 width = BRW_WIDTH_4;
825 }
826
827 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
828 src.negate, src.abs,
829 BRW_REGISTER_TYPE_F,
830 vstride,
831 width,
832 BRW_HORIZONTAL_STRIDE_0,
833 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
834 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
835 src.negate, src.abs,
836 BRW_REGISTER_TYPE_F,
837 vstride,
838 width,
839 BRW_HORIZONTAL_STRIDE_0,
840 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
841 brw_ADD(p, dst, src0, negate(src1));
842 }
843
844 /* The negate_value boolean is used to negate the derivative computation for
845 * FBOs, since they place the origin at the upper left instead of the lower
846 * left.
847 */
848 void
849 fs_generator::generate_ddy(enum opcode opcode,
850 struct brw_reg dst, struct brw_reg src,
851 bool negate_value)
852 {
853 if (opcode == FS_OPCODE_DDY_FINE) {
854 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
855 * Region Restrictions):
856 *
857 * In Align16 access mode, SIMD16 is not allowed for DW operations
858 * and SIMD8 is not allowed for DF operations.
859 *
860 * In this context, "DW operations" means "operations acting on 32-bit
861 * values", so it includes operations on floats.
862 *
863 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
864 * (Instruction Compression -> Rules and Restrictions):
865 *
866 * A compressed instruction must be in Align1 access mode. Align16
867 * mode instructions cannot be compressed.
868 *
869 * Similar text exists in the g45 PRM.
870 *
871 * On these platforms, if we're building a SIMD16 shader, we need to
872 * manually unroll to a pair of SIMD8 instructions.
873 */
874 bool unroll_to_simd8 =
875 (dispatch_width == 16 &&
876 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
877
878 /* produce accurate derivatives */
879 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
880 src.negate, src.abs,
881 BRW_REGISTER_TYPE_F,
882 BRW_VERTICAL_STRIDE_4,
883 BRW_WIDTH_4,
884 BRW_HORIZONTAL_STRIDE_1,
885 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
886 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
887 src.negate, src.abs,
888 BRW_REGISTER_TYPE_F,
889 BRW_VERTICAL_STRIDE_4,
890 BRW_WIDTH_4,
891 BRW_HORIZONTAL_STRIDE_1,
892 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
893 brw_push_insn_state(p);
894 brw_set_default_access_mode(p, BRW_ALIGN_16);
895 if (unroll_to_simd8) {
896 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
897 if (negate_value) {
898 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
899 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
900 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
901 } else {
902 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
903 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
904 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
905 }
906 } else {
907 if (negate_value)
908 brw_ADD(p, dst, src1, negate(src0));
909 else
910 brw_ADD(p, dst, src0, negate(src1));
911 }
912 brw_pop_insn_state(p);
913 } else {
914 /* replicate the derivative at the top-left pixel to other pixels */
915 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
916 src.negate, src.abs,
917 BRW_REGISTER_TYPE_F,
918 BRW_VERTICAL_STRIDE_4,
919 BRW_WIDTH_4,
920 BRW_HORIZONTAL_STRIDE_0,
921 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
922 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
923 src.negate, src.abs,
924 BRW_REGISTER_TYPE_F,
925 BRW_VERTICAL_STRIDE_4,
926 BRW_WIDTH_4,
927 BRW_HORIZONTAL_STRIDE_0,
928 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
929 if (negate_value)
930 brw_ADD(p, dst, src1, negate(src0));
931 else
932 brw_ADD(p, dst, src0, negate(src1));
933 }
934 }
935
936 void
937 fs_generator::generate_discard_jump(fs_inst *inst)
938 {
939 assert(brw->gen >= 6);
940
941 /* This HALT will be patched up at FB write time to point UIP at the end of
942 * the program, and at brw_uip_jip() JIP will be set to the end of the
943 * current block (or the program).
944 */
945 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
946
947 brw_push_insn_state(p);
948 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
949 gen6_HALT(p);
950 brw_pop_insn_state(p);
951 }
952
953 void
954 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
955 {
956 assert(inst->mlen != 0);
957
958 brw_MOV(p,
959 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
960 retype(src, BRW_REGISTER_TYPE_UD));
961 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
962 inst->exec_size / 8, inst->offset);
963 }
964
965 void
966 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
967 {
968 assert(inst->mlen != 0);
969
970 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
971 inst->exec_size / 8, inst->offset);
972 }
973
974 void
975 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
976 {
977 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
978 }
979
980 void
981 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
982 struct brw_reg dst,
983 struct brw_reg index,
984 struct brw_reg offset)
985 {
986 assert(inst->mlen != 0);
987
988 assert(index.file == BRW_IMMEDIATE_VALUE &&
989 index.type == BRW_REGISTER_TYPE_UD);
990 uint32_t surf_index = index.dw1.ud;
991
992 assert(offset.file == BRW_IMMEDIATE_VALUE &&
993 offset.type == BRW_REGISTER_TYPE_UD);
994 uint32_t read_offset = offset.dw1.ud;
995
996 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
997 read_offset, surf_index);
998
999 brw_mark_surface_used(prog_data, surf_index);
1000 }
1001
1002 void
1003 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1004 struct brw_reg dst,
1005 struct brw_reg index,
1006 struct brw_reg offset)
1007 {
1008 assert(inst->mlen == 0);
1009 assert(index.type == BRW_REGISTER_TYPE_UD);
1010
1011 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1012 /* Reference just the dword we need, to avoid angering validate_reg(). */
1013 offset = brw_vec1_grf(offset.nr, 0);
1014
1015 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1016 * the destination loaded consecutively from the same offset (which appears
1017 * in the first component, and the rest are ignored).
1018 */
1019 dst.width = BRW_WIDTH_4;
1020
1021 struct brw_reg src = offset;
1022 bool header_present = false;
1023 int mlen = 1;
1024
1025 if (brw->gen >= 9) {
1026 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1027 src = retype(brw_vec8_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD);
1028 mlen = 2;
1029 header_present = true;
1030
1031 brw_push_insn_state(p);
1032 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1033 brw_MOV(p, src, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1034 brw_set_default_access_mode(p, BRW_ALIGN_1);
1035
1036 brw_MOV(p, get_element_ud(src, 2),
1037 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1038 brw_pop_insn_state(p);
1039 }
1040
1041 if (index.file == BRW_IMMEDIATE_VALUE) {
1042
1043 uint32_t surf_index = index.dw1.ud;
1044
1045 brw_push_insn_state(p);
1046 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1047 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1048 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1049 brw_pop_insn_state(p);
1050
1051 brw_set_dest(p, send, dst);
1052 brw_set_src0(p, send, src);
1053 brw_set_sampler_message(p, send,
1054 surf_index,
1055 0, /* LD message ignores sampler unit */
1056 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1057 1, /* rlen */
1058 mlen,
1059 header_present,
1060 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1061 0);
1062
1063 brw_mark_surface_used(prog_data, surf_index);
1064
1065 } else {
1066
1067 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1068
1069 brw_push_insn_state(p);
1070 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1071 brw_set_default_access_mode(p, BRW_ALIGN_1);
1072
1073 /* a0.0 = surf_index & 0xff */
1074 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1075 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1076 brw_set_dest(p, insn_and, addr);
1077 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1078 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1079
1080
1081 /* a0.0 |= <descriptor> */
1082 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1083 brw_set_sampler_message(p, insn_or,
1084 0 /* surface */,
1085 0 /* sampler */,
1086 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1087 1 /* rlen */,
1088 mlen,
1089 header_present,
1090 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1091 0);
1092 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1093 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1094 brw_set_src0(p, insn_or, addr);
1095 brw_set_dest(p, insn_or, addr);
1096
1097
1098 /* dst = send(offset, a0.0) */
1099 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1100 brw_set_dest(p, insn_send, dst);
1101 brw_set_src0(p, insn_send, src);
1102 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1103
1104 brw_pop_insn_state(p);
1105
1106 /* visitor knows more than we do about the surface limit required,
1107 * so has already done marking.
1108 */
1109
1110 }
1111 }
1112
1113 void
1114 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1115 struct brw_reg dst,
1116 struct brw_reg index,
1117 struct brw_reg offset)
1118 {
1119 assert(brw->gen < 7); /* Should use the gen7 variant. */
1120 assert(inst->header_present);
1121 assert(inst->mlen);
1122
1123 assert(index.file == BRW_IMMEDIATE_VALUE &&
1124 index.type == BRW_REGISTER_TYPE_UD);
1125 uint32_t surf_index = index.dw1.ud;
1126
1127 uint32_t simd_mode, rlen, msg_type;
1128 if (dispatch_width == 16) {
1129 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1130 rlen = 8;
1131 } else {
1132 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1133 rlen = 4;
1134 }
1135
1136 if (brw->gen >= 5)
1137 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1138 else {
1139 /* We always use the SIMD16 message so that we only have to load U, and
1140 * not V or R.
1141 */
1142 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1143 assert(inst->mlen == 3);
1144 assert(inst->regs_written == 8);
1145 rlen = 8;
1146 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1147 }
1148
1149 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1150 BRW_REGISTER_TYPE_D);
1151 brw_MOV(p, offset_mrf, offset);
1152
1153 struct brw_reg header = brw_vec8_grf(0, 0);
1154 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1155
1156 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1157 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
1158 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1159 brw_set_src0(p, send, header);
1160 if (brw->gen < 6)
1161 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
1162
1163 /* Our surface is set up as floats, regardless of what actual data is
1164 * stored in it.
1165 */
1166 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1167 brw_set_sampler_message(p, send,
1168 surf_index,
1169 0, /* sampler (unused) */
1170 msg_type,
1171 rlen,
1172 inst->mlen,
1173 inst->header_present,
1174 simd_mode,
1175 return_format);
1176
1177 brw_mark_surface_used(prog_data, surf_index);
1178 }
1179
1180 void
1181 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1182 struct brw_reg dst,
1183 struct brw_reg index,
1184 struct brw_reg offset)
1185 {
1186 assert(brw->gen >= 7);
1187 /* Varying-offset pull constant loads are treated as a normal expression on
1188 * gen7, so the fact that it's a send message is hidden at the IR level.
1189 */
1190 assert(!inst->header_present);
1191 assert(!inst->mlen);
1192 assert(index.type == BRW_REGISTER_TYPE_UD);
1193
1194 uint32_t simd_mode, rlen, mlen;
1195 if (dispatch_width == 16) {
1196 mlen = 2;
1197 rlen = 8;
1198 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1199 } else {
1200 mlen = 1;
1201 rlen = 4;
1202 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1203 }
1204
1205 if (index.file == BRW_IMMEDIATE_VALUE) {
1206
1207 uint32_t surf_index = index.dw1.ud;
1208
1209 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1210 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1211 brw_set_src0(p, send, offset);
1212 brw_set_sampler_message(p, send,
1213 surf_index,
1214 0, /* LD message ignores sampler unit */
1215 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1216 rlen,
1217 mlen,
1218 false, /* no header */
1219 simd_mode,
1220 0);
1221
1222 brw_mark_surface_used(prog_data, surf_index);
1223
1224 } else {
1225
1226 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1227
1228 brw_push_insn_state(p);
1229 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1230 brw_set_default_access_mode(p, BRW_ALIGN_1);
1231
1232 /* a0.0 = surf_index & 0xff */
1233 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1234 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1235 brw_set_dest(p, insn_and, addr);
1236 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1237 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1238
1239
1240 /* a0.0 |= <descriptor> */
1241 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1242 brw_set_sampler_message(p, insn_or,
1243 0 /* surface */,
1244 0 /* sampler */,
1245 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1246 rlen /* rlen */,
1247 mlen /* mlen */,
1248 false /* header */,
1249 simd_mode,
1250 0);
1251 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1252 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1253 brw_set_src0(p, insn_or, addr);
1254 brw_set_dest(p, insn_or, addr);
1255
1256
1257 /* dst = send(offset, a0.0) */
1258 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1259 brw_set_dest(p, insn_send, retype(dst, BRW_REGISTER_TYPE_UW));
1260 brw_set_src0(p, insn_send, offset);
1261 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1262
1263 brw_pop_insn_state(p);
1264
1265 /* visitor knows more than we do about the surface limit required,
1266 * so has already done marking.
1267 */
1268 }
1269 }
1270
1271 /**
1272 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1273 * into the flags register (f0.0).
1274 *
1275 * Used only on Gen6 and above.
1276 */
1277 void
1278 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1279 {
1280 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1281 struct brw_reg dispatch_mask;
1282
1283 if (brw->gen >= 6)
1284 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1285 else
1286 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1287
1288 brw_push_insn_state(p);
1289 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1290 brw_MOV(p, flags, dispatch_mask);
1291 brw_pop_insn_state(p);
1292 }
1293
1294 void
1295 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1296 struct brw_reg dst,
1297 struct brw_reg src,
1298 struct brw_reg msg_data,
1299 unsigned msg_type)
1300 {
1301 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1302 msg_data.type == BRW_REGISTER_TYPE_UD);
1303
1304 brw_pixel_interpolator_query(p,
1305 retype(dst, BRW_REGISTER_TYPE_UW),
1306 src,
1307 inst->pi_noperspective,
1308 msg_type,
1309 msg_data.dw1.ud,
1310 inst->mlen,
1311 inst->regs_written);
1312 }
1313
1314
1315 /**
1316 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1317 * sampler LD messages.
1318 *
1319 * We don't want to bake it into the send message's code generation because
1320 * that means we don't get a chance to schedule the instructions.
1321 */
1322 void
1323 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1324 struct brw_reg dst,
1325 struct brw_reg value)
1326 {
1327 assert(value.file == BRW_IMMEDIATE_VALUE);
1328
1329 brw_push_insn_state(p);
1330 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1331 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1332 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1333 brw_pop_insn_state(p);
1334 }
1335
1336 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1337 * (when mask is passed as a uniform) of register mask before moving it
1338 * to register dst.
1339 */
1340 void
1341 fs_generator::generate_set_omask(fs_inst *inst,
1342 struct brw_reg dst,
1343 struct brw_reg mask)
1344 {
1345 bool stride_8_8_1 =
1346 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1347 mask.width == BRW_WIDTH_8 &&
1348 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1349
1350 bool stride_0_1_0 = has_scalar_region(mask);
1351
1352 assert(stride_8_8_1 || stride_0_1_0);
1353 assert(dst.type == BRW_REGISTER_TYPE_UW);
1354
1355 if (dispatch_width == 16)
1356 dst = vec16(dst);
1357 brw_push_insn_state(p);
1358 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1359 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1360
1361 if (stride_8_8_1) {
1362 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1363 } else if (stride_0_1_0) {
1364 brw_MOV(p, dst, retype(mask, dst.type));
1365 }
1366 brw_pop_insn_state(p);
1367 }
1368
1369 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1370 * the ADD instruction.
1371 */
1372 void
1373 fs_generator::generate_set_sample_id(fs_inst *inst,
1374 struct brw_reg dst,
1375 struct brw_reg src0,
1376 struct brw_reg src1)
1377 {
1378 assert(dst.type == BRW_REGISTER_TYPE_D ||
1379 dst.type == BRW_REGISTER_TYPE_UD);
1380 assert(src0.type == BRW_REGISTER_TYPE_D ||
1381 src0.type == BRW_REGISTER_TYPE_UD);
1382
1383 brw_push_insn_state(p);
1384 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1385 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1386 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1387 if (dispatch_width == 8) {
1388 brw_ADD(p, dst, src0, reg);
1389 } else if (dispatch_width == 16) {
1390 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1391 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1392 }
1393 brw_pop_insn_state(p);
1394 }
1395
1396 /**
1397 * Change the register's data type from UD to W, doubling the strides in order
1398 * to compensate for halving the data type width.
1399 */
1400 static struct brw_reg
1401 ud_reg_to_w(struct brw_reg r)
1402 {
1403 assert(r.type == BRW_REGISTER_TYPE_UD);
1404 r.type = BRW_REGISTER_TYPE_W;
1405
1406 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1407 * doubles the real stride.
1408 */
1409 if (r.hstride != 0)
1410 ++r.hstride;
1411 if (r.vstride != 0)
1412 ++r.vstride;
1413
1414 return r;
1415 }
1416
1417 void
1418 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1419 struct brw_reg dst,
1420 struct brw_reg x,
1421 struct brw_reg y)
1422 {
1423 assert(brw->gen >= 7);
1424 assert(dst.type == BRW_REGISTER_TYPE_UD);
1425 assert(x.type == BRW_REGISTER_TYPE_F);
1426 assert(y.type == BRW_REGISTER_TYPE_F);
1427
1428 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1429 *
1430 * Because this instruction does not have a 16-bit floating-point type,
1431 * the destination data type must be Word (W).
1432 *
1433 * The destination must be DWord-aligned and specify a horizontal stride
1434 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1435 * each destination channel and the upper word is not modified.
1436 */
1437 struct brw_reg dst_w = ud_reg_to_w(dst);
1438
1439 /* Give each 32-bit channel of dst the form below , where "." means
1440 * unchanged.
1441 * 0x....hhhh
1442 */
1443 brw_F32TO16(p, dst_w, y);
1444
1445 /* Now the form:
1446 * 0xhhhh0000
1447 */
1448 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1449
1450 /* And, finally the form of packHalf2x16's output:
1451 * 0xhhhhllll
1452 */
1453 brw_F32TO16(p, dst_w, x);
1454 }
1455
1456 void
1457 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1458 struct brw_reg dst,
1459 struct brw_reg src)
1460 {
1461 assert(brw->gen >= 7);
1462 assert(dst.type == BRW_REGISTER_TYPE_F);
1463 assert(src.type == BRW_REGISTER_TYPE_UD);
1464
1465 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1466 *
1467 * Because this instruction does not have a 16-bit floating-point type,
1468 * the source data type must be Word (W). The destination type must be
1469 * F (Float).
1470 */
1471 struct brw_reg src_w = ud_reg_to_w(src);
1472
1473 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1474 * For the Y case, we wish to access only the upper word; therefore
1475 * a 16-bit subregister offset is needed.
1476 */
1477 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1478 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1479 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1480 src_w.subnr += 2;
1481
1482 brw_F16TO32(p, dst, src_w);
1483 }
1484
1485 void
1486 fs_generator::generate_shader_time_add(fs_inst *inst,
1487 struct brw_reg payload,
1488 struct brw_reg offset,
1489 struct brw_reg value)
1490 {
1491 assert(brw->gen >= 7);
1492 brw_push_insn_state(p);
1493 brw_set_default_mask_control(p, true);
1494
1495 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1496 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1497 offset.type);
1498 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1499 value.type);
1500
1501 assert(offset.file == BRW_IMMEDIATE_VALUE);
1502 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1503 value.width = BRW_WIDTH_1;
1504 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1505 value.vstride = BRW_VERTICAL_STRIDE_0;
1506 } else {
1507 assert(value.file == BRW_IMMEDIATE_VALUE);
1508 }
1509
1510 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1511 * case, and we don't really care about squeezing every bit of performance
1512 * out of this path, so we just emit the MOVs from here.
1513 */
1514 brw_MOV(p, payload_offset, offset);
1515 brw_MOV(p, payload_value, value);
1516 brw_shader_time_add(p, payload,
1517 prog_data->binding_table.shader_time_start);
1518 brw_pop_insn_state(p);
1519
1520 brw_mark_surface_used(prog_data,
1521 prog_data->binding_table.shader_time_start);
1522 }
1523
1524 void
1525 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1526 struct brw_reg payload,
1527 struct brw_reg atomic_op,
1528 struct brw_reg surf_index)
1529 {
1530 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1531 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1532 surf_index.file == BRW_IMMEDIATE_VALUE &&
1533 surf_index.type == BRW_REGISTER_TYPE_UD);
1534
1535 brw_untyped_atomic(p, dst, payload, atomic_op.dw1.ud, surf_index.dw1.ud,
1536 inst->mlen, inst->exec_size / 8);
1537
1538 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1539 }
1540
1541 void
1542 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1543 struct brw_reg payload,
1544 struct brw_reg surf_index)
1545 {
1546 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1547 surf_index.type == BRW_REGISTER_TYPE_UD);
1548
1549 brw_untyped_surface_read(p, dst, payload,
1550 surf_index.dw1.ud,
1551 inst->mlen, inst->exec_size / 8);
1552
1553 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1554 }
1555
1556 void
1557 fs_generator::enable_debug(const char *shader_name)
1558 {
1559 debug_flag = true;
1560 this->shader_name = shader_name;
1561 }
1562
1563 int
1564 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1565 {
1566 /* align to 64 byte boundary. */
1567 while (p->next_insn_offset % 64)
1568 brw_NOP(p);
1569
1570 this->dispatch_width = dispatch_width;
1571 if (dispatch_width == 16)
1572 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1573
1574 int start_offset = p->next_insn_offset;
1575 int loop_count = 0;
1576
1577 struct annotation_info annotation;
1578 memset(&annotation, 0, sizeof(annotation));
1579
1580 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1581 struct brw_reg src[3], dst;
1582 unsigned int last_insn_offset = p->next_insn_offset;
1583
1584 if (unlikely(debug_flag))
1585 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1586
1587 for (unsigned int i = 0; i < inst->sources; i++) {
1588 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1589
1590 /* The accumulator result appears to get used for the
1591 * conditional modifier generation. When negating a UD
1592 * value, there is a 33rd bit generated for the sign in the
1593 * accumulator value, so now you can't check, for example,
1594 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1595 */
1596 assert(!inst->conditional_mod ||
1597 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1598 !inst->src[i].negate);
1599 }
1600 dst = brw_reg_from_fs_reg(&inst->dst);
1601
1602 brw_set_default_predicate_control(p, inst->predicate);
1603 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1604 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1605 brw_set_default_saturate(p, inst->saturate);
1606 brw_set_default_mask_control(p, inst->force_writemask_all);
1607 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1608
1609 switch (inst->exec_size) {
1610 case 1:
1611 case 2:
1612 case 4:
1613 assert(inst->force_writemask_all);
1614 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1615 break;
1616 case 8:
1617 if (inst->force_sechalf) {
1618 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1619 } else {
1620 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1621 }
1622 break;
1623 case 16:
1624 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1625 break;
1626 default:
1627 unreachable(!"Invalid instruction width");
1628 }
1629
1630 switch (inst->opcode) {
1631 case BRW_OPCODE_MOV:
1632 brw_MOV(p, dst, src[0]);
1633 break;
1634 case BRW_OPCODE_ADD:
1635 brw_ADD(p, dst, src[0], src[1]);
1636 break;
1637 case BRW_OPCODE_MUL:
1638 brw_MUL(p, dst, src[0], src[1]);
1639 break;
1640 case BRW_OPCODE_AVG:
1641 brw_AVG(p, dst, src[0], src[1]);
1642 break;
1643 case BRW_OPCODE_MACH:
1644 brw_MACH(p, dst, src[0], src[1]);
1645 break;
1646
1647 case BRW_OPCODE_LINE:
1648 brw_LINE(p, dst, src[0], src[1]);
1649 break;
1650
1651 case BRW_OPCODE_MAD:
1652 assert(brw->gen >= 6);
1653 brw_set_default_access_mode(p, BRW_ALIGN_16);
1654 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1655 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1656 brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1657 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1658 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1659 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1660 } else {
1661 brw_MAD(p, dst, src[0], src[1], src[2]);
1662 }
1663 brw_set_default_access_mode(p, BRW_ALIGN_1);
1664 break;
1665
1666 case BRW_OPCODE_LRP:
1667 assert(brw->gen >= 6);
1668 brw_set_default_access_mode(p, BRW_ALIGN_16);
1669 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1670 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1671 brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1672 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1673 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1674 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1675 } else {
1676 brw_LRP(p, dst, src[0], src[1], src[2]);
1677 }
1678 brw_set_default_access_mode(p, BRW_ALIGN_1);
1679 break;
1680
1681 case BRW_OPCODE_FRC:
1682 brw_FRC(p, dst, src[0]);
1683 break;
1684 case BRW_OPCODE_RNDD:
1685 brw_RNDD(p, dst, src[0]);
1686 break;
1687 case BRW_OPCODE_RNDE:
1688 brw_RNDE(p, dst, src[0]);
1689 break;
1690 case BRW_OPCODE_RNDZ:
1691 brw_RNDZ(p, dst, src[0]);
1692 break;
1693
1694 case BRW_OPCODE_AND:
1695 brw_AND(p, dst, src[0], src[1]);
1696 break;
1697 case BRW_OPCODE_OR:
1698 brw_OR(p, dst, src[0], src[1]);
1699 break;
1700 case BRW_OPCODE_XOR:
1701 brw_XOR(p, dst, src[0], src[1]);
1702 break;
1703 case BRW_OPCODE_NOT:
1704 brw_NOT(p, dst, src[0]);
1705 break;
1706 case BRW_OPCODE_ASR:
1707 brw_ASR(p, dst, src[0], src[1]);
1708 break;
1709 case BRW_OPCODE_SHR:
1710 brw_SHR(p, dst, src[0], src[1]);
1711 break;
1712 case BRW_OPCODE_SHL:
1713 brw_SHL(p, dst, src[0], src[1]);
1714 break;
1715 case BRW_OPCODE_F32TO16:
1716 assert(brw->gen >= 7);
1717 brw_F32TO16(p, dst, src[0]);
1718 break;
1719 case BRW_OPCODE_F16TO32:
1720 assert(brw->gen >= 7);
1721 brw_F16TO32(p, dst, src[0]);
1722 break;
1723 case BRW_OPCODE_CMP:
1724 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1725 break;
1726 case BRW_OPCODE_SEL:
1727 brw_SEL(p, dst, src[0], src[1]);
1728 break;
1729 case BRW_OPCODE_BFREV:
1730 assert(brw->gen >= 7);
1731 /* BFREV only supports UD type for src and dst. */
1732 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1733 retype(src[0], BRW_REGISTER_TYPE_UD));
1734 break;
1735 case BRW_OPCODE_FBH:
1736 assert(brw->gen >= 7);
1737 /* FBH only supports UD type for dst. */
1738 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1739 break;
1740 case BRW_OPCODE_FBL:
1741 assert(brw->gen >= 7);
1742 /* FBL only supports UD type for dst. */
1743 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1744 break;
1745 case BRW_OPCODE_CBIT:
1746 assert(brw->gen >= 7);
1747 /* CBIT only supports UD type for dst. */
1748 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1749 break;
1750 case BRW_OPCODE_ADDC:
1751 assert(brw->gen >= 7);
1752 brw_ADDC(p, dst, src[0], src[1]);
1753 break;
1754 case BRW_OPCODE_SUBB:
1755 assert(brw->gen >= 7);
1756 brw_SUBB(p, dst, src[0], src[1]);
1757 break;
1758 case BRW_OPCODE_MAC:
1759 brw_MAC(p, dst, src[0], src[1]);
1760 break;
1761
1762 case BRW_OPCODE_BFE:
1763 assert(brw->gen >= 7);
1764 brw_set_default_access_mode(p, BRW_ALIGN_16);
1765 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1766 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1767 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1768 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1769 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1770 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1771 } else {
1772 brw_BFE(p, dst, src[0], src[1], src[2]);
1773 }
1774 brw_set_default_access_mode(p, BRW_ALIGN_1);
1775 break;
1776
1777 case BRW_OPCODE_BFI1:
1778 assert(brw->gen >= 7);
1779 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1780 * should
1781 *
1782 * "Force BFI instructions to be executed always in SIMD8."
1783 */
1784 if (dispatch_width == 16 && brw->is_haswell) {
1785 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1786 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1787 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1788 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1789 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1790 } else {
1791 brw_BFI1(p, dst, src[0], src[1]);
1792 }
1793 break;
1794 case BRW_OPCODE_BFI2:
1795 assert(brw->gen >= 7);
1796 brw_set_default_access_mode(p, BRW_ALIGN_16);
1797 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1798 * should
1799 *
1800 * "Force BFI instructions to be executed always in SIMD8."
1801 *
1802 * Otherwise we would be able to emit compressed instructions like we
1803 * do for the other three-source instructions.
1804 */
1805 if (dispatch_width == 16 && brw->gen < 8) {
1806 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1807 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1808 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1809 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1810 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1811 } else {
1812 brw_BFI2(p, dst, src[0], src[1], src[2]);
1813 }
1814 brw_set_default_access_mode(p, BRW_ALIGN_1);
1815 break;
1816
1817 case BRW_OPCODE_IF:
1818 if (inst->src[0].file != BAD_FILE) {
1819 /* The instruction has an embedded compare (only allowed on gen6) */
1820 assert(brw->gen == 6);
1821 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1822 } else {
1823 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1824 }
1825 break;
1826
1827 case BRW_OPCODE_ELSE:
1828 brw_ELSE(p);
1829 break;
1830 case BRW_OPCODE_ENDIF:
1831 brw_ENDIF(p);
1832 break;
1833
1834 case BRW_OPCODE_DO:
1835 brw_DO(p, BRW_EXECUTE_8);
1836 break;
1837
1838 case BRW_OPCODE_BREAK:
1839 brw_BREAK(p);
1840 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1841 break;
1842 case BRW_OPCODE_CONTINUE:
1843 brw_CONT(p);
1844 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1845 break;
1846
1847 case BRW_OPCODE_WHILE:
1848 brw_WHILE(p);
1849 loop_count++;
1850 break;
1851
1852 case SHADER_OPCODE_RCP:
1853 case SHADER_OPCODE_RSQ:
1854 case SHADER_OPCODE_SQRT:
1855 case SHADER_OPCODE_EXP2:
1856 case SHADER_OPCODE_LOG2:
1857 case SHADER_OPCODE_SIN:
1858 case SHADER_OPCODE_COS:
1859 assert(brw->gen < 6 || inst->mlen == 0);
1860 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1861 if (brw->gen >= 7) {
1862 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1863 brw_null_reg());
1864 } else if (brw->gen == 6) {
1865 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1866 } else if (brw->gen == 5 || brw->is_g4x) {
1867 generate_math_g45(inst, dst, src[0]);
1868 } else {
1869 generate_math_gen4(inst, dst, src[0]);
1870 }
1871 break;
1872 case SHADER_OPCODE_INT_QUOTIENT:
1873 case SHADER_OPCODE_INT_REMAINDER:
1874 case SHADER_OPCODE_POW:
1875 assert(brw->gen < 6 || inst->mlen == 0);
1876 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1877 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1878 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1879 } else if (brw->gen >= 6) {
1880 generate_math_gen6(inst, dst, src[0], src[1]);
1881 } else {
1882 generate_math_gen4(inst, dst, src[0]);
1883 }
1884 break;
1885 case FS_OPCODE_PIXEL_X:
1886 generate_pixel_xy(dst, true);
1887 break;
1888 case FS_OPCODE_PIXEL_Y:
1889 generate_pixel_xy(dst, false);
1890 break;
1891 case FS_OPCODE_CINTERP:
1892 brw_MOV(p, dst, src[0]);
1893 break;
1894 case FS_OPCODE_LINTERP:
1895 generate_linterp(inst, dst, src);
1896 break;
1897 case SHADER_OPCODE_TEX:
1898 case FS_OPCODE_TXB:
1899 case SHADER_OPCODE_TXD:
1900 case SHADER_OPCODE_TXF:
1901 case SHADER_OPCODE_TXF_CMS:
1902 case SHADER_OPCODE_TXF_UMS:
1903 case SHADER_OPCODE_TXF_MCS:
1904 case SHADER_OPCODE_TXL:
1905 case SHADER_OPCODE_TXS:
1906 case SHADER_OPCODE_LOD:
1907 case SHADER_OPCODE_TG4:
1908 case SHADER_OPCODE_TG4_OFFSET:
1909 generate_tex(inst, dst, src[0], src[1]);
1910 break;
1911 case FS_OPCODE_DDX_COARSE:
1912 case FS_OPCODE_DDX_FINE:
1913 generate_ddx(inst->opcode, dst, src[0]);
1914 break;
1915 case FS_OPCODE_DDY_COARSE:
1916 case FS_OPCODE_DDY_FINE:
1917 assert(src[1].file == BRW_IMMEDIATE_VALUE);
1918 generate_ddy(inst->opcode, dst, src[0], src[1].dw1.ud);
1919 break;
1920
1921 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1922 generate_scratch_write(inst, src[0]);
1923 break;
1924
1925 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1926 generate_scratch_read(inst, dst);
1927 break;
1928
1929 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1930 generate_scratch_read_gen7(inst, dst);
1931 break;
1932
1933 case SHADER_OPCODE_URB_WRITE_SIMD8:
1934 generate_urb_write(inst, src[0]);
1935 break;
1936
1937 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1938 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1939 break;
1940
1941 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1942 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1943 break;
1944
1945 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1946 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1947 break;
1948
1949 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1950 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1951 break;
1952
1953 case FS_OPCODE_REP_FB_WRITE:
1954 case FS_OPCODE_FB_WRITE:
1955 generate_fb_write(inst, src[0]);
1956 break;
1957
1958 case FS_OPCODE_BLORP_FB_WRITE:
1959 generate_blorp_fb_write(inst);
1960 break;
1961
1962 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1963 generate_mov_dispatch_to_flags(inst);
1964 break;
1965
1966 case FS_OPCODE_DISCARD_JUMP:
1967 generate_discard_jump(inst);
1968 break;
1969
1970 case SHADER_OPCODE_SHADER_TIME_ADD:
1971 generate_shader_time_add(inst, src[0], src[1], src[2]);
1972 break;
1973
1974 case SHADER_OPCODE_UNTYPED_ATOMIC:
1975 generate_untyped_atomic(inst, dst, src[0], src[1], src[2]);
1976 break;
1977
1978 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1979 generate_untyped_surface_read(inst, dst, src[0], src[1]);
1980 break;
1981
1982 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1983 generate_set_simd4x2_offset(inst, dst, src[0]);
1984 break;
1985
1986 case FS_OPCODE_SET_OMASK:
1987 generate_set_omask(inst, dst, src[0]);
1988 break;
1989
1990 case FS_OPCODE_SET_SAMPLE_ID:
1991 generate_set_sample_id(inst, dst, src[0], src[1]);
1992 break;
1993
1994 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1995 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1996 break;
1997
1998 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1999 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2000 generate_unpack_half_2x16_split(inst, dst, src[0]);
2001 break;
2002
2003 case FS_OPCODE_PLACEHOLDER_HALT:
2004 /* This is the place where the final HALT needs to be inserted if
2005 * we've emitted any discards. If not, this will emit no code.
2006 */
2007 if (!patch_discard_jumps_to_fb_writes()) {
2008 if (unlikely(debug_flag)) {
2009 annotation.ann_count--;
2010 }
2011 }
2012 break;
2013
2014 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2015 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2016 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2017 break;
2018
2019 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2020 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2021 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2022 break;
2023
2024 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2025 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2026 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2027 break;
2028
2029 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2030 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2031 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2032 break;
2033
2034 default:
2035 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
2036 _mesa_problem(ctx, "Unsupported opcode `%s' in %s",
2037 opcode_descs[inst->opcode].name, stage_abbrev);
2038 } else {
2039 _mesa_problem(ctx, "Unsupported opcode %d in %s", inst->opcode,
2040 stage_abbrev);
2041 }
2042 abort();
2043
2044 case SHADER_OPCODE_LOAD_PAYLOAD:
2045 unreachable("Should be lowered by lower_load_payload()");
2046 }
2047
2048 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2049 assert(p->next_insn_offset == last_insn_offset + 16 ||
2050 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2051 "emitting more than 1 instruction");
2052
2053 brw_inst *last = &p->store[last_insn_offset / 16];
2054
2055 if (inst->conditional_mod)
2056 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
2057 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
2058 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
2059 }
2060 }
2061
2062 brw_set_uip_jip(p);
2063 annotation_finalize(&annotation, p->next_insn_offset);
2064
2065 int before_size = p->next_insn_offset - start_offset;
2066 brw_compact_instructions(p, start_offset, annotation.ann_count,
2067 annotation.ann);
2068 int after_size = p->next_insn_offset - start_offset;
2069
2070 if (unlikely(debug_flag)) {
2071 fprintf(stderr, "Native code for %s\n"
2072 "SIMD%d shader: %d instructions. %d loops. Compacted %d to %d"
2073 " bytes (%.0f%%)\n",
2074 shader_name,
2075 dispatch_width, before_size / 16, loop_count, before_size, after_size,
2076 100.0f * (before_size - after_size) / before_size);
2077
2078 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
2079 ralloc_free(annotation.ann);
2080 }
2081
2082 static GLuint msg_id = 0;
2083 _mesa_gl_debug(&brw->ctx, &msg_id,
2084 MESA_DEBUG_SOURCE_SHADER_COMPILER,
2085 MESA_DEBUG_TYPE_OTHER,
2086 MESA_DEBUG_SEVERITY_NOTIFICATION,
2087 "%s SIMD%d shader: %d inst, %d loops, "
2088 "compacted %d to %d bytes.\n",
2089 stage_abbrev, dispatch_width, before_size / 16, loop_count,
2090 before_size, after_size);
2091
2092 return start_offset;
2093 }
2094
2095 const unsigned *
2096 fs_generator::get_assembly(unsigned int *assembly_size)
2097 {
2098 return brw_get_program(p, assembly_size);
2099 }