2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
33 #include "brw_program.h"
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg
*reg
)
40 return BRW_ARCHITECTURE_REGISTER_FILE
;
43 return BRW_GENERAL_REGISTER_FILE
;
45 return BRW_MESSAGE_REGISTER_FILE
;
47 return BRW_IMMEDIATE_VALUE
;
51 unreachable("not reached");
53 return BRW_ARCHITECTURE_REGISTER_FILE
;
57 brw_reg_from_fs_reg(const struct brw_codegen
*p
,
58 fs_inst
*inst
, fs_reg
*reg
, unsigned gen
)
60 struct brw_reg brw_reg
;
64 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(gen
));
67 if (reg
->stride
== 0) {
68 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
69 } else if (!p
->compressed
&&
70 inst
->exec_size
* reg
->stride
* type_sz(reg
->type
) <= 32) {
71 brw_reg
= brw_vecn_reg(inst
->exec_size
, brw_file_from_reg(reg
),
73 brw_reg
= stride(brw_reg
, inst
->exec_size
* reg
->stride
,
74 inst
->exec_size
, reg
->stride
);
76 /* From the Haswell PRM:
78 * VertStride must be used to cross GRF register boundaries. This
79 * rule implies that elements within a 'Width' cannot cross GRF
82 * So, for registers that are large enough, we have to split the exec
83 * size in two and trust the compression state to sort it out.
85 assert(inst
->exec_size
/ 2 * reg
->stride
* type_sz(reg
->type
) <= 32);
86 brw_reg
= brw_vecn_reg(inst
->exec_size
/ 2, brw_file_from_reg(reg
),
88 brw_reg
= stride(brw_reg
, inst
->exec_size
/ 2 * reg
->stride
,
89 inst
->exec_size
/ 2, reg
->stride
);
92 brw_reg
= retype(brw_reg
, reg
->type
);
93 brw_reg
= byte_offset(brw_reg
, reg
->subreg_offset
);
94 brw_reg
.abs
= reg
->abs
;
95 brw_reg
.negate
= reg
->negate
;
100 brw_reg
= reg
->as_brw_reg();
103 /* Probably unused. */
104 brw_reg
= brw_null_reg();
108 unreachable("not reached");
114 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
117 struct brw_stage_prog_data
*prog_data
,
118 unsigned promoted_constants
,
119 bool runtime_check_aads_emit
,
120 gl_shader_stage stage
)
122 : compiler(compiler
), log_data(log_data
),
123 devinfo(compiler
->devinfo
), key(key
),
124 prog_data(prog_data
),
125 promoted_constants(promoted_constants
),
126 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
127 stage(stage
), mem_ctx(mem_ctx
)
129 p
= rzalloc(mem_ctx
, struct brw_codegen
);
130 brw_init_codegen(devinfo
, p
, mem_ctx
);
133 fs_generator::~fs_generator()
137 class ip_record
: public exec_node
{
139 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
150 fs_generator::patch_discard_jumps_to_fb_writes()
152 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
155 int scale
= brw_jump_scale(p
->devinfo
);
157 /* There is a somewhat strange undocumented requirement of using
158 * HALT, according to the simulator. If some channel has HALTed to
159 * a particular UIP, then by the end of the program, every channel
160 * must have HALTed to that UIP. Furthermore, the tracking is a
161 * stack, so you can't do the final halt of a UIP after starting
162 * halting to a new UIP.
164 * Symptoms of not emitting this instruction on actual hardware
165 * included GPU hangs and sparkly rendering on the piglit discard
168 brw_inst
*last_halt
= gen6_HALT(p
);
169 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
170 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
174 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
175 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
177 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
178 /* HALT takes a half-instruction distance from the pre-incremented IP. */
179 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
182 this->discard_halt_patches
.make_empty();
187 fs_generator::fire_fb_write(fs_inst
*inst
,
188 struct brw_reg payload
,
189 struct brw_reg implied_header
,
192 uint32_t msg_control
;
194 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
196 if (devinfo
->gen
< 6) {
197 brw_push_insn_state(p
);
198 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
199 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
200 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
201 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
202 brw_MOV(p
, offset(payload
, 1), brw_vec8_grf(1, 0));
203 brw_pop_insn_state(p
);
206 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
)
207 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
208 else if (prog_data
->dual_src_blend
) {
209 if (!inst
->force_sechalf
)
210 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
212 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
213 } else if (inst
->exec_size
== 16)
214 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
216 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
218 uint32_t surf_index
=
219 prog_data
->binding_table
.render_target_start
+ inst
->target
;
221 bool last_render_target
= inst
->eot
||
222 (prog_data
->dual_src_blend
&& dispatch_width
== 16);
235 inst
->header_size
!= 0);
237 brw_mark_surface_used(&prog_data
->base
, surf_index
);
241 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
243 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
244 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
245 struct brw_reg implied_header
;
247 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
248 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
251 if (inst
->base_mrf
>= 0)
252 payload
= brw_message_reg(inst
->base_mrf
);
254 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
257 if (inst
->header_size
!= 0) {
258 brw_push_insn_state(p
);
259 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
260 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
261 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
262 brw_set_default_flag_reg(p
, 0, 0);
264 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
267 if (prog_data
->uses_kill
) {
268 struct brw_reg pixel_mask
;
270 if (devinfo
->gen
>= 6)
271 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
273 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
275 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
278 if (devinfo
->gen
>= 6) {
279 brw_push_insn_state(p
);
280 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
281 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
283 retype(payload
, BRW_REGISTER_TYPE_UD
),
284 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
285 brw_pop_insn_state(p
);
287 if (inst
->target
> 0 && key
->replicate_alpha
) {
288 /* Set "Source0 Alpha Present to RenderTarget" bit in message
292 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
293 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
294 brw_imm_ud(0x1 << 11));
297 if (inst
->target
> 0) {
298 /* Set the render target index for choosing BLEND_STATE. */
299 brw_MOV(p
, retype(vec1(suboffset(payload
, 2)),
300 BRW_REGISTER_TYPE_UD
),
301 brw_imm_ud(inst
->target
));
304 /* Set computes stencil to render target */
305 if (prog_data
->computed_stencil
) {
307 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
308 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
309 brw_imm_ud(0x1 << 14));
312 implied_header
= brw_null_reg();
314 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
317 brw_pop_insn_state(p
);
319 implied_header
= brw_null_reg();
322 if (!runtime_check_aads_emit
) {
323 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
325 /* This can only happen in gen < 6 */
326 assert(devinfo
->gen
< 6);
328 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
330 /* Check runtime bit to detect if we have to send AA data or not */
331 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
334 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
336 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
338 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
339 brw_inst_set_exec_size(p
->devinfo
, brw_last_inst
, BRW_EXECUTE_1
);
341 /* Don't send AA data */
342 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
344 brw_land_fwd_jump(p
, jmp
);
345 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
350 fs_generator::generate_mov_indirect(fs_inst
*inst
,
353 struct brw_reg indirect_byte_offset
)
355 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
356 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
358 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
360 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
361 imm_byte_offset
+= indirect_byte_offset
.ud
;
363 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
364 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
365 brw_MOV(p
, dst
, reg
);
367 /* Prior to Broadwell, there are only 8 address registers. */
368 assert(inst
->exec_size
== 8 || devinfo
->gen
>= 8);
370 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
371 struct brw_reg addr
= vec8(brw_address_reg(0));
373 /* The destination stride of an instruction (in bytes) must be greater
374 * than or equal to the size of the rest of the instruction. Since the
375 * address register is of type UW, we can't use a D-type instruction.
376 * In order to get around this, re retype to UW and use a stride.
378 indirect_byte_offset
=
379 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
381 struct brw_reg ind_src
;
382 if (devinfo
->gen
< 8) {
383 /* From the Haswell PRM section "Register Region Restrictions":
385 * "The lower bits of the AddressImmediate must not overflow to
386 * change the register address. The lower 5 bits of Address
387 * Immediate when added to lower 5 bits of address register gives
388 * the sub-register offset. The upper bits of Address Immediate
389 * when added to upper bits of address register gives the register
390 * address. Any overflow from sub-register offset is dropped."
392 * This restriction is only listed in the Haswell PRM but emperical
393 * testing indicates that it applies on all older generations and is
394 * lifted on Broadwell.
396 * Since the indirect may cause us to cross a register boundary, this
397 * makes the base offset almost useless. We could try and do
398 * something clever where we use a actual base offset if
399 * base_offset % 32 == 0 but that would mean we were generating
400 * different code depending on the base offset. Instead, for the
401 * sake of consistency, we'll just do the add ourselves.
403 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
404 ind_src
= brw_VxH_indirect(0, 0);
406 brw_MOV(p
, addr
, indirect_byte_offset
);
407 ind_src
= brw_VxH_indirect(0, imm_byte_offset
);
410 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, dst
.type
));
412 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
413 !inst
->get_next()->is_tail_sentinel() &&
414 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
415 /* From the Sandybridge PRM:
417 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
418 * instruction that “indexed/indirect” source AND is followed by a
419 * send, the instruction requires a “Switch”. This is to avoid
420 * race condition where send may dispatch before MRF is updated."
422 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
428 fs_generator::generate_urb_read(fs_inst
*inst
,
430 struct brw_reg header
)
432 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
433 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
435 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
436 brw_set_dest(p
, send
, dst
);
437 brw_set_src0(p
, send
, header
);
438 brw_set_src1(p
, send
, brw_imm_ud(0u));
440 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
441 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
443 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
444 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
446 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
447 brw_inst_set_rlen(p
->devinfo
, send
, inst
->regs_written
);
448 brw_inst_set_header_present(p
->devinfo
, send
, true);
449 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
453 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
457 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
459 brw_set_dest(p
, insn
, brw_null_reg());
460 brw_set_src0(p
, insn
, payload
);
461 brw_set_src1(p
, insn
, brw_imm_d(0));
463 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
464 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
466 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
467 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
468 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
470 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
471 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
472 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
474 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
475 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
476 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
477 brw_inst_set_header_present(p
->devinfo
, insn
, true);
478 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
482 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
484 struct brw_inst
*insn
;
486 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
488 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
489 brw_set_src0(p
, insn
, payload
);
490 brw_set_src1(p
, insn
, brw_imm_d(0));
492 /* Terminate a compute shader by sending a message to the thread spawner.
494 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
495 brw_inst_set_mlen(devinfo
, insn
, 1);
496 brw_inst_set_rlen(devinfo
, insn
, 0);
497 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
498 brw_inst_set_header_present(devinfo
, insn
, false);
500 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
501 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
503 /* Note that even though the thread has a URB resource associated with it,
504 * we set the "do not dereference URB" bit, because the URB resource is
505 * managed by the fixed-function unit, so it will free it automatically.
507 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
509 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
513 fs_generator::generate_stencil_ref_packing(fs_inst
*inst
,
517 assert(dispatch_width
== 8);
518 assert(devinfo
->gen
>= 9);
520 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
521 * Presumably, in order to save memory bandwidth, the stencil reference
522 * values written from the FS need to be packed into 2 dwords (this makes
523 * sense because the stencil values are limited to 1 byte each and a SIMD8
524 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
526 * The spec is confusing here because in the payload definition of MDP_RTW_S8
527 * (Message Data Payload for Render Target Writes with Stencil 8b) the
528 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
529 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
530 * packed values specified above and diagrammed below:
533 * --------------------------------
537 * --------------------------------
538 * DW1 | STC | STC | STC | STC |
539 * | slot7 | slot6 | slot5 | slot4|
540 * --------------------------------
541 * DW0 | STC | STC | STC | STC |
542 * | slot3 | slot2 | slot1 | slot0|
543 * --------------------------------
546 src
.vstride
= BRW_VERTICAL_STRIDE_4
;
547 src
.width
= BRW_WIDTH_1
;
548 src
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
549 assert(src
.type
== BRW_REGISTER_TYPE_UB
);
550 brw_MOV(p
, retype(dst
, BRW_REGISTER_TYPE_UB
), src
);
554 fs_generator::generate_barrier(fs_inst
*inst
, struct brw_reg src
)
561 fs_generator::generate_linterp(fs_inst
*inst
,
562 struct brw_reg dst
, struct brw_reg
*src
)
566 * -----------------------------------
567 * | src1+0 | src1+1 | src1+2 | src1+3 |
568 * |-----------------------------------|
569 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
570 * -----------------------------------
572 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
574 * -----------------------------------
575 * | src1+0 | src1+1 | src1+2 | src1+3 |
576 * |-----------------------------------|
577 * |(x0, x1)|(y0, y1)| | | in SIMD8
578 * |-----------------------------------|
579 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
580 * -----------------------------------
582 * See also: emit_interpolation_setup_gen4().
584 struct brw_reg delta_x
= src
[0];
585 struct brw_reg delta_y
= offset(src
[0], dispatch_width
/ 8);
586 struct brw_reg interp
= src
[1];
588 if (devinfo
->has_pln
&&
589 (devinfo
->gen
>= 7 || (delta_x
.nr
& 1) == 0)) {
590 brw_PLN(p
, dst
, interp
, delta_x
);
592 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
593 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
598 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
601 struct brw_reg surf_index
)
603 assert(devinfo
->gen
>= 7);
604 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
609 switch (inst
->exec_size
) {
611 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
614 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
617 unreachable("Invalid width for texture instruction");
620 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
626 retype(dst
, BRW_REGISTER_TYPE_UW
),
631 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
632 rlen
, /* response length */
634 inst
->header_size
> 0,
636 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
638 brw_mark_surface_used(prog_data
, surf_index
.ud
);
642 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
643 struct brw_reg surface_index
,
644 struct brw_reg sampler_index
)
648 uint32_t return_format
;
649 bool is_combined_send
= inst
->eot
;
652 case BRW_REGISTER_TYPE_D
:
653 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
655 case BRW_REGISTER_TYPE_UD
:
656 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
659 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
663 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
664 * is set as part of the message descriptor. On gen4, the PRM seems to
665 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
666 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
667 * gone from the message descriptor entirely and you just get UINT32 all
668 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
669 * just stomp it to UINT32 all the time.
671 if (inst
->opcode
== SHADER_OPCODE_TXS
)
672 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
674 switch (inst
->exec_size
) {
676 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
679 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
682 unreachable("Invalid width for texture instruction");
685 if (devinfo
->gen
>= 5) {
686 switch (inst
->opcode
) {
687 case SHADER_OPCODE_TEX
:
688 if (inst
->shadow_compare
) {
689 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
691 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
695 if (inst
->shadow_compare
) {
696 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
698 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
701 case SHADER_OPCODE_TXL
:
702 if (inst
->shadow_compare
) {
703 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
705 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
708 case SHADER_OPCODE_TXL_LZ
:
709 assert(devinfo
->gen
>= 9);
710 if (inst
->shadow_compare
) {
711 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
;
713 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
716 case SHADER_OPCODE_TXS
:
717 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
719 case SHADER_OPCODE_TXD
:
720 if (inst
->shadow_compare
) {
721 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
722 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
723 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
725 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
728 case SHADER_OPCODE_TXF
:
729 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
731 case SHADER_OPCODE_TXF_LZ
:
732 assert(devinfo
->gen
>= 9);
733 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
735 case SHADER_OPCODE_TXF_CMS_W
:
736 assert(devinfo
->gen
>= 9);
737 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
739 case SHADER_OPCODE_TXF_CMS
:
740 if (devinfo
->gen
>= 7)
741 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
743 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
745 case SHADER_OPCODE_TXF_UMS
:
746 assert(devinfo
->gen
>= 7);
747 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
749 case SHADER_OPCODE_TXF_MCS
:
750 assert(devinfo
->gen
>= 7);
751 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
753 case SHADER_OPCODE_LOD
:
754 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
756 case SHADER_OPCODE_TG4
:
757 if (inst
->shadow_compare
) {
758 assert(devinfo
->gen
>= 7);
759 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
761 assert(devinfo
->gen
>= 6);
762 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
765 case SHADER_OPCODE_TG4_OFFSET
:
766 assert(devinfo
->gen
>= 7);
767 if (inst
->shadow_compare
) {
768 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
770 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
773 case SHADER_OPCODE_SAMPLEINFO
:
774 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
777 unreachable("not reached");
780 switch (inst
->opcode
) {
781 case SHADER_OPCODE_TEX
:
782 /* Note that G45 and older determines shadow compare and dispatch width
783 * from message length for most messages.
785 if (inst
->exec_size
== 8) {
786 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
787 if (inst
->shadow_compare
) {
788 assert(inst
->mlen
== 6);
790 assert(inst
->mlen
<= 4);
793 if (inst
->shadow_compare
) {
794 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
795 assert(inst
->mlen
== 9);
797 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
798 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
803 if (inst
->shadow_compare
) {
804 assert(inst
->exec_size
== 8);
805 assert(inst
->mlen
== 6);
806 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
808 assert(inst
->mlen
== 9);
809 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
810 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
813 case SHADER_OPCODE_TXL
:
814 if (inst
->shadow_compare
) {
815 assert(inst
->exec_size
== 8);
816 assert(inst
->mlen
== 6);
817 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
819 assert(inst
->mlen
== 9);
820 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
821 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
824 case SHADER_OPCODE_TXD
:
825 /* There is no sample_d_c message; comparisons are done manually */
826 assert(inst
->exec_size
== 8);
827 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
828 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
830 case SHADER_OPCODE_TXF
:
831 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
832 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
833 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
835 case SHADER_OPCODE_TXS
:
836 assert(inst
->mlen
== 3);
837 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
838 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
841 unreachable("not reached");
844 assert(msg_type
!= -1);
846 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
850 assert(devinfo
->gen
< 7 || inst
->header_size
== 0 ||
851 src
.file
== BRW_GENERAL_REGISTER_FILE
);
853 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
855 /* Load the message header if present. If there's a texture offset,
856 * we need to set it up explicitly and load the offset bitfield.
857 * Otherwise, we can use an implied move from g0 to the first message reg.
859 if (inst
->header_size
!= 0) {
860 if (devinfo
->gen
< 6 && !inst
->offset
) {
861 /* Set up an implied move from g0 to the MRF. */
862 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
864 struct brw_reg header_reg
;
866 if (devinfo
->gen
>= 7) {
869 assert(inst
->base_mrf
!= -1);
870 header_reg
= brw_message_reg(inst
->base_mrf
);
873 brw_push_insn_state(p
);
874 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
875 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
876 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
877 /* Explicitly set up the message header by copying g0 to the MRF. */
878 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
881 /* Set the offset bits in DWord 2. */
882 brw_MOV(p
, get_element_ud(header_reg
, 2),
883 brw_imm_ud(inst
->offset
));
884 } else if (stage
!= MESA_SHADER_VERTEX
&&
885 stage
!= MESA_SHADER_FRAGMENT
) {
886 /* The vertex and fragment stages have g0.2 set to 0, so
887 * header0.2 is 0 when g0 is copied. Other stages may not, so we
888 * must set it to 0 to avoid setting undesirable bits in the
891 brw_MOV(p
, get_element_ud(header_reg
, 2), brw_imm_ud(0));
894 brw_adjust_sampler_state_pointer(p
, header_reg
, sampler_index
);
895 brw_pop_insn_state(p
);
899 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
900 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
901 ? prog_data
->binding_table
.gather_texture_start
902 : prog_data
->binding_table
.texture_start
;
904 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
905 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
906 uint32_t surface
= surface_index
.ud
;
907 uint32_t sampler
= sampler_index
.ud
;
910 retype(dst
, BRW_REGISTER_TYPE_UW
),
913 surface
+ base_binding_table_index
,
918 inst
->header_size
!= 0,
922 brw_mark_surface_used(prog_data
, surface
+ base_binding_table_index
);
924 /* Non-const sampler index */
926 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
927 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
928 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
930 brw_push_insn_state(p
);
931 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
932 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
934 if (brw_regs_equal(&surface_reg
, &sampler_reg
)) {
935 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
937 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
938 brw_OR(p
, addr
, addr
, surface_reg
);
940 if (base_binding_table_index
)
941 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
942 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
944 brw_pop_insn_state(p
);
946 /* dst = send(offset, a0.0 | <descriptor>) */
947 brw_inst
*insn
= brw_send_indirect_message(
948 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
949 brw_set_sampler_message(p
, insn
,
954 inst
->mlen
/* mlen */,
955 inst
->header_size
!= 0 /* header */,
959 /* visitor knows more than we do about the surface limit required,
960 * so has already done marking.
964 if (is_combined_send
) {
965 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, true);
966 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
971 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
974 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
976 * Ideally, we want to produce:
979 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
980 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
981 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
982 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
983 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
984 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
985 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
986 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
988 * and add another set of two more subspans if in 16-pixel dispatch mode.
990 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
991 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
992 * pair. But the ideal approximation may impose a huge performance cost on
993 * sample_d. On at least Haswell, sample_d instruction does some
994 * optimizations if the same LOD is used for all pixels in the subspan.
996 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
997 * appropriate swizzling.
1000 fs_generator::generate_ddx(enum opcode opcode
,
1001 struct brw_reg dst
, struct brw_reg src
)
1003 unsigned vstride
, width
;
1005 if (opcode
== FS_OPCODE_DDX_FINE
) {
1006 /* produce accurate derivatives */
1007 vstride
= BRW_VERTICAL_STRIDE_2
;
1008 width
= BRW_WIDTH_2
;
1010 /* replicate the derivative at the top-left pixel to other pixels */
1011 vstride
= BRW_VERTICAL_STRIDE_4
;
1012 width
= BRW_WIDTH_4
;
1015 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
1016 src
.negate
, src
.abs
,
1017 BRW_REGISTER_TYPE_F
,
1020 BRW_HORIZONTAL_STRIDE_0
,
1021 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1022 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1023 src
.negate
, src
.abs
,
1024 BRW_REGISTER_TYPE_F
,
1027 BRW_HORIZONTAL_STRIDE_0
,
1028 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1029 brw_ADD(p
, dst
, src0
, negate(src1
));
1032 /* The negate_value boolean is used to negate the derivative computation for
1033 * FBOs, since they place the origin at the upper left instead of the lower
1037 fs_generator::generate_ddy(enum opcode opcode
,
1038 struct brw_reg dst
, struct brw_reg src
)
1040 if (opcode
== FS_OPCODE_DDY_FINE
) {
1041 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1042 * Region Restrictions):
1044 * In Align16 access mode, SIMD16 is not allowed for DW operations
1045 * and SIMD8 is not allowed for DF operations.
1047 * In this context, "DW operations" means "operations acting on 32-bit
1048 * values", so it includes operations on floats.
1050 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1051 * (Instruction Compression -> Rules and Restrictions):
1053 * A compressed instruction must be in Align1 access mode. Align16
1054 * mode instructions cannot be compressed.
1056 * Similar text exists in the g45 PRM.
1058 * Empirically, compressed align16 instructions using odd register
1059 * numbers don't appear to work on Sandybridge either.
1061 * On these platforms, if we're building a SIMD16 shader, we need to
1062 * manually unroll to a pair of SIMD8 instructions.
1064 bool unroll_to_simd8
=
1065 (dispatch_width
== 16 &&
1066 (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
1067 (devinfo
->gen
== 7 && !devinfo
->is_haswell
)));
1069 /* produce accurate derivatives */
1070 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1071 src
.negate
, src
.abs
,
1072 BRW_REGISTER_TYPE_F
,
1073 BRW_VERTICAL_STRIDE_4
,
1075 BRW_HORIZONTAL_STRIDE_1
,
1076 BRW_SWIZZLE_XYXY
, WRITEMASK_XYZW
);
1077 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1078 src
.negate
, src
.abs
,
1079 BRW_REGISTER_TYPE_F
,
1080 BRW_VERTICAL_STRIDE_4
,
1082 BRW_HORIZONTAL_STRIDE_1
,
1083 BRW_SWIZZLE_ZWZW
, WRITEMASK_XYZW
);
1084 brw_push_insn_state(p
);
1085 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1086 if (unroll_to_simd8
) {
1087 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1088 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1089 brw_ADD(p
, firsthalf(dst
), negate(firsthalf(src0
)), firsthalf(src1
));
1090 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1091 brw_ADD(p
, sechalf(dst
), negate(sechalf(src0
)), sechalf(src1
));
1093 brw_ADD(p
, dst
, negate(src0
), src1
);
1095 brw_pop_insn_state(p
);
1097 /* replicate the derivative at the top-left pixel to other pixels */
1098 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1099 src
.negate
, src
.abs
,
1100 BRW_REGISTER_TYPE_F
,
1101 BRW_VERTICAL_STRIDE_4
,
1103 BRW_HORIZONTAL_STRIDE_0
,
1104 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1105 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
1106 src
.negate
, src
.abs
,
1107 BRW_REGISTER_TYPE_F
,
1108 BRW_VERTICAL_STRIDE_4
,
1110 BRW_HORIZONTAL_STRIDE_0
,
1111 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1112 brw_ADD(p
, dst
, negate(src0
), src1
);
1117 fs_generator::generate_discard_jump(fs_inst
*inst
)
1119 assert(devinfo
->gen
>= 6);
1121 /* This HALT will be patched up at FB write time to point UIP at the end of
1122 * the program, and at brw_uip_jip() JIP will be set to the end of the
1123 * current block (or the program).
1125 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1127 brw_push_insn_state(p
);
1128 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1130 brw_pop_insn_state(p
);
1134 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1136 assert(inst
->mlen
!= 0);
1139 brw_uvec_mrf(inst
->exec_size
, (inst
->base_mrf
+ 1), 0),
1140 retype(src
, BRW_REGISTER_TYPE_UD
));
1141 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1142 inst
->exec_size
/ 8, inst
->offset
);
1146 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1148 assert(inst
->mlen
!= 0);
1150 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1151 inst
->exec_size
/ 8, inst
->offset
);
1155 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1157 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1161 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1163 struct brw_reg index
,
1164 struct brw_reg offset
)
1166 assert(inst
->mlen
!= 0);
1168 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1169 index
.type
== BRW_REGISTER_TYPE_UD
);
1170 uint32_t surf_index
= index
.ud
;
1172 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1173 offset
.type
== BRW_REGISTER_TYPE_UD
);
1174 uint32_t read_offset
= offset
.ud
;
1176 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1177 read_offset
, surf_index
);
1181 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1183 struct brw_reg index
,
1184 struct brw_reg offset
)
1186 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1188 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
1189 /* Reference just the dword we need, to avoid angering validate_reg(). */
1190 offset
= brw_vec1_grf(offset
.nr
, 0);
1192 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1193 * the destination loaded consecutively from the same offset (which appears
1194 * in the first component, and the rest are ignored).
1196 dst
.width
= BRW_WIDTH_4
;
1198 struct brw_reg src
= offset
;
1199 bool header_present
= false;
1201 if (devinfo
->gen
>= 9) {
1202 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1203 src
= retype(brw_vec4_grf(offset
.nr
, 0), BRW_REGISTER_TYPE_UD
);
1204 header_present
= true;
1206 brw_push_insn_state(p
);
1207 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1208 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1209 brw_MOV(p
, vec8(src
), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1210 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1212 brw_MOV(p
, get_element_ud(src
, 2),
1213 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
));
1214 brw_pop_insn_state(p
);
1217 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1219 uint32_t surf_index
= index
.ud
;
1221 brw_push_insn_state(p
);
1222 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1223 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1224 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1225 brw_inst_set_exec_size(devinfo
, send
, BRW_EXECUTE_4
);
1226 brw_pop_insn_state(p
);
1228 brw_set_dest(p
, send
, dst
);
1229 brw_set_src0(p
, send
, src
);
1230 brw_set_sampler_message(p
, send
,
1232 0, /* LD message ignores sampler unit */
1233 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1237 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1241 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1243 brw_push_insn_state(p
);
1244 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1245 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1247 /* a0.0 = surf_index & 0xff */
1248 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1249 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1250 brw_set_dest(p
, insn_and
, addr
);
1251 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1252 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1254 /* dst = send(payload, a0.0 | <descriptor>) */
1255 brw_inst
*insn
= brw_send_indirect_message(
1256 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1257 brw_set_sampler_message(p
, insn
,
1259 0, /* LD message ignores sampler unit */
1260 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1264 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1267 brw_pop_insn_state(p
);
1272 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1274 struct brw_reg index
)
1276 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1277 assert(inst
->header_size
!= 0);
1280 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1281 index
.type
== BRW_REGISTER_TYPE_UD
);
1282 uint32_t surf_index
= index
.ud
;
1284 uint32_t simd_mode
, rlen
, msg_type
;
1285 if (dispatch_width
== 16) {
1286 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1289 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1293 if (devinfo
->gen
>= 5)
1294 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1296 /* We always use the SIMD16 message so that we only have to load U, and
1299 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1300 assert(inst
->mlen
== 3);
1301 assert(inst
->regs_written
== 8);
1303 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1306 struct brw_reg header
= brw_vec8_grf(0, 0);
1307 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1309 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1310 brw_inst_set_qtr_control(p
->devinfo
, send
, BRW_COMPRESSION_NONE
);
1311 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1312 brw_set_src0(p
, send
, header
);
1313 if (devinfo
->gen
< 6)
1314 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1316 /* Our surface is set up as floats, regardless of what actual data is
1319 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1320 brw_set_sampler_message(p
, send
,
1322 0, /* sampler (unused) */
1326 inst
->header_size
!= 0,
1332 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1334 struct brw_reg index
,
1335 struct brw_reg offset
)
1337 assert(devinfo
->gen
>= 7);
1338 /* Varying-offset pull constant loads are treated as a normal expression on
1339 * gen7, so the fact that it's a send message is hidden at the IR level.
1341 assert(inst
->header_size
== 0);
1342 assert(!inst
->mlen
);
1343 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1345 uint32_t simd_mode
, rlen
, mlen
;
1346 if (dispatch_width
== 16) {
1349 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1353 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1356 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1358 uint32_t surf_index
= index
.ud
;
1360 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1361 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1362 brw_set_src0(p
, send
, offset
);
1363 brw_set_sampler_message(p
, send
,
1365 0, /* LD message ignores sampler unit */
1366 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1369 false, /* no header */
1375 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1377 brw_push_insn_state(p
);
1378 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1379 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1381 /* a0.0 = surf_index & 0xff */
1382 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1383 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1384 brw_set_dest(p
, insn_and
, addr
);
1385 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1386 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1388 brw_pop_insn_state(p
);
1390 /* dst = send(offset, a0.0 | <descriptor>) */
1391 brw_inst
*insn
= brw_send_indirect_message(
1392 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1394 brw_set_sampler_message(p
, insn
,
1397 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1407 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1408 * into the flags register (f0.0).
1410 * Used only on Gen6 and above.
1413 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1415 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
1416 struct brw_reg dispatch_mask
;
1418 if (devinfo
->gen
>= 6)
1419 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1421 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1423 brw_push_insn_state(p
);
1424 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1425 brw_MOV(p
, flags
, dispatch_mask
);
1426 brw_pop_insn_state(p
);
1430 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1433 struct brw_reg msg_data
,
1436 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1438 brw_pixel_interpolator_query(p
,
1439 retype(dst
, BRW_REGISTER_TYPE_UW
),
1441 inst
->pi_noperspective
,
1445 inst
->regs_written
);
1450 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1451 * sampler LD messages.
1453 * We don't want to bake it into the send message's code generation because
1454 * that means we don't get a chance to schedule the instructions.
1457 fs_generator::generate_set_simd4x2_offset(fs_inst
*inst
,
1459 struct brw_reg value
)
1461 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1463 brw_push_insn_state(p
);
1464 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1465 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1466 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1467 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 0), value
.type
), value
);
1468 brw_pop_insn_state(p
);
1471 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1472 * the ADD instruction.
1475 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1477 struct brw_reg src0
,
1478 struct brw_reg src1
)
1480 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1481 dst
.type
== BRW_REGISTER_TYPE_UD
);
1482 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1483 src0
.type
== BRW_REGISTER_TYPE_UD
);
1485 struct brw_reg reg
= stride(src1
, 1, 4, 0);
1486 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
1487 brw_ADD(p
, dst
, src0
, reg
);
1488 } else if (dispatch_width
== 16) {
1489 brw_push_insn_state(p
);
1490 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1491 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1492 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), reg
);
1493 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1494 brw_ADD(p
, sechalf(dst
), sechalf(src0
), suboffset(reg
, 2));
1495 brw_pop_insn_state(p
);
1500 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
1505 assert(devinfo
->gen
>= 7);
1506 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1507 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1508 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1510 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1512 * Because this instruction does not have a 16-bit floating-point type,
1513 * the destination data type must be Word (W).
1515 * The destination must be DWord-aligned and specify a horizontal stride
1516 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1517 * each destination channel and the upper word is not modified.
1519 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1521 /* Give each 32-bit channel of dst the form below, where "." means
1525 brw_F32TO16(p
, dst_w
, y
);
1530 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1532 /* And, finally the form of packHalf2x16's output:
1535 brw_F32TO16(p
, dst_w
, x
);
1539 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1543 assert(devinfo
->gen
>= 7);
1544 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1545 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1547 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1549 * Because this instruction does not have a 16-bit floating-point type,
1550 * the source data type must be Word (W). The destination type must be
1553 struct brw_reg src_w
= spread(retype(src
, BRW_REGISTER_TYPE_W
), 2);
1555 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1556 * For the Y case, we wish to access only the upper word; therefore
1557 * a 16-bit subregister offset is needed.
1559 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1560 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1561 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1564 brw_F16TO32(p
, dst
, src_w
);
1568 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1569 struct brw_reg payload
,
1570 struct brw_reg offset
,
1571 struct brw_reg value
)
1573 assert(devinfo
->gen
>= 7);
1574 brw_push_insn_state(p
);
1575 brw_set_default_mask_control(p
, true);
1577 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1578 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1580 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1583 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1584 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1585 value
.width
= BRW_WIDTH_1
;
1586 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1587 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1589 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1592 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1593 * case, and we don't really care about squeezing every bit of performance
1594 * out of this path, so we just emit the MOVs from here.
1596 brw_MOV(p
, payload_offset
, offset
);
1597 brw_MOV(p
, payload_value
, value
);
1598 brw_shader_time_add(p
, payload
,
1599 prog_data
->binding_table
.shader_time_start
);
1600 brw_pop_insn_state(p
);
1602 brw_mark_surface_used(prog_data
,
1603 prog_data
->binding_table
.shader_time_start
);
1607 fs_generator::enable_debug(const char *shader_name
)
1610 this->shader_name
= shader_name
;
1614 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1616 /* align to 64 byte boundary. */
1617 while (p
->next_insn_offset
% 64)
1620 this->dispatch_width
= dispatch_width
;
1621 if (dispatch_width
== 16)
1622 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1624 int start_offset
= p
->next_insn_offset
;
1625 int spill_count
= 0, fill_count
= 0;
1628 struct annotation_info annotation
;
1629 memset(&annotation
, 0, sizeof(annotation
));
1631 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1632 struct brw_reg src
[3], dst
;
1633 unsigned int last_insn_offset
= p
->next_insn_offset
;
1634 bool multiple_instructions_emitted
= false;
1636 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1637 * "Register Region Restrictions" section: for BDW, SKL:
1639 * "A POW/FDIV operation must not be followed by an instruction
1640 * that requires two destination registers."
1642 * The documentation is often lacking annotations for Atom parts,
1643 * and empirically this affects CHV as well.
1645 if (devinfo
->gen
>= 8 &&
1647 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1648 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1649 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1651 last_insn_offset
= p
->next_insn_offset
;
1654 if (unlikely(debug_flag
))
1655 annotate(p
->devinfo
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1657 switch (inst
->exec_size
) {
1661 assert(inst
->force_writemask_all
);
1662 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1665 if (inst
->force_sechalf
) {
1666 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1668 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1673 /* If the instruction writes to more than one register, it needs to
1674 * be a "compressed" instruction on Gen <= 5.
1676 if (inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
)
1677 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1679 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1682 unreachable("Invalid instruction width");
1685 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1686 src
[i
] = brw_reg_from_fs_reg(p
, inst
, &inst
->src
[i
], devinfo
->gen
);
1688 /* The accumulator result appears to get used for the
1689 * conditional modifier generation. When negating a UD
1690 * value, there is a 33rd bit generated for the sign in the
1691 * accumulator value, so now you can't check, for example,
1692 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1694 assert(!inst
->conditional_mod
||
1695 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1696 !inst
->src
[i
].negate
);
1698 dst
= brw_reg_from_fs_reg(p
, inst
, &inst
->dst
, devinfo
->gen
);
1700 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1701 brw_set_default_predicate_control(p
, inst
->predicate
);
1702 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1703 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1704 brw_set_default_saturate(p
, inst
->saturate
);
1705 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1706 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1707 brw_set_default_exec_size(p
, cvt(inst
->exec_size
) - 1);
1709 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1710 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1712 switch (inst
->opcode
) {
1713 case BRW_OPCODE_MOV
:
1714 brw_MOV(p
, dst
, src
[0]);
1716 case BRW_OPCODE_ADD
:
1717 brw_ADD(p
, dst
, src
[0], src
[1]);
1719 case BRW_OPCODE_MUL
:
1720 brw_MUL(p
, dst
, src
[0], src
[1]);
1722 case BRW_OPCODE_AVG
:
1723 brw_AVG(p
, dst
, src
[0], src
[1]);
1725 case BRW_OPCODE_MACH
:
1726 brw_MACH(p
, dst
, src
[0], src
[1]);
1729 case BRW_OPCODE_LINE
:
1730 brw_LINE(p
, dst
, src
[0], src
[1]);
1733 case BRW_OPCODE_MAD
:
1734 assert(devinfo
->gen
>= 6);
1735 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1736 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1739 case BRW_OPCODE_LRP
:
1740 assert(devinfo
->gen
>= 6);
1741 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1742 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1745 case BRW_OPCODE_FRC
:
1746 brw_FRC(p
, dst
, src
[0]);
1748 case BRW_OPCODE_RNDD
:
1749 brw_RNDD(p
, dst
, src
[0]);
1751 case BRW_OPCODE_RNDE
:
1752 brw_RNDE(p
, dst
, src
[0]);
1754 case BRW_OPCODE_RNDZ
:
1755 brw_RNDZ(p
, dst
, src
[0]);
1758 case BRW_OPCODE_AND
:
1759 brw_AND(p
, dst
, src
[0], src
[1]);
1762 brw_OR(p
, dst
, src
[0], src
[1]);
1764 case BRW_OPCODE_XOR
:
1765 brw_XOR(p
, dst
, src
[0], src
[1]);
1767 case BRW_OPCODE_NOT
:
1768 brw_NOT(p
, dst
, src
[0]);
1770 case BRW_OPCODE_ASR
:
1771 brw_ASR(p
, dst
, src
[0], src
[1]);
1773 case BRW_OPCODE_SHR
:
1774 brw_SHR(p
, dst
, src
[0], src
[1]);
1776 case BRW_OPCODE_SHL
:
1777 brw_SHL(p
, dst
, src
[0], src
[1]);
1779 case BRW_OPCODE_F32TO16
:
1780 assert(devinfo
->gen
>= 7);
1781 brw_F32TO16(p
, dst
, src
[0]);
1783 case BRW_OPCODE_F16TO32
:
1784 assert(devinfo
->gen
>= 7);
1785 brw_F16TO32(p
, dst
, src
[0]);
1787 case BRW_OPCODE_CMP
:
1788 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1789 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1790 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1791 * implemented in the compiler is not sufficient. Overriding the
1792 * type when the destination is the null register is necessary but
1793 * not sufficient by itself.
1795 assert(dst
.nr
== BRW_ARF_NULL
);
1796 dst
.type
= BRW_REGISTER_TYPE_D
;
1798 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1800 case BRW_OPCODE_SEL
:
1801 brw_SEL(p
, dst
, src
[0], src
[1]);
1803 case BRW_OPCODE_BFREV
:
1804 assert(devinfo
->gen
>= 7);
1805 /* BFREV only supports UD type for src and dst. */
1806 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1807 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1809 case BRW_OPCODE_FBH
:
1810 assert(devinfo
->gen
>= 7);
1811 /* FBH only supports UD type for dst. */
1812 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1814 case BRW_OPCODE_FBL
:
1815 assert(devinfo
->gen
>= 7);
1816 /* FBL only supports UD type for dst. */
1817 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1819 case BRW_OPCODE_CBIT
:
1820 assert(devinfo
->gen
>= 7);
1821 /* CBIT only supports UD type for dst. */
1822 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1824 case BRW_OPCODE_ADDC
:
1825 assert(devinfo
->gen
>= 7);
1826 brw_ADDC(p
, dst
, src
[0], src
[1]);
1828 case BRW_OPCODE_SUBB
:
1829 assert(devinfo
->gen
>= 7);
1830 brw_SUBB(p
, dst
, src
[0], src
[1]);
1832 case BRW_OPCODE_MAC
:
1833 brw_MAC(p
, dst
, src
[0], src
[1]);
1836 case BRW_OPCODE_BFE
:
1837 assert(devinfo
->gen
>= 7);
1838 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1839 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1842 case BRW_OPCODE_BFI1
:
1843 assert(devinfo
->gen
>= 7);
1844 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1847 * "Force BFI instructions to be executed always in SIMD8."
1849 if (dispatch_width
== 16 && devinfo
->is_haswell
) {
1850 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1851 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1852 brw_BFI1(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]));
1853 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1854 brw_BFI1(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]));
1855 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1857 brw_BFI1(p
, dst
, src
[0], src
[1]);
1860 case BRW_OPCODE_BFI2
:
1861 assert(devinfo
->gen
>= 7);
1862 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1863 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1866 * "Force BFI instructions to be executed always in SIMD8."
1868 * Otherwise we would be able to emit compressed instructions like we
1869 * do for the other three-source instructions.
1871 if (dispatch_width
== 16 && devinfo
->is_haswell
) {
1872 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1873 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1874 brw_BFI2(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1875 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1876 brw_BFI2(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1877 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1879 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1881 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1885 if (inst
->src
[0].file
!= BAD_FILE
) {
1886 /* The instruction has an embedded compare (only allowed on gen6) */
1887 assert(devinfo
->gen
== 6);
1888 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1890 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1894 case BRW_OPCODE_ELSE
:
1897 case BRW_OPCODE_ENDIF
:
1902 brw_DO(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1905 case BRW_OPCODE_BREAK
:
1907 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1909 case BRW_OPCODE_CONTINUE
:
1911 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1914 case BRW_OPCODE_WHILE
:
1919 case SHADER_OPCODE_RCP
:
1920 case SHADER_OPCODE_RSQ
:
1921 case SHADER_OPCODE_SQRT
:
1922 case SHADER_OPCODE_EXP2
:
1923 case SHADER_OPCODE_LOG2
:
1924 case SHADER_OPCODE_SIN
:
1925 case SHADER_OPCODE_COS
:
1926 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1927 if (devinfo
->gen
>= 6) {
1928 assert(inst
->mlen
== 0);
1929 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
1930 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
1931 src
[0], brw_null_reg());
1933 assert(inst
->mlen
>= 1);
1934 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
1936 brw_math_function(inst
->opcode
),
1937 inst
->base_mrf
, src
[0],
1938 BRW_MATH_PRECISION_FULL
);
1941 case SHADER_OPCODE_INT_QUOTIENT
:
1942 case SHADER_OPCODE_INT_REMAINDER
:
1943 case SHADER_OPCODE_POW
:
1944 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1945 if (devinfo
->gen
>= 6) {
1946 assert(inst
->mlen
== 0);
1947 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
1948 inst
->exec_size
== 8);
1949 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1951 assert(inst
->mlen
>= 1);
1952 assert(inst
->exec_size
== 8);
1953 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
1954 inst
->base_mrf
, src
[0],
1955 BRW_MATH_PRECISION_FULL
);
1958 case FS_OPCODE_CINTERP
:
1959 brw_MOV(p
, dst
, src
[0]);
1961 case FS_OPCODE_LINTERP
:
1962 generate_linterp(inst
, dst
, src
);
1964 case FS_OPCODE_PIXEL_X
:
1965 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1966 src
[0].subnr
= 0 * type_sz(src
[0].type
);
1967 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1969 case FS_OPCODE_PIXEL_Y
:
1970 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1971 src
[0].subnr
= 4 * type_sz(src
[0].type
);
1972 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1974 case FS_OPCODE_GET_BUFFER_SIZE
:
1975 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
1977 case SHADER_OPCODE_TEX
:
1979 case SHADER_OPCODE_TXD
:
1980 case SHADER_OPCODE_TXF
:
1981 case SHADER_OPCODE_TXF_LZ
:
1982 case SHADER_OPCODE_TXF_CMS
:
1983 case SHADER_OPCODE_TXF_CMS_W
:
1984 case SHADER_OPCODE_TXF_UMS
:
1985 case SHADER_OPCODE_TXF_MCS
:
1986 case SHADER_OPCODE_TXL
:
1987 case SHADER_OPCODE_TXL_LZ
:
1988 case SHADER_OPCODE_TXS
:
1989 case SHADER_OPCODE_LOD
:
1990 case SHADER_OPCODE_TG4
:
1991 case SHADER_OPCODE_TG4_OFFSET
:
1992 case SHADER_OPCODE_SAMPLEINFO
:
1993 generate_tex(inst
, dst
, src
[0], src
[1], src
[2]);
1995 case FS_OPCODE_DDX_COARSE
:
1996 case FS_OPCODE_DDX_FINE
:
1997 generate_ddx(inst
->opcode
, dst
, src
[0]);
1999 case FS_OPCODE_DDY_COARSE
:
2000 case FS_OPCODE_DDY_FINE
:
2001 generate_ddy(inst
->opcode
, dst
, src
[0]);
2004 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2005 generate_scratch_write(inst
, src
[0]);
2009 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2010 generate_scratch_read(inst
, dst
);
2014 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2015 generate_scratch_read_gen7(inst
, dst
);
2019 case SHADER_OPCODE_MOV_INDIRECT
:
2020 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2023 case SHADER_OPCODE_URB_READ_SIMD8
:
2024 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2025 generate_urb_read(inst
, dst
, src
[0]);
2028 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2029 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2030 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2031 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2032 generate_urb_write(inst
, src
[0]);
2035 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2036 assert(inst
->force_writemask_all
);
2037 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2040 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2041 assert(inst
->force_writemask_all
);
2042 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2045 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2046 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2049 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
2050 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2053 case FS_OPCODE_REP_FB_WRITE
:
2054 case FS_OPCODE_FB_WRITE
:
2055 generate_fb_write(inst
, src
[0]);
2058 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
2059 generate_mov_dispatch_to_flags(inst
);
2062 case FS_OPCODE_DISCARD_JUMP
:
2063 generate_discard_jump(inst
);
2066 case SHADER_OPCODE_SHADER_TIME_ADD
:
2067 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2070 case SHADER_OPCODE_UNTYPED_ATOMIC
:
2071 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2072 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
,
2073 inst
->mlen
, !inst
->dst
.is_null());
2076 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
2077 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2078 brw_untyped_surface_read(p
, dst
, src
[0], src
[1],
2079 inst
->mlen
, src
[2].ud
);
2082 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
2083 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2084 brw_untyped_surface_write(p
, src
[0], src
[1],
2085 inst
->mlen
, src
[2].ud
);
2088 case SHADER_OPCODE_TYPED_ATOMIC
:
2089 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2090 brw_typed_atomic(p
, dst
, src
[0], src
[1],
2091 src
[2].ud
, inst
->mlen
, !inst
->dst
.is_null());
2094 case SHADER_OPCODE_TYPED_SURFACE_READ
:
2095 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2096 brw_typed_surface_read(p
, dst
, src
[0], src
[1],
2097 inst
->mlen
, src
[2].ud
);
2100 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
2101 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2102 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
, src
[2].ud
);
2105 case SHADER_OPCODE_MEMORY_FENCE
:
2106 brw_memory_fence(p
, dst
);
2109 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
2110 generate_set_simd4x2_offset(inst
, dst
, src
[0]);
2113 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2114 brw_find_live_channel(p
, dst
);
2117 case SHADER_OPCODE_BROADCAST
:
2118 brw_broadcast(p
, dst
, src
[0], src
[1]);
2121 case SHADER_OPCODE_EXTRACT_BYTE
: {
2122 assert(src
[0].type
== BRW_REGISTER_TYPE_D
||
2123 src
[0].type
== BRW_REGISTER_TYPE_UD
);
2125 enum brw_reg_type type
=
2126 src
[0].type
== BRW_REGISTER_TYPE_D
? BRW_REGISTER_TYPE_B
2127 : BRW_REGISTER_TYPE_UB
;
2128 brw_MOV(p
, dst
, spread(suboffset(retype(src
[0], type
), src
[1].ud
), 4));
2132 case SHADER_OPCODE_EXTRACT_WORD
: {
2133 assert(src
[0].type
== BRW_REGISTER_TYPE_D
||
2134 src
[0].type
== BRW_REGISTER_TYPE_UD
);
2136 enum brw_reg_type type
=
2137 src
[0].type
== BRW_REGISTER_TYPE_D
? BRW_REGISTER_TYPE_W
2138 : BRW_REGISTER_TYPE_UW
;
2139 brw_MOV(p
, dst
, spread(suboffset(retype(src
[0], type
), src
[1].ud
), 2));
2143 case FS_OPCODE_SET_SAMPLE_ID
:
2144 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2147 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2148 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2151 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
2152 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
2153 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
2156 case FS_OPCODE_PLACEHOLDER_HALT
:
2157 /* This is the place where the final HALT needs to be inserted if
2158 * we've emitted any discards. If not, this will emit no code.
2160 if (!patch_discard_jumps_to_fb_writes()) {
2161 if (unlikely(debug_flag
)) {
2162 annotation
.ann_count
--;
2167 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
2168 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2169 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID
);
2172 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2173 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2174 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2177 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2178 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2179 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2182 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2183 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2184 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2187 case CS_OPCODE_CS_TERMINATE
:
2188 generate_cs_terminate(inst
, src
[0]);
2191 case SHADER_OPCODE_BARRIER
:
2192 generate_barrier(inst
, src
[0]);
2195 case FS_OPCODE_PACK_STENCIL_REF
:
2196 generate_stencil_ref_packing(inst
, dst
, src
[0]);
2200 unreachable("Unsupported opcode");
2202 case SHADER_OPCODE_LOAD_PAYLOAD
:
2203 unreachable("Should be lowered by lower_load_payload()");
2206 if (multiple_instructions_emitted
)
2209 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2210 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2211 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2212 "emitting more than 1 instruction");
2214 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2216 if (inst
->conditional_mod
)
2217 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2218 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2219 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2224 annotation_finalize(&annotation
, p
->next_insn_offset
);
2227 bool validated
= brw_validate_instructions(p
, start_offset
, &annotation
);
2229 if (unlikely(debug_flag
))
2230 brw_validate_instructions(p
, start_offset
, &annotation
);
2233 int before_size
= p
->next_insn_offset
- start_offset
;
2234 brw_compact_instructions(p
, start_offset
, annotation
.ann_count
,
2236 int after_size
= p
->next_insn_offset
- start_offset
;
2238 if (unlikely(debug_flag
)) {
2239 fprintf(stderr
, "Native code for %s\n"
2240 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2241 " bytes (%.0f%%)\n",
2242 shader_name
, dispatch_width
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2243 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2244 100.0f
* (before_size
- after_size
) / before_size
);
2246 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
,
2248 ralloc_free(annotation
.mem_ctx
);
2252 compiler
->shader_debug_log(log_data
,
2253 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2254 "%d:%d spills:fills, Promoted %u constants, "
2255 "compacted %d to %d bytes.",
2256 _mesa_shader_stage_to_abbrev(stage
),
2257 dispatch_width
, before_size
/ 16,
2258 loop_count
, cfg
->cycle_count
, spill_count
,
2259 fill_count
, promoted_constants
, before_size
,
2262 return start_offset
;
2266 fs_generator::get_assembly(unsigned int *assembly_size
)
2268 return brw_get_program(p
, assembly_size
);