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i965: Pass a cfg pointer to generate_{code,assembly}.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 void *mem_ctx,
41 const struct brw_wm_prog_key *key,
42 struct brw_wm_prog_data *prog_data,
43 struct gl_shader_program *prog,
44 struct gl_fragment_program *fp,
45 bool runtime_check_aads_emit,
46 bool debug_flag)
47
48 : brw(brw), key(key), prog_data(prog_data), prog(prog), fp(fp),
49 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(debug_flag),
50 mem_ctx(mem_ctx)
51 {
52 ctx = &brw->ctx;
53
54 p = rzalloc(mem_ctx, struct brw_compile);
55 brw_init_compile(brw, p, mem_ctx);
56 }
57
58 fs_generator::~fs_generator()
59 {
60 }
61
62 bool
63 fs_generator::patch_discard_jumps_to_fb_writes()
64 {
65 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
66 return false;
67
68 int scale = brw_jump_scale(brw);
69
70 /* There is a somewhat strange undocumented requirement of using
71 * HALT, according to the simulator. If some channel has HALTed to
72 * a particular UIP, then by the end of the program, every channel
73 * must have HALTed to that UIP. Furthermore, the tracking is a
74 * stack, so you can't do the final halt of a UIP after starting
75 * halting to a new UIP.
76 *
77 * Symptoms of not emitting this instruction on actual hardware
78 * included GPU hangs and sparkly rendering on the piglit discard
79 * tests.
80 */
81 brw_inst *last_halt = gen6_HALT(p);
82 brw_inst_set_uip(brw, last_halt, 1 * scale);
83 brw_inst_set_jip(brw, last_halt, 1 * scale);
84
85 int ip = p->nr_insn;
86
87 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
88 brw_inst *patch = &p->store[patch_ip->ip];
89
90 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
91 /* HALT takes a half-instruction distance from the pre-incremented IP. */
92 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
93 }
94
95 this->discard_halt_patches.make_empty();
96 return true;
97 }
98
99 void
100 fs_generator::fire_fb_write(fs_inst *inst,
101 GLuint base_reg,
102 struct brw_reg implied_header,
103 GLuint nr)
104 {
105 uint32_t msg_control;
106
107 if (brw->gen < 6) {
108 brw_push_insn_state(p);
109 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
110 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
111 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
112 brw_MOV(p,
113 brw_message_reg(base_reg + 1),
114 brw_vec8_grf(1, 0));
115 brw_pop_insn_state(p);
116 }
117
118 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
119 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
120 else if (prog_data->dual_src_blend)
121 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
122 else if (dispatch_width == 16)
123 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
124 else
125 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
126
127 uint32_t surf_index =
128 prog_data->binding_table.render_target_start + inst->target;
129
130 brw_fb_WRITE(p,
131 dispatch_width,
132 base_reg,
133 implied_header,
134 msg_control,
135 surf_index,
136 nr,
137 0,
138 inst->eot,
139 inst->header_present);
140
141 brw_mark_surface_used(&prog_data->base, surf_index);
142 }
143
144 void
145 fs_generator::generate_fb_write(fs_inst *inst)
146 {
147 struct brw_reg implied_header;
148
149 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
150 * move, here's g1.
151 */
152 if (inst->header_present) {
153 brw_push_insn_state(p);
154 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
155 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
156 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
157 brw_set_default_flag_reg(p, 0, 0);
158
159 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
160 * present.
161 */
162 if ((fp && fp->UsesKill) || key->alpha_test_func) {
163 struct brw_reg pixel_mask;
164
165 if (brw->gen >= 6)
166 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
167 else
168 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
169
170 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
171 }
172
173 if (brw->gen >= 6) {
174 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
175 brw_MOV(p,
176 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
177 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
178 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
179
180 if (inst->target > 0 && key->replicate_alpha) {
181 /* Set "Source0 Alpha Present to RenderTarget" bit in message
182 * header.
183 */
184 brw_OR(p,
185 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
186 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
187 brw_imm_ud(0x1 << 11));
188 }
189
190 if (inst->target > 0) {
191 /* Set the render target index for choosing BLEND_STATE. */
192 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
193 inst->base_mrf, 2),
194 BRW_REGISTER_TYPE_UD),
195 brw_imm_ud(inst->target));
196 }
197
198 implied_header = brw_null_reg();
199 } else {
200 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
201 }
202
203 brw_pop_insn_state(p);
204 } else {
205 implied_header = brw_null_reg();
206 }
207
208 if (!runtime_check_aads_emit) {
209 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
210 } else {
211 /* This can only happen in gen < 6 */
212 assert(brw->gen < 6);
213
214 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
215
216 /* Check runtime bit to detect if we have to send AA data or not */
217 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
218 brw_AND(p,
219 v1_null_ud,
220 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
221 brw_imm_ud(1<<26));
222 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
223
224 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
225 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
226 {
227 /* Don't send AA data */
228 fire_fb_write(inst, inst->base_mrf+1, implied_header, inst->mlen-1);
229 }
230 brw_land_fwd_jump(p, jmp);
231 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
232 }
233 }
234
235 void
236 fs_generator::generate_blorp_fb_write(fs_inst *inst)
237 {
238 brw_fb_WRITE(p,
239 16 /* dispatch_width */,
240 inst->base_mrf,
241 brw_reg_from_fs_reg(&inst->src[0]),
242 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
243 inst->target,
244 inst->mlen,
245 0,
246 true,
247 inst->header_present);
248 }
249
250 /* Computes the integer pixel x,y values from the origin.
251 *
252 * This is the basis of gl_FragCoord computation, but is also used
253 * pre-gen6 for computing the deltas from v0 for computing
254 * interpolation.
255 */
256 void
257 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
258 {
259 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
260 struct brw_reg src;
261 struct brw_reg deltas;
262
263 if (is_x) {
264 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
265 deltas = brw_imm_v(0x10101010);
266 } else {
267 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
268 deltas = brw_imm_v(0x11001100);
269 }
270
271 if (dispatch_width == 16) {
272 dst = vec16(dst);
273 }
274
275 /* We do this SIMD8 or SIMD16, but since the destination is UW we
276 * don't do compression in the SIMD16 case.
277 */
278 brw_push_insn_state(p);
279 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
280 brw_ADD(p, dst, src, deltas);
281 brw_pop_insn_state(p);
282 }
283
284 void
285 fs_generator::generate_linterp(fs_inst *inst,
286 struct brw_reg dst, struct brw_reg *src)
287 {
288 struct brw_reg delta_x = src[0];
289 struct brw_reg delta_y = src[1];
290 struct brw_reg interp = src[2];
291
292 if (brw->has_pln &&
293 delta_y.nr == delta_x.nr + 1 &&
294 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
295 brw_PLN(p, dst, interp, delta_x);
296 } else {
297 brw_LINE(p, brw_null_reg(), interp, delta_x);
298 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
299 }
300 }
301
302 void
303 fs_generator::generate_math_gen6(fs_inst *inst,
304 struct brw_reg dst,
305 struct brw_reg src0,
306 struct brw_reg src1)
307 {
308 int op = brw_math_function(inst->opcode);
309 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
310
311 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
312 gen6_math(p, dst, op, src0, src1);
313
314 if (dispatch_width == 16) {
315 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
316 gen6_math(p, sechalf(dst), op, sechalf(src0),
317 binop ? sechalf(src1) : brw_null_reg());
318 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
319 }
320 }
321
322 void
323 fs_generator::generate_math_gen4(fs_inst *inst,
324 struct brw_reg dst,
325 struct brw_reg src)
326 {
327 int op = brw_math_function(inst->opcode);
328
329 assert(inst->mlen >= 1);
330
331 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
332 gen4_math(p, dst,
333 op,
334 inst->base_mrf, src,
335 BRW_MATH_DATA_VECTOR,
336 BRW_MATH_PRECISION_FULL);
337
338 if (dispatch_width == 16) {
339 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
340 gen4_math(p, sechalf(dst),
341 op,
342 inst->base_mrf + 1, sechalf(src),
343 BRW_MATH_DATA_VECTOR,
344 BRW_MATH_PRECISION_FULL);
345
346 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
347 }
348 }
349
350 void
351 fs_generator::generate_math_g45(fs_inst *inst,
352 struct brw_reg dst,
353 struct brw_reg src)
354 {
355 if (inst->opcode == SHADER_OPCODE_POW ||
356 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
357 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
358 generate_math_gen4(inst, dst, src);
359 return;
360 }
361
362 int op = brw_math_function(inst->opcode);
363
364 assert(inst->mlen >= 1);
365
366 gen4_math(p, dst,
367 op,
368 inst->base_mrf, src,
369 BRW_MATH_DATA_VECTOR,
370 BRW_MATH_PRECISION_FULL);
371 }
372
373 void
374 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
375 struct brw_reg sampler_index)
376 {
377 int msg_type = -1;
378 int rlen = 4;
379 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
380 uint32_t return_format;
381
382 switch (dst.type) {
383 case BRW_REGISTER_TYPE_D:
384 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
385 break;
386 case BRW_REGISTER_TYPE_UD:
387 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
388 break;
389 default:
390 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
391 break;
392 }
393
394 if (dispatch_width == 16 &&
395 !inst->force_uncompressed && !inst->force_sechalf)
396 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
397
398 if (brw->gen >= 5) {
399 switch (inst->opcode) {
400 case SHADER_OPCODE_TEX:
401 if (inst->shadow_compare) {
402 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
403 } else {
404 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
405 }
406 break;
407 case FS_OPCODE_TXB:
408 if (inst->shadow_compare) {
409 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
410 } else {
411 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
412 }
413 break;
414 case SHADER_OPCODE_TXL:
415 if (inst->shadow_compare) {
416 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
417 } else {
418 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
419 }
420 break;
421 case SHADER_OPCODE_TXS:
422 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
423 break;
424 case SHADER_OPCODE_TXD:
425 if (inst->shadow_compare) {
426 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
427 assert(brw->gen >= 8 || brw->is_haswell);
428 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
429 } else {
430 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
431 }
432 break;
433 case SHADER_OPCODE_TXF:
434 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
435 break;
436 case SHADER_OPCODE_TXF_CMS:
437 if (brw->gen >= 7)
438 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
439 else
440 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
441 break;
442 case SHADER_OPCODE_TXF_UMS:
443 assert(brw->gen >= 7);
444 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
445 break;
446 case SHADER_OPCODE_TXF_MCS:
447 assert(brw->gen >= 7);
448 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
449 break;
450 case SHADER_OPCODE_LOD:
451 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
452 break;
453 case SHADER_OPCODE_TG4:
454 if (inst->shadow_compare) {
455 assert(brw->gen >= 7);
456 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
457 } else {
458 assert(brw->gen >= 6);
459 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
460 }
461 break;
462 case SHADER_OPCODE_TG4_OFFSET:
463 assert(brw->gen >= 7);
464 if (inst->shadow_compare) {
465 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
466 } else {
467 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
468 }
469 break;
470 default:
471 unreachable("not reached");
472 }
473 } else {
474 switch (inst->opcode) {
475 case SHADER_OPCODE_TEX:
476 /* Note that G45 and older determines shadow compare and dispatch width
477 * from message length for most messages.
478 */
479 assert(dispatch_width == 8);
480 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
481 if (inst->shadow_compare) {
482 assert(inst->mlen == 6);
483 } else {
484 assert(inst->mlen <= 4);
485 }
486 break;
487 case FS_OPCODE_TXB:
488 if (inst->shadow_compare) {
489 assert(inst->mlen == 6);
490 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
491 } else {
492 assert(inst->mlen == 9);
493 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
494 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
495 }
496 break;
497 case SHADER_OPCODE_TXL:
498 if (inst->shadow_compare) {
499 assert(inst->mlen == 6);
500 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
501 } else {
502 assert(inst->mlen == 9);
503 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
504 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
505 }
506 break;
507 case SHADER_OPCODE_TXD:
508 /* There is no sample_d_c message; comparisons are done manually */
509 assert(inst->mlen == 7 || inst->mlen == 10);
510 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
511 break;
512 case SHADER_OPCODE_TXF:
513 assert(inst->mlen == 9);
514 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
515 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
516 break;
517 case SHADER_OPCODE_TXS:
518 assert(inst->mlen == 3);
519 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
520 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
521 break;
522 default:
523 unreachable("not reached");
524 }
525 }
526 assert(msg_type != -1);
527
528 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
529 rlen = 8;
530 dst = vec16(dst);
531 }
532
533 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
534 /* The send-from-GRF for SIMD16 texturing with a header has an extra
535 * hardware register allocated to it, which we need to skip over (since
536 * our coordinates in the payload are in the even-numbered registers,
537 * and the header comes right before the first one).
538 */
539 assert(src.file == BRW_GENERAL_REGISTER_FILE);
540 src.nr++;
541 }
542
543 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
544
545 /* Load the message header if present. If there's a texture offset,
546 * we need to set it up explicitly and load the offset bitfield.
547 * Otherwise, we can use an implied move from g0 to the first message reg.
548 */
549 if (inst->header_present) {
550 if (brw->gen < 6 && !inst->texture_offset) {
551 /* Set up an implied move from g0 to the MRF. */
552 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
553 } else {
554 struct brw_reg header_reg;
555
556 if (brw->gen >= 7) {
557 header_reg = src;
558 } else {
559 assert(inst->base_mrf != -1);
560 header_reg = brw_message_reg(inst->base_mrf);
561 }
562
563 brw_push_insn_state(p);
564 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
565 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
566 /* Explicitly set up the message header by copying g0 to the MRF. */
567 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
568
569 if (inst->texture_offset) {
570 /* Set the offset bits in DWord 2. */
571 brw_MOV(p, get_element_ud(header_reg, 2),
572 brw_imm_ud(inst->texture_offset));
573 }
574
575 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index, dst);
576 brw_pop_insn_state(p);
577 }
578 }
579
580 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
581 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
582 ? prog_data->base.binding_table.gather_texture_start
583 : prog_data->base.binding_table.texture_start;
584
585 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
586 uint32_t sampler = sampler_index.dw1.ud;
587
588 brw_SAMPLE(p,
589 retype(dst, BRW_REGISTER_TYPE_UW),
590 inst->base_mrf,
591 src,
592 sampler + base_binding_table_index,
593 sampler % 16,
594 msg_type,
595 rlen,
596 inst->mlen,
597 inst->header_present,
598 simd_mode,
599 return_format);
600
601 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
602 } else {
603 /* Non-const sampler index */
604 /* Note: this clobbers `dst` as a temporary before emitting the send */
605
606 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
607 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
608
609 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
610
611 brw_push_insn_state(p);
612 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
613 brw_set_default_access_mode(p, BRW_ALIGN_1);
614
615 /* Some care required: `sampler` and `temp` may alias:
616 * addr = sampler & 0xff
617 * temp = (sampler << 8) & 0xf00
618 * addr = addr | temp
619 */
620 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
621 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
622 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
623 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
624 brw_OR(p, addr, addr, temp);
625
626 /* a0.0 |= <descriptor> */
627 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
628 brw_set_sampler_message(p, insn_or,
629 0 /* surface */,
630 0 /* sampler */,
631 msg_type,
632 rlen,
633 inst->mlen /* mlen */,
634 inst->header_present /* header */,
635 simd_mode,
636 return_format);
637 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
638 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
639 brw_set_src0(p, insn_or, addr);
640 brw_set_dest(p, insn_or, addr);
641
642
643 /* dst = send(offset, a0.0) */
644 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
645 brw_set_dest(p, insn_send, dst);
646 brw_set_src0(p, insn_send, src);
647 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
648
649 brw_pop_insn_state(p);
650
651 /* visitor knows more than we do about the surface limit required,
652 * so has already done marking.
653 */
654 }
655 }
656
657
658 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
659 * looking like:
660 *
661 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
662 *
663 * Ideally, we want to produce:
664 *
665 * DDX DDY
666 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
667 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
668 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
669 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
670 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
671 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
672 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
673 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
674 *
675 * and add another set of two more subspans if in 16-pixel dispatch mode.
676 *
677 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
678 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
679 * pair. But the ideal approximation may impose a huge performance cost on
680 * sample_d. On at least Haswell, sample_d instruction does some
681 * optimizations if the same LOD is used for all pixels in the subspan.
682 *
683 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
684 * appropriate swizzling.
685 */
686 void
687 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
688 struct brw_reg quality)
689 {
690 unsigned vstride, width;
691 assert(quality.file == BRW_IMMEDIATE_VALUE);
692 assert(quality.type == BRW_REGISTER_TYPE_D);
693
694 int quality_value = quality.dw1.d;
695
696 if (quality_value == BRW_DERIVATIVE_FINE ||
697 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
698 /* produce accurate derivatives */
699 vstride = BRW_VERTICAL_STRIDE_2;
700 width = BRW_WIDTH_2;
701 }
702 else {
703 /* replicate the derivative at the top-left pixel to other pixels */
704 vstride = BRW_VERTICAL_STRIDE_4;
705 width = BRW_WIDTH_4;
706 }
707
708 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
709 BRW_REGISTER_TYPE_F,
710 vstride,
711 width,
712 BRW_HORIZONTAL_STRIDE_0,
713 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
714 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
715 BRW_REGISTER_TYPE_F,
716 vstride,
717 width,
718 BRW_HORIZONTAL_STRIDE_0,
719 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
720 brw_ADD(p, dst, src0, negate(src1));
721 }
722
723 /* The negate_value boolean is used to negate the derivative computation for
724 * FBOs, since they place the origin at the upper left instead of the lower
725 * left.
726 */
727 void
728 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
729 struct brw_reg quality, bool negate_value)
730 {
731 assert(quality.file == BRW_IMMEDIATE_VALUE);
732 assert(quality.type == BRW_REGISTER_TYPE_D);
733
734 int quality_value = quality.dw1.d;
735
736 if (quality_value == BRW_DERIVATIVE_FINE ||
737 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
738 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
739 * Region Restrictions):
740 *
741 * In Align16 access mode, SIMD16 is not allowed for DW operations
742 * and SIMD8 is not allowed for DF operations.
743 *
744 * In this context, "DW operations" means "operations acting on 32-bit
745 * values", so it includes operations on floats.
746 *
747 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
748 * (Instruction Compression -> Rules and Restrictions):
749 *
750 * A compressed instruction must be in Align1 access mode. Align16
751 * mode instructions cannot be compressed.
752 *
753 * Similar text exists in the g45 PRM.
754 *
755 * On these platforms, if we're building a SIMD16 shader, we need to
756 * manually unroll to a pair of SIMD8 instructions.
757 */
758 bool unroll_to_simd8 =
759 (dispatch_width == 16 &&
760 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
761
762 /* produce accurate derivatives */
763 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
764 BRW_REGISTER_TYPE_F,
765 BRW_VERTICAL_STRIDE_4,
766 BRW_WIDTH_4,
767 BRW_HORIZONTAL_STRIDE_1,
768 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
769 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
770 BRW_REGISTER_TYPE_F,
771 BRW_VERTICAL_STRIDE_4,
772 BRW_WIDTH_4,
773 BRW_HORIZONTAL_STRIDE_1,
774 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
775 brw_push_insn_state(p);
776 brw_set_default_access_mode(p, BRW_ALIGN_16);
777 if (unroll_to_simd8)
778 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
779 if (negate_value)
780 brw_ADD(p, dst, src1, negate(src0));
781 else
782 brw_ADD(p, dst, src0, negate(src1));
783 if (unroll_to_simd8) {
784 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
785 src0 = sechalf(src0);
786 src1 = sechalf(src1);
787 dst = sechalf(dst);
788 if (negate_value)
789 brw_ADD(p, dst, src1, negate(src0));
790 else
791 brw_ADD(p, dst, src0, negate(src1));
792 }
793 brw_pop_insn_state(p);
794 } else {
795 /* replicate the derivative at the top-left pixel to other pixels */
796 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
797 BRW_REGISTER_TYPE_F,
798 BRW_VERTICAL_STRIDE_4,
799 BRW_WIDTH_4,
800 BRW_HORIZONTAL_STRIDE_0,
801 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
802 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
803 BRW_REGISTER_TYPE_F,
804 BRW_VERTICAL_STRIDE_4,
805 BRW_WIDTH_4,
806 BRW_HORIZONTAL_STRIDE_0,
807 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
808 if (negate_value)
809 brw_ADD(p, dst, src1, negate(src0));
810 else
811 brw_ADD(p, dst, src0, negate(src1));
812 }
813 }
814
815 void
816 fs_generator::generate_discard_jump(fs_inst *inst)
817 {
818 assert(brw->gen >= 6);
819
820 /* This HALT will be patched up at FB write time to point UIP at the end of
821 * the program, and at brw_uip_jip() JIP will be set to the end of the
822 * current block (or the program).
823 */
824 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
825
826 brw_push_insn_state(p);
827 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
828 gen6_HALT(p);
829 brw_pop_insn_state(p);
830 }
831
832 void
833 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
834 {
835 assert(inst->mlen != 0);
836
837 brw_MOV(p,
838 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
839 retype(src, BRW_REGISTER_TYPE_UD));
840 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
841 dispatch_width / 8, inst->offset);
842 }
843
844 void
845 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
846 {
847 assert(inst->mlen != 0);
848
849 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
850 dispatch_width / 8, inst->offset);
851 }
852
853 void
854 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
855 {
856 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
857 }
858
859 void
860 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
861 struct brw_reg dst,
862 struct brw_reg index,
863 struct brw_reg offset)
864 {
865 assert(inst->mlen != 0);
866
867 assert(index.file == BRW_IMMEDIATE_VALUE &&
868 index.type == BRW_REGISTER_TYPE_UD);
869 uint32_t surf_index = index.dw1.ud;
870
871 assert(offset.file == BRW_IMMEDIATE_VALUE &&
872 offset.type == BRW_REGISTER_TYPE_UD);
873 uint32_t read_offset = offset.dw1.ud;
874
875 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
876 read_offset, surf_index);
877
878 brw_mark_surface_used(&prog_data->base, surf_index);
879 }
880
881 void
882 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
883 struct brw_reg dst,
884 struct brw_reg index,
885 struct brw_reg offset)
886 {
887 assert(inst->mlen == 0);
888 assert(index.type == BRW_REGISTER_TYPE_UD);
889
890 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
891 /* Reference just the dword we need, to avoid angering validate_reg(). */
892 offset = brw_vec1_grf(offset.nr, 0);
893
894 /* We use the SIMD4x2 mode because we want to end up with 4 components in
895 * the destination loaded consecutively from the same offset (which appears
896 * in the first component, and the rest are ignored).
897 */
898 dst.width = BRW_WIDTH_4;
899
900 if (index.file == BRW_IMMEDIATE_VALUE) {
901
902 uint32_t surf_index = index.dw1.ud;
903
904 brw_push_insn_state(p);
905 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
906 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
907 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
908 brw_pop_insn_state(p);
909
910 brw_set_dest(p, send, dst);
911 brw_set_src0(p, send, offset);
912 brw_set_sampler_message(p, send,
913 surf_index,
914 0, /* LD message ignores sampler unit */
915 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
916 1, /* rlen */
917 1, /* mlen */
918 false, /* no header */
919 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
920 0);
921
922 brw_mark_surface_used(&prog_data->base, surf_index);
923
924 } else {
925
926 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
927
928 brw_push_insn_state(p);
929 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
930 brw_set_default_access_mode(p, BRW_ALIGN_1);
931
932 /* a0.0 = surf_index & 0xff */
933 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
934 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
935 brw_set_dest(p, insn_and, addr);
936 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
937 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
938
939
940 /* a0.0 |= <descriptor> */
941 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
942 brw_set_sampler_message(p, insn_or,
943 0 /* surface */,
944 0 /* sampler */,
945 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
946 1 /* rlen */,
947 1 /* mlen */,
948 false /* header */,
949 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
950 0);
951 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
952 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
953 brw_set_src0(p, insn_or, addr);
954 brw_set_dest(p, insn_or, addr);
955
956
957 /* dst = send(offset, a0.0) */
958 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
959 brw_set_dest(p, insn_send, dst);
960 brw_set_src0(p, insn_send, offset);
961 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
962
963 brw_pop_insn_state(p);
964
965 /* visitor knows more than we do about the surface limit required,
966 * so has already done marking.
967 */
968
969 }
970 }
971
972 void
973 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
974 struct brw_reg dst,
975 struct brw_reg index,
976 struct brw_reg offset)
977 {
978 assert(brw->gen < 7); /* Should use the gen7 variant. */
979 assert(inst->header_present);
980 assert(inst->mlen);
981
982 assert(index.file == BRW_IMMEDIATE_VALUE &&
983 index.type == BRW_REGISTER_TYPE_UD);
984 uint32_t surf_index = index.dw1.ud;
985
986 uint32_t simd_mode, rlen, msg_type;
987 if (dispatch_width == 16) {
988 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
989 rlen = 8;
990 } else {
991 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
992 rlen = 4;
993 }
994
995 if (brw->gen >= 5)
996 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
997 else {
998 /* We always use the SIMD16 message so that we only have to load U, and
999 * not V or R.
1000 */
1001 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1002 assert(inst->mlen == 3);
1003 assert(inst->regs_written == 8);
1004 rlen = 8;
1005 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1006 }
1007
1008 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1009 BRW_REGISTER_TYPE_D);
1010 brw_MOV(p, offset_mrf, offset);
1011
1012 struct brw_reg header = brw_vec8_grf(0, 0);
1013 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1014
1015 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1016 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
1017 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1018 brw_set_src0(p, send, header);
1019 if (brw->gen < 6)
1020 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
1021
1022 /* Our surface is set up as floats, regardless of what actual data is
1023 * stored in it.
1024 */
1025 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1026 brw_set_sampler_message(p, send,
1027 surf_index,
1028 0, /* sampler (unused) */
1029 msg_type,
1030 rlen,
1031 inst->mlen,
1032 inst->header_present,
1033 simd_mode,
1034 return_format);
1035
1036 brw_mark_surface_used(&prog_data->base, surf_index);
1037 }
1038
1039 void
1040 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1041 struct brw_reg dst,
1042 struct brw_reg index,
1043 struct brw_reg offset)
1044 {
1045 assert(brw->gen >= 7);
1046 /* Varying-offset pull constant loads are treated as a normal expression on
1047 * gen7, so the fact that it's a send message is hidden at the IR level.
1048 */
1049 assert(!inst->header_present);
1050 assert(!inst->mlen);
1051 assert(index.type == BRW_REGISTER_TYPE_UD);
1052
1053 uint32_t simd_mode, rlen, mlen;
1054 if (dispatch_width == 16) {
1055 mlen = 2;
1056 rlen = 8;
1057 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1058 } else {
1059 mlen = 1;
1060 rlen = 4;
1061 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1062 }
1063
1064 if (index.file == BRW_IMMEDIATE_VALUE) {
1065
1066 uint32_t surf_index = index.dw1.ud;
1067
1068 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1069 brw_set_dest(p, send, dst);
1070 brw_set_src0(p, send, offset);
1071 brw_set_sampler_message(p, send,
1072 surf_index,
1073 0, /* LD message ignores sampler unit */
1074 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1075 rlen,
1076 mlen,
1077 false, /* no header */
1078 simd_mode,
1079 0);
1080
1081 brw_mark_surface_used(&prog_data->base, surf_index);
1082
1083 } else {
1084
1085 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1086
1087 brw_push_insn_state(p);
1088 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1089 brw_set_default_access_mode(p, BRW_ALIGN_1);
1090
1091 /* a0.0 = surf_index & 0xff */
1092 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1093 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1094 brw_set_dest(p, insn_and, addr);
1095 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1096 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1097
1098
1099 /* a0.0 |= <descriptor> */
1100 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1101 brw_set_sampler_message(p, insn_or,
1102 0 /* surface */,
1103 0 /* sampler */,
1104 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1105 rlen /* rlen */,
1106 mlen /* mlen */,
1107 false /* header */,
1108 simd_mode,
1109 0);
1110 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1111 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1112 brw_set_src0(p, insn_or, addr);
1113 brw_set_dest(p, insn_or, addr);
1114
1115
1116 /* dst = send(offset, a0.0) */
1117 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1118 brw_set_dest(p, insn_send, dst);
1119 brw_set_src0(p, insn_send, offset);
1120 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1121
1122 brw_pop_insn_state(p);
1123
1124 /* visitor knows more than we do about the surface limit required,
1125 * so has already done marking.
1126 */
1127 }
1128 }
1129
1130 /**
1131 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1132 * into the flags register (f0.0).
1133 *
1134 * Used only on Gen6 and above.
1135 */
1136 void
1137 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1138 {
1139 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1140 struct brw_reg dispatch_mask;
1141
1142 if (brw->gen >= 6)
1143 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1144 else
1145 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1146
1147 brw_push_insn_state(p);
1148 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1149 brw_MOV(p, flags, dispatch_mask);
1150 brw_pop_insn_state(p);
1151 }
1152
1153 void
1154 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1155 struct brw_reg dst,
1156 struct brw_reg src,
1157 struct brw_reg msg_data,
1158 unsigned msg_type)
1159 {
1160 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1161 msg_data.type == BRW_REGISTER_TYPE_UD);
1162
1163 brw_pixel_interpolator_query(p,
1164 retype(dst, BRW_REGISTER_TYPE_UW),
1165 src,
1166 inst->pi_noperspective,
1167 msg_type,
1168 msg_data.dw1.ud,
1169 inst->mlen,
1170 inst->regs_written);
1171 }
1172
1173
1174 static uint32_t brw_file_from_reg(fs_reg *reg)
1175 {
1176 switch (reg->file) {
1177 case GRF:
1178 return BRW_GENERAL_REGISTER_FILE;
1179 case MRF:
1180 return BRW_MESSAGE_REGISTER_FILE;
1181 case IMM:
1182 return BRW_IMMEDIATE_VALUE;
1183 default:
1184 unreachable("not reached");
1185 }
1186 }
1187
1188 struct brw_reg
1189 brw_reg_from_fs_reg(fs_reg *reg)
1190 {
1191 struct brw_reg brw_reg;
1192
1193 switch (reg->file) {
1194 case GRF:
1195 case MRF:
1196 if (reg->stride == 0) {
1197 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
1198 } else {
1199 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1200 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1201 }
1202
1203 brw_reg = retype(brw_reg, reg->type);
1204 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1205 break;
1206 case IMM:
1207 switch (reg->type) {
1208 case BRW_REGISTER_TYPE_F:
1209 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
1210 break;
1211 case BRW_REGISTER_TYPE_D:
1212 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
1213 break;
1214 case BRW_REGISTER_TYPE_UD:
1215 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
1216 break;
1217 default:
1218 unreachable("not reached");
1219 }
1220 break;
1221 case HW_REG:
1222 assert(reg->type == reg->fixed_hw_reg.type);
1223 brw_reg = reg->fixed_hw_reg;
1224 break;
1225 case BAD_FILE:
1226 /* Probably unused. */
1227 brw_reg = brw_null_reg();
1228 break;
1229 case UNIFORM:
1230 unreachable("not reached");
1231 default:
1232 unreachable("not reached");
1233 }
1234 if (reg->abs)
1235 brw_reg = brw_abs(brw_reg);
1236 if (reg->negate)
1237 brw_reg = negate(brw_reg);
1238
1239 return brw_reg;
1240 }
1241
1242 /**
1243 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1244 * sampler LD messages.
1245 *
1246 * We don't want to bake it into the send message's code generation because
1247 * that means we don't get a chance to schedule the instructions.
1248 */
1249 void
1250 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1251 struct brw_reg dst,
1252 struct brw_reg value)
1253 {
1254 assert(value.file == BRW_IMMEDIATE_VALUE);
1255
1256 brw_push_insn_state(p);
1257 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1258 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1259 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1260 brw_pop_insn_state(p);
1261 }
1262
1263 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1264 * (when mask is passed as a uniform) of register mask before moving it
1265 * to register dst.
1266 */
1267 void
1268 fs_generator::generate_set_omask(fs_inst *inst,
1269 struct brw_reg dst,
1270 struct brw_reg mask)
1271 {
1272 bool stride_8_8_1 =
1273 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1274 mask.width == BRW_WIDTH_8 &&
1275 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1276
1277 bool stride_0_1_0 =
1278 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1279 mask.width == BRW_WIDTH_1 &&
1280 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1281
1282 assert(stride_8_8_1 || stride_0_1_0);
1283 assert(dst.type == BRW_REGISTER_TYPE_UW);
1284
1285 if (dispatch_width == 16)
1286 dst = vec16(dst);
1287 brw_push_insn_state(p);
1288 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1289 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1290
1291 if (stride_8_8_1) {
1292 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1293 } else if (stride_0_1_0) {
1294 brw_MOV(p, dst, retype(mask, dst.type));
1295 }
1296 brw_pop_insn_state(p);
1297 }
1298
1299 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1300 * the ADD instruction.
1301 */
1302 void
1303 fs_generator::generate_set_sample_id(fs_inst *inst,
1304 struct brw_reg dst,
1305 struct brw_reg src0,
1306 struct brw_reg src1)
1307 {
1308 assert(dst.type == BRW_REGISTER_TYPE_D ||
1309 dst.type == BRW_REGISTER_TYPE_UD);
1310 assert(src0.type == BRW_REGISTER_TYPE_D ||
1311 src0.type == BRW_REGISTER_TYPE_UD);
1312
1313 brw_push_insn_state(p);
1314 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1315 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1316 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1317 brw_ADD(p, dst, src0, reg);
1318 if (dispatch_width == 16)
1319 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1320 brw_pop_insn_state(p);
1321 }
1322
1323 /**
1324 * Change the register's data type from UD to W, doubling the strides in order
1325 * to compensate for halving the data type width.
1326 */
1327 static struct brw_reg
1328 ud_reg_to_w(struct brw_reg r)
1329 {
1330 assert(r.type == BRW_REGISTER_TYPE_UD);
1331 r.type = BRW_REGISTER_TYPE_W;
1332
1333 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1334 * doubles the real stride.
1335 */
1336 if (r.hstride != 0)
1337 ++r.hstride;
1338 if (r.vstride != 0)
1339 ++r.vstride;
1340
1341 return r;
1342 }
1343
1344 void
1345 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1346 struct brw_reg dst,
1347 struct brw_reg x,
1348 struct brw_reg y)
1349 {
1350 assert(brw->gen >= 7);
1351 assert(dst.type == BRW_REGISTER_TYPE_UD);
1352 assert(x.type == BRW_REGISTER_TYPE_F);
1353 assert(y.type == BRW_REGISTER_TYPE_F);
1354
1355 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1356 *
1357 * Because this instruction does not have a 16-bit floating-point type,
1358 * the destination data type must be Word (W).
1359 *
1360 * The destination must be DWord-aligned and specify a horizontal stride
1361 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1362 * each destination channel and the upper word is not modified.
1363 */
1364 struct brw_reg dst_w = ud_reg_to_w(dst);
1365
1366 /* Give each 32-bit channel of dst the form below , where "." means
1367 * unchanged.
1368 * 0x....hhhh
1369 */
1370 brw_F32TO16(p, dst_w, y);
1371
1372 /* Now the form:
1373 * 0xhhhh0000
1374 */
1375 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1376
1377 /* And, finally the form of packHalf2x16's output:
1378 * 0xhhhhllll
1379 */
1380 brw_F32TO16(p, dst_w, x);
1381 }
1382
1383 void
1384 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1385 struct brw_reg dst,
1386 struct brw_reg src)
1387 {
1388 assert(brw->gen >= 7);
1389 assert(dst.type == BRW_REGISTER_TYPE_F);
1390 assert(src.type == BRW_REGISTER_TYPE_UD);
1391
1392 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1393 *
1394 * Because this instruction does not have a 16-bit floating-point type,
1395 * the source data type must be Word (W). The destination type must be
1396 * F (Float).
1397 */
1398 struct brw_reg src_w = ud_reg_to_w(src);
1399
1400 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1401 * For the Y case, we wish to access only the upper word; therefore
1402 * a 16-bit subregister offset is needed.
1403 */
1404 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1405 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1406 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1407 src_w.subnr += 2;
1408
1409 brw_F16TO32(p, dst, src_w);
1410 }
1411
1412 void
1413 fs_generator::generate_shader_time_add(fs_inst *inst,
1414 struct brw_reg payload,
1415 struct brw_reg offset,
1416 struct brw_reg value)
1417 {
1418 assert(brw->gen >= 7);
1419 brw_push_insn_state(p);
1420 brw_set_default_mask_control(p, true);
1421
1422 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1423 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1424 offset.type);
1425 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1426 value.type);
1427
1428 assert(offset.file == BRW_IMMEDIATE_VALUE);
1429 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1430 value.width = BRW_WIDTH_1;
1431 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1432 value.vstride = BRW_VERTICAL_STRIDE_0;
1433 } else {
1434 assert(value.file == BRW_IMMEDIATE_VALUE);
1435 }
1436
1437 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1438 * case, and we don't really care about squeezing every bit of performance
1439 * out of this path, so we just emit the MOVs from here.
1440 */
1441 brw_MOV(p, payload_offset, offset);
1442 brw_MOV(p, payload_value, value);
1443 brw_shader_time_add(p, payload,
1444 prog_data->base.binding_table.shader_time_start);
1445 brw_pop_insn_state(p);
1446
1447 brw_mark_surface_used(&prog_data->base,
1448 prog_data->base.binding_table.shader_time_start);
1449 }
1450
1451 void
1452 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1453 struct brw_reg atomic_op,
1454 struct brw_reg surf_index)
1455 {
1456 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1457 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1458 surf_index.file == BRW_IMMEDIATE_VALUE &&
1459 surf_index.type == BRW_REGISTER_TYPE_UD);
1460
1461 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1462 atomic_op.dw1.ud, surf_index.dw1.ud,
1463 inst->mlen, dispatch_width / 8);
1464
1465 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1466 }
1467
1468 void
1469 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1470 struct brw_reg surf_index)
1471 {
1472 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1473 surf_index.type == BRW_REGISTER_TYPE_UD);
1474
1475 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1476 surf_index.dw1.ud,
1477 inst->mlen, dispatch_width / 8);
1478
1479 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1480 }
1481
1482 void
1483 fs_generator::generate_code(const cfg_t *cfg)
1484 {
1485 int start_offset = p->next_insn_offset;
1486
1487 struct annotation_info annotation;
1488 memset(&annotation, 0, sizeof(annotation));
1489
1490 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1491 struct brw_reg src[3], dst;
1492 unsigned int last_insn_offset = p->next_insn_offset;
1493
1494 if (unlikely(debug_flag))
1495 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1496
1497 for (unsigned int i = 0; i < inst->sources; i++) {
1498 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1499
1500 /* The accumulator result appears to get used for the
1501 * conditional modifier generation. When negating a UD
1502 * value, there is a 33rd bit generated for the sign in the
1503 * accumulator value, so now you can't check, for example,
1504 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1505 */
1506 assert(!inst->conditional_mod ||
1507 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1508 !inst->src[i].negate);
1509 }
1510 dst = brw_reg_from_fs_reg(&inst->dst);
1511
1512 brw_set_default_predicate_control(p, inst->predicate);
1513 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1514 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1515 brw_set_default_saturate(p, inst->saturate);
1516 brw_set_default_mask_control(p, inst->force_writemask_all);
1517 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1518
1519 if (inst->force_uncompressed || dispatch_width == 8) {
1520 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1521 } else if (inst->force_sechalf) {
1522 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1523 } else {
1524 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1525 }
1526
1527 switch (inst->opcode) {
1528 case BRW_OPCODE_MOV:
1529 brw_MOV(p, dst, src[0]);
1530 break;
1531 case BRW_OPCODE_ADD:
1532 brw_ADD(p, dst, src[0], src[1]);
1533 break;
1534 case BRW_OPCODE_MUL:
1535 brw_MUL(p, dst, src[0], src[1]);
1536 break;
1537 case BRW_OPCODE_AVG:
1538 brw_AVG(p, dst, src[0], src[1]);
1539 break;
1540 case BRW_OPCODE_MACH:
1541 brw_MACH(p, dst, src[0], src[1]);
1542 break;
1543
1544 case BRW_OPCODE_MAD:
1545 assert(brw->gen >= 6);
1546 brw_set_default_access_mode(p, BRW_ALIGN_16);
1547 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1548 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1549 brw_MAD(p, dst, src[0], src[1], src[2]);
1550 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1551 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1552 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1553 } else {
1554 brw_MAD(p, dst, src[0], src[1], src[2]);
1555 }
1556 brw_set_default_access_mode(p, BRW_ALIGN_1);
1557 break;
1558
1559 case BRW_OPCODE_LRP:
1560 assert(brw->gen >= 6);
1561 brw_set_default_access_mode(p, BRW_ALIGN_16);
1562 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1563 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1564 brw_LRP(p, dst, src[0], src[1], src[2]);
1565 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1566 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1567 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1568 } else {
1569 brw_LRP(p, dst, src[0], src[1], src[2]);
1570 }
1571 brw_set_default_access_mode(p, BRW_ALIGN_1);
1572 break;
1573
1574 case BRW_OPCODE_FRC:
1575 brw_FRC(p, dst, src[0]);
1576 break;
1577 case BRW_OPCODE_RNDD:
1578 brw_RNDD(p, dst, src[0]);
1579 break;
1580 case BRW_OPCODE_RNDE:
1581 brw_RNDE(p, dst, src[0]);
1582 break;
1583 case BRW_OPCODE_RNDZ:
1584 brw_RNDZ(p, dst, src[0]);
1585 break;
1586
1587 case BRW_OPCODE_AND:
1588 brw_AND(p, dst, src[0], src[1]);
1589 break;
1590 case BRW_OPCODE_OR:
1591 brw_OR(p, dst, src[0], src[1]);
1592 break;
1593 case BRW_OPCODE_XOR:
1594 brw_XOR(p, dst, src[0], src[1]);
1595 break;
1596 case BRW_OPCODE_NOT:
1597 brw_NOT(p, dst, src[0]);
1598 break;
1599 case BRW_OPCODE_ASR:
1600 brw_ASR(p, dst, src[0], src[1]);
1601 break;
1602 case BRW_OPCODE_SHR:
1603 brw_SHR(p, dst, src[0], src[1]);
1604 break;
1605 case BRW_OPCODE_SHL:
1606 brw_SHL(p, dst, src[0], src[1]);
1607 break;
1608 case BRW_OPCODE_F32TO16:
1609 assert(brw->gen >= 7);
1610 brw_F32TO16(p, dst, src[0]);
1611 break;
1612 case BRW_OPCODE_F16TO32:
1613 assert(brw->gen >= 7);
1614 brw_F16TO32(p, dst, src[0]);
1615 break;
1616 case BRW_OPCODE_CMP:
1617 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1618 break;
1619 case BRW_OPCODE_SEL:
1620 brw_SEL(p, dst, src[0], src[1]);
1621 break;
1622 case BRW_OPCODE_BFREV:
1623 assert(brw->gen >= 7);
1624 /* BFREV only supports UD type for src and dst. */
1625 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1626 retype(src[0], BRW_REGISTER_TYPE_UD));
1627 break;
1628 case BRW_OPCODE_FBH:
1629 assert(brw->gen >= 7);
1630 /* FBH only supports UD type for dst. */
1631 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1632 break;
1633 case BRW_OPCODE_FBL:
1634 assert(brw->gen >= 7);
1635 /* FBL only supports UD type for dst. */
1636 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1637 break;
1638 case BRW_OPCODE_CBIT:
1639 assert(brw->gen >= 7);
1640 /* CBIT only supports UD type for dst. */
1641 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1642 break;
1643 case BRW_OPCODE_ADDC:
1644 assert(brw->gen >= 7);
1645 brw_ADDC(p, dst, src[0], src[1]);
1646 break;
1647 case BRW_OPCODE_SUBB:
1648 assert(brw->gen >= 7);
1649 brw_SUBB(p, dst, src[0], src[1]);
1650 break;
1651 case BRW_OPCODE_MAC:
1652 brw_MAC(p, dst, src[0], src[1]);
1653 break;
1654
1655 case BRW_OPCODE_BFE:
1656 assert(brw->gen >= 7);
1657 brw_set_default_access_mode(p, BRW_ALIGN_16);
1658 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1659 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1660 brw_BFE(p, dst, src[0], src[1], src[2]);
1661 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1662 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1663 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1664 } else {
1665 brw_BFE(p, dst, src[0], src[1], src[2]);
1666 }
1667 brw_set_default_access_mode(p, BRW_ALIGN_1);
1668 break;
1669
1670 case BRW_OPCODE_BFI1:
1671 assert(brw->gen >= 7);
1672 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1673 * should
1674 *
1675 * "Force BFI instructions to be executed always in SIMD8."
1676 */
1677 if (dispatch_width == 16 && brw->is_haswell) {
1678 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1679 brw_BFI1(p, dst, src[0], src[1]);
1680 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1681 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1682 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1683 } else {
1684 brw_BFI1(p, dst, src[0], src[1]);
1685 }
1686 break;
1687 case BRW_OPCODE_BFI2:
1688 assert(brw->gen >= 7);
1689 brw_set_default_access_mode(p, BRW_ALIGN_16);
1690 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1691 * should
1692 *
1693 * "Force BFI instructions to be executed always in SIMD8."
1694 *
1695 * Otherwise we would be able to emit compressed instructions like we
1696 * do for the other three-source instructions.
1697 */
1698 if (dispatch_width == 16) {
1699 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1700 brw_BFI2(p, dst, src[0], src[1], src[2]);
1701 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1702 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1703 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1704 } else {
1705 brw_BFI2(p, dst, src[0], src[1], src[2]);
1706 }
1707 brw_set_default_access_mode(p, BRW_ALIGN_1);
1708 break;
1709
1710 case BRW_OPCODE_IF:
1711 if (inst->src[0].file != BAD_FILE) {
1712 /* The instruction has an embedded compare (only allowed on gen6) */
1713 assert(brw->gen == 6);
1714 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1715 } else {
1716 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1717 }
1718 break;
1719
1720 case BRW_OPCODE_ELSE:
1721 brw_ELSE(p);
1722 break;
1723 case BRW_OPCODE_ENDIF:
1724 brw_ENDIF(p);
1725 break;
1726
1727 case BRW_OPCODE_DO:
1728 brw_DO(p, BRW_EXECUTE_8);
1729 break;
1730
1731 case BRW_OPCODE_BREAK:
1732 brw_BREAK(p);
1733 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1734 break;
1735 case BRW_OPCODE_CONTINUE:
1736 brw_CONT(p);
1737 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1738 break;
1739
1740 case BRW_OPCODE_WHILE:
1741 brw_WHILE(p);
1742 break;
1743
1744 case SHADER_OPCODE_RCP:
1745 case SHADER_OPCODE_RSQ:
1746 case SHADER_OPCODE_SQRT:
1747 case SHADER_OPCODE_EXP2:
1748 case SHADER_OPCODE_LOG2:
1749 case SHADER_OPCODE_SIN:
1750 case SHADER_OPCODE_COS:
1751 assert(brw->gen < 6 || inst->mlen == 0);
1752 if (brw->gen >= 7) {
1753 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1754 brw_null_reg());
1755 } else if (brw->gen == 6) {
1756 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1757 } else if (brw->gen == 5 || brw->is_g4x) {
1758 generate_math_g45(inst, dst, src[0]);
1759 } else {
1760 generate_math_gen4(inst, dst, src[0]);
1761 }
1762 break;
1763 case SHADER_OPCODE_INT_QUOTIENT:
1764 case SHADER_OPCODE_INT_REMAINDER:
1765 case SHADER_OPCODE_POW:
1766 assert(brw->gen < 6 || inst->mlen == 0);
1767 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1768 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1769 } else if (brw->gen >= 6) {
1770 generate_math_gen6(inst, dst, src[0], src[1]);
1771 } else {
1772 generate_math_gen4(inst, dst, src[0]);
1773 }
1774 break;
1775 case FS_OPCODE_PIXEL_X:
1776 generate_pixel_xy(dst, true);
1777 break;
1778 case FS_OPCODE_PIXEL_Y:
1779 generate_pixel_xy(dst, false);
1780 break;
1781 case FS_OPCODE_CINTERP:
1782 brw_MOV(p, dst, src[0]);
1783 break;
1784 case FS_OPCODE_LINTERP:
1785 generate_linterp(inst, dst, src);
1786 break;
1787 case SHADER_OPCODE_TEX:
1788 case FS_OPCODE_TXB:
1789 case SHADER_OPCODE_TXD:
1790 case SHADER_OPCODE_TXF:
1791 case SHADER_OPCODE_TXF_CMS:
1792 case SHADER_OPCODE_TXF_UMS:
1793 case SHADER_OPCODE_TXF_MCS:
1794 case SHADER_OPCODE_TXL:
1795 case SHADER_OPCODE_TXS:
1796 case SHADER_OPCODE_LOD:
1797 case SHADER_OPCODE_TG4:
1798 case SHADER_OPCODE_TG4_OFFSET:
1799 generate_tex(inst, dst, src[0], src[1]);
1800 break;
1801 case FS_OPCODE_DDX:
1802 generate_ddx(inst, dst, src[0], src[1]);
1803 break;
1804 case FS_OPCODE_DDY:
1805 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1806 * guarantee that key->render_to_fbo is set).
1807 */
1808 assert(fp->UsesDFdy);
1809 generate_ddy(inst, dst, src[0], src[1], key->render_to_fbo);
1810 break;
1811
1812 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1813 generate_scratch_write(inst, src[0]);
1814 break;
1815
1816 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1817 generate_scratch_read(inst, dst);
1818 break;
1819
1820 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1821 generate_scratch_read_gen7(inst, dst);
1822 break;
1823
1824 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1825 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1826 break;
1827
1828 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1829 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1830 break;
1831
1832 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1833 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1834 break;
1835
1836 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1837 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1838 break;
1839
1840 case FS_OPCODE_REP_FB_WRITE:
1841 case FS_OPCODE_FB_WRITE:
1842 generate_fb_write(inst);
1843 break;
1844
1845 case FS_OPCODE_BLORP_FB_WRITE:
1846 generate_blorp_fb_write(inst);
1847 break;
1848
1849 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1850 generate_mov_dispatch_to_flags(inst);
1851 break;
1852
1853 case FS_OPCODE_DISCARD_JUMP:
1854 generate_discard_jump(inst);
1855 break;
1856
1857 case SHADER_OPCODE_SHADER_TIME_ADD:
1858 generate_shader_time_add(inst, src[0], src[1], src[2]);
1859 break;
1860
1861 case SHADER_OPCODE_UNTYPED_ATOMIC:
1862 generate_untyped_atomic(inst, dst, src[0], src[1]);
1863 break;
1864
1865 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1866 generate_untyped_surface_read(inst, dst, src[0]);
1867 break;
1868
1869 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1870 generate_set_simd4x2_offset(inst, dst, src[0]);
1871 break;
1872
1873 case FS_OPCODE_SET_OMASK:
1874 generate_set_omask(inst, dst, src[0]);
1875 break;
1876
1877 case FS_OPCODE_SET_SAMPLE_ID:
1878 generate_set_sample_id(inst, dst, src[0], src[1]);
1879 break;
1880
1881 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1882 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1883 break;
1884
1885 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1886 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1887 generate_unpack_half_2x16_split(inst, dst, src[0]);
1888 break;
1889
1890 case FS_OPCODE_PLACEHOLDER_HALT:
1891 /* This is the place where the final HALT needs to be inserted if
1892 * we've emitted any discards. If not, this will emit no code.
1893 */
1894 if (!patch_discard_jumps_to_fb_writes()) {
1895 if (unlikely(debug_flag)) {
1896 annotation.ann_count--;
1897 }
1898 }
1899 break;
1900
1901 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
1902 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1903 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
1904 break;
1905
1906 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
1907 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1908 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
1909 break;
1910
1911 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
1912 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1913 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
1914 break;
1915
1916 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
1917 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1918 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
1919 break;
1920
1921 default:
1922 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1923 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1924 opcode_descs[inst->opcode].name);
1925 } else {
1926 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1927 }
1928 abort();
1929
1930 case SHADER_OPCODE_LOAD_PAYLOAD:
1931 unreachable("Should be lowered by lower_load_payload()");
1932 }
1933
1934 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1935 assert(p->next_insn_offset == last_insn_offset + 16 ||
1936 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1937 "emitting more than 1 instruction");
1938
1939 brw_inst *last = &p->store[last_insn_offset / 16];
1940
1941 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1942 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1943 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1944 }
1945 }
1946
1947 brw_set_uip_jip(p);
1948 annotation_finalize(&annotation, p->next_insn_offset);
1949
1950 int before_size = p->next_insn_offset - start_offset;
1951 brw_compact_instructions(p, start_offset, annotation.ann_count,
1952 annotation.ann);
1953 int after_size = p->next_insn_offset - start_offset;
1954
1955 if (unlikely(debug_flag)) {
1956 if (prog) {
1957 fprintf(stderr,
1958 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
1959 prog->Label ? prog->Label : "unnamed",
1960 prog->Name, dispatch_width);
1961 } else if (fp) {
1962 fprintf(stderr,
1963 "Native code for fragment program %d (SIMD%d dispatch):\n",
1964 fp->Base.Id, dispatch_width);
1965 } else {
1966 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
1967 dispatch_width);
1968 }
1969 fprintf(stderr, "SIMD%d shader: %d instructions. Compacted %d to %d"
1970 " bytes (%.0f%%)\n",
1971 dispatch_width, before_size / 16, before_size, after_size,
1972 100.0f * (before_size - after_size) / before_size);
1973
1974 const struct gl_program *prog = fp ? &fp->Base : NULL;
1975
1976 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1977 ralloc_free(annotation.ann);
1978 }
1979 }
1980
1981 const unsigned *
1982 fs_generator::generate_assembly(const cfg_t *simd8_cfg,
1983 const cfg_t *simd16_cfg,
1984 unsigned *assembly_size)
1985 {
1986 assert(simd8_cfg || simd16_cfg);
1987
1988 if (simd8_cfg) {
1989 dispatch_width = 8;
1990 generate_code(simd8_cfg);
1991 }
1992
1993 if (simd16_cfg) {
1994 /* align to 64 byte boundary. */
1995 while (p->next_insn_offset % 64) {
1996 brw_NOP(p);
1997 }
1998
1999 /* Save off the start of this SIMD16 program */
2000 prog_data->prog_offset_16 = p->next_insn_offset;
2001
2002 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
2003
2004 dispatch_width = 16;
2005 generate_code(simd16_cfg);
2006 }
2007
2008 return brw_get_program(p, assembly_size);
2009 }