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Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "main/macros.h"
31 #include "brw_context.h"
32 #include "brw_eu.h"
33 #include "brw_fs.h"
34 #include "brw_cfg.h"
35
36 static uint32_t brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case GRF:
40 return BRW_GENERAL_REGISTER_FILE;
41 case MRF:
42 return BRW_MESSAGE_REGISTER_FILE;
43 case IMM:
44 return BRW_IMMEDIATE_VALUE;
45 case BAD_FILE:
46 case HW_REG:
47 case ATTR:
48 case UNIFORM:
49 unreachable("not reached");
50 }
51 return 0;
52 }
53
54 static struct brw_reg
55 brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
56 {
57 struct brw_reg brw_reg;
58
59 switch (reg->file) {
60 case MRF:
61 assert((reg->reg & ~(1 << 7)) < BRW_MAX_MRF(gen));
62 /* Fallthrough */
63 case GRF:
64 if (reg->stride == 0) {
65 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
66 } else if (inst->exec_size < 8) {
67 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
68 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
69 inst->exec_size, reg->stride);
70 } else {
71 /* From the Haswell PRM:
72 *
73 * VertStride must be used to cross GRF register boundaries. This
74 * rule implies that elements within a 'Width' cannot cross GRF
75 * boundaries.
76 *
77 * So, for registers with width > 8, we have to use a width of 8
78 * and trust the compression state to sort out the exec size.
79 */
80 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
81 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
82 }
83
84 brw_reg = retype(brw_reg, reg->type);
85 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
86 break;
87 case IMM:
88 assert(reg->stride == ((reg->type == BRW_REGISTER_TYPE_V ||
89 reg->type == BRW_REGISTER_TYPE_UV ||
90 reg->type == BRW_REGISTER_TYPE_VF) ? 1 : 0));
91
92 switch (reg->type) {
93 case BRW_REGISTER_TYPE_F:
94 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
95 break;
96 case BRW_REGISTER_TYPE_D:
97 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
98 break;
99 case BRW_REGISTER_TYPE_UD:
100 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
101 break;
102 case BRW_REGISTER_TYPE_W:
103 brw_reg = brw_imm_w(reg->fixed_hw_reg.dw1.d);
104 break;
105 case BRW_REGISTER_TYPE_UW:
106 brw_reg = brw_imm_uw(reg->fixed_hw_reg.dw1.ud);
107 break;
108 case BRW_REGISTER_TYPE_VF:
109 brw_reg = brw_imm_vf(reg->fixed_hw_reg.dw1.ud);
110 break;
111 default:
112 unreachable("not reached");
113 }
114 break;
115 case HW_REG:
116 assert(reg->type == reg->fixed_hw_reg.type);
117 brw_reg = reg->fixed_hw_reg;
118 break;
119 case BAD_FILE:
120 /* Probably unused. */
121 brw_reg = brw_null_reg();
122 break;
123 case ATTR:
124 case UNIFORM:
125 unreachable("not reached");
126 }
127 if (reg->abs)
128 brw_reg = brw_abs(brw_reg);
129 if (reg->negate)
130 brw_reg = negate(brw_reg);
131
132 return brw_reg;
133 }
134
135 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
136 void *mem_ctx,
137 const void *key,
138 struct brw_stage_prog_data *prog_data,
139 unsigned promoted_constants,
140 bool runtime_check_aads_emit,
141 const char *stage_abbrev)
142
143 : compiler(compiler), log_data(log_data),
144 devinfo(compiler->devinfo), key(key),
145 prog_data(prog_data),
146 promoted_constants(promoted_constants),
147 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
148 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
149 {
150 p = rzalloc(mem_ctx, struct brw_codegen);
151 brw_init_codegen(devinfo, p, mem_ctx);
152 }
153
154 fs_generator::~fs_generator()
155 {
156 }
157
158 class ip_record : public exec_node {
159 public:
160 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
161
162 ip_record(int ip)
163 {
164 this->ip = ip;
165 }
166
167 int ip;
168 };
169
170 bool
171 fs_generator::patch_discard_jumps_to_fb_writes()
172 {
173 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
174 return false;
175
176 int scale = brw_jump_scale(p->devinfo);
177
178 /* There is a somewhat strange undocumented requirement of using
179 * HALT, according to the simulator. If some channel has HALTed to
180 * a particular UIP, then by the end of the program, every channel
181 * must have HALTed to that UIP. Furthermore, the tracking is a
182 * stack, so you can't do the final halt of a UIP after starting
183 * halting to a new UIP.
184 *
185 * Symptoms of not emitting this instruction on actual hardware
186 * included GPU hangs and sparkly rendering on the piglit discard
187 * tests.
188 */
189 brw_inst *last_halt = gen6_HALT(p);
190 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
191 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
192
193 int ip = p->nr_insn;
194
195 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
196 brw_inst *patch = &p->store[patch_ip->ip];
197
198 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
199 /* HALT takes a half-instruction distance from the pre-incremented IP. */
200 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
201 }
202
203 this->discard_halt_patches.make_empty();
204 return true;
205 }
206
207 void
208 fs_generator::fire_fb_write(fs_inst *inst,
209 struct brw_reg payload,
210 struct brw_reg implied_header,
211 GLuint nr)
212 {
213 uint32_t msg_control;
214
215 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
216
217 if (devinfo->gen < 6) {
218 brw_push_insn_state(p);
219 brw_set_default_exec_size(p, BRW_EXECUTE_8);
220 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
221 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
222 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
223 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
224 brw_pop_insn_state(p);
225 }
226
227 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
228 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
229 else if (prog_data->dual_src_blend) {
230 if (!inst->force_sechalf)
231 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
232 else
233 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
234 } else if (inst->exec_size == 16)
235 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
236 else
237 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
238
239 uint32_t surf_index =
240 prog_data->binding_table.render_target_start + inst->target;
241
242 bool last_render_target = inst->eot ||
243 (prog_data->dual_src_blend && dispatch_width == 16);
244
245
246 brw_fb_WRITE(p,
247 dispatch_width,
248 payload,
249 implied_header,
250 msg_control,
251 surf_index,
252 nr,
253 0,
254 inst->eot,
255 last_render_target,
256 inst->header_size != 0);
257
258 brw_mark_surface_used(&prog_data->base, surf_index);
259 }
260
261 void
262 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
263 {
264 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
265 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
266 struct brw_reg implied_header;
267
268 if (devinfo->gen < 8 && !devinfo->is_haswell) {
269 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
270 }
271
272 if (inst->base_mrf >= 0)
273 payload = brw_message_reg(inst->base_mrf);
274
275 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
276 * move, here's g1.
277 */
278 if (inst->header_size != 0) {
279 brw_push_insn_state(p);
280 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
281 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
282 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
283 brw_set_default_flag_reg(p, 0, 0);
284
285 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
286 * present.
287 */
288 if (prog_data->uses_kill) {
289 struct brw_reg pixel_mask;
290
291 if (devinfo->gen >= 6)
292 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
293 else
294 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
295
296 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
297 }
298
299 if (devinfo->gen >= 6) {
300 brw_push_insn_state(p);
301 brw_set_default_exec_size(p, BRW_EXECUTE_16);
302 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
303 brw_MOV(p,
304 retype(payload, BRW_REGISTER_TYPE_UD),
305 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
306 brw_pop_insn_state(p);
307
308 if (inst->target > 0 && key->replicate_alpha) {
309 /* Set "Source0 Alpha Present to RenderTarget" bit in message
310 * header.
311 */
312 brw_OR(p,
313 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
314 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
315 brw_imm_ud(0x1 << 11));
316 }
317
318 if (inst->target > 0) {
319 /* Set the render target index for choosing BLEND_STATE. */
320 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
321 BRW_REGISTER_TYPE_UD),
322 brw_imm_ud(inst->target));
323 }
324
325 /* Set computes stencil to render target */
326 if (prog_data->computed_stencil) {
327 brw_OR(p,
328 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
329 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
330 brw_imm_ud(0x1 << 14));
331 }
332
333 implied_header = brw_null_reg();
334 } else {
335 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
336 }
337
338 brw_pop_insn_state(p);
339 } else {
340 implied_header = brw_null_reg();
341 }
342
343 if (!runtime_check_aads_emit) {
344 fire_fb_write(inst, payload, implied_header, inst->mlen);
345 } else {
346 /* This can only happen in gen < 6 */
347 assert(devinfo->gen < 6);
348
349 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
350
351 /* Check runtime bit to detect if we have to send AA data or not */
352 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
353 brw_AND(p,
354 v1_null_ud,
355 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
356 brw_imm_ud(1<<26));
357 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
358
359 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
360 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
361 {
362 /* Don't send AA data */
363 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
364 }
365 brw_land_fwd_jump(p, jmp);
366 fire_fb_write(inst, payload, implied_header, inst->mlen);
367 }
368 }
369
370 void
371 fs_generator::generate_urb_read(fs_inst *inst,
372 struct brw_reg dst,
373 struct brw_reg header)
374 {
375 assert(header.file == BRW_GENERAL_REGISTER_FILE);
376 assert(header.type == BRW_REGISTER_TYPE_UD);
377
378 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
379 brw_set_dest(p, send, dst);
380 brw_set_src0(p, send, header);
381 brw_set_src1(p, send, brw_imm_ud(0u));
382
383 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
384 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
385
386 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
387 brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
388 brw_inst_set_header_present(p->devinfo, send, true);
389 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
390 }
391
392 void
393 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
394 {
395 brw_inst *insn;
396
397 insn = brw_next_insn(p, BRW_OPCODE_SEND);
398
399 brw_set_dest(p, insn, brw_null_reg());
400 brw_set_src0(p, insn, payload);
401 brw_set_src1(p, insn, brw_imm_d(0));
402
403 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
404 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
405
406 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
407 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
408 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
409
410 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
411 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
412 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
413
414 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
415 brw_inst_set_rlen(p->devinfo, insn, 0);
416 brw_inst_set_eot(p->devinfo, insn, inst->eot);
417 brw_inst_set_header_present(p->devinfo, insn, true);
418 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
419 }
420
421 void
422 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
423 {
424 struct brw_inst *insn;
425
426 insn = brw_next_insn(p, BRW_OPCODE_SEND);
427
428 brw_set_dest(p, insn, brw_null_reg());
429 brw_set_src0(p, insn, payload);
430 brw_set_src1(p, insn, brw_imm_d(0));
431
432 /* Terminate a compute shader by sending a message to the thread spawner.
433 */
434 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
435 brw_inst_set_mlen(devinfo, insn, 1);
436 brw_inst_set_rlen(devinfo, insn, 0);
437 brw_inst_set_eot(devinfo, insn, inst->eot);
438 brw_inst_set_header_present(devinfo, insn, false);
439
440 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
441 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
442
443 /* Note that even though the thread has a URB resource associated with it,
444 * we set the "do not dereference URB" bit, because the URB resource is
445 * managed by the fixed-function unit, so it will free it automatically.
446 */
447 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
448
449 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
450 }
451
452 void
453 fs_generator::generate_stencil_ref_packing(fs_inst *inst,
454 struct brw_reg dst,
455 struct brw_reg src)
456 {
457 assert(dispatch_width == 8);
458 assert(devinfo->gen >= 9);
459
460 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
461 * Presumably, in order to save memory bandwidth, the stencil reference
462 * values written from the FS need to be packed into 2 dwords (this makes
463 * sense because the stencil values are limited to 1 byte each and a SIMD8
464 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
465 *
466 * The spec is confusing here because in the payload definition of MDP_RTW_S8
467 * (Message Data Payload for Render Target Writes with Stencil 8b) the
468 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
469 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
470 * packed values specified above and diagrammed below:
471 *
472 * 31 0
473 * --------------------------------
474 * DW | |
475 * 2-7 | IGNORED |
476 * | |
477 * --------------------------------
478 * DW1 | STC | STC | STC | STC |
479 * | slot7 | slot6 | slot5 | slot4|
480 * --------------------------------
481 * DW0 | STC | STC | STC | STC |
482 * | slot3 | slot2 | slot1 | slot0|
483 * --------------------------------
484 */
485
486 src.vstride = BRW_VERTICAL_STRIDE_4;
487 src.width = BRW_WIDTH_1;
488 src.hstride = BRW_HORIZONTAL_STRIDE_0;
489 assert(src.type == BRW_REGISTER_TYPE_UB);
490 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UB), src);
491 }
492
493 void
494 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
495 {
496 brw_barrier(p, src);
497 brw_WAIT(p);
498 }
499
500 void
501 fs_generator::generate_blorp_fb_write(fs_inst *inst)
502 {
503 brw_fb_WRITE(p,
504 16 /* dispatch_width */,
505 brw_message_reg(inst->base_mrf),
506 brw_reg_from_fs_reg(inst, &inst->src[0], devinfo->gen),
507 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
508 inst->target,
509 inst->mlen,
510 0,
511 true,
512 true,
513 inst->header_size != 0);
514 }
515
516 void
517 fs_generator::generate_linterp(fs_inst *inst,
518 struct brw_reg dst, struct brw_reg *src)
519 {
520 /* PLN reads:
521 * / in SIMD16 \
522 * -----------------------------------
523 * | src1+0 | src1+1 | src1+2 | src1+3 |
524 * |-----------------------------------|
525 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
526 * -----------------------------------
527 *
528 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
529 *
530 * -----------------------------------
531 * | src1+0 | src1+1 | src1+2 | src1+3 |
532 * |-----------------------------------|
533 * |(x0, x1)|(y0, y1)| | | in SIMD8
534 * |-----------------------------------|
535 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
536 * -----------------------------------
537 *
538 * See also: emit_interpolation_setup_gen4().
539 */
540 struct brw_reg delta_x = src[0];
541 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
542 struct brw_reg interp = src[1];
543
544 if (devinfo->has_pln &&
545 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
546 brw_PLN(p, dst, interp, delta_x);
547 } else {
548 brw_LINE(p, brw_null_reg(), interp, delta_x);
549 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
550 }
551 }
552
553 void
554 fs_generator::generate_math_gen6(fs_inst *inst,
555 struct brw_reg dst,
556 struct brw_reg src0,
557 struct brw_reg src1)
558 {
559 int op = brw_math_function(inst->opcode);
560 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
561
562 if (dispatch_width == 8) {
563 gen6_math(p, dst, op, src0, src1);
564 } else if (dispatch_width == 16) {
565 brw_push_insn_state(p);
566 brw_set_default_exec_size(p, BRW_EXECUTE_8);
567 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
568 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
569 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
570 gen6_math(p, sechalf(dst), op, sechalf(src0),
571 binop ? sechalf(src1) : brw_null_reg());
572 brw_pop_insn_state(p);
573 }
574 }
575
576 void
577 fs_generator::generate_math_gen4(fs_inst *inst,
578 struct brw_reg dst,
579 struct brw_reg src)
580 {
581 int op = brw_math_function(inst->opcode);
582
583 assert(inst->mlen >= 1);
584
585 if (dispatch_width == 8) {
586 gen4_math(p, dst,
587 op,
588 inst->base_mrf, src,
589 BRW_MATH_PRECISION_FULL);
590 } else if (dispatch_width == 16) {
591 brw_set_default_exec_size(p, BRW_EXECUTE_8);
592 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
593 gen4_math(p, firsthalf(dst),
594 op,
595 inst->base_mrf, firsthalf(src),
596 BRW_MATH_PRECISION_FULL);
597 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
598 gen4_math(p, sechalf(dst),
599 op,
600 inst->base_mrf + 1, sechalf(src),
601 BRW_MATH_PRECISION_FULL);
602
603 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
604 }
605 }
606
607 void
608 fs_generator::generate_math_g45(fs_inst *inst,
609 struct brw_reg dst,
610 struct brw_reg src)
611 {
612 if (inst->opcode == SHADER_OPCODE_POW ||
613 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
614 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
615 generate_math_gen4(inst, dst, src);
616 return;
617 }
618
619 int op = brw_math_function(inst->opcode);
620
621 assert(inst->mlen >= 1);
622
623 gen4_math(p, dst,
624 op,
625 inst->base_mrf, src,
626 BRW_MATH_PRECISION_FULL);
627 }
628
629 void
630 fs_generator::generate_get_buffer_size(fs_inst *inst,
631 struct brw_reg dst,
632 struct brw_reg src,
633 struct brw_reg surf_index)
634 {
635 assert(devinfo->gen >= 7);
636 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
637
638 uint32_t simd_mode;
639 int rlen = 4;
640
641 switch (inst->exec_size) {
642 case 8:
643 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
644 break;
645 case 16:
646 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
647 break;
648 default:
649 unreachable("Invalid width for texture instruction");
650 }
651
652 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
653 rlen = 8;
654 dst = vec16(dst);
655 }
656
657 brw_SAMPLE(p,
658 retype(dst, BRW_REGISTER_TYPE_UW),
659 inst->base_mrf,
660 src,
661 surf_index.dw1.ud,
662 0,
663 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
664 rlen, /* response length */
665 inst->mlen,
666 inst->header_size > 0,
667 simd_mode,
668 BRW_SAMPLER_RETURN_FORMAT_SINT32);
669
670 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
671 }
672
673 void
674 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
675 struct brw_reg sampler_index)
676 {
677 int msg_type = -1;
678 int rlen = 4;
679 uint32_t simd_mode;
680 uint32_t return_format;
681 bool is_combined_send = inst->eot;
682
683 switch (dst.type) {
684 case BRW_REGISTER_TYPE_D:
685 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
686 break;
687 case BRW_REGISTER_TYPE_UD:
688 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
689 break;
690 default:
691 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
692 break;
693 }
694
695 switch (inst->exec_size) {
696 case 8:
697 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
698 break;
699 case 16:
700 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
701 break;
702 default:
703 unreachable("Invalid width for texture instruction");
704 }
705
706 if (devinfo->gen >= 5) {
707 switch (inst->opcode) {
708 case SHADER_OPCODE_TEX:
709 if (inst->shadow_compare) {
710 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
711 } else {
712 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
713 }
714 break;
715 case FS_OPCODE_TXB:
716 if (inst->shadow_compare) {
717 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
718 } else {
719 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
720 }
721 break;
722 case SHADER_OPCODE_TXL:
723 if (inst->shadow_compare) {
724 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
725 } else {
726 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
727 }
728 break;
729 case SHADER_OPCODE_TXS:
730 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
731 break;
732 case SHADER_OPCODE_TXD:
733 if (inst->shadow_compare) {
734 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
735 assert(devinfo->gen >= 8 || devinfo->is_haswell);
736 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
737 } else {
738 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
739 }
740 break;
741 case SHADER_OPCODE_TXF:
742 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
743 break;
744 case SHADER_OPCODE_TXF_CMS:
745 if (devinfo->gen >= 7)
746 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
747 else
748 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
749 break;
750 case SHADER_OPCODE_TXF_UMS:
751 assert(devinfo->gen >= 7);
752 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
753 break;
754 case SHADER_OPCODE_TXF_MCS:
755 assert(devinfo->gen >= 7);
756 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
757 break;
758 case SHADER_OPCODE_LOD:
759 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
760 break;
761 case SHADER_OPCODE_TG4:
762 if (inst->shadow_compare) {
763 assert(devinfo->gen >= 7);
764 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
765 } else {
766 assert(devinfo->gen >= 6);
767 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
768 }
769 break;
770 case SHADER_OPCODE_TG4_OFFSET:
771 assert(devinfo->gen >= 7);
772 if (inst->shadow_compare) {
773 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
774 } else {
775 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
776 }
777 break;
778 case SHADER_OPCODE_SAMPLEINFO:
779 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
780 break;
781 default:
782 unreachable("not reached");
783 }
784 } else {
785 switch (inst->opcode) {
786 case SHADER_OPCODE_TEX:
787 /* Note that G45 and older determines shadow compare and dispatch width
788 * from message length for most messages.
789 */
790 if (inst->exec_size == 8) {
791 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
792 if (inst->shadow_compare) {
793 assert(inst->mlen == 6);
794 } else {
795 assert(inst->mlen <= 4);
796 }
797 } else {
798 if (inst->shadow_compare) {
799 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
800 assert(inst->mlen == 9);
801 } else {
802 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
803 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
804 }
805 }
806 break;
807 case FS_OPCODE_TXB:
808 if (inst->shadow_compare) {
809 assert(inst->exec_size == 8);
810 assert(inst->mlen == 6);
811 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
812 } else {
813 assert(inst->mlen == 9);
814 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
815 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
816 }
817 break;
818 case SHADER_OPCODE_TXL:
819 if (inst->shadow_compare) {
820 assert(inst->exec_size == 8);
821 assert(inst->mlen == 6);
822 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
823 } else {
824 assert(inst->mlen == 9);
825 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
826 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
827 }
828 break;
829 case SHADER_OPCODE_TXD:
830 /* There is no sample_d_c message; comparisons are done manually */
831 assert(inst->exec_size == 8);
832 assert(inst->mlen == 7 || inst->mlen == 10);
833 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
834 break;
835 case SHADER_OPCODE_TXF:
836 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
837 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
838 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
839 break;
840 case SHADER_OPCODE_TXS:
841 assert(inst->mlen == 3);
842 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
843 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
844 break;
845 default:
846 unreachable("not reached");
847 }
848 }
849 assert(msg_type != -1);
850
851 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
852 rlen = 8;
853 dst = vec16(dst);
854 }
855
856 if (is_combined_send) {
857 assert(devinfo->gen >= 9 || devinfo->is_cherryview);
858 rlen = 0;
859 }
860
861 assert(devinfo->gen < 7 || inst->header_size == 0 ||
862 src.file == BRW_GENERAL_REGISTER_FILE);
863
864 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
865
866 /* Load the message header if present. If there's a texture offset,
867 * we need to set it up explicitly and load the offset bitfield.
868 * Otherwise, we can use an implied move from g0 to the first message reg.
869 */
870 if (inst->header_size != 0) {
871 if (devinfo->gen < 6 && !inst->offset) {
872 /* Set up an implied move from g0 to the MRF. */
873 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
874 } else {
875 struct brw_reg header_reg;
876
877 if (devinfo->gen >= 7) {
878 header_reg = src;
879 } else {
880 assert(inst->base_mrf != -1);
881 header_reg = brw_message_reg(inst->base_mrf);
882 }
883
884 brw_push_insn_state(p);
885 brw_set_default_exec_size(p, BRW_EXECUTE_8);
886 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
887 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
888 /* Explicitly set up the message header by copying g0 to the MRF. */
889 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
890
891 if (inst->offset) {
892 /* Set the offset bits in DWord 2. */
893 brw_MOV(p, get_element_ud(header_reg, 2),
894 brw_imm_ud(inst->offset));
895 }
896
897 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
898 brw_pop_insn_state(p);
899 }
900 }
901
902 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
903 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
904 ? prog_data->binding_table.gather_texture_start
905 : prog_data->binding_table.texture_start;
906
907 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
908 uint32_t sampler = sampler_index.dw1.ud;
909
910 brw_SAMPLE(p,
911 retype(dst, BRW_REGISTER_TYPE_UW),
912 inst->base_mrf,
913 src,
914 sampler + base_binding_table_index,
915 sampler % 16,
916 msg_type,
917 rlen,
918 inst->mlen,
919 inst->header_size != 0,
920 simd_mode,
921 return_format);
922
923 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
924 } else {
925 /* Non-const sampler index */
926
927 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
928 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
929
930 brw_push_insn_state(p);
931 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
932 brw_set_default_access_mode(p, BRW_ALIGN_1);
933
934 /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
935 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
936 if (base_binding_table_index)
937 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
938 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
939
940 brw_pop_insn_state(p);
941
942 /* dst = send(offset, a0.0 | <descriptor>) */
943 brw_inst *insn = brw_send_indirect_message(
944 p, BRW_SFID_SAMPLER, dst, src, addr);
945 brw_set_sampler_message(p, insn,
946 0 /* surface */,
947 0 /* sampler */,
948 msg_type,
949 rlen,
950 inst->mlen /* mlen */,
951 inst->header_size != 0 /* header */,
952 simd_mode,
953 return_format);
954
955 /* visitor knows more than we do about the surface limit required,
956 * so has already done marking.
957 */
958 }
959
960 if (is_combined_send) {
961 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
962 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
963 }
964 }
965
966
967 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
968 * looking like:
969 *
970 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
971 *
972 * Ideally, we want to produce:
973 *
974 * DDX DDY
975 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
976 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
977 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
978 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
979 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
980 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
981 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
982 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
983 *
984 * and add another set of two more subspans if in 16-pixel dispatch mode.
985 *
986 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
987 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
988 * pair. But the ideal approximation may impose a huge performance cost on
989 * sample_d. On at least Haswell, sample_d instruction does some
990 * optimizations if the same LOD is used for all pixels in the subspan.
991 *
992 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
993 * appropriate swizzling.
994 */
995 void
996 fs_generator::generate_ddx(enum opcode opcode,
997 struct brw_reg dst, struct brw_reg src)
998 {
999 unsigned vstride, width;
1000
1001 if (opcode == FS_OPCODE_DDX_FINE) {
1002 /* produce accurate derivatives */
1003 vstride = BRW_VERTICAL_STRIDE_2;
1004 width = BRW_WIDTH_2;
1005 } else {
1006 /* replicate the derivative at the top-left pixel to other pixels */
1007 vstride = BRW_VERTICAL_STRIDE_4;
1008 width = BRW_WIDTH_4;
1009 }
1010
1011 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
1012 src.negate, src.abs,
1013 BRW_REGISTER_TYPE_F,
1014 vstride,
1015 width,
1016 BRW_HORIZONTAL_STRIDE_0,
1017 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1018 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1019 src.negate, src.abs,
1020 BRW_REGISTER_TYPE_F,
1021 vstride,
1022 width,
1023 BRW_HORIZONTAL_STRIDE_0,
1024 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1025 brw_ADD(p, dst, src0, negate(src1));
1026 }
1027
1028 /* The negate_value boolean is used to negate the derivative computation for
1029 * FBOs, since they place the origin at the upper left instead of the lower
1030 * left.
1031 */
1032 void
1033 fs_generator::generate_ddy(enum opcode opcode,
1034 struct brw_reg dst, struct brw_reg src,
1035 bool negate_value)
1036 {
1037 if (opcode == FS_OPCODE_DDY_FINE) {
1038 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1039 * Region Restrictions):
1040 *
1041 * In Align16 access mode, SIMD16 is not allowed for DW operations
1042 * and SIMD8 is not allowed for DF operations.
1043 *
1044 * In this context, "DW operations" means "operations acting on 32-bit
1045 * values", so it includes operations on floats.
1046 *
1047 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1048 * (Instruction Compression -> Rules and Restrictions):
1049 *
1050 * A compressed instruction must be in Align1 access mode. Align16
1051 * mode instructions cannot be compressed.
1052 *
1053 * Similar text exists in the g45 PRM.
1054 *
1055 * On these platforms, if we're building a SIMD16 shader, we need to
1056 * manually unroll to a pair of SIMD8 instructions.
1057 */
1058 bool unroll_to_simd8 =
1059 (dispatch_width == 16 &&
1060 (devinfo->gen == 4 || (devinfo->gen == 7 && !devinfo->is_haswell)));
1061
1062 /* produce accurate derivatives */
1063 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1064 src.negate, src.abs,
1065 BRW_REGISTER_TYPE_F,
1066 BRW_VERTICAL_STRIDE_4,
1067 BRW_WIDTH_4,
1068 BRW_HORIZONTAL_STRIDE_1,
1069 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
1070 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1071 src.negate, src.abs,
1072 BRW_REGISTER_TYPE_F,
1073 BRW_VERTICAL_STRIDE_4,
1074 BRW_WIDTH_4,
1075 BRW_HORIZONTAL_STRIDE_1,
1076 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
1077 brw_push_insn_state(p);
1078 brw_set_default_access_mode(p, BRW_ALIGN_16);
1079 if (unroll_to_simd8) {
1080 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1081 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1082 if (negate_value) {
1083 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
1084 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1085 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
1086 } else {
1087 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
1088 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1089 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
1090 }
1091 } else {
1092 if (negate_value)
1093 brw_ADD(p, dst, src1, negate(src0));
1094 else
1095 brw_ADD(p, dst, src0, negate(src1));
1096 }
1097 brw_pop_insn_state(p);
1098 } else {
1099 /* replicate the derivative at the top-left pixel to other pixels */
1100 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1101 src.negate, src.abs,
1102 BRW_REGISTER_TYPE_F,
1103 BRW_VERTICAL_STRIDE_4,
1104 BRW_WIDTH_4,
1105 BRW_HORIZONTAL_STRIDE_0,
1106 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1107 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1108 src.negate, src.abs,
1109 BRW_REGISTER_TYPE_F,
1110 BRW_VERTICAL_STRIDE_4,
1111 BRW_WIDTH_4,
1112 BRW_HORIZONTAL_STRIDE_0,
1113 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1114 if (negate_value)
1115 brw_ADD(p, dst, src1, negate(src0));
1116 else
1117 brw_ADD(p, dst, src0, negate(src1));
1118 }
1119 }
1120
1121 void
1122 fs_generator::generate_discard_jump(fs_inst *inst)
1123 {
1124 assert(devinfo->gen >= 6);
1125
1126 /* This HALT will be patched up at FB write time to point UIP at the end of
1127 * the program, and at brw_uip_jip() JIP will be set to the end of the
1128 * current block (or the program).
1129 */
1130 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1131
1132 brw_push_insn_state(p);
1133 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1134 gen6_HALT(p);
1135 brw_pop_insn_state(p);
1136 }
1137
1138 void
1139 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1140 {
1141 assert(inst->mlen != 0);
1142
1143 brw_MOV(p,
1144 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1145 retype(src, BRW_REGISTER_TYPE_UD));
1146 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1147 inst->exec_size / 8, inst->offset);
1148 }
1149
1150 void
1151 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1152 {
1153 assert(inst->mlen != 0);
1154
1155 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1156 inst->exec_size / 8, inst->offset);
1157 }
1158
1159 void
1160 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1161 {
1162 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1163 }
1164
1165 void
1166 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1167 struct brw_reg dst,
1168 struct brw_reg index,
1169 struct brw_reg offset)
1170 {
1171 assert(inst->mlen != 0);
1172
1173 assert(index.file == BRW_IMMEDIATE_VALUE &&
1174 index.type == BRW_REGISTER_TYPE_UD);
1175 uint32_t surf_index = index.dw1.ud;
1176
1177 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1178 offset.type == BRW_REGISTER_TYPE_UD);
1179 uint32_t read_offset = offset.dw1.ud;
1180
1181 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1182 read_offset, surf_index);
1183
1184 brw_mark_surface_used(prog_data, surf_index);
1185 }
1186
1187 void
1188 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1189 struct brw_reg dst,
1190 struct brw_reg index,
1191 struct brw_reg offset)
1192 {
1193 assert(index.type == BRW_REGISTER_TYPE_UD);
1194
1195 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1196 /* Reference just the dword we need, to avoid angering validate_reg(). */
1197 offset = brw_vec1_grf(offset.nr, 0);
1198
1199 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1200 * the destination loaded consecutively from the same offset (which appears
1201 * in the first component, and the rest are ignored).
1202 */
1203 dst.width = BRW_WIDTH_4;
1204
1205 struct brw_reg src = offset;
1206 bool header_present = false;
1207
1208 if (devinfo->gen >= 9) {
1209 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1210 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1211 header_present = true;
1212
1213 brw_push_insn_state(p);
1214 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1215 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1216 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1217 brw_set_default_access_mode(p, BRW_ALIGN_1);
1218
1219 brw_MOV(p, get_element_ud(src, 2),
1220 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1221 brw_pop_insn_state(p);
1222 }
1223
1224 if (index.file == BRW_IMMEDIATE_VALUE) {
1225
1226 uint32_t surf_index = index.dw1.ud;
1227
1228 brw_push_insn_state(p);
1229 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1230 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1231 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1232 brw_pop_insn_state(p);
1233
1234 brw_set_dest(p, send, dst);
1235 brw_set_src0(p, send, src);
1236 brw_set_sampler_message(p, send,
1237 surf_index,
1238 0, /* LD message ignores sampler unit */
1239 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1240 1, /* rlen */
1241 inst->mlen,
1242 header_present,
1243 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1244 0);
1245
1246 brw_mark_surface_used(prog_data, surf_index);
1247
1248 } else {
1249
1250 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1251
1252 brw_push_insn_state(p);
1253 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1254 brw_set_default_access_mode(p, BRW_ALIGN_1);
1255
1256 /* a0.0 = surf_index & 0xff */
1257 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1258 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1259 brw_set_dest(p, insn_and, addr);
1260 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1261 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1262
1263 /* dst = send(payload, a0.0 | <descriptor>) */
1264 brw_inst *insn = brw_send_indirect_message(
1265 p, BRW_SFID_SAMPLER, dst, src, addr);
1266 brw_set_sampler_message(p, insn,
1267 0,
1268 0, /* LD message ignores sampler unit */
1269 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1270 1, /* rlen */
1271 inst->mlen,
1272 header_present,
1273 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1274 0);
1275
1276 brw_pop_insn_state(p);
1277
1278 /* visitor knows more than we do about the surface limit required,
1279 * so has already done marking.
1280 */
1281
1282 }
1283 }
1284
1285 void
1286 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1287 struct brw_reg dst,
1288 struct brw_reg index,
1289 struct brw_reg offset)
1290 {
1291 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1292 assert(inst->header_size != 0);
1293 assert(inst->mlen);
1294
1295 assert(index.file == BRW_IMMEDIATE_VALUE &&
1296 index.type == BRW_REGISTER_TYPE_UD);
1297 uint32_t surf_index = index.dw1.ud;
1298
1299 uint32_t simd_mode, rlen, msg_type;
1300 if (dispatch_width == 16) {
1301 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1302 rlen = 8;
1303 } else {
1304 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1305 rlen = 4;
1306 }
1307
1308 if (devinfo->gen >= 5)
1309 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1310 else {
1311 /* We always use the SIMD16 message so that we only have to load U, and
1312 * not V or R.
1313 */
1314 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1315 assert(inst->mlen == 3);
1316 assert(inst->regs_written == 8);
1317 rlen = 8;
1318 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1319 }
1320
1321 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1322 BRW_REGISTER_TYPE_D);
1323 brw_MOV(p, offset_mrf, offset);
1324
1325 struct brw_reg header = brw_vec8_grf(0, 0);
1326 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1327
1328 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1329 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1330 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1331 brw_set_src0(p, send, header);
1332 if (devinfo->gen < 6)
1333 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1334
1335 /* Our surface is set up as floats, regardless of what actual data is
1336 * stored in it.
1337 */
1338 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1339 brw_set_sampler_message(p, send,
1340 surf_index,
1341 0, /* sampler (unused) */
1342 msg_type,
1343 rlen,
1344 inst->mlen,
1345 inst->header_size != 0,
1346 simd_mode,
1347 return_format);
1348
1349 brw_mark_surface_used(prog_data, surf_index);
1350 }
1351
1352 void
1353 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1354 struct brw_reg dst,
1355 struct brw_reg index,
1356 struct brw_reg offset)
1357 {
1358 assert(devinfo->gen >= 7);
1359 /* Varying-offset pull constant loads are treated as a normal expression on
1360 * gen7, so the fact that it's a send message is hidden at the IR level.
1361 */
1362 assert(inst->header_size == 0);
1363 assert(!inst->mlen);
1364 assert(index.type == BRW_REGISTER_TYPE_UD);
1365
1366 uint32_t simd_mode, rlen, mlen;
1367 if (dispatch_width == 16) {
1368 mlen = 2;
1369 rlen = 8;
1370 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1371 } else {
1372 mlen = 1;
1373 rlen = 4;
1374 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1375 }
1376
1377 if (index.file == BRW_IMMEDIATE_VALUE) {
1378
1379 uint32_t surf_index = index.dw1.ud;
1380
1381 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1382 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1383 brw_set_src0(p, send, offset);
1384 brw_set_sampler_message(p, send,
1385 surf_index,
1386 0, /* LD message ignores sampler unit */
1387 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1388 rlen,
1389 mlen,
1390 false, /* no header */
1391 simd_mode,
1392 0);
1393
1394 brw_mark_surface_used(prog_data, surf_index);
1395
1396 } else {
1397
1398 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1399
1400 brw_push_insn_state(p);
1401 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1402 brw_set_default_access_mode(p, BRW_ALIGN_1);
1403
1404 /* a0.0 = surf_index & 0xff */
1405 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1406 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1407 brw_set_dest(p, insn_and, addr);
1408 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1409 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1410
1411 brw_pop_insn_state(p);
1412
1413 /* dst = send(offset, a0.0 | <descriptor>) */
1414 brw_inst *insn = brw_send_indirect_message(
1415 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1416 offset, addr);
1417 brw_set_sampler_message(p, insn,
1418 0 /* surface */,
1419 0 /* sampler */,
1420 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1421 rlen /* rlen */,
1422 mlen /* mlen */,
1423 false /* header */,
1424 simd_mode,
1425 0);
1426
1427 /* visitor knows more than we do about the surface limit required,
1428 * so has already done marking.
1429 */
1430 }
1431 }
1432
1433 /**
1434 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1435 * into the flags register (f0.0).
1436 *
1437 * Used only on Gen6 and above.
1438 */
1439 void
1440 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1441 {
1442 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1443 struct brw_reg dispatch_mask;
1444
1445 if (devinfo->gen >= 6)
1446 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1447 else
1448 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1449
1450 brw_push_insn_state(p);
1451 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1452 brw_MOV(p, flags, dispatch_mask);
1453 brw_pop_insn_state(p);
1454 }
1455
1456 void
1457 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1458 struct brw_reg dst,
1459 struct brw_reg src,
1460 struct brw_reg msg_data,
1461 unsigned msg_type)
1462 {
1463 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1464
1465 brw_pixel_interpolator_query(p,
1466 retype(dst, BRW_REGISTER_TYPE_UW),
1467 src,
1468 inst->pi_noperspective,
1469 msg_type,
1470 msg_data,
1471 inst->mlen,
1472 inst->regs_written);
1473 }
1474
1475
1476 /**
1477 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1478 * sampler LD messages.
1479 *
1480 * We don't want to bake it into the send message's code generation because
1481 * that means we don't get a chance to schedule the instructions.
1482 */
1483 void
1484 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1485 struct brw_reg dst,
1486 struct brw_reg value)
1487 {
1488 assert(value.file == BRW_IMMEDIATE_VALUE);
1489
1490 brw_push_insn_state(p);
1491 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1492 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1493 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1494 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1495 brw_pop_insn_state(p);
1496 }
1497
1498 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1499 * the ADD instruction.
1500 */
1501 void
1502 fs_generator::generate_set_sample_id(fs_inst *inst,
1503 struct brw_reg dst,
1504 struct brw_reg src0,
1505 struct brw_reg src1)
1506 {
1507 assert(dst.type == BRW_REGISTER_TYPE_D ||
1508 dst.type == BRW_REGISTER_TYPE_UD);
1509 assert(src0.type == BRW_REGISTER_TYPE_D ||
1510 src0.type == BRW_REGISTER_TYPE_UD);
1511
1512 struct brw_reg reg = stride(src1, 1, 4, 0);
1513 if (devinfo->gen >= 8 || dispatch_width == 8) {
1514 brw_ADD(p, dst, src0, reg);
1515 } else if (dispatch_width == 16) {
1516 brw_push_insn_state(p);
1517 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1518 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1519 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1520 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1521 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1522 brw_pop_insn_state(p);
1523 }
1524 }
1525
1526 void
1527 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1528 struct brw_reg dst,
1529 struct brw_reg x,
1530 struct brw_reg y)
1531 {
1532 assert(devinfo->gen >= 7);
1533 assert(dst.type == BRW_REGISTER_TYPE_UD);
1534 assert(x.type == BRW_REGISTER_TYPE_F);
1535 assert(y.type == BRW_REGISTER_TYPE_F);
1536
1537 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1538 *
1539 * Because this instruction does not have a 16-bit floating-point type,
1540 * the destination data type must be Word (W).
1541 *
1542 * The destination must be DWord-aligned and specify a horizontal stride
1543 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1544 * each destination channel and the upper word is not modified.
1545 */
1546 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1547
1548 /* Give each 32-bit channel of dst the form below, where "." means
1549 * unchanged.
1550 * 0x....hhhh
1551 */
1552 brw_F32TO16(p, dst_w, y);
1553
1554 /* Now the form:
1555 * 0xhhhh0000
1556 */
1557 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1558
1559 /* And, finally the form of packHalf2x16's output:
1560 * 0xhhhhllll
1561 */
1562 brw_F32TO16(p, dst_w, x);
1563 }
1564
1565 void
1566 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1567 struct brw_reg dst,
1568 struct brw_reg src)
1569 {
1570 assert(devinfo->gen >= 7);
1571 assert(dst.type == BRW_REGISTER_TYPE_F);
1572 assert(src.type == BRW_REGISTER_TYPE_UD);
1573
1574 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1575 *
1576 * Because this instruction does not have a 16-bit floating-point type,
1577 * the source data type must be Word (W). The destination type must be
1578 * F (Float).
1579 */
1580 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1581
1582 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1583 * For the Y case, we wish to access only the upper word; therefore
1584 * a 16-bit subregister offset is needed.
1585 */
1586 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1587 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1588 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1589 src_w.subnr += 2;
1590
1591 brw_F16TO32(p, dst, src_w);
1592 }
1593
1594 void
1595 fs_generator::generate_shader_time_add(fs_inst *inst,
1596 struct brw_reg payload,
1597 struct brw_reg offset,
1598 struct brw_reg value)
1599 {
1600 assert(devinfo->gen >= 7);
1601 brw_push_insn_state(p);
1602 brw_set_default_mask_control(p, true);
1603
1604 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1605 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1606 offset.type);
1607 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1608 value.type);
1609
1610 assert(offset.file == BRW_IMMEDIATE_VALUE);
1611 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1612 value.width = BRW_WIDTH_1;
1613 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1614 value.vstride = BRW_VERTICAL_STRIDE_0;
1615 } else {
1616 assert(value.file == BRW_IMMEDIATE_VALUE);
1617 }
1618
1619 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1620 * case, and we don't really care about squeezing every bit of performance
1621 * out of this path, so we just emit the MOVs from here.
1622 */
1623 brw_MOV(p, payload_offset, offset);
1624 brw_MOV(p, payload_value, value);
1625 brw_shader_time_add(p, payload,
1626 prog_data->binding_table.shader_time_start);
1627 brw_pop_insn_state(p);
1628
1629 brw_mark_surface_used(prog_data,
1630 prog_data->binding_table.shader_time_start);
1631 }
1632
1633 void
1634 fs_generator::enable_debug(const char *shader_name)
1635 {
1636 debug_flag = true;
1637 this->shader_name = shader_name;
1638 }
1639
1640 int
1641 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1642 {
1643 /* align to 64 byte boundary. */
1644 while (p->next_insn_offset % 64)
1645 brw_NOP(p);
1646
1647 this->dispatch_width = dispatch_width;
1648 if (dispatch_width == 16)
1649 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1650
1651 int start_offset = p->next_insn_offset;
1652 int spill_count = 0, fill_count = 0;
1653 int loop_count = 0;
1654
1655 struct annotation_info annotation;
1656 memset(&annotation, 0, sizeof(annotation));
1657
1658 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1659 struct brw_reg src[3], dst;
1660 unsigned int last_insn_offset = p->next_insn_offset;
1661 bool multiple_instructions_emitted = false;
1662
1663 if (unlikely(debug_flag))
1664 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1665
1666 for (unsigned int i = 0; i < inst->sources; i++) {
1667 src[i] = brw_reg_from_fs_reg(inst, &inst->src[i], devinfo->gen);
1668
1669 /* The accumulator result appears to get used for the
1670 * conditional modifier generation. When negating a UD
1671 * value, there is a 33rd bit generated for the sign in the
1672 * accumulator value, so now you can't check, for example,
1673 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1674 */
1675 assert(!inst->conditional_mod ||
1676 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1677 !inst->src[i].negate);
1678 }
1679 dst = brw_reg_from_fs_reg(inst, &inst->dst, devinfo->gen);
1680
1681 brw_set_default_predicate_control(p, inst->predicate);
1682 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1683 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1684 brw_set_default_saturate(p, inst->saturate);
1685 brw_set_default_mask_control(p, inst->force_writemask_all);
1686 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1687 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1688
1689 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1690 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1691
1692 switch (inst->exec_size) {
1693 case 1:
1694 case 2:
1695 case 4:
1696 assert(inst->force_writemask_all);
1697 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1698 break;
1699 case 8:
1700 if (inst->force_sechalf) {
1701 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1702 } else {
1703 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1704 }
1705 break;
1706 case 16:
1707 case 32:
1708 /* If the instruction writes to more than one register, it needs to
1709 * be a "compressed" instruction on Gen <= 5.
1710 */
1711 if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
1712 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1713 else
1714 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1715 break;
1716 default:
1717 unreachable("Invalid instruction width");
1718 }
1719
1720 switch (inst->opcode) {
1721 case BRW_OPCODE_MOV:
1722 brw_MOV(p, dst, src[0]);
1723 break;
1724 case BRW_OPCODE_ADD:
1725 brw_ADD(p, dst, src[0], src[1]);
1726 break;
1727 case BRW_OPCODE_MUL:
1728 brw_MUL(p, dst, src[0], src[1]);
1729 break;
1730 case BRW_OPCODE_AVG:
1731 brw_AVG(p, dst, src[0], src[1]);
1732 break;
1733 case BRW_OPCODE_MACH:
1734 brw_MACH(p, dst, src[0], src[1]);
1735 break;
1736
1737 case BRW_OPCODE_LINE:
1738 brw_LINE(p, dst, src[0], src[1]);
1739 break;
1740
1741 case BRW_OPCODE_MAD:
1742 assert(devinfo->gen >= 6);
1743 brw_set_default_access_mode(p, BRW_ALIGN_16);
1744 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1745 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1746 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1747 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1748 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1749 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1750 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1751
1752 if (inst->conditional_mod) {
1753 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1754 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1755 multiple_instructions_emitted = true;
1756 }
1757 } else {
1758 brw_MAD(p, dst, src[0], src[1], src[2]);
1759 }
1760 brw_set_default_access_mode(p, BRW_ALIGN_1);
1761 break;
1762
1763 case BRW_OPCODE_LRP:
1764 assert(devinfo->gen >= 6);
1765 brw_set_default_access_mode(p, BRW_ALIGN_16);
1766 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1767 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1768 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1769 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1770 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1771 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1772 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1773
1774 if (inst->conditional_mod) {
1775 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1776 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1777 multiple_instructions_emitted = true;
1778 }
1779 } else {
1780 brw_LRP(p, dst, src[0], src[1], src[2]);
1781 }
1782 brw_set_default_access_mode(p, BRW_ALIGN_1);
1783 break;
1784
1785 case BRW_OPCODE_FRC:
1786 brw_FRC(p, dst, src[0]);
1787 break;
1788 case BRW_OPCODE_RNDD:
1789 brw_RNDD(p, dst, src[0]);
1790 break;
1791 case BRW_OPCODE_RNDE:
1792 brw_RNDE(p, dst, src[0]);
1793 break;
1794 case BRW_OPCODE_RNDZ:
1795 brw_RNDZ(p, dst, src[0]);
1796 break;
1797
1798 case BRW_OPCODE_AND:
1799 brw_AND(p, dst, src[0], src[1]);
1800 break;
1801 case BRW_OPCODE_OR:
1802 brw_OR(p, dst, src[0], src[1]);
1803 break;
1804 case BRW_OPCODE_XOR:
1805 brw_XOR(p, dst, src[0], src[1]);
1806 break;
1807 case BRW_OPCODE_NOT:
1808 brw_NOT(p, dst, src[0]);
1809 break;
1810 case BRW_OPCODE_ASR:
1811 brw_ASR(p, dst, src[0], src[1]);
1812 break;
1813 case BRW_OPCODE_SHR:
1814 brw_SHR(p, dst, src[0], src[1]);
1815 break;
1816 case BRW_OPCODE_SHL:
1817 brw_SHL(p, dst, src[0], src[1]);
1818 break;
1819 case BRW_OPCODE_F32TO16:
1820 assert(devinfo->gen >= 7);
1821 brw_F32TO16(p, dst, src[0]);
1822 break;
1823 case BRW_OPCODE_F16TO32:
1824 assert(devinfo->gen >= 7);
1825 brw_F16TO32(p, dst, src[0]);
1826 break;
1827 case BRW_OPCODE_CMP:
1828 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1829 * that when the destination is a GRF that the dependency-clear bit on
1830 * the flag register is cleared early.
1831 *
1832 * Suggested workarounds are to disable coissuing CMP instructions
1833 * or to split CMP(16) instructions into two CMP(8) instructions.
1834 *
1835 * We choose to split into CMP(8) instructions since disabling
1836 * coissuing would affect CMP instructions not otherwise affected by
1837 * the errata.
1838 */
1839 if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) {
1840 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1841 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1842 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1843 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1844 firsthalf(src[0]), firsthalf(src[1]));
1845 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1846 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1847 sechalf(src[0]), sechalf(src[1]));
1848 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1849
1850 multiple_instructions_emitted = true;
1851 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1852 /* For unknown reasons, the aforementioned workaround is not
1853 * sufficient. Overriding the type when the destination is the
1854 * null register is necessary but not sufficient by itself.
1855 */
1856 assert(dst.nr == BRW_ARF_NULL);
1857 dst.type = BRW_REGISTER_TYPE_D;
1858 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1859 } else {
1860 unreachable("not reached");
1861 }
1862 } else {
1863 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1864 }
1865 break;
1866 case BRW_OPCODE_SEL:
1867 brw_SEL(p, dst, src[0], src[1]);
1868 break;
1869 case BRW_OPCODE_BFREV:
1870 assert(devinfo->gen >= 7);
1871 /* BFREV only supports UD type for src and dst. */
1872 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1873 retype(src[0], BRW_REGISTER_TYPE_UD));
1874 break;
1875 case BRW_OPCODE_FBH:
1876 assert(devinfo->gen >= 7);
1877 /* FBH only supports UD type for dst. */
1878 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1879 break;
1880 case BRW_OPCODE_FBL:
1881 assert(devinfo->gen >= 7);
1882 /* FBL only supports UD type for dst. */
1883 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1884 break;
1885 case BRW_OPCODE_CBIT:
1886 assert(devinfo->gen >= 7);
1887 /* CBIT only supports UD type for dst. */
1888 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1889 break;
1890 case BRW_OPCODE_ADDC:
1891 assert(devinfo->gen >= 7);
1892 brw_ADDC(p, dst, src[0], src[1]);
1893 break;
1894 case BRW_OPCODE_SUBB:
1895 assert(devinfo->gen >= 7);
1896 brw_SUBB(p, dst, src[0], src[1]);
1897 break;
1898 case BRW_OPCODE_MAC:
1899 brw_MAC(p, dst, src[0], src[1]);
1900 break;
1901
1902 case BRW_OPCODE_BFE:
1903 assert(devinfo->gen >= 7);
1904 brw_set_default_access_mode(p, BRW_ALIGN_16);
1905 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1906 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1907 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1908 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1909 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1910 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1911 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1912 } else {
1913 brw_BFE(p, dst, src[0], src[1], src[2]);
1914 }
1915 brw_set_default_access_mode(p, BRW_ALIGN_1);
1916 break;
1917
1918 case BRW_OPCODE_BFI1:
1919 assert(devinfo->gen >= 7);
1920 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1921 * should
1922 *
1923 * "Force BFI instructions to be executed always in SIMD8."
1924 */
1925 if (dispatch_width == 16 && devinfo->is_haswell) {
1926 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1927 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1928 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1929 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1930 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1931 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1932 } else {
1933 brw_BFI1(p, dst, src[0], src[1]);
1934 }
1935 break;
1936 case BRW_OPCODE_BFI2:
1937 assert(devinfo->gen >= 7);
1938 brw_set_default_access_mode(p, BRW_ALIGN_16);
1939 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1940 * should
1941 *
1942 * "Force BFI instructions to be executed always in SIMD8."
1943 *
1944 * Otherwise we would be able to emit compressed instructions like we
1945 * do for the other three-source instructions.
1946 */
1947 if (dispatch_width == 16 &&
1948 (devinfo->is_haswell || !devinfo->supports_simd16_3src)) {
1949 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1950 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1951 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1952 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1953 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1954 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1955 } else {
1956 brw_BFI2(p, dst, src[0], src[1], src[2]);
1957 }
1958 brw_set_default_access_mode(p, BRW_ALIGN_1);
1959 break;
1960
1961 case BRW_OPCODE_IF:
1962 if (inst->src[0].file != BAD_FILE) {
1963 /* The instruction has an embedded compare (only allowed on gen6) */
1964 assert(devinfo->gen == 6);
1965 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1966 } else {
1967 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1968 }
1969 break;
1970
1971 case BRW_OPCODE_ELSE:
1972 brw_ELSE(p);
1973 break;
1974 case BRW_OPCODE_ENDIF:
1975 brw_ENDIF(p);
1976 break;
1977
1978 case BRW_OPCODE_DO:
1979 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1980 break;
1981
1982 case BRW_OPCODE_BREAK:
1983 brw_BREAK(p);
1984 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1985 break;
1986 case BRW_OPCODE_CONTINUE:
1987 brw_CONT(p);
1988 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1989 break;
1990
1991 case BRW_OPCODE_WHILE:
1992 brw_WHILE(p);
1993 loop_count++;
1994 break;
1995
1996 case SHADER_OPCODE_RCP:
1997 case SHADER_OPCODE_RSQ:
1998 case SHADER_OPCODE_SQRT:
1999 case SHADER_OPCODE_EXP2:
2000 case SHADER_OPCODE_LOG2:
2001 case SHADER_OPCODE_SIN:
2002 case SHADER_OPCODE_COS:
2003 assert(devinfo->gen < 6 || inst->mlen == 0);
2004 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2005 if (devinfo->gen >= 7) {
2006 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
2007 brw_null_reg());
2008 } else if (devinfo->gen == 6) {
2009 generate_math_gen6(inst, dst, src[0], brw_null_reg());
2010 } else if (devinfo->gen == 5 || devinfo->is_g4x) {
2011 generate_math_g45(inst, dst, src[0]);
2012 } else {
2013 generate_math_gen4(inst, dst, src[0]);
2014 }
2015 break;
2016 case SHADER_OPCODE_INT_QUOTIENT:
2017 case SHADER_OPCODE_INT_REMAINDER:
2018 case SHADER_OPCODE_POW:
2019 assert(devinfo->gen < 6 || inst->mlen == 0);
2020 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2021 if (devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
2022 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
2023 } else if (devinfo->gen >= 6) {
2024 generate_math_gen6(inst, dst, src[0], src[1]);
2025 } else {
2026 generate_math_gen4(inst, dst, src[0]);
2027 }
2028 break;
2029 case FS_OPCODE_CINTERP:
2030 brw_MOV(p, dst, src[0]);
2031 break;
2032 case FS_OPCODE_LINTERP:
2033 generate_linterp(inst, dst, src);
2034 break;
2035 case FS_OPCODE_PIXEL_X:
2036 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2037 src[0].subnr = 0 * type_sz(src[0].type);
2038 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2039 break;
2040 case FS_OPCODE_PIXEL_Y:
2041 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2042 src[0].subnr = 4 * type_sz(src[0].type);
2043 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2044 break;
2045 case FS_OPCODE_GET_BUFFER_SIZE:
2046 generate_get_buffer_size(inst, dst, src[0], src[1]);
2047 break;
2048 case SHADER_OPCODE_TEX:
2049 case FS_OPCODE_TXB:
2050 case SHADER_OPCODE_TXD:
2051 case SHADER_OPCODE_TXF:
2052 case SHADER_OPCODE_TXF_CMS:
2053 case SHADER_OPCODE_TXF_UMS:
2054 case SHADER_OPCODE_TXF_MCS:
2055 case SHADER_OPCODE_TXL:
2056 case SHADER_OPCODE_TXS:
2057 case SHADER_OPCODE_LOD:
2058 case SHADER_OPCODE_TG4:
2059 case SHADER_OPCODE_TG4_OFFSET:
2060 case SHADER_OPCODE_SAMPLEINFO:
2061 generate_tex(inst, dst, src[0], src[1]);
2062 break;
2063 case FS_OPCODE_DDX_COARSE:
2064 case FS_OPCODE_DDX_FINE:
2065 generate_ddx(inst->opcode, dst, src[0]);
2066 break;
2067 case FS_OPCODE_DDY_COARSE:
2068 case FS_OPCODE_DDY_FINE:
2069 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2070 generate_ddy(inst->opcode, dst, src[0], src[1].dw1.ud);
2071 break;
2072
2073 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
2074 generate_scratch_write(inst, src[0]);
2075 spill_count++;
2076 break;
2077
2078 case SHADER_OPCODE_GEN4_SCRATCH_READ:
2079 generate_scratch_read(inst, dst);
2080 fill_count++;
2081 break;
2082
2083 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2084 generate_scratch_read_gen7(inst, dst);
2085 fill_count++;
2086 break;
2087
2088 case SHADER_OPCODE_URB_READ_SIMD8:
2089 generate_urb_read(inst, dst, src[0]);
2090 break;
2091
2092 case SHADER_OPCODE_URB_WRITE_SIMD8:
2093 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
2094 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
2095 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
2096 generate_urb_write(inst, src[0]);
2097 break;
2098
2099 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2100 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2101 break;
2102
2103 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2104 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2105 break;
2106
2107 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
2108 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
2109 break;
2110
2111 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2112 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2113 break;
2114
2115 case FS_OPCODE_REP_FB_WRITE:
2116 case FS_OPCODE_FB_WRITE:
2117 generate_fb_write(inst, src[0]);
2118 break;
2119
2120 case FS_OPCODE_BLORP_FB_WRITE:
2121 generate_blorp_fb_write(inst);
2122 break;
2123
2124 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2125 generate_mov_dispatch_to_flags(inst);
2126 break;
2127
2128 case FS_OPCODE_DISCARD_JUMP:
2129 generate_discard_jump(inst);
2130 break;
2131
2132 case SHADER_OPCODE_SHADER_TIME_ADD:
2133 generate_shader_time_add(inst, src[0], src[1], src[2]);
2134 break;
2135
2136 case SHADER_OPCODE_UNTYPED_ATOMIC:
2137 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2138 brw_untyped_atomic(p, dst, src[0], src[1], src[2].dw1.ud,
2139 inst->mlen, !inst->dst.is_null());
2140 break;
2141
2142 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2143 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2144 brw_untyped_surface_read(p, dst, src[0], src[1],
2145 inst->mlen, src[2].dw1.ud);
2146 break;
2147
2148 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2149 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2150 brw_untyped_surface_write(p, src[0], src[1],
2151 inst->mlen, src[2].dw1.ud);
2152 break;
2153
2154 case SHADER_OPCODE_TYPED_ATOMIC:
2155 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2156 brw_typed_atomic(p, dst, src[0], src[1],
2157 src[2].dw1.ud, inst->mlen, !inst->dst.is_null());
2158 break;
2159
2160 case SHADER_OPCODE_TYPED_SURFACE_READ:
2161 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2162 brw_typed_surface_read(p, dst, src[0], src[1],
2163 inst->mlen, src[2].dw1.ud);
2164 break;
2165
2166 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2167 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2168 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].dw1.ud);
2169 break;
2170
2171 case SHADER_OPCODE_MEMORY_FENCE:
2172 brw_memory_fence(p, dst);
2173 break;
2174
2175 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2176 generate_set_simd4x2_offset(inst, dst, src[0]);
2177 break;
2178
2179 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
2180 brw_find_live_channel(p, dst);
2181 break;
2182
2183 case SHADER_OPCODE_BROADCAST:
2184 brw_broadcast(p, dst, src[0], src[1]);
2185 break;
2186
2187 case FS_OPCODE_SET_SAMPLE_ID:
2188 generate_set_sample_id(inst, dst, src[0], src[1]);
2189 break;
2190
2191 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2192 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2193 break;
2194
2195 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2196 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2197 generate_unpack_half_2x16_split(inst, dst, src[0]);
2198 break;
2199
2200 case FS_OPCODE_PLACEHOLDER_HALT:
2201 /* This is the place where the final HALT needs to be inserted if
2202 * we've emitted any discards. If not, this will emit no code.
2203 */
2204 if (!patch_discard_jumps_to_fb_writes()) {
2205 if (unlikely(debug_flag)) {
2206 annotation.ann_count--;
2207 }
2208 }
2209 break;
2210
2211 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2212 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2213 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2214 break;
2215
2216 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2217 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2218 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2219 break;
2220
2221 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2222 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2223 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2224 break;
2225
2226 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2227 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2228 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2229 break;
2230
2231 case CS_OPCODE_CS_TERMINATE:
2232 generate_cs_terminate(inst, src[0]);
2233 break;
2234
2235 case SHADER_OPCODE_BARRIER:
2236 generate_barrier(inst, src[0]);
2237 break;
2238
2239 case FS_OPCODE_PACK_STENCIL_REF:
2240 generate_stencil_ref_packing(inst, dst, src[0]);
2241 break;
2242
2243 default:
2244 unreachable("Unsupported opcode");
2245
2246 case SHADER_OPCODE_LOAD_PAYLOAD:
2247 unreachable("Should be lowered by lower_load_payload()");
2248 }
2249
2250 if (multiple_instructions_emitted)
2251 continue;
2252
2253 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2254 assert(p->next_insn_offset == last_insn_offset + 16 ||
2255 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2256 "emitting more than 1 instruction");
2257
2258 brw_inst *last = &p->store[last_insn_offset / 16];
2259
2260 if (inst->conditional_mod)
2261 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2262 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2263 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2264 }
2265 }
2266
2267 brw_set_uip_jip(p);
2268 annotation_finalize(&annotation, p->next_insn_offset);
2269
2270 int before_size = p->next_insn_offset - start_offset;
2271 brw_compact_instructions(p, start_offset, annotation.ann_count,
2272 annotation.ann);
2273 int after_size = p->next_insn_offset - start_offset;
2274
2275 if (unlikely(debug_flag)) {
2276 fprintf(stderr, "Native code for %s\n"
2277 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2278 " bytes (%.0f%%)\n",
2279 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2280 spill_count, fill_count, promoted_constants, before_size, after_size,
2281 100.0f * (before_size - after_size) / before_size);
2282
2283 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2284 p->devinfo);
2285 ralloc_free(annotation.ann);
2286 }
2287
2288 compiler->shader_debug_log(log_data,
2289 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2290 "%d:%d spills:fills, Promoted %u constants, "
2291 "compacted %d to %d bytes.\n",
2292 stage_abbrev, dispatch_width, before_size / 16,
2293 loop_count, cfg->cycle_count, spill_count,
2294 fill_count, promoted_constants, before_size,
2295 after_size);
2296
2297 return start_offset;
2298 }
2299
2300 const unsigned *
2301 fs_generator::get_assembly(unsigned int *assembly_size)
2302 {
2303 return brw_get_program(p, assembly_size);
2304 }