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i965/fs: Allow an execution size of 32.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "main/macros.h"
31 #include "brw_context.h"
32 #include "brw_eu.h"
33 #include "brw_fs.h"
34 #include "brw_cfg.h"
35
36 static uint32_t brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case GRF:
40 return BRW_GENERAL_REGISTER_FILE;
41 case MRF:
42 return BRW_MESSAGE_REGISTER_FILE;
43 case IMM:
44 return BRW_IMMEDIATE_VALUE;
45 default:
46 unreachable("not reached");
47 }
48 }
49
50 static struct brw_reg
51 brw_reg_from_fs_reg(fs_reg *reg)
52 {
53 struct brw_reg brw_reg;
54
55 switch (reg->file) {
56 case GRF:
57 case MRF:
58 if (reg->stride == 0) {
59 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
60 } else if (reg->width < 8) {
61 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
62 brw_reg = stride(brw_reg, reg->width * reg->stride,
63 reg->width, reg->stride);
64 } else {
65 /* From the Haswell PRM:
66 *
67 * VertStride must be used to cross GRF register boundaries. This
68 * rule implies that elements within a 'Width' cannot cross GRF
69 * boundaries.
70 *
71 * So, for registers with width > 8, we have to use a width of 8
72 * and trust the compression state to sort out the exec size.
73 */
74 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
75 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
76 }
77
78 brw_reg = retype(brw_reg, reg->type);
79 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
80 break;
81 case IMM:
82 switch (reg->type) {
83 case BRW_REGISTER_TYPE_F:
84 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
85 break;
86 case BRW_REGISTER_TYPE_D:
87 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
88 break;
89 case BRW_REGISTER_TYPE_UD:
90 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
91 break;
92 case BRW_REGISTER_TYPE_W:
93 brw_reg = brw_imm_w(reg->fixed_hw_reg.dw1.d);
94 break;
95 case BRW_REGISTER_TYPE_UW:
96 brw_reg = brw_imm_uw(reg->fixed_hw_reg.dw1.ud);
97 break;
98 case BRW_REGISTER_TYPE_VF:
99 brw_reg = brw_imm_vf(reg->fixed_hw_reg.dw1.ud);
100 break;
101 default:
102 unreachable("not reached");
103 }
104 break;
105 case HW_REG:
106 assert(reg->type == reg->fixed_hw_reg.type);
107 brw_reg = reg->fixed_hw_reg;
108 break;
109 case BAD_FILE:
110 /* Probably unused. */
111 brw_reg = brw_null_reg();
112 break;
113 default:
114 unreachable("not reached");
115 }
116 if (reg->abs)
117 brw_reg = brw_abs(brw_reg);
118 if (reg->negate)
119 brw_reg = negate(brw_reg);
120
121 return brw_reg;
122 }
123
124 fs_generator::fs_generator(struct brw_context *brw,
125 void *mem_ctx,
126 const void *key,
127 struct brw_stage_prog_data *prog_data,
128 struct gl_program *prog,
129 unsigned promoted_constants,
130 bool runtime_check_aads_emit,
131 const char *stage_abbrev)
132
133 : brw(brw), key(key),
134 prog_data(prog_data),
135 prog(prog), promoted_constants(promoted_constants),
136 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
137 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
138 {
139 ctx = &brw->ctx;
140
141 p = rzalloc(mem_ctx, struct brw_compile);
142 brw_init_compile(brw, p, mem_ctx);
143 }
144
145 fs_generator::~fs_generator()
146 {
147 }
148
149 class ip_record : public exec_node {
150 public:
151 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
152
153 ip_record(int ip)
154 {
155 this->ip = ip;
156 }
157
158 int ip;
159 };
160
161 bool
162 fs_generator::patch_discard_jumps_to_fb_writes()
163 {
164 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
165 return false;
166
167 int scale = brw_jump_scale(brw);
168
169 /* There is a somewhat strange undocumented requirement of using
170 * HALT, according to the simulator. If some channel has HALTed to
171 * a particular UIP, then by the end of the program, every channel
172 * must have HALTed to that UIP. Furthermore, the tracking is a
173 * stack, so you can't do the final halt of a UIP after starting
174 * halting to a new UIP.
175 *
176 * Symptoms of not emitting this instruction on actual hardware
177 * included GPU hangs and sparkly rendering on the piglit discard
178 * tests.
179 */
180 brw_inst *last_halt = gen6_HALT(p);
181 brw_inst_set_uip(brw, last_halt, 1 * scale);
182 brw_inst_set_jip(brw, last_halt, 1 * scale);
183
184 int ip = p->nr_insn;
185
186 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
187 brw_inst *patch = &p->store[patch_ip->ip];
188
189 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
190 /* HALT takes a half-instruction distance from the pre-incremented IP. */
191 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
192 }
193
194 this->discard_halt_patches.make_empty();
195 return true;
196 }
197
198 void
199 fs_generator::fire_fb_write(fs_inst *inst,
200 struct brw_reg payload,
201 struct brw_reg implied_header,
202 GLuint nr)
203 {
204 uint32_t msg_control;
205
206 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
207
208 if (brw->gen < 6) {
209 brw_push_insn_state(p);
210 brw_set_default_exec_size(p, BRW_EXECUTE_8);
211 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
212 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
213 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
214 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
215 brw_pop_insn_state(p);
216 }
217
218 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
219 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
220 else if (prog_data->dual_src_blend) {
221 if (dispatch_width == 8 || !inst->eot)
222 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
223 else
224 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
225 } else if (dispatch_width == 16)
226 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
227 else
228 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
229
230 uint32_t surf_index =
231 prog_data->binding_table.render_target_start + inst->target;
232
233 bool last_render_target = inst->eot ||
234 (prog_data->dual_src_blend && dispatch_width == 16);
235
236
237 brw_fb_WRITE(p,
238 dispatch_width,
239 payload,
240 implied_header,
241 msg_control,
242 surf_index,
243 nr,
244 0,
245 inst->eot,
246 last_render_target,
247 inst->header_present);
248
249 brw_mark_surface_used(&prog_data->base, surf_index);
250 }
251
252 void
253 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
254 {
255 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
256 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
257 struct brw_reg implied_header;
258
259 if (brw->gen < 8 && !brw->is_haswell) {
260 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
261 }
262
263 if (inst->base_mrf >= 0)
264 payload = brw_message_reg(inst->base_mrf);
265
266 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
267 * move, here's g1.
268 */
269 if (inst->header_present) {
270 brw_push_insn_state(p);
271 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
272 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
273 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
274 brw_set_default_flag_reg(p, 0, 0);
275
276 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
277 * present.
278 */
279 if (prog_data->uses_kill) {
280 struct brw_reg pixel_mask;
281
282 if (brw->gen >= 6)
283 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
284 else
285 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
286
287 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
288 }
289
290 if (brw->gen >= 6) {
291 brw_push_insn_state(p);
292 brw_set_default_exec_size(p, BRW_EXECUTE_16);
293 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
294 brw_MOV(p,
295 retype(payload, BRW_REGISTER_TYPE_UD),
296 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
297 brw_pop_insn_state(p);
298
299 if (inst->target > 0 && key->replicate_alpha) {
300 /* Set "Source0 Alpha Present to RenderTarget" bit in message
301 * header.
302 */
303 brw_OR(p,
304 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
305 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
306 brw_imm_ud(0x1 << 11));
307 }
308
309 if (inst->target > 0) {
310 /* Set the render target index for choosing BLEND_STATE. */
311 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
312 BRW_REGISTER_TYPE_UD),
313 brw_imm_ud(inst->target));
314 }
315
316 implied_header = brw_null_reg();
317 } else {
318 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
319 }
320
321 brw_pop_insn_state(p);
322 } else {
323 implied_header = brw_null_reg();
324 }
325
326 if (!runtime_check_aads_emit) {
327 fire_fb_write(inst, payload, implied_header, inst->mlen);
328 } else {
329 /* This can only happen in gen < 6 */
330 assert(brw->gen < 6);
331
332 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
333
334 /* Check runtime bit to detect if we have to send AA data or not */
335 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
336 brw_AND(p,
337 v1_null_ud,
338 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
339 brw_imm_ud(1<<26));
340 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
341
342 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
343 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
344 {
345 /* Don't send AA data */
346 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
347 }
348 brw_land_fwd_jump(p, jmp);
349 fire_fb_write(inst, payload, implied_header, inst->mlen);
350 }
351 }
352
353 void
354 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
355 {
356 brw_inst *insn;
357
358 insn = brw_next_insn(p, BRW_OPCODE_SEND);
359
360 brw_set_dest(p, insn, brw_null_reg());
361 brw_set_src0(p, insn, payload);
362 brw_set_src1(p, insn, brw_imm_d(0));
363
364 brw_inst_set_sfid(brw, insn, BRW_SFID_URB);
365 brw_inst_set_urb_opcode(brw, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
366
367 brw_inst_set_mlen(brw, insn, inst->mlen);
368 brw_inst_set_rlen(brw, insn, 0);
369 brw_inst_set_eot(brw, insn, inst->eot);
370 brw_inst_set_header_present(brw, insn, true);
371 brw_inst_set_urb_global_offset(brw, insn, inst->offset);
372 }
373
374 void
375 fs_generator::generate_blorp_fb_write(fs_inst *inst)
376 {
377 brw_fb_WRITE(p,
378 16 /* dispatch_width */,
379 brw_message_reg(inst->base_mrf),
380 brw_reg_from_fs_reg(&inst->src[0]),
381 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
382 inst->target,
383 inst->mlen,
384 0,
385 true,
386 true,
387 inst->header_present);
388 }
389
390 /* Computes the integer pixel x,y values from the origin.
391 *
392 * This is the basis of gl_FragCoord computation, but is also used
393 * pre-gen6 for computing the deltas from v0 for computing
394 * interpolation.
395 */
396 void
397 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
398 {
399 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
400 struct brw_reg src;
401 struct brw_reg deltas;
402
403 if (is_x) {
404 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
405 deltas = brw_imm_v(0x10101010);
406 } else {
407 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
408 deltas = brw_imm_v(0x11001100);
409 }
410
411 if (dispatch_width == 16) {
412 dst = vec16(dst);
413 }
414
415 /* We do this SIMD8 or SIMD16, but since the destination is UW we
416 * don't do compression in the SIMD16 case.
417 */
418 brw_push_insn_state(p);
419 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
420 brw_ADD(p, dst, src, deltas);
421 brw_pop_insn_state(p);
422 }
423
424 void
425 fs_generator::generate_linterp(fs_inst *inst,
426 struct brw_reg dst, struct brw_reg *src)
427 {
428 struct brw_reg delta_x = src[0];
429 struct brw_reg delta_y = src[1];
430 struct brw_reg interp = src[2];
431
432 if (brw->has_pln &&
433 delta_y.nr == delta_x.nr + 1 &&
434 (brw->gen >= 7 || (delta_x.nr & 1) == 0)) {
435 brw_PLN(p, dst, interp, delta_x);
436 } else {
437 brw_LINE(p, brw_null_reg(), interp, delta_x);
438 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
439 }
440 }
441
442 void
443 fs_generator::generate_math_gen6(fs_inst *inst,
444 struct brw_reg dst,
445 struct brw_reg src0,
446 struct brw_reg src1)
447 {
448 int op = brw_math_function(inst->opcode);
449 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
450
451 if (dispatch_width == 8) {
452 gen6_math(p, dst, op, src0, src1);
453 } else if (dispatch_width == 16) {
454 brw_push_insn_state(p);
455 brw_set_default_exec_size(p, BRW_EXECUTE_8);
456 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
457 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
458 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
459 gen6_math(p, sechalf(dst), op, sechalf(src0),
460 binop ? sechalf(src1) : brw_null_reg());
461 brw_pop_insn_state(p);
462 }
463 }
464
465 void
466 fs_generator::generate_math_gen4(fs_inst *inst,
467 struct brw_reg dst,
468 struct brw_reg src)
469 {
470 int op = brw_math_function(inst->opcode);
471
472 assert(inst->mlen >= 1);
473
474 if (dispatch_width == 8) {
475 gen4_math(p, dst,
476 op,
477 inst->base_mrf, src,
478 BRW_MATH_PRECISION_FULL);
479 } else if (dispatch_width == 16) {
480 brw_set_default_exec_size(p, BRW_EXECUTE_8);
481 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
482 gen4_math(p, firsthalf(dst),
483 op,
484 inst->base_mrf, firsthalf(src),
485 BRW_MATH_PRECISION_FULL);
486 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
487 gen4_math(p, sechalf(dst),
488 op,
489 inst->base_mrf + 1, sechalf(src),
490 BRW_MATH_PRECISION_FULL);
491
492 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
493 }
494 }
495
496 void
497 fs_generator::generate_math_g45(fs_inst *inst,
498 struct brw_reg dst,
499 struct brw_reg src)
500 {
501 if (inst->opcode == SHADER_OPCODE_POW ||
502 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
503 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
504 generate_math_gen4(inst, dst, src);
505 return;
506 }
507
508 int op = brw_math_function(inst->opcode);
509
510 assert(inst->mlen >= 1);
511
512 gen4_math(p, dst,
513 op,
514 inst->base_mrf, src,
515 BRW_MATH_PRECISION_FULL);
516 }
517
518 void
519 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
520 struct brw_reg sampler_index)
521 {
522 int msg_type = -1;
523 int rlen = 4;
524 uint32_t simd_mode;
525 uint32_t return_format;
526 bool is_combined_send = inst->eot;
527
528 switch (dst.type) {
529 case BRW_REGISTER_TYPE_D:
530 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
531 break;
532 case BRW_REGISTER_TYPE_UD:
533 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
534 break;
535 default:
536 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
537 break;
538 }
539
540 switch (inst->exec_size) {
541 case 8:
542 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
543 break;
544 case 16:
545 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
546 break;
547 default:
548 unreachable("Invalid width for texture instruction");
549 }
550
551 if (brw->gen >= 5) {
552 switch (inst->opcode) {
553 case SHADER_OPCODE_TEX:
554 if (inst->shadow_compare) {
555 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
556 } else {
557 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
558 }
559 break;
560 case FS_OPCODE_TXB:
561 if (inst->shadow_compare) {
562 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
563 } else {
564 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
565 }
566 break;
567 case SHADER_OPCODE_TXL:
568 if (inst->shadow_compare) {
569 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
570 } else {
571 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
572 }
573 break;
574 case SHADER_OPCODE_TXS:
575 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
576 break;
577 case SHADER_OPCODE_TXD:
578 if (inst->shadow_compare) {
579 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
580 assert(brw->gen >= 8 || brw->is_haswell);
581 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
582 } else {
583 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
584 }
585 break;
586 case SHADER_OPCODE_TXF:
587 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
588 break;
589 case SHADER_OPCODE_TXF_CMS:
590 if (brw->gen >= 7)
591 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
592 else
593 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
594 break;
595 case SHADER_OPCODE_TXF_UMS:
596 assert(brw->gen >= 7);
597 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
598 break;
599 case SHADER_OPCODE_TXF_MCS:
600 assert(brw->gen >= 7);
601 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
602 break;
603 case SHADER_OPCODE_LOD:
604 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
605 break;
606 case SHADER_OPCODE_TG4:
607 if (inst->shadow_compare) {
608 assert(brw->gen >= 7);
609 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
610 } else {
611 assert(brw->gen >= 6);
612 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
613 }
614 break;
615 case SHADER_OPCODE_TG4_OFFSET:
616 assert(brw->gen >= 7);
617 if (inst->shadow_compare) {
618 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
619 } else {
620 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
621 }
622 break;
623 default:
624 unreachable("not reached");
625 }
626 } else {
627 switch (inst->opcode) {
628 case SHADER_OPCODE_TEX:
629 /* Note that G45 and older determines shadow compare and dispatch width
630 * from message length for most messages.
631 */
632 if (dispatch_width == 8) {
633 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
634 if (inst->shadow_compare) {
635 assert(inst->mlen == 6);
636 } else {
637 assert(inst->mlen <= 4);
638 }
639 } else {
640 if (inst->shadow_compare) {
641 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
642 assert(inst->mlen == 9);
643 } else {
644 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
645 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
646 }
647 }
648 break;
649 case FS_OPCODE_TXB:
650 if (inst->shadow_compare) {
651 assert(dispatch_width == 8);
652 assert(inst->mlen == 6);
653 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
654 } else {
655 assert(inst->mlen == 9);
656 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
657 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
658 }
659 break;
660 case SHADER_OPCODE_TXL:
661 if (inst->shadow_compare) {
662 assert(dispatch_width == 8);
663 assert(inst->mlen == 6);
664 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
665 } else {
666 assert(inst->mlen == 9);
667 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
668 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
669 }
670 break;
671 case SHADER_OPCODE_TXD:
672 /* There is no sample_d_c message; comparisons are done manually */
673 assert(dispatch_width == 8);
674 assert(inst->mlen == 7 || inst->mlen == 10);
675 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
676 break;
677 case SHADER_OPCODE_TXF:
678 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
679 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
680 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
681 break;
682 case SHADER_OPCODE_TXS:
683 assert(inst->mlen == 3);
684 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
685 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
686 break;
687 default:
688 unreachable("not reached");
689 }
690 }
691 assert(msg_type != -1);
692
693 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
694 rlen = 8;
695 dst = vec16(dst);
696 }
697
698 if (is_combined_send) {
699 assert(brw->gen >= 9 || brw->is_cherryview);
700 rlen = 0;
701 }
702
703 assert(brw->gen < 7 || !inst->header_present ||
704 src.file == BRW_GENERAL_REGISTER_FILE);
705
706 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
707
708 /* Load the message header if present. If there's a texture offset,
709 * we need to set it up explicitly and load the offset bitfield.
710 * Otherwise, we can use an implied move from g0 to the first message reg.
711 */
712 if (inst->header_present) {
713 if (brw->gen < 6 && !inst->offset) {
714 /* Set up an implied move from g0 to the MRF. */
715 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
716 } else {
717 struct brw_reg header_reg;
718
719 if (brw->gen >= 7) {
720 header_reg = src;
721 } else {
722 assert(inst->base_mrf != -1);
723 header_reg = brw_message_reg(inst->base_mrf);
724 }
725
726 brw_push_insn_state(p);
727 brw_set_default_exec_size(p, BRW_EXECUTE_8);
728 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
729 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
730 /* Explicitly set up the message header by copying g0 to the MRF. */
731 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
732
733 if (inst->offset) {
734 /* Set the offset bits in DWord 2. */
735 brw_MOV(p, get_element_ud(header_reg, 2),
736 brw_imm_ud(inst->offset));
737 }
738
739 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
740 brw_pop_insn_state(p);
741 }
742 }
743
744 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
745 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
746 ? prog_data->binding_table.gather_texture_start
747 : prog_data->binding_table.texture_start;
748
749 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
750 uint32_t sampler = sampler_index.dw1.ud;
751
752 brw_SAMPLE(p,
753 retype(dst, BRW_REGISTER_TYPE_UW),
754 inst->base_mrf,
755 src,
756 sampler + base_binding_table_index,
757 sampler % 16,
758 msg_type,
759 rlen,
760 inst->mlen,
761 inst->header_present,
762 simd_mode,
763 return_format);
764
765 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
766 } else {
767 /* Non-const sampler index */
768 /* Note: this clobbers `dst` as a temporary before emitting the send */
769
770 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
771 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
772
773 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
774
775 brw_push_insn_state(p);
776 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
777 brw_set_default_access_mode(p, BRW_ALIGN_1);
778
779 /* Some care required: `sampler` and `temp` may alias:
780 * addr = sampler & 0xff
781 * temp = (sampler << 8) & 0xf00
782 * addr = addr | temp
783 */
784 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
785 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
786 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
787 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
788 brw_OR(p, addr, addr, temp);
789
790 brw_pop_insn_state(p);
791
792 /* dst = send(offset, a0.0 | <descriptor>) */
793 brw_inst *insn = brw_send_indirect_message(
794 p, BRW_SFID_SAMPLER, dst, src, addr);
795 brw_set_sampler_message(p, insn,
796 0 /* surface */,
797 0 /* sampler */,
798 msg_type,
799 rlen,
800 inst->mlen /* mlen */,
801 inst->header_present /* header */,
802 simd_mode,
803 return_format);
804
805 /* visitor knows more than we do about the surface limit required,
806 * so has already done marking.
807 */
808 }
809
810 if (is_combined_send) {
811 brw_inst_set_eot(brw, brw_last_inst, true);
812 brw_inst_set_opcode(brw, brw_last_inst, BRW_OPCODE_SENDC);
813 }
814 }
815
816
817 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
818 * looking like:
819 *
820 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
821 *
822 * Ideally, we want to produce:
823 *
824 * DDX DDY
825 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
826 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
827 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
828 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
829 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
830 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
831 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
832 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
833 *
834 * and add another set of two more subspans if in 16-pixel dispatch mode.
835 *
836 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
837 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
838 * pair. But the ideal approximation may impose a huge performance cost on
839 * sample_d. On at least Haswell, sample_d instruction does some
840 * optimizations if the same LOD is used for all pixels in the subspan.
841 *
842 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
843 * appropriate swizzling.
844 */
845 void
846 fs_generator::generate_ddx(enum opcode opcode,
847 struct brw_reg dst, struct brw_reg src)
848 {
849 unsigned vstride, width;
850
851 if (opcode == FS_OPCODE_DDX_FINE) {
852 /* produce accurate derivatives */
853 vstride = BRW_VERTICAL_STRIDE_2;
854 width = BRW_WIDTH_2;
855 } else {
856 /* replicate the derivative at the top-left pixel to other pixels */
857 vstride = BRW_VERTICAL_STRIDE_4;
858 width = BRW_WIDTH_4;
859 }
860
861 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
862 src.negate, src.abs,
863 BRW_REGISTER_TYPE_F,
864 vstride,
865 width,
866 BRW_HORIZONTAL_STRIDE_0,
867 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
868 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
869 src.negate, src.abs,
870 BRW_REGISTER_TYPE_F,
871 vstride,
872 width,
873 BRW_HORIZONTAL_STRIDE_0,
874 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
875 brw_ADD(p, dst, src0, negate(src1));
876 }
877
878 /* The negate_value boolean is used to negate the derivative computation for
879 * FBOs, since they place the origin at the upper left instead of the lower
880 * left.
881 */
882 void
883 fs_generator::generate_ddy(enum opcode opcode,
884 struct brw_reg dst, struct brw_reg src,
885 bool negate_value)
886 {
887 if (opcode == FS_OPCODE_DDY_FINE) {
888 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
889 * Region Restrictions):
890 *
891 * In Align16 access mode, SIMD16 is not allowed for DW operations
892 * and SIMD8 is not allowed for DF operations.
893 *
894 * In this context, "DW operations" means "operations acting on 32-bit
895 * values", so it includes operations on floats.
896 *
897 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
898 * (Instruction Compression -> Rules and Restrictions):
899 *
900 * A compressed instruction must be in Align1 access mode. Align16
901 * mode instructions cannot be compressed.
902 *
903 * Similar text exists in the g45 PRM.
904 *
905 * On these platforms, if we're building a SIMD16 shader, we need to
906 * manually unroll to a pair of SIMD8 instructions.
907 */
908 bool unroll_to_simd8 =
909 (dispatch_width == 16 &&
910 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
911
912 /* produce accurate derivatives */
913 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
914 src.negate, src.abs,
915 BRW_REGISTER_TYPE_F,
916 BRW_VERTICAL_STRIDE_4,
917 BRW_WIDTH_4,
918 BRW_HORIZONTAL_STRIDE_1,
919 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
920 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
921 src.negate, src.abs,
922 BRW_REGISTER_TYPE_F,
923 BRW_VERTICAL_STRIDE_4,
924 BRW_WIDTH_4,
925 BRW_HORIZONTAL_STRIDE_1,
926 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
927 brw_push_insn_state(p);
928 brw_set_default_access_mode(p, BRW_ALIGN_16);
929 if (unroll_to_simd8) {
930 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
931 if (negate_value) {
932 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
933 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
934 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
935 } else {
936 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
937 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
938 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
939 }
940 } else {
941 if (negate_value)
942 brw_ADD(p, dst, src1, negate(src0));
943 else
944 brw_ADD(p, dst, src0, negate(src1));
945 }
946 brw_pop_insn_state(p);
947 } else {
948 /* replicate the derivative at the top-left pixel to other pixels */
949 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
950 src.negate, src.abs,
951 BRW_REGISTER_TYPE_F,
952 BRW_VERTICAL_STRIDE_4,
953 BRW_WIDTH_4,
954 BRW_HORIZONTAL_STRIDE_0,
955 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
956 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
957 src.negate, src.abs,
958 BRW_REGISTER_TYPE_F,
959 BRW_VERTICAL_STRIDE_4,
960 BRW_WIDTH_4,
961 BRW_HORIZONTAL_STRIDE_0,
962 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
963 if (negate_value)
964 brw_ADD(p, dst, src1, negate(src0));
965 else
966 brw_ADD(p, dst, src0, negate(src1));
967 }
968 }
969
970 void
971 fs_generator::generate_discard_jump(fs_inst *inst)
972 {
973 assert(brw->gen >= 6);
974
975 /* This HALT will be patched up at FB write time to point UIP at the end of
976 * the program, and at brw_uip_jip() JIP will be set to the end of the
977 * current block (or the program).
978 */
979 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
980
981 brw_push_insn_state(p);
982 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
983 gen6_HALT(p);
984 brw_pop_insn_state(p);
985 }
986
987 void
988 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
989 {
990 assert(inst->mlen != 0);
991
992 brw_MOV(p,
993 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
994 retype(src, BRW_REGISTER_TYPE_UD));
995 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
996 inst->exec_size / 8, inst->offset);
997 }
998
999 void
1000 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1001 {
1002 assert(inst->mlen != 0);
1003
1004 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1005 inst->exec_size / 8, inst->offset);
1006 }
1007
1008 void
1009 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1010 {
1011 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1012 }
1013
1014 void
1015 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1016 struct brw_reg dst,
1017 struct brw_reg index,
1018 struct brw_reg offset)
1019 {
1020 assert(inst->mlen != 0);
1021
1022 assert(index.file == BRW_IMMEDIATE_VALUE &&
1023 index.type == BRW_REGISTER_TYPE_UD);
1024 uint32_t surf_index = index.dw1.ud;
1025
1026 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1027 offset.type == BRW_REGISTER_TYPE_UD);
1028 uint32_t read_offset = offset.dw1.ud;
1029
1030 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1031 read_offset, surf_index);
1032
1033 brw_mark_surface_used(prog_data, surf_index);
1034 }
1035
1036 void
1037 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1038 struct brw_reg dst,
1039 struct brw_reg index,
1040 struct brw_reg offset)
1041 {
1042 assert(inst->mlen == 0);
1043 assert(index.type == BRW_REGISTER_TYPE_UD);
1044
1045 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1046 /* Reference just the dword we need, to avoid angering validate_reg(). */
1047 offset = brw_vec1_grf(offset.nr, 0);
1048
1049 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1050 * the destination loaded consecutively from the same offset (which appears
1051 * in the first component, and the rest are ignored).
1052 */
1053 dst.width = BRW_WIDTH_4;
1054
1055 struct brw_reg src = offset;
1056 bool header_present = false;
1057 int mlen = 1;
1058
1059 if (brw->gen >= 9) {
1060 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1061 src = retype(brw_vec4_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD);
1062 mlen = 2;
1063 header_present = true;
1064
1065 brw_push_insn_state(p);
1066 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1067 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1068 brw_set_default_access_mode(p, BRW_ALIGN_1);
1069
1070 brw_MOV(p, get_element_ud(src, 2),
1071 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1072 brw_pop_insn_state(p);
1073 }
1074
1075 if (index.file == BRW_IMMEDIATE_VALUE) {
1076
1077 uint32_t surf_index = index.dw1.ud;
1078
1079 brw_push_insn_state(p);
1080 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1081 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1082 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1083 brw_pop_insn_state(p);
1084
1085 brw_set_dest(p, send, dst);
1086 brw_set_src0(p, send, src);
1087 brw_set_sampler_message(p, send,
1088 surf_index,
1089 0, /* LD message ignores sampler unit */
1090 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1091 1, /* rlen */
1092 mlen,
1093 header_present,
1094 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1095 0);
1096
1097 brw_mark_surface_used(prog_data, surf_index);
1098
1099 } else {
1100
1101 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1102
1103 brw_push_insn_state(p);
1104 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1105 brw_set_default_access_mode(p, BRW_ALIGN_1);
1106
1107 /* a0.0 = surf_index & 0xff */
1108 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1109 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1110 brw_set_dest(p, insn_and, addr);
1111 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1112 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1113
1114 /* dst = send(payload, a0.0 | <descriptor>) */
1115 brw_inst *insn = brw_send_indirect_message(
1116 p, BRW_SFID_SAMPLER, dst, src, addr);
1117 brw_set_sampler_message(p, insn,
1118 0,
1119 0, /* LD message ignores sampler unit */
1120 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1121 1, /* rlen */
1122 mlen,
1123 header_present,
1124 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1125 0);
1126
1127 brw_pop_insn_state(p);
1128
1129 /* visitor knows more than we do about the surface limit required,
1130 * so has already done marking.
1131 */
1132
1133 }
1134 }
1135
1136 void
1137 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1138 struct brw_reg dst,
1139 struct brw_reg index,
1140 struct brw_reg offset)
1141 {
1142 assert(brw->gen < 7); /* Should use the gen7 variant. */
1143 assert(inst->header_present);
1144 assert(inst->mlen);
1145
1146 assert(index.file == BRW_IMMEDIATE_VALUE &&
1147 index.type == BRW_REGISTER_TYPE_UD);
1148 uint32_t surf_index = index.dw1.ud;
1149
1150 uint32_t simd_mode, rlen, msg_type;
1151 if (dispatch_width == 16) {
1152 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1153 rlen = 8;
1154 } else {
1155 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1156 rlen = 4;
1157 }
1158
1159 if (brw->gen >= 5)
1160 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1161 else {
1162 /* We always use the SIMD16 message so that we only have to load U, and
1163 * not V or R.
1164 */
1165 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1166 assert(inst->mlen == 3);
1167 assert(inst->regs_written == 8);
1168 rlen = 8;
1169 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1170 }
1171
1172 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1173 BRW_REGISTER_TYPE_D);
1174 brw_MOV(p, offset_mrf, offset);
1175
1176 struct brw_reg header = brw_vec8_grf(0, 0);
1177 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1178
1179 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1180 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
1181 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1182 brw_set_src0(p, send, header);
1183 if (brw->gen < 6)
1184 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
1185
1186 /* Our surface is set up as floats, regardless of what actual data is
1187 * stored in it.
1188 */
1189 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1190 brw_set_sampler_message(p, send,
1191 surf_index,
1192 0, /* sampler (unused) */
1193 msg_type,
1194 rlen,
1195 inst->mlen,
1196 inst->header_present,
1197 simd_mode,
1198 return_format);
1199
1200 brw_mark_surface_used(prog_data, surf_index);
1201 }
1202
1203 void
1204 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1205 struct brw_reg dst,
1206 struct brw_reg index,
1207 struct brw_reg offset)
1208 {
1209 assert(brw->gen >= 7);
1210 /* Varying-offset pull constant loads are treated as a normal expression on
1211 * gen7, so the fact that it's a send message is hidden at the IR level.
1212 */
1213 assert(!inst->header_present);
1214 assert(!inst->mlen);
1215 assert(index.type == BRW_REGISTER_TYPE_UD);
1216
1217 uint32_t simd_mode, rlen, mlen;
1218 if (dispatch_width == 16) {
1219 mlen = 2;
1220 rlen = 8;
1221 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1222 } else {
1223 mlen = 1;
1224 rlen = 4;
1225 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1226 }
1227
1228 if (index.file == BRW_IMMEDIATE_VALUE) {
1229
1230 uint32_t surf_index = index.dw1.ud;
1231
1232 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1233 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1234 brw_set_src0(p, send, offset);
1235 brw_set_sampler_message(p, send,
1236 surf_index,
1237 0, /* LD message ignores sampler unit */
1238 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1239 rlen,
1240 mlen,
1241 false, /* no header */
1242 simd_mode,
1243 0);
1244
1245 brw_mark_surface_used(prog_data, surf_index);
1246
1247 } else {
1248
1249 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1250
1251 brw_push_insn_state(p);
1252 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1253 brw_set_default_access_mode(p, BRW_ALIGN_1);
1254
1255 /* a0.0 = surf_index & 0xff */
1256 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1257 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1258 brw_set_dest(p, insn_and, addr);
1259 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1260 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1261
1262 brw_pop_insn_state(p);
1263
1264 /* dst = send(offset, a0.0 | <descriptor>) */
1265 brw_inst *insn = brw_send_indirect_message(
1266 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1267 offset, addr);
1268 brw_set_sampler_message(p, insn,
1269 0 /* surface */,
1270 0 /* sampler */,
1271 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1272 rlen /* rlen */,
1273 mlen /* mlen */,
1274 false /* header */,
1275 simd_mode,
1276 0);
1277
1278 /* visitor knows more than we do about the surface limit required,
1279 * so has already done marking.
1280 */
1281 }
1282 }
1283
1284 /**
1285 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1286 * into the flags register (f0.0).
1287 *
1288 * Used only on Gen6 and above.
1289 */
1290 void
1291 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1292 {
1293 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1294 struct brw_reg dispatch_mask;
1295
1296 if (brw->gen >= 6)
1297 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1298 else
1299 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1300
1301 brw_push_insn_state(p);
1302 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1303 brw_MOV(p, flags, dispatch_mask);
1304 brw_pop_insn_state(p);
1305 }
1306
1307 void
1308 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1309 struct brw_reg dst,
1310 struct brw_reg src,
1311 struct brw_reg msg_data,
1312 unsigned msg_type)
1313 {
1314 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1315 msg_data.type == BRW_REGISTER_TYPE_UD);
1316
1317 brw_pixel_interpolator_query(p,
1318 retype(dst, BRW_REGISTER_TYPE_UW),
1319 src,
1320 inst->pi_noperspective,
1321 msg_type,
1322 msg_data.dw1.ud,
1323 inst->mlen,
1324 inst->regs_written);
1325 }
1326
1327
1328 /**
1329 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1330 * sampler LD messages.
1331 *
1332 * We don't want to bake it into the send message's code generation because
1333 * that means we don't get a chance to schedule the instructions.
1334 */
1335 void
1336 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1337 struct brw_reg dst,
1338 struct brw_reg value)
1339 {
1340 assert(value.file == BRW_IMMEDIATE_VALUE);
1341
1342 brw_push_insn_state(p);
1343 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1344 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1345 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1346 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1347 brw_pop_insn_state(p);
1348 }
1349
1350 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1351 * (when mask is passed as a uniform) of register mask before moving it
1352 * to register dst.
1353 */
1354 void
1355 fs_generator::generate_set_omask(fs_inst *inst,
1356 struct brw_reg dst,
1357 struct brw_reg mask)
1358 {
1359 bool stride_8_8_1 =
1360 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1361 mask.width == BRW_WIDTH_8 &&
1362 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1363
1364 bool stride_0_1_0 = has_scalar_region(mask);
1365
1366 assert(stride_8_8_1 || stride_0_1_0);
1367 assert(dst.type == BRW_REGISTER_TYPE_UW);
1368
1369 brw_push_insn_state(p);
1370 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1371 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1372
1373 if (stride_8_8_1) {
1374 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1375 } else if (stride_0_1_0) {
1376 brw_MOV(p, dst, retype(mask, dst.type));
1377 }
1378 brw_pop_insn_state(p);
1379 }
1380
1381 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1382 * the ADD instruction.
1383 */
1384 void
1385 fs_generator::generate_set_sample_id(fs_inst *inst,
1386 struct brw_reg dst,
1387 struct brw_reg src0,
1388 struct brw_reg src1)
1389 {
1390 assert(dst.type == BRW_REGISTER_TYPE_D ||
1391 dst.type == BRW_REGISTER_TYPE_UD);
1392 assert(src0.type == BRW_REGISTER_TYPE_D ||
1393 src0.type == BRW_REGISTER_TYPE_UD);
1394
1395 brw_push_insn_state(p);
1396 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1397 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1398 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1399 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1400 if (dispatch_width == 8) {
1401 brw_ADD(p, dst, src0, reg);
1402 } else if (dispatch_width == 16) {
1403 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1404 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1405 }
1406 brw_pop_insn_state(p);
1407 }
1408
1409 void
1410 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1411 struct brw_reg dst,
1412 struct brw_reg x,
1413 struct brw_reg y)
1414 {
1415 assert(brw->gen >= 7);
1416 assert(dst.type == BRW_REGISTER_TYPE_UD);
1417 assert(x.type == BRW_REGISTER_TYPE_F);
1418 assert(y.type == BRW_REGISTER_TYPE_F);
1419
1420 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1421 *
1422 * Because this instruction does not have a 16-bit floating-point type,
1423 * the destination data type must be Word (W).
1424 *
1425 * The destination must be DWord-aligned and specify a horizontal stride
1426 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1427 * each destination channel and the upper word is not modified.
1428 */
1429 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1430
1431 /* Give each 32-bit channel of dst the form below, where "." means
1432 * unchanged.
1433 * 0x....hhhh
1434 */
1435 brw_F32TO16(p, dst_w, y);
1436
1437 /* Now the form:
1438 * 0xhhhh0000
1439 */
1440 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1441
1442 /* And, finally the form of packHalf2x16's output:
1443 * 0xhhhhllll
1444 */
1445 brw_F32TO16(p, dst_w, x);
1446 }
1447
1448 void
1449 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1450 struct brw_reg dst,
1451 struct brw_reg src)
1452 {
1453 assert(brw->gen >= 7);
1454 assert(dst.type == BRW_REGISTER_TYPE_F);
1455 assert(src.type == BRW_REGISTER_TYPE_UD);
1456
1457 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1458 *
1459 * Because this instruction does not have a 16-bit floating-point type,
1460 * the source data type must be Word (W). The destination type must be
1461 * F (Float).
1462 */
1463 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1464
1465 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1466 * For the Y case, we wish to access only the upper word; therefore
1467 * a 16-bit subregister offset is needed.
1468 */
1469 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1470 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1471 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1472 src_w.subnr += 2;
1473
1474 brw_F16TO32(p, dst, src_w);
1475 }
1476
1477 void
1478 fs_generator::generate_shader_time_add(fs_inst *inst,
1479 struct brw_reg payload,
1480 struct brw_reg offset,
1481 struct brw_reg value)
1482 {
1483 assert(brw->gen >= 7);
1484 brw_push_insn_state(p);
1485 brw_set_default_mask_control(p, true);
1486
1487 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1488 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1489 offset.type);
1490 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1491 value.type);
1492
1493 assert(offset.file == BRW_IMMEDIATE_VALUE);
1494 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1495 value.width = BRW_WIDTH_1;
1496 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1497 value.vstride = BRW_VERTICAL_STRIDE_0;
1498 } else {
1499 assert(value.file == BRW_IMMEDIATE_VALUE);
1500 }
1501
1502 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1503 * case, and we don't really care about squeezing every bit of performance
1504 * out of this path, so we just emit the MOVs from here.
1505 */
1506 brw_MOV(p, payload_offset, offset);
1507 brw_MOV(p, payload_value, value);
1508 brw_shader_time_add(p, payload,
1509 prog_data->binding_table.shader_time_start);
1510 brw_pop_insn_state(p);
1511
1512 brw_mark_surface_used(prog_data,
1513 prog_data->binding_table.shader_time_start);
1514 }
1515
1516 void
1517 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1518 struct brw_reg payload,
1519 struct brw_reg atomic_op,
1520 struct brw_reg surf_index)
1521 {
1522 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1523 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1524 surf_index.file == BRW_IMMEDIATE_VALUE &&
1525 surf_index.type == BRW_REGISTER_TYPE_UD);
1526
1527 brw_untyped_atomic(p, dst, payload,
1528 atomic_op.dw1.ud, surf_index.dw1.ud,
1529 inst->mlen, true);
1530
1531 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1532 }
1533
1534 void
1535 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1536 struct brw_reg payload,
1537 struct brw_reg surf_index)
1538 {
1539 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1540 surf_index.type == BRW_REGISTER_TYPE_UD);
1541
1542 brw_untyped_surface_read(p, dst, payload, surf_index.dw1.ud, inst->mlen, 1);
1543
1544 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1545 }
1546
1547 void
1548 fs_generator::enable_debug(const char *shader_name)
1549 {
1550 debug_flag = true;
1551 this->shader_name = shader_name;
1552 }
1553
1554 /**
1555 * Some hardware doesn't support SIMD16 instructions with 3 sources.
1556 */
1557 static bool
1558 brw_supports_simd16_3src(const struct brw_context *brw)
1559 {
1560 /* WaDisableSIMD16On3SrcInstr: 3-source instructions don't work in SIMD16
1561 * on a few steppings of Skylake.
1562 */
1563 if (brw->gen == 9)
1564 return brw->revision != 2 && brw->revision != 3 && brw->revision != -1;
1565
1566 return brw->is_haswell || brw->gen >= 8;
1567 }
1568
1569 int
1570 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1571 {
1572 /* align to 64 byte boundary. */
1573 while (p->next_insn_offset % 64)
1574 brw_NOP(p);
1575
1576 this->dispatch_width = dispatch_width;
1577 if (dispatch_width == 16)
1578 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1579
1580 int start_offset = p->next_insn_offset;
1581 int spill_count = 0, fill_count = 0;
1582 int loop_count = 0;
1583
1584 struct annotation_info annotation;
1585 memset(&annotation, 0, sizeof(annotation));
1586
1587 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1588 struct brw_reg src[3], dst;
1589 unsigned int last_insn_offset = p->next_insn_offset;
1590 bool multiple_instructions_emitted = false;
1591
1592 if (unlikely(debug_flag))
1593 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1594
1595 for (unsigned int i = 0; i < inst->sources; i++) {
1596 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1597
1598 /* The accumulator result appears to get used for the
1599 * conditional modifier generation. When negating a UD
1600 * value, there is a 33rd bit generated for the sign in the
1601 * accumulator value, so now you can't check, for example,
1602 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1603 */
1604 assert(!inst->conditional_mod ||
1605 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1606 !inst->src[i].negate);
1607 }
1608 dst = brw_reg_from_fs_reg(&inst->dst);
1609
1610 brw_set_default_predicate_control(p, inst->predicate);
1611 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1612 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1613 brw_set_default_saturate(p, inst->saturate);
1614 brw_set_default_mask_control(p, inst->force_writemask_all);
1615 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1616 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1617
1618 switch (inst->exec_size) {
1619 case 1:
1620 case 2:
1621 case 4:
1622 assert(inst->force_writemask_all);
1623 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1624 break;
1625 case 8:
1626 if (inst->force_sechalf) {
1627 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1628 } else {
1629 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1630 }
1631 break;
1632 case 16:
1633 case 32:
1634 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1635 break;
1636 default:
1637 unreachable("Invalid instruction width");
1638 }
1639
1640 switch (inst->opcode) {
1641 case BRW_OPCODE_MOV:
1642 brw_MOV(p, dst, src[0]);
1643 break;
1644 case BRW_OPCODE_ADD:
1645 brw_ADD(p, dst, src[0], src[1]);
1646 break;
1647 case BRW_OPCODE_MUL:
1648 brw_MUL(p, dst, src[0], src[1]);
1649 break;
1650 case BRW_OPCODE_AVG:
1651 brw_AVG(p, dst, src[0], src[1]);
1652 break;
1653 case BRW_OPCODE_MACH:
1654 brw_MACH(p, dst, src[0], src[1]);
1655 break;
1656
1657 case BRW_OPCODE_LINE:
1658 brw_LINE(p, dst, src[0], src[1]);
1659 break;
1660
1661 case BRW_OPCODE_MAD:
1662 assert(brw->gen >= 6);
1663 brw_set_default_access_mode(p, BRW_ALIGN_16);
1664 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1665 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1666 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1667 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1668 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1669 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1670 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1671
1672 if (inst->conditional_mod) {
1673 brw_inst_set_cond_modifier(brw, f, inst->conditional_mod);
1674 brw_inst_set_cond_modifier(brw, s, inst->conditional_mod);
1675 multiple_instructions_emitted = true;
1676 }
1677 } else {
1678 brw_MAD(p, dst, src[0], src[1], src[2]);
1679 }
1680 brw_set_default_access_mode(p, BRW_ALIGN_1);
1681 break;
1682
1683 case BRW_OPCODE_LRP:
1684 assert(brw->gen >= 6);
1685 brw_set_default_access_mode(p, BRW_ALIGN_16);
1686 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1687 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1688 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1689 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1690 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1691 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1692 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1693
1694 if (inst->conditional_mod) {
1695 brw_inst_set_cond_modifier(brw, f, inst->conditional_mod);
1696 brw_inst_set_cond_modifier(brw, s, inst->conditional_mod);
1697 multiple_instructions_emitted = true;
1698 }
1699 } else {
1700 brw_LRP(p, dst, src[0], src[1], src[2]);
1701 }
1702 brw_set_default_access_mode(p, BRW_ALIGN_1);
1703 break;
1704
1705 case BRW_OPCODE_FRC:
1706 brw_FRC(p, dst, src[0]);
1707 break;
1708 case BRW_OPCODE_RNDD:
1709 brw_RNDD(p, dst, src[0]);
1710 break;
1711 case BRW_OPCODE_RNDE:
1712 brw_RNDE(p, dst, src[0]);
1713 break;
1714 case BRW_OPCODE_RNDZ:
1715 brw_RNDZ(p, dst, src[0]);
1716 break;
1717
1718 case BRW_OPCODE_AND:
1719 brw_AND(p, dst, src[0], src[1]);
1720 break;
1721 case BRW_OPCODE_OR:
1722 brw_OR(p, dst, src[0], src[1]);
1723 break;
1724 case BRW_OPCODE_XOR:
1725 brw_XOR(p, dst, src[0], src[1]);
1726 break;
1727 case BRW_OPCODE_NOT:
1728 brw_NOT(p, dst, src[0]);
1729 break;
1730 case BRW_OPCODE_ASR:
1731 brw_ASR(p, dst, src[0], src[1]);
1732 break;
1733 case BRW_OPCODE_SHR:
1734 brw_SHR(p, dst, src[0], src[1]);
1735 break;
1736 case BRW_OPCODE_SHL:
1737 brw_SHL(p, dst, src[0], src[1]);
1738 break;
1739 case BRW_OPCODE_F32TO16:
1740 assert(brw->gen >= 7);
1741 brw_F32TO16(p, dst, src[0]);
1742 break;
1743 case BRW_OPCODE_F16TO32:
1744 assert(brw->gen >= 7);
1745 brw_F16TO32(p, dst, src[0]);
1746 break;
1747 case BRW_OPCODE_CMP:
1748 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1749 * that when the destination is a GRF that the dependency-clear bit on
1750 * the flag register is cleared early.
1751 *
1752 * Suggested workarounds are to disable coissuing CMP instructions
1753 * or to split CMP(16) instructions into two CMP(8) instructions.
1754 *
1755 * We choose to split into CMP(8) instructions since disabling
1756 * coissuing would affect CMP instructions not otherwise affected by
1757 * the errata.
1758 */
1759 if (dispatch_width == 16 && brw->gen == 7 && !brw->is_haswell) {
1760 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1761 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1762 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1763 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1764 firsthalf(src[0]), firsthalf(src[1]));
1765 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1766 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1767 sechalf(src[0]), sechalf(src[1]));
1768 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1769
1770 multiple_instructions_emitted = true;
1771 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1772 /* For unknown reasons, the aforementioned workaround is not
1773 * sufficient. Overriding the type when the destination is the
1774 * null register is necessary but not sufficient by itself.
1775 */
1776 assert(dst.nr == BRW_ARF_NULL);
1777 dst.type = BRW_REGISTER_TYPE_D;
1778 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1779 } else {
1780 unreachable("not reached");
1781 }
1782 } else {
1783 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1784 }
1785 break;
1786 case BRW_OPCODE_SEL:
1787 brw_SEL(p, dst, src[0], src[1]);
1788 break;
1789 case BRW_OPCODE_BFREV:
1790 assert(brw->gen >= 7);
1791 /* BFREV only supports UD type for src and dst. */
1792 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1793 retype(src[0], BRW_REGISTER_TYPE_UD));
1794 break;
1795 case BRW_OPCODE_FBH:
1796 assert(brw->gen >= 7);
1797 /* FBH only supports UD type for dst. */
1798 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1799 break;
1800 case BRW_OPCODE_FBL:
1801 assert(brw->gen >= 7);
1802 /* FBL only supports UD type for dst. */
1803 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1804 break;
1805 case BRW_OPCODE_CBIT:
1806 assert(brw->gen >= 7);
1807 /* CBIT only supports UD type for dst. */
1808 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1809 break;
1810 case BRW_OPCODE_ADDC:
1811 assert(brw->gen >= 7);
1812 brw_ADDC(p, dst, src[0], src[1]);
1813 break;
1814 case BRW_OPCODE_SUBB:
1815 assert(brw->gen >= 7);
1816 brw_SUBB(p, dst, src[0], src[1]);
1817 break;
1818 case BRW_OPCODE_MAC:
1819 brw_MAC(p, dst, src[0], src[1]);
1820 break;
1821
1822 case BRW_OPCODE_BFE:
1823 assert(brw->gen >= 7);
1824 brw_set_default_access_mode(p, BRW_ALIGN_16);
1825 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1826 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1827 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1828 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1829 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1830 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1831 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1832 } else {
1833 brw_BFE(p, dst, src[0], src[1], src[2]);
1834 }
1835 brw_set_default_access_mode(p, BRW_ALIGN_1);
1836 break;
1837
1838 case BRW_OPCODE_BFI1:
1839 assert(brw->gen >= 7);
1840 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1841 * should
1842 *
1843 * "Force BFI instructions to be executed always in SIMD8."
1844 */
1845 if (dispatch_width == 16 && brw->is_haswell) {
1846 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1847 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1848 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1849 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1850 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1851 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1852 } else {
1853 brw_BFI1(p, dst, src[0], src[1]);
1854 }
1855 break;
1856 case BRW_OPCODE_BFI2:
1857 assert(brw->gen >= 7);
1858 brw_set_default_access_mode(p, BRW_ALIGN_16);
1859 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1860 * should
1861 *
1862 * "Force BFI instructions to be executed always in SIMD8."
1863 *
1864 * Otherwise we would be able to emit compressed instructions like we
1865 * do for the other three-source instructions.
1866 */
1867 if (dispatch_width == 16 &&
1868 (brw->is_haswell || !brw_supports_simd16_3src(brw))) {
1869 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1870 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1871 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1872 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1873 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1874 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1875 } else {
1876 brw_BFI2(p, dst, src[0], src[1], src[2]);
1877 }
1878 brw_set_default_access_mode(p, BRW_ALIGN_1);
1879 break;
1880
1881 case BRW_OPCODE_IF:
1882 if (inst->src[0].file != BAD_FILE) {
1883 /* The instruction has an embedded compare (only allowed on gen6) */
1884 assert(brw->gen == 6);
1885 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1886 } else {
1887 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1888 }
1889 break;
1890
1891 case BRW_OPCODE_ELSE:
1892 brw_ELSE(p);
1893 break;
1894 case BRW_OPCODE_ENDIF:
1895 brw_ENDIF(p);
1896 break;
1897
1898 case BRW_OPCODE_DO:
1899 brw_DO(p, BRW_EXECUTE_8);
1900 break;
1901
1902 case BRW_OPCODE_BREAK:
1903 brw_BREAK(p);
1904 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1905 break;
1906 case BRW_OPCODE_CONTINUE:
1907 brw_CONT(p);
1908 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1909 break;
1910
1911 case BRW_OPCODE_WHILE:
1912 brw_WHILE(p);
1913 loop_count++;
1914 break;
1915
1916 case SHADER_OPCODE_RCP:
1917 case SHADER_OPCODE_RSQ:
1918 case SHADER_OPCODE_SQRT:
1919 case SHADER_OPCODE_EXP2:
1920 case SHADER_OPCODE_LOG2:
1921 case SHADER_OPCODE_SIN:
1922 case SHADER_OPCODE_COS:
1923 assert(brw->gen < 6 || inst->mlen == 0);
1924 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1925 if (brw->gen >= 7) {
1926 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1927 brw_null_reg());
1928 } else if (brw->gen == 6) {
1929 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1930 } else if (brw->gen == 5 || brw->is_g4x) {
1931 generate_math_g45(inst, dst, src[0]);
1932 } else {
1933 generate_math_gen4(inst, dst, src[0]);
1934 }
1935 break;
1936 case SHADER_OPCODE_INT_QUOTIENT:
1937 case SHADER_OPCODE_INT_REMAINDER:
1938 case SHADER_OPCODE_POW:
1939 assert(brw->gen < 6 || inst->mlen == 0);
1940 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1941 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1942 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1943 } else if (brw->gen >= 6) {
1944 generate_math_gen6(inst, dst, src[0], src[1]);
1945 } else {
1946 generate_math_gen4(inst, dst, src[0]);
1947 }
1948 break;
1949 case FS_OPCODE_PIXEL_X:
1950 generate_pixel_xy(dst, true);
1951 break;
1952 case FS_OPCODE_PIXEL_Y:
1953 generate_pixel_xy(dst, false);
1954 break;
1955 case FS_OPCODE_CINTERP:
1956 brw_MOV(p, dst, src[0]);
1957 break;
1958 case FS_OPCODE_LINTERP:
1959 generate_linterp(inst, dst, src);
1960 break;
1961 case SHADER_OPCODE_TEX:
1962 case FS_OPCODE_TXB:
1963 case SHADER_OPCODE_TXD:
1964 case SHADER_OPCODE_TXF:
1965 case SHADER_OPCODE_TXF_CMS:
1966 case SHADER_OPCODE_TXF_UMS:
1967 case SHADER_OPCODE_TXF_MCS:
1968 case SHADER_OPCODE_TXL:
1969 case SHADER_OPCODE_TXS:
1970 case SHADER_OPCODE_LOD:
1971 case SHADER_OPCODE_TG4:
1972 case SHADER_OPCODE_TG4_OFFSET:
1973 generate_tex(inst, dst, src[0], src[1]);
1974 break;
1975 case FS_OPCODE_DDX_COARSE:
1976 case FS_OPCODE_DDX_FINE:
1977 generate_ddx(inst->opcode, dst, src[0]);
1978 break;
1979 case FS_OPCODE_DDY_COARSE:
1980 case FS_OPCODE_DDY_FINE:
1981 assert(src[1].file == BRW_IMMEDIATE_VALUE);
1982 generate_ddy(inst->opcode, dst, src[0], src[1].dw1.ud);
1983 break;
1984
1985 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1986 generate_scratch_write(inst, src[0]);
1987 spill_count++;
1988 break;
1989
1990 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1991 generate_scratch_read(inst, dst);
1992 fill_count++;
1993 break;
1994
1995 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1996 generate_scratch_read_gen7(inst, dst);
1997 fill_count++;
1998 break;
1999
2000 case SHADER_OPCODE_URB_WRITE_SIMD8:
2001 generate_urb_write(inst, src[0]);
2002 break;
2003
2004 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2005 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2006 break;
2007
2008 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2009 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2010 break;
2011
2012 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
2013 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
2014 break;
2015
2016 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2017 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2018 break;
2019
2020 case FS_OPCODE_REP_FB_WRITE:
2021 case FS_OPCODE_FB_WRITE:
2022 generate_fb_write(inst, src[0]);
2023 break;
2024
2025 case FS_OPCODE_BLORP_FB_WRITE:
2026 generate_blorp_fb_write(inst);
2027 break;
2028
2029 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2030 generate_mov_dispatch_to_flags(inst);
2031 break;
2032
2033 case FS_OPCODE_DISCARD_JUMP:
2034 generate_discard_jump(inst);
2035 break;
2036
2037 case SHADER_OPCODE_SHADER_TIME_ADD:
2038 generate_shader_time_add(inst, src[0], src[1], src[2]);
2039 break;
2040
2041 case SHADER_OPCODE_UNTYPED_ATOMIC:
2042 generate_untyped_atomic(inst, dst, src[0], src[1], src[2]);
2043 break;
2044
2045 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2046 generate_untyped_surface_read(inst, dst, src[0], src[1]);
2047 break;
2048
2049 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2050 generate_set_simd4x2_offset(inst, dst, src[0]);
2051 break;
2052
2053 case FS_OPCODE_SET_OMASK:
2054 generate_set_omask(inst, dst, src[0]);
2055 break;
2056
2057 case FS_OPCODE_SET_SAMPLE_ID:
2058 generate_set_sample_id(inst, dst, src[0], src[1]);
2059 break;
2060
2061 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2062 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2063 break;
2064
2065 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2066 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2067 generate_unpack_half_2x16_split(inst, dst, src[0]);
2068 break;
2069
2070 case FS_OPCODE_PLACEHOLDER_HALT:
2071 /* This is the place where the final HALT needs to be inserted if
2072 * we've emitted any discards. If not, this will emit no code.
2073 */
2074 if (!patch_discard_jumps_to_fb_writes()) {
2075 if (unlikely(debug_flag)) {
2076 annotation.ann_count--;
2077 }
2078 }
2079 break;
2080
2081 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2082 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2083 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2084 break;
2085
2086 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2087 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2088 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2089 break;
2090
2091 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2092 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2093 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2094 break;
2095
2096 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2097 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2098 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2099 break;
2100
2101 default:
2102 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
2103 _mesa_problem(ctx, "Unsupported opcode `%s' in %s",
2104 opcode_descs[inst->opcode].name, stage_abbrev);
2105 } else {
2106 _mesa_problem(ctx, "Unsupported opcode %d in %s", inst->opcode,
2107 stage_abbrev);
2108 }
2109 abort();
2110
2111 case SHADER_OPCODE_LOAD_PAYLOAD:
2112 unreachable("Should be lowered by lower_load_payload()");
2113 }
2114
2115 if (multiple_instructions_emitted)
2116 continue;
2117
2118 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2119 assert(p->next_insn_offset == last_insn_offset + 16 ||
2120 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2121 "emitting more than 1 instruction");
2122
2123 brw_inst *last = &p->store[last_insn_offset / 16];
2124
2125 if (inst->conditional_mod)
2126 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
2127 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
2128 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
2129 }
2130 }
2131
2132 brw_set_uip_jip(p);
2133 annotation_finalize(&annotation, p->next_insn_offset);
2134
2135 int before_size = p->next_insn_offset - start_offset;
2136 brw_compact_instructions(p, start_offset, annotation.ann_count,
2137 annotation.ann);
2138 int after_size = p->next_insn_offset - start_offset;
2139
2140 if (unlikely(debug_flag)) {
2141 fprintf(stderr, "Native code for %s\n"
2142 "SIMD%d shader: %d instructions. %d loops. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2143 " bytes (%.0f%%)\n",
2144 shader_name, dispatch_width, before_size / 16, loop_count,
2145 spill_count, fill_count, promoted_constants, before_size, after_size,
2146 100.0f * (before_size - after_size) / before_size);
2147
2148 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
2149 ralloc_free(annotation.ann);
2150 }
2151
2152 static GLuint msg_id = 0;
2153 _mesa_gl_debug(&brw->ctx, &msg_id,
2154 MESA_DEBUG_SOURCE_SHADER_COMPILER,
2155 MESA_DEBUG_TYPE_OTHER,
2156 MESA_DEBUG_SEVERITY_NOTIFICATION,
2157 "%s SIMD%d shader: %d inst, %d loops, %d:%d spills:fills, "
2158 "Promoted %u constants, compacted %d to %d bytes.\n",
2159 stage_abbrev, dispatch_width, before_size / 16, loop_count,
2160 spill_count, fill_count, promoted_constants, before_size, after_size);
2161
2162 return start_offset;
2163 }
2164
2165 const unsigned *
2166 fs_generator::get_assembly(unsigned int *assembly_size)
2167 {
2168 return brw_get_program(p, assembly_size);
2169 }