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i965/fs: Plumb separate surfaces and samplers through from NIR
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "main/macros.h"
31 #include "brw_context.h"
32 #include "brw_eu.h"
33 #include "brw_fs.h"
34 #include "brw_cfg.h"
35
36 static enum brw_reg_file
37 brw_file_from_reg(fs_reg *reg)
38 {
39 switch (reg->file) {
40 case ARF:
41 return BRW_ARCHITECTURE_REGISTER_FILE;
42 case FIXED_GRF:
43 case VGRF:
44 return BRW_GENERAL_REGISTER_FILE;
45 case MRF:
46 return BRW_MESSAGE_REGISTER_FILE;
47 case IMM:
48 return BRW_IMMEDIATE_VALUE;
49 case BAD_FILE:
50 case ATTR:
51 case UNIFORM:
52 unreachable("not reached");
53 }
54 return BRW_ARCHITECTURE_REGISTER_FILE;
55 }
56
57 static struct brw_reg
58 brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
59 {
60 struct brw_reg brw_reg;
61
62 switch (reg->file) {
63 case MRF:
64 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(gen));
65 /* Fallthrough */
66 case VGRF:
67 if (reg->stride == 0) {
68 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
69 } else if (inst->exec_size < 8) {
70 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
71 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
72 inst->exec_size, reg->stride);
73 } else {
74 /* From the Haswell PRM:
75 *
76 * VertStride must be used to cross GRF register boundaries. This
77 * rule implies that elements within a 'Width' cannot cross GRF
78 * boundaries.
79 *
80 * So, for registers with width > 8, we have to use a width of 8
81 * and trust the compression state to sort out the exec size.
82 */
83 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
84 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
85 }
86
87 brw_reg = retype(brw_reg, reg->type);
88 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
89 brw_reg.abs = reg->abs;
90 brw_reg.negate = reg->negate;
91 break;
92 case IMM:
93 assert(reg->stride == ((reg->type == BRW_REGISTER_TYPE_V ||
94 reg->type == BRW_REGISTER_TYPE_UV ||
95 reg->type == BRW_REGISTER_TYPE_VF) ? 1 : 0));
96
97 switch (reg->type) {
98 case BRW_REGISTER_TYPE_F:
99 brw_reg = brw_imm_f(reg->f);
100 break;
101 case BRW_REGISTER_TYPE_D:
102 brw_reg = brw_imm_d(reg->d);
103 break;
104 case BRW_REGISTER_TYPE_UD:
105 brw_reg = brw_imm_ud(reg->ud);
106 break;
107 case BRW_REGISTER_TYPE_W:
108 brw_reg = brw_imm_w(reg->d);
109 break;
110 case BRW_REGISTER_TYPE_UW:
111 brw_reg = brw_imm_uw(reg->ud);
112 break;
113 case BRW_REGISTER_TYPE_VF:
114 brw_reg = brw_imm_vf(reg->ud);
115 break;
116 case BRW_REGISTER_TYPE_V:
117 brw_reg = brw_imm_v(reg->ud);
118 break;
119 default:
120 unreachable("not reached");
121 }
122 break;
123 case ARF:
124 case FIXED_GRF:
125 brw_reg = *static_cast<struct brw_reg *>(reg);
126 break;
127 case BAD_FILE:
128 /* Probably unused. */
129 brw_reg = brw_null_reg();
130 break;
131 case ATTR:
132 case UNIFORM:
133 unreachable("not reached");
134 }
135
136 return brw_reg;
137 }
138
139 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
140 void *mem_ctx,
141 const void *key,
142 struct brw_stage_prog_data *prog_data,
143 unsigned promoted_constants,
144 bool runtime_check_aads_emit,
145 const char *stage_abbrev)
146
147 : compiler(compiler), log_data(log_data),
148 devinfo(compiler->devinfo), key(key),
149 prog_data(prog_data),
150 promoted_constants(promoted_constants),
151 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
152 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
153 {
154 p = rzalloc(mem_ctx, struct brw_codegen);
155 brw_init_codegen(devinfo, p, mem_ctx);
156 }
157
158 fs_generator::~fs_generator()
159 {
160 }
161
162 class ip_record : public exec_node {
163 public:
164 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
165
166 ip_record(int ip)
167 {
168 this->ip = ip;
169 }
170
171 int ip;
172 };
173
174 bool
175 fs_generator::patch_discard_jumps_to_fb_writes()
176 {
177 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
178 return false;
179
180 int scale = brw_jump_scale(p->devinfo);
181
182 /* There is a somewhat strange undocumented requirement of using
183 * HALT, according to the simulator. If some channel has HALTed to
184 * a particular UIP, then by the end of the program, every channel
185 * must have HALTed to that UIP. Furthermore, the tracking is a
186 * stack, so you can't do the final halt of a UIP after starting
187 * halting to a new UIP.
188 *
189 * Symptoms of not emitting this instruction on actual hardware
190 * included GPU hangs and sparkly rendering on the piglit discard
191 * tests.
192 */
193 brw_inst *last_halt = gen6_HALT(p);
194 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
195 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
196
197 int ip = p->nr_insn;
198
199 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
200 brw_inst *patch = &p->store[patch_ip->ip];
201
202 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
203 /* HALT takes a half-instruction distance from the pre-incremented IP. */
204 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
205 }
206
207 this->discard_halt_patches.make_empty();
208 return true;
209 }
210
211 void
212 fs_generator::fire_fb_write(fs_inst *inst,
213 struct brw_reg payload,
214 struct brw_reg implied_header,
215 GLuint nr)
216 {
217 uint32_t msg_control;
218
219 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
220
221 if (devinfo->gen < 6) {
222 brw_push_insn_state(p);
223 brw_set_default_exec_size(p, BRW_EXECUTE_8);
224 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
225 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
226 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
227 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
228 brw_pop_insn_state(p);
229 }
230
231 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
232 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
233 else if (prog_data->dual_src_blend) {
234 if (!inst->force_sechalf)
235 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
236 else
237 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
238 } else if (inst->exec_size == 16)
239 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
240 else
241 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
242
243 uint32_t surf_index =
244 prog_data->binding_table.render_target_start + inst->target;
245
246 bool last_render_target = inst->eot ||
247 (prog_data->dual_src_blend && dispatch_width == 16);
248
249
250 brw_fb_WRITE(p,
251 dispatch_width,
252 payload,
253 implied_header,
254 msg_control,
255 surf_index,
256 nr,
257 0,
258 inst->eot,
259 last_render_target,
260 inst->header_size != 0);
261
262 brw_mark_surface_used(&prog_data->base, surf_index);
263 }
264
265 void
266 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
267 {
268 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
269 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
270 struct brw_reg implied_header;
271
272 if (devinfo->gen < 8 && !devinfo->is_haswell) {
273 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
274 }
275
276 if (inst->base_mrf >= 0)
277 payload = brw_message_reg(inst->base_mrf);
278
279 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
280 * move, here's g1.
281 */
282 if (inst->header_size != 0) {
283 brw_push_insn_state(p);
284 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
285 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
286 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
287 brw_set_default_flag_reg(p, 0, 0);
288
289 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
290 * present.
291 */
292 if (prog_data->uses_kill) {
293 struct brw_reg pixel_mask;
294
295 if (devinfo->gen >= 6)
296 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
297 else
298 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
299
300 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
301 }
302
303 if (devinfo->gen >= 6) {
304 brw_push_insn_state(p);
305 brw_set_default_exec_size(p, BRW_EXECUTE_16);
306 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
307 brw_MOV(p,
308 retype(payload, BRW_REGISTER_TYPE_UD),
309 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
310 brw_pop_insn_state(p);
311
312 if (inst->target > 0 && key->replicate_alpha) {
313 /* Set "Source0 Alpha Present to RenderTarget" bit in message
314 * header.
315 */
316 brw_OR(p,
317 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
318 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
319 brw_imm_ud(0x1 << 11));
320 }
321
322 if (inst->target > 0) {
323 /* Set the render target index for choosing BLEND_STATE. */
324 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
325 BRW_REGISTER_TYPE_UD),
326 brw_imm_ud(inst->target));
327 }
328
329 /* Set computes stencil to render target */
330 if (prog_data->computed_stencil) {
331 brw_OR(p,
332 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
333 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
334 brw_imm_ud(0x1 << 14));
335 }
336
337 implied_header = brw_null_reg();
338 } else {
339 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
340 }
341
342 brw_pop_insn_state(p);
343 } else {
344 implied_header = brw_null_reg();
345 }
346
347 if (!runtime_check_aads_emit) {
348 fire_fb_write(inst, payload, implied_header, inst->mlen);
349 } else {
350 /* This can only happen in gen < 6 */
351 assert(devinfo->gen < 6);
352
353 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
354
355 /* Check runtime bit to detect if we have to send AA data or not */
356 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
357 brw_AND(p,
358 v1_null_ud,
359 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
360 brw_imm_ud(1<<26));
361 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
362
363 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
364 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
365 {
366 /* Don't send AA data */
367 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
368 }
369 brw_land_fwd_jump(p, jmp);
370 fire_fb_write(inst, payload, implied_header, inst->mlen);
371 }
372 }
373
374 void
375 fs_generator::generate_urb_read(fs_inst *inst,
376 struct brw_reg dst,
377 struct brw_reg header)
378 {
379 assert(header.file == BRW_GENERAL_REGISTER_FILE);
380 assert(header.type == BRW_REGISTER_TYPE_UD);
381
382 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
383 brw_set_dest(p, send, dst);
384 brw_set_src0(p, send, header);
385 brw_set_src1(p, send, brw_imm_ud(0u));
386
387 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
388 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
389
390 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
391 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
392
393 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
394 brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
395 brw_inst_set_header_present(p->devinfo, send, true);
396 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
397 }
398
399 void
400 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
401 {
402 brw_inst *insn;
403
404 insn = brw_next_insn(p, BRW_OPCODE_SEND);
405
406 brw_set_dest(p, insn, brw_null_reg());
407 brw_set_src0(p, insn, payload);
408 brw_set_src1(p, insn, brw_imm_d(0));
409
410 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
411 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
412
413 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
414 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
415 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
416
417 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
418 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
419 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
420
421 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
422 brw_inst_set_rlen(p->devinfo, insn, 0);
423 brw_inst_set_eot(p->devinfo, insn, inst->eot);
424 brw_inst_set_header_present(p->devinfo, insn, true);
425 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
426 }
427
428 void
429 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
430 {
431 struct brw_inst *insn;
432
433 insn = brw_next_insn(p, BRW_OPCODE_SEND);
434
435 brw_set_dest(p, insn, brw_null_reg());
436 brw_set_src0(p, insn, payload);
437 brw_set_src1(p, insn, brw_imm_d(0));
438
439 /* Terminate a compute shader by sending a message to the thread spawner.
440 */
441 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
442 brw_inst_set_mlen(devinfo, insn, 1);
443 brw_inst_set_rlen(devinfo, insn, 0);
444 brw_inst_set_eot(devinfo, insn, inst->eot);
445 brw_inst_set_header_present(devinfo, insn, false);
446
447 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
448 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
449
450 /* Note that even though the thread has a URB resource associated with it,
451 * we set the "do not dereference URB" bit, because the URB resource is
452 * managed by the fixed-function unit, so it will free it automatically.
453 */
454 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
455
456 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
457 }
458
459 void
460 fs_generator::generate_stencil_ref_packing(fs_inst *inst,
461 struct brw_reg dst,
462 struct brw_reg src)
463 {
464 assert(dispatch_width == 8);
465 assert(devinfo->gen >= 9);
466
467 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
468 * Presumably, in order to save memory bandwidth, the stencil reference
469 * values written from the FS need to be packed into 2 dwords (this makes
470 * sense because the stencil values are limited to 1 byte each and a SIMD8
471 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
472 *
473 * The spec is confusing here because in the payload definition of MDP_RTW_S8
474 * (Message Data Payload for Render Target Writes with Stencil 8b) the
475 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
476 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
477 * packed values specified above and diagrammed below:
478 *
479 * 31 0
480 * --------------------------------
481 * DW | |
482 * 2-7 | IGNORED |
483 * | |
484 * --------------------------------
485 * DW1 | STC | STC | STC | STC |
486 * | slot7 | slot6 | slot5 | slot4|
487 * --------------------------------
488 * DW0 | STC | STC | STC | STC |
489 * | slot3 | slot2 | slot1 | slot0|
490 * --------------------------------
491 */
492
493 src.vstride = BRW_VERTICAL_STRIDE_4;
494 src.width = BRW_WIDTH_1;
495 src.hstride = BRW_HORIZONTAL_STRIDE_0;
496 assert(src.type == BRW_REGISTER_TYPE_UB);
497 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UB), src);
498 }
499
500 void
501 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
502 {
503 brw_barrier(p, src);
504 brw_WAIT(p);
505 }
506
507 void
508 fs_generator::generate_blorp_fb_write(fs_inst *inst)
509 {
510 brw_fb_WRITE(p,
511 16 /* dispatch_width */,
512 brw_message_reg(inst->base_mrf),
513 brw_reg_from_fs_reg(inst, &inst->src[0], devinfo->gen),
514 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
515 inst->target,
516 inst->mlen,
517 0,
518 true,
519 true,
520 inst->header_size != 0);
521 }
522
523 void
524 fs_generator::generate_linterp(fs_inst *inst,
525 struct brw_reg dst, struct brw_reg *src)
526 {
527 /* PLN reads:
528 * / in SIMD16 \
529 * -----------------------------------
530 * | src1+0 | src1+1 | src1+2 | src1+3 |
531 * |-----------------------------------|
532 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
533 * -----------------------------------
534 *
535 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
536 *
537 * -----------------------------------
538 * | src1+0 | src1+1 | src1+2 | src1+3 |
539 * |-----------------------------------|
540 * |(x0, x1)|(y0, y1)| | | in SIMD8
541 * |-----------------------------------|
542 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
543 * -----------------------------------
544 *
545 * See also: emit_interpolation_setup_gen4().
546 */
547 struct brw_reg delta_x = src[0];
548 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
549 struct brw_reg interp = src[1];
550
551 if (devinfo->has_pln &&
552 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
553 brw_PLN(p, dst, interp, delta_x);
554 } else {
555 brw_LINE(p, brw_null_reg(), interp, delta_x);
556 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
557 }
558 }
559
560 void
561 fs_generator::generate_math_gen6(fs_inst *inst,
562 struct brw_reg dst,
563 struct brw_reg src0,
564 struct brw_reg src1)
565 {
566 int op = brw_math_function(inst->opcode);
567 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
568
569 if (dispatch_width == 8) {
570 gen6_math(p, dst, op, src0, src1);
571 } else if (dispatch_width == 16) {
572 brw_push_insn_state(p);
573 brw_set_default_exec_size(p, BRW_EXECUTE_8);
574 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
575 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
576 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
577 gen6_math(p, sechalf(dst), op, sechalf(src0),
578 binop ? sechalf(src1) : brw_null_reg());
579 brw_pop_insn_state(p);
580 }
581 }
582
583 void
584 fs_generator::generate_math_gen4(fs_inst *inst,
585 struct brw_reg dst,
586 struct brw_reg src)
587 {
588 int op = brw_math_function(inst->opcode);
589
590 assert(inst->mlen >= 1);
591
592 if (dispatch_width == 8) {
593 gen4_math(p, dst,
594 op,
595 inst->base_mrf, src,
596 BRW_MATH_PRECISION_FULL);
597 } else if (dispatch_width == 16) {
598 brw_set_default_exec_size(p, BRW_EXECUTE_8);
599 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
600 gen4_math(p, firsthalf(dst),
601 op,
602 inst->base_mrf, firsthalf(src),
603 BRW_MATH_PRECISION_FULL);
604 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
605 gen4_math(p, sechalf(dst),
606 op,
607 inst->base_mrf + 1, sechalf(src),
608 BRW_MATH_PRECISION_FULL);
609
610 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
611 }
612 }
613
614 void
615 fs_generator::generate_math_g45(fs_inst *inst,
616 struct brw_reg dst,
617 struct brw_reg src)
618 {
619 if (inst->opcode == SHADER_OPCODE_POW ||
620 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
621 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
622 generate_math_gen4(inst, dst, src);
623 return;
624 }
625
626 int op = brw_math_function(inst->opcode);
627
628 assert(inst->mlen >= 1);
629
630 gen4_math(p, dst,
631 op,
632 inst->base_mrf, src,
633 BRW_MATH_PRECISION_FULL);
634 }
635
636 void
637 fs_generator::generate_get_buffer_size(fs_inst *inst,
638 struct brw_reg dst,
639 struct brw_reg src,
640 struct brw_reg surf_index)
641 {
642 assert(devinfo->gen >= 7);
643 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
644
645 uint32_t simd_mode;
646 int rlen = 4;
647
648 switch (inst->exec_size) {
649 case 8:
650 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
651 break;
652 case 16:
653 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
654 break;
655 default:
656 unreachable("Invalid width for texture instruction");
657 }
658
659 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
660 rlen = 8;
661 dst = vec16(dst);
662 }
663
664 brw_SAMPLE(p,
665 retype(dst, BRW_REGISTER_TYPE_UW),
666 inst->base_mrf,
667 src,
668 surf_index.ud,
669 0,
670 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
671 rlen, /* response length */
672 inst->mlen,
673 inst->header_size > 0,
674 simd_mode,
675 BRW_SAMPLER_RETURN_FORMAT_SINT32);
676
677 brw_mark_surface_used(prog_data, surf_index.ud);
678 }
679
680 void
681 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
682 struct brw_reg surface_index,
683 struct brw_reg sampler_index)
684 {
685 int msg_type = -1;
686 int rlen = 4;
687 uint32_t simd_mode;
688 uint32_t return_format;
689 bool is_combined_send = inst->eot;
690
691 switch (dst.type) {
692 case BRW_REGISTER_TYPE_D:
693 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
694 break;
695 case BRW_REGISTER_TYPE_UD:
696 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
697 break;
698 default:
699 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
700 break;
701 }
702
703 switch (inst->exec_size) {
704 case 8:
705 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
706 break;
707 case 16:
708 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
709 break;
710 default:
711 unreachable("Invalid width for texture instruction");
712 }
713
714 if (devinfo->gen >= 5) {
715 switch (inst->opcode) {
716 case SHADER_OPCODE_TEX:
717 if (inst->shadow_compare) {
718 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
719 } else {
720 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
721 }
722 break;
723 case FS_OPCODE_TXB:
724 if (inst->shadow_compare) {
725 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
726 } else {
727 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
728 }
729 break;
730 case SHADER_OPCODE_TXL:
731 if (inst->shadow_compare) {
732 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
733 } else {
734 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
735 }
736 break;
737 case SHADER_OPCODE_TXS:
738 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
739 break;
740 case SHADER_OPCODE_TXD:
741 if (inst->shadow_compare) {
742 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
743 assert(devinfo->gen >= 8 || devinfo->is_haswell);
744 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
745 } else {
746 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
747 }
748 break;
749 case SHADER_OPCODE_TXF:
750 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
751 break;
752 case SHADER_OPCODE_TXF_CMS_W:
753 assert(devinfo->gen >= 9);
754 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
755 break;
756 case SHADER_OPCODE_TXF_CMS:
757 if (devinfo->gen >= 7)
758 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
759 else
760 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
761 break;
762 case SHADER_OPCODE_TXF_UMS:
763 assert(devinfo->gen >= 7);
764 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
765 break;
766 case SHADER_OPCODE_TXF_MCS:
767 assert(devinfo->gen >= 7);
768 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
769 break;
770 case SHADER_OPCODE_LOD:
771 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
772 break;
773 case SHADER_OPCODE_TG4:
774 if (inst->shadow_compare) {
775 assert(devinfo->gen >= 7);
776 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
777 } else {
778 assert(devinfo->gen >= 6);
779 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
780 }
781 break;
782 case SHADER_OPCODE_TG4_OFFSET:
783 assert(devinfo->gen >= 7);
784 if (inst->shadow_compare) {
785 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
786 } else {
787 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
788 }
789 break;
790 case SHADER_OPCODE_SAMPLEINFO:
791 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
792 break;
793 default:
794 unreachable("not reached");
795 }
796 } else {
797 switch (inst->opcode) {
798 case SHADER_OPCODE_TEX:
799 /* Note that G45 and older determines shadow compare and dispatch width
800 * from message length for most messages.
801 */
802 if (inst->exec_size == 8) {
803 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
804 if (inst->shadow_compare) {
805 assert(inst->mlen == 6);
806 } else {
807 assert(inst->mlen <= 4);
808 }
809 } else {
810 if (inst->shadow_compare) {
811 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
812 assert(inst->mlen == 9);
813 } else {
814 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
815 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
816 }
817 }
818 break;
819 case FS_OPCODE_TXB:
820 if (inst->shadow_compare) {
821 assert(inst->exec_size == 8);
822 assert(inst->mlen == 6);
823 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
824 } else {
825 assert(inst->mlen == 9);
826 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
827 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
828 }
829 break;
830 case SHADER_OPCODE_TXL:
831 if (inst->shadow_compare) {
832 assert(inst->exec_size == 8);
833 assert(inst->mlen == 6);
834 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
835 } else {
836 assert(inst->mlen == 9);
837 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
838 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
839 }
840 break;
841 case SHADER_OPCODE_TXD:
842 /* There is no sample_d_c message; comparisons are done manually */
843 assert(inst->exec_size == 8);
844 assert(inst->mlen == 7 || inst->mlen == 10);
845 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
846 break;
847 case SHADER_OPCODE_TXF:
848 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
849 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
850 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
851 break;
852 case SHADER_OPCODE_TXS:
853 assert(inst->mlen == 3);
854 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
855 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
856 break;
857 default:
858 unreachable("not reached");
859 }
860 }
861 assert(msg_type != -1);
862
863 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
864 rlen = 8;
865 dst = vec16(dst);
866 }
867
868 if (is_combined_send) {
869 assert(devinfo->gen >= 9 || devinfo->is_cherryview);
870 rlen = 0;
871 }
872
873 assert(devinfo->gen < 7 || inst->header_size == 0 ||
874 src.file == BRW_GENERAL_REGISTER_FILE);
875
876 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
877
878 /* Load the message header if present. If there's a texture offset,
879 * we need to set it up explicitly and load the offset bitfield.
880 * Otherwise, we can use an implied move from g0 to the first message reg.
881 */
882 if (inst->header_size != 0) {
883 if (devinfo->gen < 6 && !inst->offset) {
884 /* Set up an implied move from g0 to the MRF. */
885 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
886 } else {
887 struct brw_reg header_reg;
888
889 if (devinfo->gen >= 7) {
890 header_reg = src;
891 } else {
892 assert(inst->base_mrf != -1);
893 header_reg = brw_message_reg(inst->base_mrf);
894 }
895
896 brw_push_insn_state(p);
897 brw_set_default_exec_size(p, BRW_EXECUTE_8);
898 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
899 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
900 /* Explicitly set up the message header by copying g0 to the MRF. */
901 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
902
903 if (inst->offset) {
904 /* Set the offset bits in DWord 2. */
905 brw_MOV(p, get_element_ud(header_reg, 2),
906 brw_imm_ud(inst->offset));
907 }
908
909 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
910 brw_pop_insn_state(p);
911 }
912 }
913
914 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
915 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
916 ? prog_data->binding_table.gather_texture_start
917 : prog_data->binding_table.texture_start;
918
919 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
920 sampler_index.file == BRW_IMMEDIATE_VALUE) {
921 uint32_t surface = surface_index.ud;
922 uint32_t sampler = sampler_index.ud;
923
924 brw_SAMPLE(p,
925 retype(dst, BRW_REGISTER_TYPE_UW),
926 inst->base_mrf,
927 src,
928 surface + base_binding_table_index,
929 sampler % 16,
930 msg_type,
931 rlen,
932 inst->mlen,
933 inst->header_size != 0,
934 simd_mode,
935 return_format);
936
937 brw_mark_surface_used(prog_data, surface + base_binding_table_index);
938 } else {
939 /* Non-const sampler index */
940
941 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
942 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
943 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
944
945 brw_push_insn_state(p);
946 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
947 brw_set_default_access_mode(p, BRW_ALIGN_1);
948
949 if (memcmp(&surface_reg, &sampler_reg, sizeof(surface_reg)) == 0) {
950 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
951 } else {
952 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
953 brw_OR(p, addr, addr, surface_reg);
954 }
955 if (base_binding_table_index)
956 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
957 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
958
959 brw_pop_insn_state(p);
960
961 /* dst = send(offset, a0.0 | <descriptor>) */
962 brw_inst *insn = brw_send_indirect_message(
963 p, BRW_SFID_SAMPLER, dst, src, addr);
964 brw_set_sampler_message(p, insn,
965 0 /* surface */,
966 0 /* sampler */,
967 msg_type,
968 rlen,
969 inst->mlen /* mlen */,
970 inst->header_size != 0 /* header */,
971 simd_mode,
972 return_format);
973
974 /* visitor knows more than we do about the surface limit required,
975 * so has already done marking.
976 */
977 }
978
979 if (is_combined_send) {
980 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
981 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
982 }
983 }
984
985
986 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
987 * looking like:
988 *
989 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
990 *
991 * Ideally, we want to produce:
992 *
993 * DDX DDY
994 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
995 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
996 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
997 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
998 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
999 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1000 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1001 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1002 *
1003 * and add another set of two more subspans if in 16-pixel dispatch mode.
1004 *
1005 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1006 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1007 * pair. But the ideal approximation may impose a huge performance cost on
1008 * sample_d. On at least Haswell, sample_d instruction does some
1009 * optimizations if the same LOD is used for all pixels in the subspan.
1010 *
1011 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1012 * appropriate swizzling.
1013 */
1014 void
1015 fs_generator::generate_ddx(enum opcode opcode,
1016 struct brw_reg dst, struct brw_reg src)
1017 {
1018 unsigned vstride, width;
1019
1020 if (opcode == FS_OPCODE_DDX_FINE) {
1021 /* produce accurate derivatives */
1022 vstride = BRW_VERTICAL_STRIDE_2;
1023 width = BRW_WIDTH_2;
1024 } else {
1025 /* replicate the derivative at the top-left pixel to other pixels */
1026 vstride = BRW_VERTICAL_STRIDE_4;
1027 width = BRW_WIDTH_4;
1028 }
1029
1030 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
1031 src.negate, src.abs,
1032 BRW_REGISTER_TYPE_F,
1033 vstride,
1034 width,
1035 BRW_HORIZONTAL_STRIDE_0,
1036 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1037 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1038 src.negate, src.abs,
1039 BRW_REGISTER_TYPE_F,
1040 vstride,
1041 width,
1042 BRW_HORIZONTAL_STRIDE_0,
1043 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1044 brw_ADD(p, dst, src0, negate(src1));
1045 }
1046
1047 /* The negate_value boolean is used to negate the derivative computation for
1048 * FBOs, since they place the origin at the upper left instead of the lower
1049 * left.
1050 */
1051 void
1052 fs_generator::generate_ddy(enum opcode opcode,
1053 struct brw_reg dst, struct brw_reg src,
1054 bool negate_value)
1055 {
1056 if (opcode == FS_OPCODE_DDY_FINE) {
1057 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1058 * Region Restrictions):
1059 *
1060 * In Align16 access mode, SIMD16 is not allowed for DW operations
1061 * and SIMD8 is not allowed for DF operations.
1062 *
1063 * In this context, "DW operations" means "operations acting on 32-bit
1064 * values", so it includes operations on floats.
1065 *
1066 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1067 * (Instruction Compression -> Rules and Restrictions):
1068 *
1069 * A compressed instruction must be in Align1 access mode. Align16
1070 * mode instructions cannot be compressed.
1071 *
1072 * Similar text exists in the g45 PRM.
1073 *
1074 * On these platforms, if we're building a SIMD16 shader, we need to
1075 * manually unroll to a pair of SIMD8 instructions.
1076 */
1077 bool unroll_to_simd8 =
1078 (dispatch_width == 16 &&
1079 (devinfo->gen == 4 || (devinfo->gen == 7 && !devinfo->is_haswell)));
1080
1081 /* produce accurate derivatives */
1082 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1083 src.negate, src.abs,
1084 BRW_REGISTER_TYPE_F,
1085 BRW_VERTICAL_STRIDE_4,
1086 BRW_WIDTH_4,
1087 BRW_HORIZONTAL_STRIDE_1,
1088 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
1089 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1090 src.negate, src.abs,
1091 BRW_REGISTER_TYPE_F,
1092 BRW_VERTICAL_STRIDE_4,
1093 BRW_WIDTH_4,
1094 BRW_HORIZONTAL_STRIDE_1,
1095 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
1096 brw_push_insn_state(p);
1097 brw_set_default_access_mode(p, BRW_ALIGN_16);
1098 if (unroll_to_simd8) {
1099 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1100 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1101 if (negate_value) {
1102 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
1103 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1104 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
1105 } else {
1106 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
1107 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1108 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
1109 }
1110 } else {
1111 if (negate_value)
1112 brw_ADD(p, dst, src1, negate(src0));
1113 else
1114 brw_ADD(p, dst, src0, negate(src1));
1115 }
1116 brw_pop_insn_state(p);
1117 } else {
1118 /* replicate the derivative at the top-left pixel to other pixels */
1119 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1120 src.negate, src.abs,
1121 BRW_REGISTER_TYPE_F,
1122 BRW_VERTICAL_STRIDE_4,
1123 BRW_WIDTH_4,
1124 BRW_HORIZONTAL_STRIDE_0,
1125 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1126 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1127 src.negate, src.abs,
1128 BRW_REGISTER_TYPE_F,
1129 BRW_VERTICAL_STRIDE_4,
1130 BRW_WIDTH_4,
1131 BRW_HORIZONTAL_STRIDE_0,
1132 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1133 if (negate_value)
1134 brw_ADD(p, dst, src1, negate(src0));
1135 else
1136 brw_ADD(p, dst, src0, negate(src1));
1137 }
1138 }
1139
1140 void
1141 fs_generator::generate_discard_jump(fs_inst *inst)
1142 {
1143 assert(devinfo->gen >= 6);
1144
1145 /* This HALT will be patched up at FB write time to point UIP at the end of
1146 * the program, and at brw_uip_jip() JIP will be set to the end of the
1147 * current block (or the program).
1148 */
1149 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1150
1151 brw_push_insn_state(p);
1152 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1153 gen6_HALT(p);
1154 brw_pop_insn_state(p);
1155 }
1156
1157 void
1158 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1159 {
1160 assert(inst->mlen != 0);
1161
1162 brw_MOV(p,
1163 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1164 retype(src, BRW_REGISTER_TYPE_UD));
1165 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1166 inst->exec_size / 8, inst->offset);
1167 }
1168
1169 void
1170 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1171 {
1172 assert(inst->mlen != 0);
1173
1174 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1175 inst->exec_size / 8, inst->offset);
1176 }
1177
1178 void
1179 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1180 {
1181 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1182 }
1183
1184 void
1185 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1186 struct brw_reg dst,
1187 struct brw_reg index,
1188 struct brw_reg offset)
1189 {
1190 assert(inst->mlen != 0);
1191
1192 assert(index.file == BRW_IMMEDIATE_VALUE &&
1193 index.type == BRW_REGISTER_TYPE_UD);
1194 uint32_t surf_index = index.ud;
1195
1196 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1197 offset.type == BRW_REGISTER_TYPE_UD);
1198 uint32_t read_offset = offset.ud;
1199
1200 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1201 read_offset, surf_index);
1202 }
1203
1204 void
1205 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1206 struct brw_reg dst,
1207 struct brw_reg index,
1208 struct brw_reg offset)
1209 {
1210 assert(index.type == BRW_REGISTER_TYPE_UD);
1211
1212 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1213 /* Reference just the dword we need, to avoid angering validate_reg(). */
1214 offset = brw_vec1_grf(offset.nr, 0);
1215
1216 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1217 * the destination loaded consecutively from the same offset (which appears
1218 * in the first component, and the rest are ignored).
1219 */
1220 dst.width = BRW_WIDTH_4;
1221
1222 struct brw_reg src = offset;
1223 bool header_present = false;
1224
1225 if (devinfo->gen >= 9) {
1226 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1227 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1228 header_present = true;
1229
1230 brw_push_insn_state(p);
1231 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1232 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1233 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1234 brw_set_default_access_mode(p, BRW_ALIGN_1);
1235
1236 brw_MOV(p, get_element_ud(src, 2),
1237 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1238 brw_pop_insn_state(p);
1239 }
1240
1241 if (index.file == BRW_IMMEDIATE_VALUE) {
1242
1243 uint32_t surf_index = index.ud;
1244
1245 brw_push_insn_state(p);
1246 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1247 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1248 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1249 brw_pop_insn_state(p);
1250
1251 brw_set_dest(p, send, dst);
1252 brw_set_src0(p, send, src);
1253 brw_set_sampler_message(p, send,
1254 surf_index,
1255 0, /* LD message ignores sampler unit */
1256 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1257 1, /* rlen */
1258 inst->mlen,
1259 header_present,
1260 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1261 0);
1262 } else {
1263
1264 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1265
1266 brw_push_insn_state(p);
1267 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1268 brw_set_default_access_mode(p, BRW_ALIGN_1);
1269
1270 /* a0.0 = surf_index & 0xff */
1271 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1272 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1273 brw_set_dest(p, insn_and, addr);
1274 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1275 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1276
1277 /* dst = send(payload, a0.0 | <descriptor>) */
1278 brw_inst *insn = brw_send_indirect_message(
1279 p, BRW_SFID_SAMPLER, dst, src, addr);
1280 brw_set_sampler_message(p, insn,
1281 0,
1282 0, /* LD message ignores sampler unit */
1283 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1284 1, /* rlen */
1285 inst->mlen,
1286 header_present,
1287 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1288 0);
1289
1290 brw_pop_insn_state(p);
1291 }
1292 }
1293
1294 void
1295 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1296 struct brw_reg dst,
1297 struct brw_reg index,
1298 struct brw_reg offset)
1299 {
1300 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1301 assert(inst->header_size != 0);
1302 assert(inst->mlen);
1303
1304 assert(index.file == BRW_IMMEDIATE_VALUE &&
1305 index.type == BRW_REGISTER_TYPE_UD);
1306 uint32_t surf_index = index.ud;
1307
1308 uint32_t simd_mode, rlen, msg_type;
1309 if (dispatch_width == 16) {
1310 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1311 rlen = 8;
1312 } else {
1313 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1314 rlen = 4;
1315 }
1316
1317 if (devinfo->gen >= 5)
1318 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1319 else {
1320 /* We always use the SIMD16 message so that we only have to load U, and
1321 * not V or R.
1322 */
1323 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1324 assert(inst->mlen == 3);
1325 assert(inst->regs_written == 8);
1326 rlen = 8;
1327 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1328 }
1329
1330 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1331 BRW_REGISTER_TYPE_D);
1332 brw_MOV(p, offset_mrf, offset);
1333
1334 struct brw_reg header = brw_vec8_grf(0, 0);
1335 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1336
1337 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1338 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1339 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1340 brw_set_src0(p, send, header);
1341 if (devinfo->gen < 6)
1342 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1343
1344 /* Our surface is set up as floats, regardless of what actual data is
1345 * stored in it.
1346 */
1347 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1348 brw_set_sampler_message(p, send,
1349 surf_index,
1350 0, /* sampler (unused) */
1351 msg_type,
1352 rlen,
1353 inst->mlen,
1354 inst->header_size != 0,
1355 simd_mode,
1356 return_format);
1357 }
1358
1359 void
1360 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1361 struct brw_reg dst,
1362 struct brw_reg index,
1363 struct brw_reg offset)
1364 {
1365 assert(devinfo->gen >= 7);
1366 /* Varying-offset pull constant loads are treated as a normal expression on
1367 * gen7, so the fact that it's a send message is hidden at the IR level.
1368 */
1369 assert(inst->header_size == 0);
1370 assert(!inst->mlen);
1371 assert(index.type == BRW_REGISTER_TYPE_UD);
1372
1373 uint32_t simd_mode, rlen, mlen;
1374 if (dispatch_width == 16) {
1375 mlen = 2;
1376 rlen = 8;
1377 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1378 } else {
1379 mlen = 1;
1380 rlen = 4;
1381 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1382 }
1383
1384 if (index.file == BRW_IMMEDIATE_VALUE) {
1385
1386 uint32_t surf_index = index.ud;
1387
1388 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1389 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1390 brw_set_src0(p, send, offset);
1391 brw_set_sampler_message(p, send,
1392 surf_index,
1393 0, /* LD message ignores sampler unit */
1394 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1395 rlen,
1396 mlen,
1397 false, /* no header */
1398 simd_mode,
1399 0);
1400
1401 } else {
1402
1403 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1404
1405 brw_push_insn_state(p);
1406 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1407 brw_set_default_access_mode(p, BRW_ALIGN_1);
1408
1409 /* a0.0 = surf_index & 0xff */
1410 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1411 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1412 brw_set_dest(p, insn_and, addr);
1413 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1414 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1415
1416 brw_pop_insn_state(p);
1417
1418 /* dst = send(offset, a0.0 | <descriptor>) */
1419 brw_inst *insn = brw_send_indirect_message(
1420 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1421 offset, addr);
1422 brw_set_sampler_message(p, insn,
1423 0 /* surface */,
1424 0 /* sampler */,
1425 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1426 rlen /* rlen */,
1427 mlen /* mlen */,
1428 false /* header */,
1429 simd_mode,
1430 0);
1431 }
1432 }
1433
1434 /**
1435 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1436 * into the flags register (f0.0).
1437 *
1438 * Used only on Gen6 and above.
1439 */
1440 void
1441 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1442 {
1443 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1444 struct brw_reg dispatch_mask;
1445
1446 if (devinfo->gen >= 6)
1447 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1448 else
1449 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1450
1451 brw_push_insn_state(p);
1452 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1453 brw_MOV(p, flags, dispatch_mask);
1454 brw_pop_insn_state(p);
1455 }
1456
1457 void
1458 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1459 struct brw_reg dst,
1460 struct brw_reg src,
1461 struct brw_reg msg_data,
1462 unsigned msg_type)
1463 {
1464 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1465
1466 brw_pixel_interpolator_query(p,
1467 retype(dst, BRW_REGISTER_TYPE_UW),
1468 src,
1469 inst->pi_noperspective,
1470 msg_type,
1471 msg_data,
1472 inst->mlen,
1473 inst->regs_written);
1474 }
1475
1476
1477 /**
1478 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1479 * sampler LD messages.
1480 *
1481 * We don't want to bake it into the send message's code generation because
1482 * that means we don't get a chance to schedule the instructions.
1483 */
1484 void
1485 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1486 struct brw_reg dst,
1487 struct brw_reg value)
1488 {
1489 assert(value.file == BRW_IMMEDIATE_VALUE);
1490
1491 brw_push_insn_state(p);
1492 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1493 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1494 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1495 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1496 brw_pop_insn_state(p);
1497 }
1498
1499 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1500 * the ADD instruction.
1501 */
1502 void
1503 fs_generator::generate_set_sample_id(fs_inst *inst,
1504 struct brw_reg dst,
1505 struct brw_reg src0,
1506 struct brw_reg src1)
1507 {
1508 assert(dst.type == BRW_REGISTER_TYPE_D ||
1509 dst.type == BRW_REGISTER_TYPE_UD);
1510 assert(src0.type == BRW_REGISTER_TYPE_D ||
1511 src0.type == BRW_REGISTER_TYPE_UD);
1512
1513 struct brw_reg reg = stride(src1, 1, 4, 0);
1514 if (devinfo->gen >= 8 || dispatch_width == 8) {
1515 brw_ADD(p, dst, src0, reg);
1516 } else if (dispatch_width == 16) {
1517 brw_push_insn_state(p);
1518 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1519 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1520 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1521 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1522 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1523 brw_pop_insn_state(p);
1524 }
1525 }
1526
1527 void
1528 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1529 struct brw_reg dst,
1530 struct brw_reg x,
1531 struct brw_reg y)
1532 {
1533 assert(devinfo->gen >= 7);
1534 assert(dst.type == BRW_REGISTER_TYPE_UD);
1535 assert(x.type == BRW_REGISTER_TYPE_F);
1536 assert(y.type == BRW_REGISTER_TYPE_F);
1537
1538 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1539 *
1540 * Because this instruction does not have a 16-bit floating-point type,
1541 * the destination data type must be Word (W).
1542 *
1543 * The destination must be DWord-aligned and specify a horizontal stride
1544 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1545 * each destination channel and the upper word is not modified.
1546 */
1547 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1548
1549 /* Give each 32-bit channel of dst the form below, where "." means
1550 * unchanged.
1551 * 0x....hhhh
1552 */
1553 brw_F32TO16(p, dst_w, y);
1554
1555 /* Now the form:
1556 * 0xhhhh0000
1557 */
1558 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1559
1560 /* And, finally the form of packHalf2x16's output:
1561 * 0xhhhhllll
1562 */
1563 brw_F32TO16(p, dst_w, x);
1564 }
1565
1566 void
1567 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1568 struct brw_reg dst,
1569 struct brw_reg src)
1570 {
1571 assert(devinfo->gen >= 7);
1572 assert(dst.type == BRW_REGISTER_TYPE_F);
1573 assert(src.type == BRW_REGISTER_TYPE_UD);
1574
1575 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1576 *
1577 * Because this instruction does not have a 16-bit floating-point type,
1578 * the source data type must be Word (W). The destination type must be
1579 * F (Float).
1580 */
1581 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1582
1583 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1584 * For the Y case, we wish to access only the upper word; therefore
1585 * a 16-bit subregister offset is needed.
1586 */
1587 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1588 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1589 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1590 src_w.subnr += 2;
1591
1592 brw_F16TO32(p, dst, src_w);
1593 }
1594
1595 void
1596 fs_generator::generate_shader_time_add(fs_inst *inst,
1597 struct brw_reg payload,
1598 struct brw_reg offset,
1599 struct brw_reg value)
1600 {
1601 assert(devinfo->gen >= 7);
1602 brw_push_insn_state(p);
1603 brw_set_default_mask_control(p, true);
1604
1605 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1606 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1607 offset.type);
1608 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1609 value.type);
1610
1611 assert(offset.file == BRW_IMMEDIATE_VALUE);
1612 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1613 value.width = BRW_WIDTH_1;
1614 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1615 value.vstride = BRW_VERTICAL_STRIDE_0;
1616 } else {
1617 assert(value.file == BRW_IMMEDIATE_VALUE);
1618 }
1619
1620 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1621 * case, and we don't really care about squeezing every bit of performance
1622 * out of this path, so we just emit the MOVs from here.
1623 */
1624 brw_MOV(p, payload_offset, offset);
1625 brw_MOV(p, payload_value, value);
1626 brw_shader_time_add(p, payload,
1627 prog_data->binding_table.shader_time_start);
1628 brw_pop_insn_state(p);
1629
1630 brw_mark_surface_used(prog_data,
1631 prog_data->binding_table.shader_time_start);
1632 }
1633
1634 void
1635 fs_generator::enable_debug(const char *shader_name)
1636 {
1637 debug_flag = true;
1638 this->shader_name = shader_name;
1639 }
1640
1641 int
1642 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1643 {
1644 /* align to 64 byte boundary. */
1645 while (p->next_insn_offset % 64)
1646 brw_NOP(p);
1647
1648 this->dispatch_width = dispatch_width;
1649 if (dispatch_width == 16)
1650 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1651
1652 int start_offset = p->next_insn_offset;
1653 int spill_count = 0, fill_count = 0;
1654 int loop_count = 0;
1655
1656 struct annotation_info annotation;
1657 memset(&annotation, 0, sizeof(annotation));
1658
1659 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1660 struct brw_reg src[3], dst;
1661 unsigned int last_insn_offset = p->next_insn_offset;
1662 bool multiple_instructions_emitted = false;
1663
1664 if (unlikely(debug_flag))
1665 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1666
1667 for (unsigned int i = 0; i < inst->sources; i++) {
1668 src[i] = brw_reg_from_fs_reg(inst, &inst->src[i], devinfo->gen);
1669
1670 /* The accumulator result appears to get used for the
1671 * conditional modifier generation. When negating a UD
1672 * value, there is a 33rd bit generated for the sign in the
1673 * accumulator value, so now you can't check, for example,
1674 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1675 */
1676 assert(!inst->conditional_mod ||
1677 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1678 !inst->src[i].negate);
1679 }
1680 dst = brw_reg_from_fs_reg(inst, &inst->dst, devinfo->gen);
1681
1682 brw_set_default_predicate_control(p, inst->predicate);
1683 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1684 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1685 brw_set_default_saturate(p, inst->saturate);
1686 brw_set_default_mask_control(p, inst->force_writemask_all);
1687 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1688 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1689
1690 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1691 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1692
1693 switch (inst->exec_size) {
1694 case 1:
1695 case 2:
1696 case 4:
1697 assert(inst->force_writemask_all);
1698 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1699 break;
1700 case 8:
1701 if (inst->force_sechalf) {
1702 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1703 } else {
1704 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1705 }
1706 break;
1707 case 16:
1708 case 32:
1709 /* If the instruction writes to more than one register, it needs to
1710 * be a "compressed" instruction on Gen <= 5.
1711 */
1712 if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
1713 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1714 else
1715 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1716 break;
1717 default:
1718 unreachable("Invalid instruction width");
1719 }
1720
1721 switch (inst->opcode) {
1722 case BRW_OPCODE_MOV:
1723 brw_MOV(p, dst, src[0]);
1724 break;
1725 case BRW_OPCODE_ADD:
1726 brw_ADD(p, dst, src[0], src[1]);
1727 break;
1728 case BRW_OPCODE_MUL:
1729 brw_MUL(p, dst, src[0], src[1]);
1730 break;
1731 case BRW_OPCODE_AVG:
1732 brw_AVG(p, dst, src[0], src[1]);
1733 break;
1734 case BRW_OPCODE_MACH:
1735 brw_MACH(p, dst, src[0], src[1]);
1736 break;
1737
1738 case BRW_OPCODE_LINE:
1739 brw_LINE(p, dst, src[0], src[1]);
1740 break;
1741
1742 case BRW_OPCODE_MAD:
1743 assert(devinfo->gen >= 6);
1744 brw_set_default_access_mode(p, BRW_ALIGN_16);
1745 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1746 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1747 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1748 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1749 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1750 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1751 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1752
1753 if (inst->conditional_mod) {
1754 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1755 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1756 multiple_instructions_emitted = true;
1757 }
1758 } else {
1759 brw_MAD(p, dst, src[0], src[1], src[2]);
1760 }
1761 brw_set_default_access_mode(p, BRW_ALIGN_1);
1762 break;
1763
1764 case BRW_OPCODE_LRP:
1765 assert(devinfo->gen >= 6);
1766 brw_set_default_access_mode(p, BRW_ALIGN_16);
1767 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1768 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1769 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1770 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1771 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1772 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1773 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1774
1775 if (inst->conditional_mod) {
1776 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1777 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1778 multiple_instructions_emitted = true;
1779 }
1780 } else {
1781 brw_LRP(p, dst, src[0], src[1], src[2]);
1782 }
1783 brw_set_default_access_mode(p, BRW_ALIGN_1);
1784 break;
1785
1786 case BRW_OPCODE_FRC:
1787 brw_FRC(p, dst, src[0]);
1788 break;
1789 case BRW_OPCODE_RNDD:
1790 brw_RNDD(p, dst, src[0]);
1791 break;
1792 case BRW_OPCODE_RNDE:
1793 brw_RNDE(p, dst, src[0]);
1794 break;
1795 case BRW_OPCODE_RNDZ:
1796 brw_RNDZ(p, dst, src[0]);
1797 break;
1798
1799 case BRW_OPCODE_AND:
1800 brw_AND(p, dst, src[0], src[1]);
1801 break;
1802 case BRW_OPCODE_OR:
1803 brw_OR(p, dst, src[0], src[1]);
1804 break;
1805 case BRW_OPCODE_XOR:
1806 brw_XOR(p, dst, src[0], src[1]);
1807 break;
1808 case BRW_OPCODE_NOT:
1809 brw_NOT(p, dst, src[0]);
1810 break;
1811 case BRW_OPCODE_ASR:
1812 brw_ASR(p, dst, src[0], src[1]);
1813 break;
1814 case BRW_OPCODE_SHR:
1815 brw_SHR(p, dst, src[0], src[1]);
1816 break;
1817 case BRW_OPCODE_SHL:
1818 brw_SHL(p, dst, src[0], src[1]);
1819 break;
1820 case BRW_OPCODE_F32TO16:
1821 assert(devinfo->gen >= 7);
1822 brw_F32TO16(p, dst, src[0]);
1823 break;
1824 case BRW_OPCODE_F16TO32:
1825 assert(devinfo->gen >= 7);
1826 brw_F16TO32(p, dst, src[0]);
1827 break;
1828 case BRW_OPCODE_CMP:
1829 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1830 * that when the destination is a GRF that the dependency-clear bit on
1831 * the flag register is cleared early.
1832 *
1833 * Suggested workarounds are to disable coissuing CMP instructions
1834 * or to split CMP(16) instructions into two CMP(8) instructions.
1835 *
1836 * We choose to split into CMP(8) instructions since disabling
1837 * coissuing would affect CMP instructions not otherwise affected by
1838 * the errata.
1839 */
1840 if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) {
1841 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1842 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1843 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1844 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1845 firsthalf(src[0]), firsthalf(src[1]));
1846 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1847 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1848 sechalf(src[0]), sechalf(src[1]));
1849 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1850
1851 multiple_instructions_emitted = true;
1852 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1853 /* For unknown reasons, the aforementioned workaround is not
1854 * sufficient. Overriding the type when the destination is the
1855 * null register is necessary but not sufficient by itself.
1856 */
1857 assert(dst.nr == BRW_ARF_NULL);
1858 dst.type = BRW_REGISTER_TYPE_D;
1859 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1860 } else {
1861 unreachable("not reached");
1862 }
1863 } else {
1864 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1865 }
1866 break;
1867 case BRW_OPCODE_SEL:
1868 brw_SEL(p, dst, src[0], src[1]);
1869 break;
1870 case BRW_OPCODE_BFREV:
1871 assert(devinfo->gen >= 7);
1872 /* BFREV only supports UD type for src and dst. */
1873 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1874 retype(src[0], BRW_REGISTER_TYPE_UD));
1875 break;
1876 case BRW_OPCODE_FBH:
1877 assert(devinfo->gen >= 7);
1878 /* FBH only supports UD type for dst. */
1879 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1880 break;
1881 case BRW_OPCODE_FBL:
1882 assert(devinfo->gen >= 7);
1883 /* FBL only supports UD type for dst. */
1884 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1885 break;
1886 case BRW_OPCODE_CBIT:
1887 assert(devinfo->gen >= 7);
1888 /* CBIT only supports UD type for dst. */
1889 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1890 break;
1891 case BRW_OPCODE_ADDC:
1892 assert(devinfo->gen >= 7);
1893 brw_ADDC(p, dst, src[0], src[1]);
1894 break;
1895 case BRW_OPCODE_SUBB:
1896 assert(devinfo->gen >= 7);
1897 brw_SUBB(p, dst, src[0], src[1]);
1898 break;
1899 case BRW_OPCODE_MAC:
1900 brw_MAC(p, dst, src[0], src[1]);
1901 break;
1902
1903 case BRW_OPCODE_BFE:
1904 assert(devinfo->gen >= 7);
1905 brw_set_default_access_mode(p, BRW_ALIGN_16);
1906 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1907 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1908 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1909 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1910 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1911 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1912 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1913 } else {
1914 brw_BFE(p, dst, src[0], src[1], src[2]);
1915 }
1916 brw_set_default_access_mode(p, BRW_ALIGN_1);
1917 break;
1918
1919 case BRW_OPCODE_BFI1:
1920 assert(devinfo->gen >= 7);
1921 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1922 * should
1923 *
1924 * "Force BFI instructions to be executed always in SIMD8."
1925 */
1926 if (dispatch_width == 16 && devinfo->is_haswell) {
1927 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1928 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1929 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1930 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1931 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1932 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1933 } else {
1934 brw_BFI1(p, dst, src[0], src[1]);
1935 }
1936 break;
1937 case BRW_OPCODE_BFI2:
1938 assert(devinfo->gen >= 7);
1939 brw_set_default_access_mode(p, BRW_ALIGN_16);
1940 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1941 * should
1942 *
1943 * "Force BFI instructions to be executed always in SIMD8."
1944 *
1945 * Otherwise we would be able to emit compressed instructions like we
1946 * do for the other three-source instructions.
1947 */
1948 if (dispatch_width == 16 &&
1949 (devinfo->is_haswell || !devinfo->supports_simd16_3src)) {
1950 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1951 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1952 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1953 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1954 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1955 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1956 } else {
1957 brw_BFI2(p, dst, src[0], src[1], src[2]);
1958 }
1959 brw_set_default_access_mode(p, BRW_ALIGN_1);
1960 break;
1961
1962 case BRW_OPCODE_IF:
1963 if (inst->src[0].file != BAD_FILE) {
1964 /* The instruction has an embedded compare (only allowed on gen6) */
1965 assert(devinfo->gen == 6);
1966 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1967 } else {
1968 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1969 }
1970 break;
1971
1972 case BRW_OPCODE_ELSE:
1973 brw_ELSE(p);
1974 break;
1975 case BRW_OPCODE_ENDIF:
1976 brw_ENDIF(p);
1977 break;
1978
1979 case BRW_OPCODE_DO:
1980 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1981 break;
1982
1983 case BRW_OPCODE_BREAK:
1984 brw_BREAK(p);
1985 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1986 break;
1987 case BRW_OPCODE_CONTINUE:
1988 brw_CONT(p);
1989 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1990 break;
1991
1992 case BRW_OPCODE_WHILE:
1993 brw_WHILE(p);
1994 loop_count++;
1995 break;
1996
1997 case SHADER_OPCODE_RCP:
1998 case SHADER_OPCODE_RSQ:
1999 case SHADER_OPCODE_SQRT:
2000 case SHADER_OPCODE_EXP2:
2001 case SHADER_OPCODE_LOG2:
2002 case SHADER_OPCODE_SIN:
2003 case SHADER_OPCODE_COS:
2004 assert(devinfo->gen < 6 || inst->mlen == 0);
2005 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2006 if (devinfo->gen >= 7) {
2007 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
2008 brw_null_reg());
2009 } else if (devinfo->gen == 6) {
2010 generate_math_gen6(inst, dst, src[0], brw_null_reg());
2011 } else if (devinfo->gen == 5 || devinfo->is_g4x) {
2012 generate_math_g45(inst, dst, src[0]);
2013 } else {
2014 generate_math_gen4(inst, dst, src[0]);
2015 }
2016 break;
2017 case SHADER_OPCODE_INT_QUOTIENT:
2018 case SHADER_OPCODE_INT_REMAINDER:
2019 case SHADER_OPCODE_POW:
2020 assert(devinfo->gen < 6 || inst->mlen == 0);
2021 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2022 if (devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
2023 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
2024 } else if (devinfo->gen >= 6) {
2025 generate_math_gen6(inst, dst, src[0], src[1]);
2026 } else {
2027 generate_math_gen4(inst, dst, src[0]);
2028 }
2029 break;
2030 case FS_OPCODE_CINTERP:
2031 brw_MOV(p, dst, src[0]);
2032 break;
2033 case FS_OPCODE_LINTERP:
2034 generate_linterp(inst, dst, src);
2035 break;
2036 case FS_OPCODE_PIXEL_X:
2037 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2038 src[0].subnr = 0 * type_sz(src[0].type);
2039 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2040 break;
2041 case FS_OPCODE_PIXEL_Y:
2042 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2043 src[0].subnr = 4 * type_sz(src[0].type);
2044 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2045 break;
2046 case FS_OPCODE_GET_BUFFER_SIZE:
2047 generate_get_buffer_size(inst, dst, src[0], src[1]);
2048 break;
2049 case SHADER_OPCODE_TEX:
2050 case FS_OPCODE_TXB:
2051 case SHADER_OPCODE_TXD:
2052 case SHADER_OPCODE_TXF:
2053 case SHADER_OPCODE_TXF_CMS:
2054 case SHADER_OPCODE_TXF_CMS_W:
2055 case SHADER_OPCODE_TXF_UMS:
2056 case SHADER_OPCODE_TXF_MCS:
2057 case SHADER_OPCODE_TXL:
2058 case SHADER_OPCODE_TXS:
2059 case SHADER_OPCODE_LOD:
2060 case SHADER_OPCODE_TG4:
2061 case SHADER_OPCODE_TG4_OFFSET:
2062 case SHADER_OPCODE_SAMPLEINFO:
2063 generate_tex(inst, dst, src[0], src[1], src[2]);
2064 break;
2065 case FS_OPCODE_DDX_COARSE:
2066 case FS_OPCODE_DDX_FINE:
2067 generate_ddx(inst->opcode, dst, src[0]);
2068 break;
2069 case FS_OPCODE_DDY_COARSE:
2070 case FS_OPCODE_DDY_FINE:
2071 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2072 generate_ddy(inst->opcode, dst, src[0], src[1].ud);
2073 break;
2074
2075 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
2076 generate_scratch_write(inst, src[0]);
2077 spill_count++;
2078 break;
2079
2080 case SHADER_OPCODE_GEN4_SCRATCH_READ:
2081 generate_scratch_read(inst, dst);
2082 fill_count++;
2083 break;
2084
2085 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2086 generate_scratch_read_gen7(inst, dst);
2087 fill_count++;
2088 break;
2089
2090 case SHADER_OPCODE_URB_READ_SIMD8:
2091 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
2092 generate_urb_read(inst, dst, src[0]);
2093 break;
2094
2095 case SHADER_OPCODE_URB_WRITE_SIMD8:
2096 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
2097 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
2098 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
2099 generate_urb_write(inst, src[0]);
2100 break;
2101
2102 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2103 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2104 break;
2105
2106 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2107 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2108 break;
2109
2110 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
2111 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
2112 break;
2113
2114 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2115 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2116 break;
2117
2118 case FS_OPCODE_REP_FB_WRITE:
2119 case FS_OPCODE_FB_WRITE:
2120 generate_fb_write(inst, src[0]);
2121 break;
2122
2123 case FS_OPCODE_BLORP_FB_WRITE:
2124 generate_blorp_fb_write(inst);
2125 break;
2126
2127 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2128 generate_mov_dispatch_to_flags(inst);
2129 break;
2130
2131 case FS_OPCODE_DISCARD_JUMP:
2132 generate_discard_jump(inst);
2133 break;
2134
2135 case SHADER_OPCODE_SHADER_TIME_ADD:
2136 generate_shader_time_add(inst, src[0], src[1], src[2]);
2137 break;
2138
2139 case SHADER_OPCODE_UNTYPED_ATOMIC:
2140 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2141 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
2142 inst->mlen, !inst->dst.is_null());
2143 break;
2144
2145 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2146 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2147 brw_untyped_surface_read(p, dst, src[0], src[1],
2148 inst->mlen, src[2].ud);
2149 break;
2150
2151 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2152 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2153 brw_untyped_surface_write(p, src[0], src[1],
2154 inst->mlen, src[2].ud);
2155 break;
2156
2157 case SHADER_OPCODE_TYPED_ATOMIC:
2158 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2159 brw_typed_atomic(p, dst, src[0], src[1],
2160 src[2].ud, inst->mlen, !inst->dst.is_null());
2161 break;
2162
2163 case SHADER_OPCODE_TYPED_SURFACE_READ:
2164 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2165 brw_typed_surface_read(p, dst, src[0], src[1],
2166 inst->mlen, src[2].ud);
2167 break;
2168
2169 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2170 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2171 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud);
2172 break;
2173
2174 case SHADER_OPCODE_MEMORY_FENCE:
2175 brw_memory_fence(p, dst);
2176 break;
2177
2178 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2179 generate_set_simd4x2_offset(inst, dst, src[0]);
2180 break;
2181
2182 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
2183 brw_find_live_channel(p, dst);
2184 break;
2185
2186 case SHADER_OPCODE_BROADCAST:
2187 brw_broadcast(p, dst, src[0], src[1]);
2188 break;
2189
2190 case FS_OPCODE_SET_SAMPLE_ID:
2191 generate_set_sample_id(inst, dst, src[0], src[1]);
2192 break;
2193
2194 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2195 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2196 break;
2197
2198 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2199 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2200 generate_unpack_half_2x16_split(inst, dst, src[0]);
2201 break;
2202
2203 case FS_OPCODE_PLACEHOLDER_HALT:
2204 /* This is the place where the final HALT needs to be inserted if
2205 * we've emitted any discards. If not, this will emit no code.
2206 */
2207 if (!patch_discard_jumps_to_fb_writes()) {
2208 if (unlikely(debug_flag)) {
2209 annotation.ann_count--;
2210 }
2211 }
2212 break;
2213
2214 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2215 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2216 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2217 break;
2218
2219 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2220 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2221 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2222 break;
2223
2224 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2225 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2226 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2227 break;
2228
2229 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2230 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2231 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2232 break;
2233
2234 case CS_OPCODE_CS_TERMINATE:
2235 generate_cs_terminate(inst, src[0]);
2236 break;
2237
2238 case SHADER_OPCODE_BARRIER:
2239 generate_barrier(inst, src[0]);
2240 break;
2241
2242 case FS_OPCODE_PACK_STENCIL_REF:
2243 generate_stencil_ref_packing(inst, dst, src[0]);
2244 break;
2245
2246 default:
2247 unreachable("Unsupported opcode");
2248
2249 case SHADER_OPCODE_LOAD_PAYLOAD:
2250 unreachable("Should be lowered by lower_load_payload()");
2251 }
2252
2253 if (multiple_instructions_emitted)
2254 continue;
2255
2256 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2257 assert(p->next_insn_offset == last_insn_offset + 16 ||
2258 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2259 "emitting more than 1 instruction");
2260
2261 brw_inst *last = &p->store[last_insn_offset / 16];
2262
2263 if (inst->conditional_mod)
2264 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2265 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2266 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2267 }
2268 }
2269
2270 brw_set_uip_jip(p);
2271 annotation_finalize(&annotation, p->next_insn_offset);
2272
2273 #ifndef NDEBUG
2274 bool validated = brw_validate_instructions(p, start_offset, &annotation);
2275 #else
2276 if (unlikely(debug_flag))
2277 brw_validate_instructions(p, start_offset, &annotation);
2278 #endif
2279
2280 int before_size = p->next_insn_offset - start_offset;
2281 brw_compact_instructions(p, start_offset, annotation.ann_count,
2282 annotation.ann);
2283 int after_size = p->next_insn_offset - start_offset;
2284
2285 if (unlikely(debug_flag)) {
2286 fprintf(stderr, "Native code for %s\n"
2287 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2288 " bytes (%.0f%%)\n",
2289 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2290 spill_count, fill_count, promoted_constants, before_size, after_size,
2291 100.0f * (before_size - after_size) / before_size);
2292
2293 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2294 p->devinfo);
2295 ralloc_free(annotation.mem_ctx);
2296 }
2297 assert(validated);
2298
2299 compiler->shader_debug_log(log_data,
2300 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2301 "%d:%d spills:fills, Promoted %u constants, "
2302 "compacted %d to %d bytes.\n",
2303 stage_abbrev, dispatch_width, before_size / 16,
2304 loop_count, cfg->cycle_count, spill_count,
2305 fill_count, promoted_constants, before_size,
2306 after_size);
2307
2308 return start_offset;
2309 }
2310
2311 const unsigned *
2312 fs_generator::get_assembly(unsigned int *assembly_size)
2313 {
2314 return brw_get_program(p, assembly_size);
2315 }