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i965/eu: Merge brw_CONT and gen6_CONT.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 void *mem_ctx,
41 const struct brw_wm_prog_key *key,
42 struct brw_wm_prog_data *prog_data,
43 struct gl_shader_program *prog,
44 struct gl_fragment_program *fp,
45 bool dual_source_output,
46 bool runtime_check_aads_emit,
47 bool debug_flag)
48
49 : brw(brw), key(key), prog_data(prog_data), prog(prog), fp(fp),
50 dual_source_output(dual_source_output),
51 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(debug_flag),
52 mem_ctx(mem_ctx)
53 {
54 ctx = &brw->ctx;
55
56 p = rzalloc(mem_ctx, struct brw_compile);
57 brw_init_compile(brw, p, mem_ctx);
58 }
59
60 fs_generator::~fs_generator()
61 {
62 }
63
64 bool
65 fs_generator::patch_discard_jumps_to_fb_writes()
66 {
67 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
68 return false;
69
70 /* There is a somewhat strange undocumented requirement of using
71 * HALT, according to the simulator. If some channel has HALTed to
72 * a particular UIP, then by the end of the program, every channel
73 * must have HALTed to that UIP. Furthermore, the tracking is a
74 * stack, so you can't do the final halt of a UIP after starting
75 * halting to a new UIP.
76 *
77 * Symptoms of not emitting this instruction on actual hardware
78 * included GPU hangs and sparkly rendering on the piglit discard
79 * tests.
80 */
81 brw_inst *last_halt = gen6_HALT(p);
82 brw_inst_set_uip(brw, last_halt, 2);
83 brw_inst_set_jip(brw, last_halt, 2);
84
85 int ip = p->nr_insn;
86
87 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
88 brw_inst *patch = &p->store[patch_ip->ip];
89
90 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
91 /* HALT takes a half-instruction distance from the pre-incremented IP. */
92 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * 2);
93 }
94
95 this->discard_halt_patches.make_empty();
96 return true;
97 }
98
99 void
100 fs_generator::fire_fb_write(fs_inst *inst,
101 GLuint base_reg,
102 struct brw_reg implied_header,
103 GLuint nr)
104 {
105 uint32_t msg_control;
106
107 if (brw->gen < 6) {
108 brw_push_insn_state(p);
109 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
110 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
111 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
112 brw_MOV(p,
113 brw_message_reg(base_reg + 1),
114 brw_vec8_grf(1, 0));
115 brw_pop_insn_state(p);
116 }
117
118 if (this->dual_source_output)
119 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
120 else if (dispatch_width == 16)
121 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
122 else
123 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
124
125 uint32_t surf_index =
126 prog_data->binding_table.render_target_start + inst->target;
127
128 brw_fb_WRITE(p,
129 dispatch_width,
130 base_reg,
131 implied_header,
132 msg_control,
133 surf_index,
134 nr,
135 0,
136 inst->eot,
137 inst->header_present);
138
139 brw_mark_surface_used(&prog_data->base, surf_index);
140 }
141
142 void
143 fs_generator::generate_fb_write(fs_inst *inst)
144 {
145 struct brw_reg implied_header;
146
147 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
148 * move, here's g1.
149 */
150 if (inst->header_present) {
151 brw_push_insn_state(p);
152 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
153 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
154 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
155
156 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
157 * present.
158 */
159 if ((fp && fp->UsesKill) || key->alpha_test_func) {
160 struct brw_reg pixel_mask;
161
162 if (brw->gen >= 6)
163 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
164 else
165 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
166
167 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
168 }
169
170 if (brw->gen >= 6) {
171 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
172 brw_MOV(p,
173 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
174 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
175 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
176
177 if (inst->target > 0 && key->replicate_alpha) {
178 /* Set "Source0 Alpha Present to RenderTarget" bit in message
179 * header.
180 */
181 brw_OR(p,
182 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
183 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
184 brw_imm_ud(0x1 << 11));
185 }
186
187 if (inst->target > 0) {
188 /* Set the render target index for choosing BLEND_STATE. */
189 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
190 inst->base_mrf, 2),
191 BRW_REGISTER_TYPE_UD),
192 brw_imm_ud(inst->target));
193 }
194
195 implied_header = brw_null_reg();
196 } else {
197 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
198 }
199
200 brw_pop_insn_state(p);
201 } else {
202 implied_header = brw_null_reg();
203 }
204
205 if (!runtime_check_aads_emit) {
206 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
207 } else {
208 /* This can only happen in gen < 6 */
209 assert(brw->gen < 6);
210
211 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
212
213 /* Check runtime bit to detect if we have to send AA data or not */
214 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
215 brw_AND(p,
216 v1_null_ud,
217 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
218 brw_imm_ud(1<<26));
219 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
220
221 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
222 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
223 {
224 /* Don't send AA data */
225 fire_fb_write(inst, inst->base_mrf+1, implied_header, inst->mlen-1);
226 }
227 brw_land_fwd_jump(p, jmp);
228 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
229 }
230 }
231
232 void
233 fs_generator::generate_blorp_fb_write(fs_inst *inst)
234 {
235 brw_fb_WRITE(p,
236 16 /* dispatch_width */,
237 inst->base_mrf,
238 brw_reg_from_fs_reg(&inst->src[0]),
239 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
240 inst->target,
241 inst->mlen,
242 0,
243 true,
244 inst->header_present);
245 }
246
247 /* Computes the integer pixel x,y values from the origin.
248 *
249 * This is the basis of gl_FragCoord computation, but is also used
250 * pre-gen6 for computing the deltas from v0 for computing
251 * interpolation.
252 */
253 void
254 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
255 {
256 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
257 struct brw_reg src;
258 struct brw_reg deltas;
259
260 if (is_x) {
261 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
262 deltas = brw_imm_v(0x10101010);
263 } else {
264 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
265 deltas = brw_imm_v(0x11001100);
266 }
267
268 if (dispatch_width == 16) {
269 dst = vec16(dst);
270 }
271
272 /* We do this SIMD8 or SIMD16, but since the destination is UW we
273 * don't do compression in the SIMD16 case.
274 */
275 brw_push_insn_state(p);
276 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
277 brw_ADD(p, dst, src, deltas);
278 brw_pop_insn_state(p);
279 }
280
281 void
282 fs_generator::generate_linterp(fs_inst *inst,
283 struct brw_reg dst, struct brw_reg *src)
284 {
285 struct brw_reg delta_x = src[0];
286 struct brw_reg delta_y = src[1];
287 struct brw_reg interp = src[2];
288
289 if (brw->has_pln &&
290 delta_y.nr == delta_x.nr + 1 &&
291 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
292 brw_PLN(p, dst, interp, delta_x);
293 } else {
294 brw_LINE(p, brw_null_reg(), interp, delta_x);
295 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
296 }
297 }
298
299 void
300 fs_generator::generate_math_gen6(fs_inst *inst,
301 struct brw_reg dst,
302 struct brw_reg src0,
303 struct brw_reg src1)
304 {
305 int op = brw_math_function(inst->opcode);
306 bool binop = src1.file == BRW_GENERAL_REGISTER_FILE;
307
308 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
309 gen6_math(p, dst, op, src0, src1);
310
311 if (dispatch_width == 16) {
312 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
313 gen6_math(p, sechalf(dst), op, sechalf(src0),
314 binop ? sechalf(src1) : brw_null_reg());
315 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
316 }
317 }
318
319 void
320 fs_generator::generate_math_gen4(fs_inst *inst,
321 struct brw_reg dst,
322 struct brw_reg src)
323 {
324 int op = brw_math_function(inst->opcode);
325
326 assert(inst->mlen >= 1);
327
328 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
329 gen4_math(p, dst,
330 op,
331 inst->base_mrf, src,
332 BRW_MATH_DATA_VECTOR,
333 BRW_MATH_PRECISION_FULL);
334
335 if (dispatch_width == 16) {
336 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
337 gen4_math(p, sechalf(dst),
338 op,
339 inst->base_mrf + 1, sechalf(src),
340 BRW_MATH_DATA_VECTOR,
341 BRW_MATH_PRECISION_FULL);
342
343 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
344 }
345 }
346
347 void
348 fs_generator::generate_math_g45(fs_inst *inst,
349 struct brw_reg dst,
350 struct brw_reg src)
351 {
352 if (inst->opcode == SHADER_OPCODE_POW ||
353 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
354 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
355 generate_math_gen4(inst, dst, src);
356 return;
357 }
358
359 int op = brw_math_function(inst->opcode);
360
361 assert(inst->mlen >= 1);
362
363 gen4_math(p, dst,
364 op,
365 inst->base_mrf, src,
366 BRW_MATH_DATA_VECTOR,
367 BRW_MATH_PRECISION_FULL);
368 }
369
370 void
371 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
372 {
373 int msg_type = -1;
374 int rlen = 4;
375 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
376 uint32_t return_format;
377
378 switch (dst.type) {
379 case BRW_REGISTER_TYPE_D:
380 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
381 break;
382 case BRW_REGISTER_TYPE_UD:
383 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
384 break;
385 default:
386 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
387 break;
388 }
389
390 if (dispatch_width == 16 &&
391 !inst->force_uncompressed && !inst->force_sechalf)
392 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
393
394 if (brw->gen >= 5) {
395 switch (inst->opcode) {
396 case SHADER_OPCODE_TEX:
397 if (inst->shadow_compare) {
398 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
399 } else {
400 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
401 }
402 break;
403 case FS_OPCODE_TXB:
404 if (inst->shadow_compare) {
405 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
406 } else {
407 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
408 }
409 break;
410 case SHADER_OPCODE_TXL:
411 if (inst->shadow_compare) {
412 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
413 } else {
414 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
415 }
416 break;
417 case SHADER_OPCODE_TXS:
418 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
419 break;
420 case SHADER_OPCODE_TXD:
421 if (inst->shadow_compare) {
422 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
423 assert(brw->gen >= 8 || brw->is_haswell);
424 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
425 } else {
426 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
427 }
428 break;
429 case SHADER_OPCODE_TXF:
430 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
431 break;
432 case SHADER_OPCODE_TXF_CMS:
433 if (brw->gen >= 7)
434 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
435 else
436 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
437 break;
438 case SHADER_OPCODE_TXF_UMS:
439 assert(brw->gen >= 7);
440 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
441 break;
442 case SHADER_OPCODE_TXF_MCS:
443 assert(brw->gen >= 7);
444 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
445 break;
446 case SHADER_OPCODE_LOD:
447 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
448 break;
449 case SHADER_OPCODE_TG4:
450 if (inst->shadow_compare) {
451 assert(brw->gen >= 7);
452 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
453 } else {
454 assert(brw->gen >= 6);
455 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
456 }
457 break;
458 case SHADER_OPCODE_TG4_OFFSET:
459 assert(brw->gen >= 7);
460 if (inst->shadow_compare) {
461 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
462 } else {
463 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
464 }
465 break;
466 default:
467 unreachable("not reached");
468 }
469 } else {
470 switch (inst->opcode) {
471 case SHADER_OPCODE_TEX:
472 /* Note that G45 and older determines shadow compare and dispatch width
473 * from message length for most messages.
474 */
475 assert(dispatch_width == 8);
476 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
477 if (inst->shadow_compare) {
478 assert(inst->mlen == 6);
479 } else {
480 assert(inst->mlen <= 4);
481 }
482 break;
483 case FS_OPCODE_TXB:
484 if (inst->shadow_compare) {
485 assert(inst->mlen == 6);
486 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
487 } else {
488 assert(inst->mlen == 9);
489 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
490 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
491 }
492 break;
493 case SHADER_OPCODE_TXL:
494 if (inst->shadow_compare) {
495 assert(inst->mlen == 6);
496 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
497 } else {
498 assert(inst->mlen == 9);
499 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
500 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
501 }
502 break;
503 case SHADER_OPCODE_TXD:
504 /* There is no sample_d_c message; comparisons are done manually */
505 assert(inst->mlen == 7 || inst->mlen == 10);
506 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
507 break;
508 case SHADER_OPCODE_TXF:
509 assert(inst->mlen == 9);
510 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
511 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
512 break;
513 case SHADER_OPCODE_TXS:
514 assert(inst->mlen == 3);
515 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
516 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
517 break;
518 default:
519 unreachable("not reached");
520 }
521 }
522 assert(msg_type != -1);
523
524 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
525 rlen = 8;
526 dst = vec16(dst);
527 }
528
529 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
530 /* The send-from-GRF for SIMD16 texturing with a header has an extra
531 * hardware register allocated to it, which we need to skip over (since
532 * our coordinates in the payload are in the even-numbered registers,
533 * and the header comes right before the first one).
534 */
535 assert(src.file == BRW_GENERAL_REGISTER_FILE);
536 src.nr++;
537 }
538
539 /* Load the message header if present. If there's a texture offset,
540 * we need to set it up explicitly and load the offset bitfield.
541 * Otherwise, we can use an implied move from g0 to the first message reg.
542 */
543 if (inst->header_present) {
544 if (brw->gen < 6 && !inst->texture_offset) {
545 /* Set up an implied move from g0 to the MRF. */
546 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
547 } else {
548 struct brw_reg header_reg;
549
550 if (brw->gen >= 7) {
551 header_reg = src;
552 } else {
553 assert(inst->base_mrf != -1);
554 header_reg = brw_message_reg(inst->base_mrf);
555 }
556
557 brw_push_insn_state(p);
558 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
559 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
560 /* Explicitly set up the message header by copying g0 to the MRF. */
561 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
562
563 if (inst->texture_offset) {
564 /* Set the offset bits in DWord 2. */
565 brw_MOV(p, get_element_ud(header_reg, 2),
566 brw_imm_ud(inst->texture_offset));
567 }
568
569 if (inst->sampler >= 16) {
570 /* The "Sampler Index" field can only store values between 0 and 15.
571 * However, we can add an offset to the "Sampler State Pointer"
572 * field, effectively selecting a different set of 16 samplers.
573 *
574 * The "Sampler State Pointer" needs to be aligned to a 32-byte
575 * offset, and each sampler state is only 16-bytes, so we can't
576 * exclusively use the offset - we have to use both.
577 */
578 assert(brw->gen >= 8 || brw->is_haswell);
579 const int sampler_state_size = 16; /* 16 bytes */
580 brw_ADD(p,
581 get_element_ud(header_reg, 3),
582 get_element_ud(brw_vec8_grf(0, 0), 3),
583 brw_imm_ud(16 * (inst->sampler / 16) * sampler_state_size));
584 }
585 brw_pop_insn_state(p);
586 }
587 }
588
589 uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
590 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
591 ? prog_data->base.binding_table.gather_texture_start
592 : prog_data->base.binding_table.texture_start) + inst->sampler;
593
594 brw_SAMPLE(p,
595 retype(dst, BRW_REGISTER_TYPE_UW),
596 inst->base_mrf,
597 src,
598 surface_index,
599 inst->sampler % 16,
600 msg_type,
601 rlen,
602 inst->mlen,
603 inst->header_present,
604 simd_mode,
605 return_format);
606
607 brw_mark_surface_used(&prog_data->base, surface_index);
608 }
609
610
611 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
612 * looking like:
613 *
614 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
615 *
616 * Ideally, we want to produce:
617 *
618 * DDX DDY
619 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
620 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
621 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
622 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
623 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
624 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
625 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
626 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
627 *
628 * and add another set of two more subspans if in 16-pixel dispatch mode.
629 *
630 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
631 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
632 * pair. But the ideal approximation may impose a huge performance cost on
633 * sample_d. On at least Haswell, sample_d instruction does some
634 * optimizations if the same LOD is used for all pixels in the subspan.
635 *
636 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
637 * appropriate swizzling.
638 */
639 void
640 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
641 {
642 unsigned vstride, width;
643
644 if (key->high_quality_derivatives) {
645 /* produce accurate derivatives */
646 vstride = BRW_VERTICAL_STRIDE_2;
647 width = BRW_WIDTH_2;
648 }
649 else {
650 /* replicate the derivative at the top-left pixel to other pixels */
651 vstride = BRW_VERTICAL_STRIDE_4;
652 width = BRW_WIDTH_4;
653 }
654
655 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
656 BRW_REGISTER_TYPE_F,
657 vstride,
658 width,
659 BRW_HORIZONTAL_STRIDE_0,
660 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
661 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
662 BRW_REGISTER_TYPE_F,
663 vstride,
664 width,
665 BRW_HORIZONTAL_STRIDE_0,
666 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
667 brw_ADD(p, dst, src0, negate(src1));
668 }
669
670 /* The negate_value boolean is used to negate the derivative computation for
671 * FBOs, since they place the origin at the upper left instead of the lower
672 * left.
673 */
674 void
675 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
676 bool negate_value)
677 {
678 if (key->high_quality_derivatives) {
679 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
680 * Region Restrictions):
681 *
682 * In Align16 access mode, SIMD16 is not allowed for DW operations
683 * and SIMD8 is not allowed for DF operations.
684 *
685 * In this context, "DW operations" means "operations acting on 32-bit
686 * values", so it includes operations on floats.
687 *
688 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
689 * (Instruction Compression -> Rules and Restrictions):
690 *
691 * A compressed instruction must be in Align1 access mode. Align16
692 * mode instructions cannot be compressed.
693 *
694 * Similar text exists in the g45 PRM.
695 *
696 * On these platforms, if we're building a SIMD16 shader, we need to
697 * manually unroll to a pair of SIMD8 instructions.
698 */
699 bool unroll_to_simd8 =
700 (dispatch_width == 16 &&
701 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
702
703 /* produce accurate derivatives */
704 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
705 BRW_REGISTER_TYPE_F,
706 BRW_VERTICAL_STRIDE_4,
707 BRW_WIDTH_4,
708 BRW_HORIZONTAL_STRIDE_1,
709 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
710 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
711 BRW_REGISTER_TYPE_F,
712 BRW_VERTICAL_STRIDE_4,
713 BRW_WIDTH_4,
714 BRW_HORIZONTAL_STRIDE_1,
715 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
716 brw_push_insn_state(p);
717 brw_set_default_access_mode(p, BRW_ALIGN_16);
718 if (unroll_to_simd8)
719 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
720 if (negate_value)
721 brw_ADD(p, dst, src1, negate(src0));
722 else
723 brw_ADD(p, dst, src0, negate(src1));
724 if (unroll_to_simd8) {
725 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
726 src0 = sechalf(src0);
727 src1 = sechalf(src1);
728 dst = sechalf(dst);
729 if (negate_value)
730 brw_ADD(p, dst, src1, negate(src0));
731 else
732 brw_ADD(p, dst, src0, negate(src1));
733 }
734 brw_pop_insn_state(p);
735 } else {
736 /* replicate the derivative at the top-left pixel to other pixels */
737 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
738 BRW_REGISTER_TYPE_F,
739 BRW_VERTICAL_STRIDE_4,
740 BRW_WIDTH_4,
741 BRW_HORIZONTAL_STRIDE_0,
742 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
743 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
744 BRW_REGISTER_TYPE_F,
745 BRW_VERTICAL_STRIDE_4,
746 BRW_WIDTH_4,
747 BRW_HORIZONTAL_STRIDE_0,
748 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
749 if (negate_value)
750 brw_ADD(p, dst, src1, negate(src0));
751 else
752 brw_ADD(p, dst, src0, negate(src1));
753 }
754 }
755
756 void
757 fs_generator::generate_discard_jump(fs_inst *inst)
758 {
759 assert(brw->gen >= 6);
760
761 /* This HALT will be patched up at FB write time to point UIP at the end of
762 * the program, and at brw_uip_jip() JIP will be set to the end of the
763 * current block (or the program).
764 */
765 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
766
767 brw_push_insn_state(p);
768 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
769 gen6_HALT(p);
770 brw_pop_insn_state(p);
771 }
772
773 void
774 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
775 {
776 assert(inst->mlen != 0);
777
778 brw_MOV(p,
779 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
780 retype(src, BRW_REGISTER_TYPE_UD));
781 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
782 dispatch_width / 8, inst->offset);
783 }
784
785 void
786 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
787 {
788 assert(inst->mlen != 0);
789
790 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
791 dispatch_width / 8, inst->offset);
792 }
793
794 void
795 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
796 {
797 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
798 }
799
800 void
801 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
802 struct brw_reg dst,
803 struct brw_reg index,
804 struct brw_reg offset)
805 {
806 assert(inst->mlen != 0);
807
808 assert(index.file == BRW_IMMEDIATE_VALUE &&
809 index.type == BRW_REGISTER_TYPE_UD);
810 uint32_t surf_index = index.dw1.ud;
811
812 assert(offset.file == BRW_IMMEDIATE_VALUE &&
813 offset.type == BRW_REGISTER_TYPE_UD);
814 uint32_t read_offset = offset.dw1.ud;
815
816 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
817 read_offset, surf_index);
818
819 brw_mark_surface_used(&prog_data->base, surf_index);
820 }
821
822 void
823 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
824 struct brw_reg dst,
825 struct brw_reg index,
826 struct brw_reg offset)
827 {
828 assert(inst->mlen == 0);
829
830 assert(index.file == BRW_IMMEDIATE_VALUE &&
831 index.type == BRW_REGISTER_TYPE_UD);
832 uint32_t surf_index = index.dw1.ud;
833
834 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
835 /* Reference just the dword we need, to avoid angering validate_reg(). */
836 offset = brw_vec1_grf(offset.nr, 0);
837
838 brw_push_insn_state(p);
839 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
840 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
841 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
842 brw_pop_insn_state(p);
843
844 /* We use the SIMD4x2 mode because we want to end up with 4 components in
845 * the destination loaded consecutively from the same offset (which appears
846 * in the first component, and the rest are ignored).
847 */
848 dst.width = BRW_WIDTH_4;
849 brw_set_dest(p, send, dst);
850 brw_set_src0(p, send, offset);
851 brw_set_sampler_message(p, send,
852 surf_index,
853 0, /* LD message ignores sampler unit */
854 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
855 1, /* rlen */
856 1, /* mlen */
857 false, /* no header */
858 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
859 0);
860
861 brw_mark_surface_used(&prog_data->base, surf_index);
862 }
863
864 void
865 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
866 struct brw_reg dst,
867 struct brw_reg index,
868 struct brw_reg offset)
869 {
870 assert(brw->gen < 7); /* Should use the gen7 variant. */
871 assert(inst->header_present);
872 assert(inst->mlen);
873
874 assert(index.file == BRW_IMMEDIATE_VALUE &&
875 index.type == BRW_REGISTER_TYPE_UD);
876 uint32_t surf_index = index.dw1.ud;
877
878 uint32_t simd_mode, rlen, msg_type;
879 if (dispatch_width == 16) {
880 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
881 rlen = 8;
882 } else {
883 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
884 rlen = 4;
885 }
886
887 if (brw->gen >= 5)
888 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
889 else {
890 /* We always use the SIMD16 message so that we only have to load U, and
891 * not V or R.
892 */
893 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
894 assert(inst->mlen == 3);
895 assert(inst->regs_written == 8);
896 rlen = 8;
897 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
898 }
899
900 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
901 BRW_REGISTER_TYPE_D);
902 brw_MOV(p, offset_mrf, offset);
903
904 struct brw_reg header = brw_vec8_grf(0, 0);
905 gen6_resolve_implied_move(p, &header, inst->base_mrf);
906
907 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
908 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
909 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
910 brw_set_src0(p, send, header);
911 if (brw->gen < 6)
912 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
913
914 /* Our surface is set up as floats, regardless of what actual data is
915 * stored in it.
916 */
917 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
918 brw_set_sampler_message(p, send,
919 surf_index,
920 0, /* sampler (unused) */
921 msg_type,
922 rlen,
923 inst->mlen,
924 inst->header_present,
925 simd_mode,
926 return_format);
927
928 brw_mark_surface_used(&prog_data->base, surf_index);
929 }
930
931 void
932 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
933 struct brw_reg dst,
934 struct brw_reg index,
935 struct brw_reg offset)
936 {
937 assert(brw->gen >= 7);
938 /* Varying-offset pull constant loads are treated as a normal expression on
939 * gen7, so the fact that it's a send message is hidden at the IR level.
940 */
941 assert(!inst->header_present);
942 assert(!inst->mlen);
943
944 assert(index.file == BRW_IMMEDIATE_VALUE &&
945 index.type == BRW_REGISTER_TYPE_UD);
946 uint32_t surf_index = index.dw1.ud;
947
948 uint32_t simd_mode, rlen, mlen;
949 if (dispatch_width == 16) {
950 mlen = 2;
951 rlen = 8;
952 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
953 } else {
954 mlen = 1;
955 rlen = 4;
956 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
957 }
958
959 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
960 brw_set_dest(p, send, dst);
961 brw_set_src0(p, send, offset);
962 brw_set_sampler_message(p, send,
963 surf_index,
964 0, /* LD message ignores sampler unit */
965 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
966 rlen,
967 mlen,
968 false, /* no header */
969 simd_mode,
970 0);
971
972 brw_mark_surface_used(&prog_data->base, surf_index);
973 }
974
975 /**
976 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
977 * into the flags register (f0.0).
978 *
979 * Used only on Gen6 and above.
980 */
981 void
982 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
983 {
984 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
985 struct brw_reg dispatch_mask;
986
987 if (brw->gen >= 6)
988 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
989 else
990 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
991
992 brw_push_insn_state(p);
993 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
994 brw_MOV(p, flags, dispatch_mask);
995 brw_pop_insn_state(p);
996 }
997
998 void
999 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1000 struct brw_reg dst,
1001 struct brw_reg src,
1002 struct brw_reg msg_data,
1003 unsigned msg_type)
1004 {
1005 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1006 msg_data.type == BRW_REGISTER_TYPE_UD);
1007
1008 brw_pixel_interpolator_query(p,
1009 retype(dst, BRW_REGISTER_TYPE_UW),
1010 src,
1011 inst->pi_noperspective,
1012 msg_type,
1013 msg_data.dw1.ud,
1014 inst->mlen,
1015 inst->regs_written);
1016 }
1017
1018
1019 static uint32_t brw_file_from_reg(fs_reg *reg)
1020 {
1021 switch (reg->file) {
1022 case GRF:
1023 return BRW_GENERAL_REGISTER_FILE;
1024 case MRF:
1025 return BRW_MESSAGE_REGISTER_FILE;
1026 case IMM:
1027 return BRW_IMMEDIATE_VALUE;
1028 default:
1029 unreachable("not reached");
1030 }
1031 }
1032
1033 struct brw_reg
1034 brw_reg_from_fs_reg(fs_reg *reg)
1035 {
1036 struct brw_reg brw_reg;
1037
1038 switch (reg->file) {
1039 case GRF:
1040 case MRF:
1041 if (reg->stride == 0) {
1042 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
1043 } else {
1044 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1045 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1046 }
1047
1048 brw_reg = retype(brw_reg, reg->type);
1049 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1050 break;
1051 case IMM:
1052 switch (reg->type) {
1053 case BRW_REGISTER_TYPE_F:
1054 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
1055 break;
1056 case BRW_REGISTER_TYPE_D:
1057 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
1058 break;
1059 case BRW_REGISTER_TYPE_UD:
1060 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
1061 break;
1062 default:
1063 unreachable("not reached");
1064 }
1065 break;
1066 case HW_REG:
1067 assert(reg->type == reg->fixed_hw_reg.type);
1068 brw_reg = reg->fixed_hw_reg;
1069 break;
1070 case BAD_FILE:
1071 /* Probably unused. */
1072 brw_reg = brw_null_reg();
1073 break;
1074 case UNIFORM:
1075 unreachable("not reached");
1076 default:
1077 unreachable("not reached");
1078 }
1079 if (reg->abs)
1080 brw_reg = brw_abs(brw_reg);
1081 if (reg->negate)
1082 brw_reg = negate(brw_reg);
1083
1084 return brw_reg;
1085 }
1086
1087 /**
1088 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1089 * sampler LD messages.
1090 *
1091 * We don't want to bake it into the send message's code generation because
1092 * that means we don't get a chance to schedule the instructions.
1093 */
1094 void
1095 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1096 struct brw_reg dst,
1097 struct brw_reg value)
1098 {
1099 assert(value.file == BRW_IMMEDIATE_VALUE);
1100
1101 brw_push_insn_state(p);
1102 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1103 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1104 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1105 brw_pop_insn_state(p);
1106 }
1107
1108 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1109 * (when mask is passed as a uniform) of register mask before moving it
1110 * to register dst.
1111 */
1112 void
1113 fs_generator::generate_set_omask(fs_inst *inst,
1114 struct brw_reg dst,
1115 struct brw_reg mask)
1116 {
1117 bool stride_8_8_1 =
1118 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1119 mask.width == BRW_WIDTH_8 &&
1120 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1121
1122 bool stride_0_1_0 =
1123 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1124 mask.width == BRW_WIDTH_1 &&
1125 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1126
1127 assert(stride_8_8_1 || stride_0_1_0);
1128 assert(dst.type == BRW_REGISTER_TYPE_UW);
1129
1130 if (dispatch_width == 16)
1131 dst = vec16(dst);
1132 brw_push_insn_state(p);
1133 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1134 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1135
1136 if (stride_8_8_1) {
1137 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1138 } else if (stride_0_1_0) {
1139 brw_MOV(p, dst, retype(mask, dst.type));
1140 }
1141 brw_pop_insn_state(p);
1142 }
1143
1144 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1145 * the ADD instruction.
1146 */
1147 void
1148 fs_generator::generate_set_sample_id(fs_inst *inst,
1149 struct brw_reg dst,
1150 struct brw_reg src0,
1151 struct brw_reg src1)
1152 {
1153 assert(dst.type == BRW_REGISTER_TYPE_D ||
1154 dst.type == BRW_REGISTER_TYPE_UD);
1155 assert(src0.type == BRW_REGISTER_TYPE_D ||
1156 src0.type == BRW_REGISTER_TYPE_UD);
1157
1158 brw_push_insn_state(p);
1159 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1160 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1161 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1162 brw_ADD(p, dst, src0, reg);
1163 if (dispatch_width == 16)
1164 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1165 brw_pop_insn_state(p);
1166 }
1167
1168 /**
1169 * Change the register's data type from UD to W, doubling the strides in order
1170 * to compensate for halving the data type width.
1171 */
1172 static struct brw_reg
1173 ud_reg_to_w(struct brw_reg r)
1174 {
1175 assert(r.type == BRW_REGISTER_TYPE_UD);
1176 r.type = BRW_REGISTER_TYPE_W;
1177
1178 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1179 * doubles the real stride.
1180 */
1181 if (r.hstride != 0)
1182 ++r.hstride;
1183 if (r.vstride != 0)
1184 ++r.vstride;
1185
1186 return r;
1187 }
1188
1189 void
1190 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1191 struct brw_reg dst,
1192 struct brw_reg x,
1193 struct brw_reg y)
1194 {
1195 assert(brw->gen >= 7);
1196 assert(dst.type == BRW_REGISTER_TYPE_UD);
1197 assert(x.type == BRW_REGISTER_TYPE_F);
1198 assert(y.type == BRW_REGISTER_TYPE_F);
1199
1200 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1201 *
1202 * Because this instruction does not have a 16-bit floating-point type,
1203 * the destination data type must be Word (W).
1204 *
1205 * The destination must be DWord-aligned and specify a horizontal stride
1206 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1207 * each destination channel and the upper word is not modified.
1208 */
1209 struct brw_reg dst_w = ud_reg_to_w(dst);
1210
1211 /* Give each 32-bit channel of dst the form below , where "." means
1212 * unchanged.
1213 * 0x....hhhh
1214 */
1215 brw_F32TO16(p, dst_w, y);
1216
1217 /* Now the form:
1218 * 0xhhhh0000
1219 */
1220 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1221
1222 /* And, finally the form of packHalf2x16's output:
1223 * 0xhhhhllll
1224 */
1225 brw_F32TO16(p, dst_w, x);
1226 }
1227
1228 void
1229 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1230 struct brw_reg dst,
1231 struct brw_reg src)
1232 {
1233 assert(brw->gen >= 7);
1234 assert(dst.type == BRW_REGISTER_TYPE_F);
1235 assert(src.type == BRW_REGISTER_TYPE_UD);
1236
1237 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1238 *
1239 * Because this instruction does not have a 16-bit floating-point type,
1240 * the source data type must be Word (W). The destination type must be
1241 * F (Float).
1242 */
1243 struct brw_reg src_w = ud_reg_to_w(src);
1244
1245 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1246 * For the Y case, we wish to access only the upper word; therefore
1247 * a 16-bit subregister offset is needed.
1248 */
1249 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1250 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1251 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1252 src_w.subnr += 2;
1253
1254 brw_F16TO32(p, dst, src_w);
1255 }
1256
1257 void
1258 fs_generator::generate_shader_time_add(fs_inst *inst,
1259 struct brw_reg payload,
1260 struct brw_reg offset,
1261 struct brw_reg value)
1262 {
1263 assert(brw->gen >= 7);
1264 brw_push_insn_state(p);
1265 brw_set_default_mask_control(p, true);
1266
1267 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1268 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1269 offset.type);
1270 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1271 value.type);
1272
1273 assert(offset.file == BRW_IMMEDIATE_VALUE);
1274 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1275 value.width = BRW_WIDTH_1;
1276 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1277 value.vstride = BRW_VERTICAL_STRIDE_0;
1278 } else {
1279 assert(value.file == BRW_IMMEDIATE_VALUE);
1280 }
1281
1282 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1283 * case, and we don't really care about squeezing every bit of performance
1284 * out of this path, so we just emit the MOVs from here.
1285 */
1286 brw_MOV(p, payload_offset, offset);
1287 brw_MOV(p, payload_value, value);
1288 brw_shader_time_add(p, payload,
1289 prog_data->base.binding_table.shader_time_start);
1290 brw_pop_insn_state(p);
1291
1292 brw_mark_surface_used(&prog_data->base,
1293 prog_data->base.binding_table.shader_time_start);
1294 }
1295
1296 void
1297 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1298 struct brw_reg atomic_op,
1299 struct brw_reg surf_index)
1300 {
1301 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1302 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1303 surf_index.file == BRW_IMMEDIATE_VALUE &&
1304 surf_index.type == BRW_REGISTER_TYPE_UD);
1305
1306 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1307 atomic_op.dw1.ud, surf_index.dw1.ud,
1308 inst->mlen, dispatch_width / 8);
1309
1310 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1311 }
1312
1313 void
1314 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1315 struct brw_reg surf_index)
1316 {
1317 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1318 surf_index.type == BRW_REGISTER_TYPE_UD);
1319
1320 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1321 surf_index.dw1.ud,
1322 inst->mlen, dispatch_width / 8);
1323
1324 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1325 }
1326
1327 void
1328 fs_generator::generate_code(exec_list *instructions)
1329 {
1330 int start_offset = p->next_insn_offset;
1331
1332 struct annotation_info annotation;
1333 memset(&annotation, 0, sizeof(annotation));
1334
1335 cfg_t *cfg = NULL;
1336 if (unlikely(debug_flag))
1337 cfg = new(mem_ctx) cfg_t(instructions);
1338
1339 foreach_in_list(fs_inst, inst, instructions) {
1340 struct brw_reg src[3], dst;
1341 unsigned int last_insn_offset = p->next_insn_offset;
1342
1343 if (unlikely(debug_flag))
1344 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1345
1346 for (unsigned int i = 0; i < inst->sources; i++) {
1347 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1348
1349 /* The accumulator result appears to get used for the
1350 * conditional modifier generation. When negating a UD
1351 * value, there is a 33rd bit generated for the sign in the
1352 * accumulator value, so now you can't check, for example,
1353 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1354 */
1355 assert(!inst->conditional_mod ||
1356 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1357 !inst->src[i].negate);
1358 }
1359 dst = brw_reg_from_fs_reg(&inst->dst);
1360
1361 brw_set_default_predicate_control(p, inst->predicate);
1362 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1363 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1364 brw_set_default_saturate(p, inst->saturate);
1365 brw_set_default_mask_control(p, inst->force_writemask_all);
1366 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1367
1368 if (inst->force_uncompressed || dispatch_width == 8) {
1369 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1370 } else if (inst->force_sechalf) {
1371 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1372 } else {
1373 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1374 }
1375
1376 switch (inst->opcode) {
1377 case BRW_OPCODE_MOV:
1378 brw_MOV(p, dst, src[0]);
1379 break;
1380 case BRW_OPCODE_ADD:
1381 brw_ADD(p, dst, src[0], src[1]);
1382 break;
1383 case BRW_OPCODE_MUL:
1384 brw_MUL(p, dst, src[0], src[1]);
1385 break;
1386 case BRW_OPCODE_AVG:
1387 brw_AVG(p, dst, src[0], src[1]);
1388 break;
1389 case BRW_OPCODE_MACH:
1390 brw_MACH(p, dst, src[0], src[1]);
1391 break;
1392
1393 case BRW_OPCODE_MAD:
1394 assert(brw->gen >= 6);
1395 brw_set_default_access_mode(p, BRW_ALIGN_16);
1396 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1397 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1398 brw_MAD(p, dst, src[0], src[1], src[2]);
1399 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1400 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1401 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1402 } else {
1403 brw_MAD(p, dst, src[0], src[1], src[2]);
1404 }
1405 brw_set_default_access_mode(p, BRW_ALIGN_1);
1406 break;
1407
1408 case BRW_OPCODE_LRP:
1409 assert(brw->gen >= 6);
1410 brw_set_default_access_mode(p, BRW_ALIGN_16);
1411 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1412 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1413 brw_LRP(p, dst, src[0], src[1], src[2]);
1414 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1415 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1416 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1417 } else {
1418 brw_LRP(p, dst, src[0], src[1], src[2]);
1419 }
1420 brw_set_default_access_mode(p, BRW_ALIGN_1);
1421 break;
1422
1423 case BRW_OPCODE_FRC:
1424 brw_FRC(p, dst, src[0]);
1425 break;
1426 case BRW_OPCODE_RNDD:
1427 brw_RNDD(p, dst, src[0]);
1428 break;
1429 case BRW_OPCODE_RNDE:
1430 brw_RNDE(p, dst, src[0]);
1431 break;
1432 case BRW_OPCODE_RNDZ:
1433 brw_RNDZ(p, dst, src[0]);
1434 break;
1435
1436 case BRW_OPCODE_AND:
1437 brw_AND(p, dst, src[0], src[1]);
1438 break;
1439 case BRW_OPCODE_OR:
1440 brw_OR(p, dst, src[0], src[1]);
1441 break;
1442 case BRW_OPCODE_XOR:
1443 brw_XOR(p, dst, src[0], src[1]);
1444 break;
1445 case BRW_OPCODE_NOT:
1446 brw_NOT(p, dst, src[0]);
1447 break;
1448 case BRW_OPCODE_ASR:
1449 brw_ASR(p, dst, src[0], src[1]);
1450 break;
1451 case BRW_OPCODE_SHR:
1452 brw_SHR(p, dst, src[0], src[1]);
1453 break;
1454 case BRW_OPCODE_SHL:
1455 brw_SHL(p, dst, src[0], src[1]);
1456 break;
1457 case BRW_OPCODE_F32TO16:
1458 assert(brw->gen >= 7);
1459 brw_F32TO16(p, dst, src[0]);
1460 break;
1461 case BRW_OPCODE_F16TO32:
1462 assert(brw->gen >= 7);
1463 brw_F16TO32(p, dst, src[0]);
1464 break;
1465 case BRW_OPCODE_CMP:
1466 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1467 break;
1468 case BRW_OPCODE_SEL:
1469 brw_SEL(p, dst, src[0], src[1]);
1470 break;
1471 case BRW_OPCODE_BFREV:
1472 assert(brw->gen >= 7);
1473 /* BFREV only supports UD type for src and dst. */
1474 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1475 retype(src[0], BRW_REGISTER_TYPE_UD));
1476 break;
1477 case BRW_OPCODE_FBH:
1478 assert(brw->gen >= 7);
1479 /* FBH only supports UD type for dst. */
1480 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1481 break;
1482 case BRW_OPCODE_FBL:
1483 assert(brw->gen >= 7);
1484 /* FBL only supports UD type for dst. */
1485 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1486 break;
1487 case BRW_OPCODE_CBIT:
1488 assert(brw->gen >= 7);
1489 /* CBIT only supports UD type for dst. */
1490 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1491 break;
1492 case BRW_OPCODE_ADDC:
1493 assert(brw->gen >= 7);
1494 brw_ADDC(p, dst, src[0], src[1]);
1495 break;
1496 case BRW_OPCODE_SUBB:
1497 assert(brw->gen >= 7);
1498 brw_SUBB(p, dst, src[0], src[1]);
1499 break;
1500 case BRW_OPCODE_MAC:
1501 brw_MAC(p, dst, src[0], src[1]);
1502 break;
1503
1504 case BRW_OPCODE_BFE:
1505 assert(brw->gen >= 7);
1506 brw_set_default_access_mode(p, BRW_ALIGN_16);
1507 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1508 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1509 brw_BFE(p, dst, src[0], src[1], src[2]);
1510 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1511 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1512 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1513 } else {
1514 brw_BFE(p, dst, src[0], src[1], src[2]);
1515 }
1516 brw_set_default_access_mode(p, BRW_ALIGN_1);
1517 break;
1518
1519 case BRW_OPCODE_BFI1:
1520 assert(brw->gen >= 7);
1521 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1522 * should
1523 *
1524 * "Force BFI instructions to be executed always in SIMD8."
1525 */
1526 if (dispatch_width == 16 && brw->is_haswell) {
1527 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1528 brw_BFI1(p, dst, src[0], src[1]);
1529 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1530 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1531 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1532 } else {
1533 brw_BFI1(p, dst, src[0], src[1]);
1534 }
1535 break;
1536 case BRW_OPCODE_BFI2:
1537 assert(brw->gen >= 7);
1538 brw_set_default_access_mode(p, BRW_ALIGN_16);
1539 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1540 * should
1541 *
1542 * "Force BFI instructions to be executed always in SIMD8."
1543 *
1544 * Otherwise we would be able to emit compressed instructions like we
1545 * do for the other three-source instructions.
1546 */
1547 if (dispatch_width == 16) {
1548 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1549 brw_BFI2(p, dst, src[0], src[1], src[2]);
1550 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1551 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1552 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1553 } else {
1554 brw_BFI2(p, dst, src[0], src[1], src[2]);
1555 }
1556 brw_set_default_access_mode(p, BRW_ALIGN_1);
1557 break;
1558
1559 case BRW_OPCODE_IF:
1560 if (inst->src[0].file != BAD_FILE) {
1561 /* The instruction has an embedded compare (only allowed on gen6) */
1562 assert(brw->gen == 6);
1563 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1564 } else {
1565 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1566 }
1567 break;
1568
1569 case BRW_OPCODE_ELSE:
1570 brw_ELSE(p);
1571 break;
1572 case BRW_OPCODE_ENDIF:
1573 brw_ENDIF(p);
1574 break;
1575
1576 case BRW_OPCODE_DO:
1577 brw_DO(p, BRW_EXECUTE_8);
1578 break;
1579
1580 case BRW_OPCODE_BREAK:
1581 brw_BREAK(p);
1582 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1583 break;
1584 case BRW_OPCODE_CONTINUE:
1585 brw_CONT(p);
1586 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1587 break;
1588
1589 case BRW_OPCODE_WHILE:
1590 brw_WHILE(p);
1591 break;
1592
1593 case SHADER_OPCODE_RCP:
1594 case SHADER_OPCODE_RSQ:
1595 case SHADER_OPCODE_SQRT:
1596 case SHADER_OPCODE_EXP2:
1597 case SHADER_OPCODE_LOG2:
1598 case SHADER_OPCODE_SIN:
1599 case SHADER_OPCODE_COS:
1600 assert(brw->gen < 6 || inst->mlen == 0);
1601 if (brw->gen >= 7) {
1602 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1603 brw_null_reg());
1604 } else if (brw->gen == 6) {
1605 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1606 } else if (brw->gen == 5 || brw->is_g4x) {
1607 generate_math_g45(inst, dst, src[0]);
1608 } else {
1609 generate_math_gen4(inst, dst, src[0]);
1610 }
1611 break;
1612 case SHADER_OPCODE_INT_QUOTIENT:
1613 case SHADER_OPCODE_INT_REMAINDER:
1614 case SHADER_OPCODE_POW:
1615 assert(brw->gen < 6 || inst->mlen == 0);
1616 if (brw->gen >= 7) {
1617 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1618 } else if (brw->gen == 6) {
1619 generate_math_gen6(inst, dst, src[0], src[1]);
1620 } else {
1621 generate_math_gen4(inst, dst, src[0]);
1622 }
1623 break;
1624 case FS_OPCODE_PIXEL_X:
1625 generate_pixel_xy(dst, true);
1626 break;
1627 case FS_OPCODE_PIXEL_Y:
1628 generate_pixel_xy(dst, false);
1629 break;
1630 case FS_OPCODE_CINTERP:
1631 brw_MOV(p, dst, src[0]);
1632 break;
1633 case FS_OPCODE_LINTERP:
1634 generate_linterp(inst, dst, src);
1635 break;
1636 case SHADER_OPCODE_TEX:
1637 case FS_OPCODE_TXB:
1638 case SHADER_OPCODE_TXD:
1639 case SHADER_OPCODE_TXF:
1640 case SHADER_OPCODE_TXF_CMS:
1641 case SHADER_OPCODE_TXF_UMS:
1642 case SHADER_OPCODE_TXF_MCS:
1643 case SHADER_OPCODE_TXL:
1644 case SHADER_OPCODE_TXS:
1645 case SHADER_OPCODE_LOD:
1646 case SHADER_OPCODE_TG4:
1647 case SHADER_OPCODE_TG4_OFFSET:
1648 generate_tex(inst, dst, src[0]);
1649 break;
1650 case FS_OPCODE_DDX:
1651 generate_ddx(inst, dst, src[0]);
1652 break;
1653 case FS_OPCODE_DDY:
1654 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1655 * guarantee that key->render_to_fbo is set).
1656 */
1657 assert(fp->UsesDFdy);
1658 generate_ddy(inst, dst, src[0], key->render_to_fbo);
1659 break;
1660
1661 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1662 generate_scratch_write(inst, src[0]);
1663 break;
1664
1665 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1666 generate_scratch_read(inst, dst);
1667 break;
1668
1669 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1670 generate_scratch_read_gen7(inst, dst);
1671 break;
1672
1673 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1674 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1675 break;
1676
1677 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1678 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1679 break;
1680
1681 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1682 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1683 break;
1684
1685 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1686 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1687 break;
1688
1689 case FS_OPCODE_FB_WRITE:
1690 generate_fb_write(inst);
1691 break;
1692
1693 case FS_OPCODE_BLORP_FB_WRITE:
1694 generate_blorp_fb_write(inst);
1695 break;
1696
1697 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1698 generate_mov_dispatch_to_flags(inst);
1699 break;
1700
1701 case FS_OPCODE_DISCARD_JUMP:
1702 generate_discard_jump(inst);
1703 break;
1704
1705 case SHADER_OPCODE_SHADER_TIME_ADD:
1706 generate_shader_time_add(inst, src[0], src[1], src[2]);
1707 break;
1708
1709 case SHADER_OPCODE_UNTYPED_ATOMIC:
1710 generate_untyped_atomic(inst, dst, src[0], src[1]);
1711 break;
1712
1713 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1714 generate_untyped_surface_read(inst, dst, src[0]);
1715 break;
1716
1717 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1718 generate_set_simd4x2_offset(inst, dst, src[0]);
1719 break;
1720
1721 case FS_OPCODE_SET_OMASK:
1722 generate_set_omask(inst, dst, src[0]);
1723 break;
1724
1725 case FS_OPCODE_SET_SAMPLE_ID:
1726 generate_set_sample_id(inst, dst, src[0], src[1]);
1727 break;
1728
1729 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1730 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1731 break;
1732
1733 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1734 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1735 generate_unpack_half_2x16_split(inst, dst, src[0]);
1736 break;
1737
1738 case FS_OPCODE_PLACEHOLDER_HALT:
1739 /* This is the place where the final HALT needs to be inserted if
1740 * we've emitted any discards. If not, this will emit no code.
1741 */
1742 if (!patch_discard_jumps_to_fb_writes()) {
1743 if (unlikely(debug_flag)) {
1744 annotation.ann_count--;
1745 }
1746 }
1747 break;
1748
1749 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
1750 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1751 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
1752 break;
1753
1754 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
1755 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1756 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
1757 break;
1758
1759 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
1760 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1761 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
1762 break;
1763
1764 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
1765 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1766 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
1767 break;
1768
1769 default:
1770 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1771 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1772 opcode_descs[inst->opcode].name);
1773 } else {
1774 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1775 }
1776 abort();
1777
1778 case SHADER_OPCODE_LOAD_PAYLOAD:
1779 unreachable("Should be lowered by lower_load_payload()");
1780 }
1781
1782 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1783 assert(p->next_insn_offset == last_insn_offset + 16 ||
1784 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1785 "emitting more than 1 instruction");
1786
1787 brw_inst *last = &p->store[last_insn_offset / 16];
1788
1789 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1790 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1791 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1792 }
1793 }
1794
1795 brw_set_uip_jip(p);
1796 annotation_finalize(&annotation, p->next_insn_offset);
1797
1798 int before_size = p->next_insn_offset - start_offset;
1799 brw_compact_instructions(p, start_offset, annotation.ann_count,
1800 annotation.ann);
1801 int after_size = p->next_insn_offset - start_offset;
1802
1803 if (unlikely(debug_flag)) {
1804 if (prog) {
1805 fprintf(stderr,
1806 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
1807 prog->Label ? prog->Label : "unnamed",
1808 prog->Name, dispatch_width);
1809 } else if (fp) {
1810 fprintf(stderr,
1811 "Native code for fragment program %d (SIMD%d dispatch):\n",
1812 fp->Base.Id, dispatch_width);
1813 } else {
1814 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
1815 dispatch_width);
1816 }
1817 fprintf(stderr, "SIMD%d shader: %d instructions. Compacted %d to %d"
1818 " bytes (%.0f%%)\n",
1819 dispatch_width, before_size / 16, before_size, after_size,
1820 100.0f * (before_size - after_size) / before_size);
1821
1822 const struct gl_program *prog = fp ? &fp->Base : NULL;
1823
1824 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1825 ralloc_free(annotation.ann);
1826 }
1827 }
1828
1829 const unsigned *
1830 fs_generator::generate_assembly(exec_list *simd8_instructions,
1831 exec_list *simd16_instructions,
1832 unsigned *assembly_size)
1833 {
1834 assert(simd8_instructions || simd16_instructions);
1835
1836 if (simd8_instructions) {
1837 dispatch_width = 8;
1838 generate_code(simd8_instructions);
1839 }
1840
1841 if (simd16_instructions) {
1842 /* align to 64 byte boundary. */
1843 while (p->next_insn_offset % 64) {
1844 brw_NOP(p);
1845 }
1846
1847 /* Save off the start of this SIMD16 program */
1848 prog_data->prog_offset_16 = p->next_insn_offset;
1849
1850 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1851
1852 dispatch_width = 16;
1853 generate_code(simd16_instructions);
1854 }
1855
1856 return brw_get_program(p, assembly_size);
1857 }