2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
31 #include "main/macros.h"
32 #include "brw_context.h"
39 fs_generator::fs_generator(struct brw_context
*brw
,
41 const struct brw_wm_prog_key
*key
,
42 struct brw_wm_prog_data
*prog_data
,
43 struct gl_shader_program
*shader_prog
,
44 struct gl_fragment_program
*fp
,
45 bool runtime_check_aads_emit
,
48 : brw(brw
), stage(MESA_SHADER_FRAGMENT
), key(key
),
49 prog_data(&prog_data
->base
), shader_prog(shader_prog
),
50 prog(&fp
->Base
), runtime_check_aads_emit(runtime_check_aads_emit
),
51 debug_flag(debug_flag
), mem_ctx(mem_ctx
)
55 p
= rzalloc(mem_ctx
, struct brw_compile
);
56 brw_init_compile(brw
, p
, mem_ctx
);
59 fs_generator::~fs_generator()
64 fs_generator::patch_discard_jumps_to_fb_writes()
66 if (brw
->gen
< 6 || this->discard_halt_patches
.is_empty())
69 int scale
= brw_jump_scale(brw
);
71 /* There is a somewhat strange undocumented requirement of using
72 * HALT, according to the simulator. If some channel has HALTed to
73 * a particular UIP, then by the end of the program, every channel
74 * must have HALTed to that UIP. Furthermore, the tracking is a
75 * stack, so you can't do the final halt of a UIP after starting
76 * halting to a new UIP.
78 * Symptoms of not emitting this instruction on actual hardware
79 * included GPU hangs and sparkly rendering on the piglit discard
82 brw_inst
*last_halt
= gen6_HALT(p
);
83 brw_inst_set_uip(brw
, last_halt
, 1 * scale
);
84 brw_inst_set_jip(brw
, last_halt
, 1 * scale
);
88 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
89 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
91 assert(brw_inst_opcode(brw
, patch
) == BRW_OPCODE_HALT
);
92 /* HALT takes a half-instruction distance from the pre-incremented IP. */
93 brw_inst_set_uip(brw
, patch
, (ip
- patch_ip
->ip
) * scale
);
96 this->discard_halt_patches
.make_empty();
101 fs_generator::fire_fb_write(fs_inst
*inst
,
103 struct brw_reg implied_header
,
106 uint32_t msg_control
;
108 assert(stage
== MESA_SHADER_FRAGMENT
);
109 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
112 brw_push_insn_state(p
);
113 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
114 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
115 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
117 brw_message_reg(base_reg
+ 1),
119 brw_pop_insn_state(p
);
122 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
)
123 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
124 else if (prog_data
->dual_src_blend
)
125 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
126 else if (dispatch_width
== 16)
127 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
129 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
131 uint32_t surf_index
=
132 prog_data
->binding_table
.render_target_start
+ inst
->target
;
143 inst
->header_present
);
145 brw_mark_surface_used(&prog_data
->base
, surf_index
);
149 fs_generator::generate_fb_write(fs_inst
*inst
)
151 assert(stage
== MESA_SHADER_FRAGMENT
);
152 gl_fragment_program
*fp
= (gl_fragment_program
*) prog
;
153 struct brw_reg implied_header
;
155 assert(stage
== MESA_SHADER_FRAGMENT
);
156 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
157 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
159 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
162 if (inst
->header_present
) {
163 brw_push_insn_state(p
);
164 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
165 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
166 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
167 brw_set_default_flag_reg(p
, 0, 0);
169 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
172 if (prog_data
->uses_kill
|| key
->alpha_test_func
) {
173 struct brw_reg pixel_mask
;
176 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
178 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
180 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
184 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
186 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
),
187 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
188 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
190 if (inst
->target
> 0 && key
->replicate_alpha
) {
191 /* Set "Source0 Alpha Present to RenderTarget" bit in message
195 vec1(retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
)),
196 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
197 brw_imm_ud(0x1 << 11));
200 if (inst
->target
> 0) {
201 /* Set the render target index for choosing BLEND_STATE. */
202 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
,
204 BRW_REGISTER_TYPE_UD
),
205 brw_imm_ud(inst
->target
));
208 implied_header
= brw_null_reg();
210 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
213 brw_pop_insn_state(p
);
215 implied_header
= brw_null_reg();
218 if (!runtime_check_aads_emit
) {
219 fire_fb_write(inst
, inst
->base_mrf
, implied_header
, inst
->mlen
);
221 /* This can only happen in gen < 6 */
222 assert(brw
->gen
< 6);
224 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
226 /* Check runtime bit to detect if we have to send AA data or not */
227 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
230 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
232 brw_inst_set_cond_modifier(brw
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
234 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
235 brw_inst_set_exec_size(brw
, brw_last_inst
, BRW_EXECUTE_1
);
237 /* Don't send AA data */
238 fire_fb_write(inst
, inst
->base_mrf
+1, implied_header
, inst
->mlen
-1);
240 brw_land_fwd_jump(p
, jmp
);
241 fire_fb_write(inst
, inst
->base_mrf
, implied_header
, inst
->mlen
);
246 fs_generator::generate_blorp_fb_write(fs_inst
*inst
)
249 16 /* dispatch_width */,
251 brw_reg_from_fs_reg(&inst
->src
[0]),
252 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
257 inst
->header_present
);
260 /* Computes the integer pixel x,y values from the origin.
262 * This is the basis of gl_FragCoord computation, but is also used
263 * pre-gen6 for computing the deltas from v0 for computing
267 fs_generator::generate_pixel_xy(struct brw_reg dst
, bool is_x
)
269 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
271 struct brw_reg deltas
;
274 src
= stride(suboffset(g1_uw
, 4), 2, 4, 0);
275 deltas
= brw_imm_v(0x10101010);
277 src
= stride(suboffset(g1_uw
, 5), 2, 4, 0);
278 deltas
= brw_imm_v(0x11001100);
281 if (dispatch_width
== 16) {
285 /* We do this SIMD8 or SIMD16, but since the destination is UW we
286 * don't do compression in the SIMD16 case.
288 brw_push_insn_state(p
);
289 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
290 brw_ADD(p
, dst
, src
, deltas
);
291 brw_pop_insn_state(p
);
295 fs_generator::generate_linterp(fs_inst
*inst
,
296 struct brw_reg dst
, struct brw_reg
*src
)
298 struct brw_reg delta_x
= src
[0];
299 struct brw_reg delta_y
= src
[1];
300 struct brw_reg interp
= src
[2];
303 delta_y
.nr
== delta_x
.nr
+ 1 &&
304 (brw
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
305 brw_PLN(p
, dst
, interp
, delta_x
);
307 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
308 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
313 fs_generator::generate_math_gen6(fs_inst
*inst
,
318 int op
= brw_math_function(inst
->opcode
);
319 bool binop
= src1
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
;
321 if (dispatch_width
== 8) {
322 gen6_math(p
, dst
, op
, src0
, src1
);
323 } else if (dispatch_width
== 16) {
324 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
325 gen6_math(p
, firsthalf(dst
), op
, firsthalf(src0
), firsthalf(src1
));
326 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
327 gen6_math(p
, sechalf(dst
), op
, sechalf(src0
),
328 binop
? sechalf(src1
) : brw_null_reg());
329 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
334 fs_generator::generate_math_gen4(fs_inst
*inst
,
338 int op
= brw_math_function(inst
->opcode
);
340 assert(inst
->mlen
>= 1);
342 if (dispatch_width
== 8) {
346 BRW_MATH_PRECISION_FULL
);
347 } else if (dispatch_width
== 16) {
348 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
349 gen4_math(p
, firsthalf(dst
),
351 inst
->base_mrf
, firsthalf(src
),
352 BRW_MATH_PRECISION_FULL
);
353 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
354 gen4_math(p
, sechalf(dst
),
356 inst
->base_mrf
+ 1, sechalf(src
),
357 BRW_MATH_PRECISION_FULL
);
359 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
364 fs_generator::generate_math_g45(fs_inst
*inst
,
368 if (inst
->opcode
== SHADER_OPCODE_POW
||
369 inst
->opcode
== SHADER_OPCODE_INT_QUOTIENT
||
370 inst
->opcode
== SHADER_OPCODE_INT_REMAINDER
) {
371 generate_math_gen4(inst
, dst
, src
);
375 int op
= brw_math_function(inst
->opcode
);
377 assert(inst
->mlen
>= 1);
382 BRW_MATH_PRECISION_FULL
);
386 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
387 struct brw_reg sampler_index
)
391 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
392 uint32_t return_format
;
395 case BRW_REGISTER_TYPE_D
:
396 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
398 case BRW_REGISTER_TYPE_UD
:
399 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
402 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
406 if (dispatch_width
== 16 &&
407 !inst
->force_uncompressed
&& !inst
->force_sechalf
)
408 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
411 switch (inst
->opcode
) {
412 case SHADER_OPCODE_TEX
:
413 if (inst
->shadow_compare
) {
414 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
416 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
420 if (inst
->shadow_compare
) {
421 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
423 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
426 case SHADER_OPCODE_TXL
:
427 if (inst
->shadow_compare
) {
428 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
430 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
433 case SHADER_OPCODE_TXS
:
434 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
436 case SHADER_OPCODE_TXD
:
437 if (inst
->shadow_compare
) {
438 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
439 assert(brw
->gen
>= 8 || brw
->is_haswell
);
440 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
442 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
445 case SHADER_OPCODE_TXF
:
446 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
448 case SHADER_OPCODE_TXF_CMS
:
450 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
452 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
454 case SHADER_OPCODE_TXF_UMS
:
455 assert(brw
->gen
>= 7);
456 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
458 case SHADER_OPCODE_TXF_MCS
:
459 assert(brw
->gen
>= 7);
460 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
462 case SHADER_OPCODE_LOD
:
463 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
465 case SHADER_OPCODE_TG4
:
466 if (inst
->shadow_compare
) {
467 assert(brw
->gen
>= 7);
468 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
470 assert(brw
->gen
>= 6);
471 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
474 case SHADER_OPCODE_TG4_OFFSET
:
475 assert(brw
->gen
>= 7);
476 if (inst
->shadow_compare
) {
477 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
479 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
483 unreachable("not reached");
486 switch (inst
->opcode
) {
487 case SHADER_OPCODE_TEX
:
488 /* Note that G45 and older determines shadow compare and dispatch width
489 * from message length for most messages.
491 assert(dispatch_width
== 8);
492 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
493 if (inst
->shadow_compare
) {
494 assert(inst
->mlen
== 6);
496 assert(inst
->mlen
<= 4);
500 if (inst
->shadow_compare
) {
501 assert(inst
->mlen
== 6);
502 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
504 assert(inst
->mlen
== 9);
505 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
506 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
509 case SHADER_OPCODE_TXL
:
510 if (inst
->shadow_compare
) {
511 assert(inst
->mlen
== 6);
512 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
514 assert(inst
->mlen
== 9);
515 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
516 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
519 case SHADER_OPCODE_TXD
:
520 /* There is no sample_d_c message; comparisons are done manually */
521 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
522 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
524 case SHADER_OPCODE_TXF
:
525 assert(inst
->mlen
== 9);
526 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
527 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
529 case SHADER_OPCODE_TXS
:
530 assert(inst
->mlen
== 3);
531 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
532 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
535 unreachable("not reached");
538 assert(msg_type
!= -1);
540 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
545 if (brw
->gen
>= 7 && inst
->header_present
&& dispatch_width
== 16) {
546 /* The send-from-GRF for SIMD16 texturing with a header has an extra
547 * hardware register allocated to it, which we need to skip over (since
548 * our coordinates in the payload are in the even-numbered registers,
549 * and the header comes right before the first one).
551 assert(src
.file
== BRW_GENERAL_REGISTER_FILE
);
555 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
557 /* Load the message header if present. If there's a texture offset,
558 * we need to set it up explicitly and load the offset bitfield.
559 * Otherwise, we can use an implied move from g0 to the first message reg.
561 if (inst
->header_present
) {
562 if (brw
->gen
< 6 && !inst
->texture_offset
) {
563 /* Set up an implied move from g0 to the MRF. */
564 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
566 struct brw_reg header_reg
;
571 assert(inst
->base_mrf
!= -1);
572 header_reg
= brw_message_reg(inst
->base_mrf
);
575 brw_push_insn_state(p
);
576 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
577 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
578 /* Explicitly set up the message header by copying g0 to the MRF. */
579 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
581 if (inst
->texture_offset
) {
582 /* Set the offset bits in DWord 2. */
583 brw_MOV(p
, get_element_ud(header_reg
, 2),
584 brw_imm_ud(inst
->texture_offset
));
587 brw_adjust_sampler_state_pointer(p
, header_reg
, sampler_index
, dst
);
588 brw_pop_insn_state(p
);
592 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
593 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
594 ? prog_data
->binding_table
.gather_texture_start
595 : prog_data
->binding_table
.texture_start
;
597 if (sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
598 uint32_t sampler
= sampler_index
.dw1
.ud
;
601 retype(dst
, BRW_REGISTER_TYPE_UW
),
604 sampler
+ base_binding_table_index
,
609 inst
->header_present
,
613 brw_mark_surface_used(prog_data
, sampler
+ base_binding_table_index
);
615 /* Non-const sampler index */
616 /* Note: this clobbers `dst` as a temporary before emitting the send */
618 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
619 struct brw_reg temp
= vec1(retype(dst
, BRW_REGISTER_TYPE_UD
));
621 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
623 brw_push_insn_state(p
);
624 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
625 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
627 /* Some care required: `sampler` and `temp` may alias:
628 * addr = sampler & 0xff
629 * temp = (sampler << 8) & 0xf00
632 brw_ADD(p
, addr
, sampler_reg
, brw_imm_ud(base_binding_table_index
));
633 brw_SHL(p
, temp
, sampler_reg
, brw_imm_ud(8u));
634 brw_AND(p
, temp
, temp
, brw_imm_ud(0x0f00));
635 brw_AND(p
, addr
, addr
, brw_imm_ud(0x0ff));
636 brw_OR(p
, addr
, addr
, temp
);
638 /* a0.0 |= <descriptor> */
639 brw_inst
*insn_or
= brw_next_insn(p
, BRW_OPCODE_OR
);
640 brw_set_sampler_message(p
, insn_or
,
645 inst
->mlen
/* mlen */,
646 inst
->header_present
/* header */,
649 brw_inst_set_exec_size(p
->brw
, insn_or
, BRW_EXECUTE_1
);
650 brw_inst_set_src1_reg_type(p
->brw
, insn_or
, BRW_REGISTER_TYPE_UD
);
651 brw_set_src0(p
, insn_or
, addr
);
652 brw_set_dest(p
, insn_or
, addr
);
655 /* dst = send(offset, a0.0) */
656 brw_inst
*insn_send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
657 brw_set_dest(p
, insn_send
, dst
);
658 brw_set_src0(p
, insn_send
, src
);
659 brw_set_indirect_send_descriptor(p
, insn_send
, BRW_SFID_SAMPLER
, addr
);
661 brw_pop_insn_state(p
);
663 /* visitor knows more than we do about the surface limit required,
664 * so has already done marking.
670 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
673 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
675 * Ideally, we want to produce:
678 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
679 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
680 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
681 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
682 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
683 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
684 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
685 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
687 * and add another set of two more subspans if in 16-pixel dispatch mode.
689 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
690 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
691 * pair. But the ideal approximation may impose a huge performance cost on
692 * sample_d. On at least Haswell, sample_d instruction does some
693 * optimizations if the same LOD is used for all pixels in the subspan.
695 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
696 * appropriate swizzling.
699 fs_generator::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
700 struct brw_reg quality
)
702 unsigned vstride
, width
;
703 assert(quality
.file
== BRW_IMMEDIATE_VALUE
);
704 assert(quality
.type
== BRW_REGISTER_TYPE_D
);
706 assert(stage
== MESA_SHADER_FRAGMENT
);
707 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
709 int quality_value
= quality
.dw1
.d
;
711 if (quality_value
== BRW_DERIVATIVE_FINE
||
712 (key
->high_quality_derivatives
&& quality_value
!= BRW_DERIVATIVE_COARSE
)) {
713 /* produce accurate derivatives */
714 vstride
= BRW_VERTICAL_STRIDE_2
;
718 /* replicate the derivative at the top-left pixel to other pixels */
719 vstride
= BRW_VERTICAL_STRIDE_4
;
723 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
727 BRW_HORIZONTAL_STRIDE_0
,
728 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
729 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
733 BRW_HORIZONTAL_STRIDE_0
,
734 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
735 brw_ADD(p
, dst
, src0
, negate(src1
));
738 /* The negate_value boolean is used to negate the derivative computation for
739 * FBOs, since they place the origin at the upper left instead of the lower
743 fs_generator::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
744 struct brw_reg quality
, bool negate_value
)
746 assert(quality
.file
== BRW_IMMEDIATE_VALUE
);
747 assert(quality
.type
== BRW_REGISTER_TYPE_D
);
749 assert(stage
== MESA_SHADER_FRAGMENT
);
750 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
752 int quality_value
= quality
.dw1
.d
;
754 if (quality_value
== BRW_DERIVATIVE_FINE
||
755 (key
->high_quality_derivatives
&& quality_value
!= BRW_DERIVATIVE_COARSE
)) {
756 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
757 * Region Restrictions):
759 * In Align16 access mode, SIMD16 is not allowed for DW operations
760 * and SIMD8 is not allowed for DF operations.
762 * In this context, "DW operations" means "operations acting on 32-bit
763 * values", so it includes operations on floats.
765 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
766 * (Instruction Compression -> Rules and Restrictions):
768 * A compressed instruction must be in Align1 access mode. Align16
769 * mode instructions cannot be compressed.
771 * Similar text exists in the g45 PRM.
773 * On these platforms, if we're building a SIMD16 shader, we need to
774 * manually unroll to a pair of SIMD8 instructions.
776 bool unroll_to_simd8
=
777 (dispatch_width
== 16 &&
778 (brw
->gen
== 4 || (brw
->gen
== 7 && !brw
->is_haswell
)));
780 /* produce accurate derivatives */
781 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
783 BRW_VERTICAL_STRIDE_4
,
785 BRW_HORIZONTAL_STRIDE_1
,
786 BRW_SWIZZLE_XYXY
, WRITEMASK_XYZW
);
787 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
789 BRW_VERTICAL_STRIDE_4
,
791 BRW_HORIZONTAL_STRIDE_1
,
792 BRW_SWIZZLE_ZWZW
, WRITEMASK_XYZW
);
793 brw_push_insn_state(p
);
794 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
795 if (unroll_to_simd8
) {
796 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
798 brw_ADD(p
, firsthalf(dst
), firsthalf(src1
), negate(firsthalf(src0
)));
799 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
800 brw_ADD(p
, sechalf(dst
), sechalf(src1
), negate(sechalf(src0
)));
802 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), negate(firsthalf(src1
)));
803 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
804 brw_ADD(p
, sechalf(dst
), sechalf(src0
), negate(sechalf(src1
)));
808 brw_ADD(p
, dst
, src1
, negate(src0
));
810 brw_ADD(p
, dst
, src0
, negate(src1
));
812 brw_pop_insn_state(p
);
814 /* replicate the derivative at the top-left pixel to other pixels */
815 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
817 BRW_VERTICAL_STRIDE_4
,
819 BRW_HORIZONTAL_STRIDE_0
,
820 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
821 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
823 BRW_VERTICAL_STRIDE_4
,
825 BRW_HORIZONTAL_STRIDE_0
,
826 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
828 brw_ADD(p
, dst
, src1
, negate(src0
));
830 brw_ADD(p
, dst
, src0
, negate(src1
));
835 fs_generator::generate_discard_jump(fs_inst
*inst
)
837 assert(brw
->gen
>= 6);
839 /* This HALT will be patched up at FB write time to point UIP at the end of
840 * the program, and at brw_uip_jip() JIP will be set to the end of the
841 * current block (or the program).
843 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
845 brw_push_insn_state(p
);
846 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
848 brw_pop_insn_state(p
);
852 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
854 assert(inst
->mlen
!= 0);
857 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
858 retype(src
, BRW_REGISTER_TYPE_UD
));
859 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
860 dispatch_width
/ 8, inst
->offset
);
864 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
866 assert(inst
->mlen
!= 0);
868 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
869 dispatch_width
/ 8, inst
->offset
);
873 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
875 gen7_block_read_scratch(p
, dst
, dispatch_width
/ 8, inst
->offset
);
879 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
881 struct brw_reg index
,
882 struct brw_reg offset
)
884 assert(inst
->mlen
!= 0);
886 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
887 index
.type
== BRW_REGISTER_TYPE_UD
);
888 uint32_t surf_index
= index
.dw1
.ud
;
890 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
891 offset
.type
== BRW_REGISTER_TYPE_UD
);
892 uint32_t read_offset
= offset
.dw1
.ud
;
894 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
895 read_offset
, surf_index
);
897 brw_mark_surface_used(prog_data
, surf_index
);
901 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
903 struct brw_reg index
,
904 struct brw_reg offset
)
906 assert(inst
->mlen
== 0);
907 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
909 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
910 /* Reference just the dword we need, to avoid angering validate_reg(). */
911 offset
= brw_vec1_grf(offset
.nr
, 0);
913 /* We use the SIMD4x2 mode because we want to end up with 4 components in
914 * the destination loaded consecutively from the same offset (which appears
915 * in the first component, and the rest are ignored).
917 dst
.width
= BRW_WIDTH_4
;
919 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
921 uint32_t surf_index
= index
.dw1
.ud
;
923 brw_push_insn_state(p
);
924 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
925 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
926 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
927 brw_pop_insn_state(p
);
929 brw_set_dest(p
, send
, dst
);
930 brw_set_src0(p
, send
, offset
);
931 brw_set_sampler_message(p
, send
,
933 0, /* LD message ignores sampler unit */
934 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
937 false, /* no header */
938 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
941 brw_mark_surface_used(prog_data
, surf_index
);
945 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
947 brw_push_insn_state(p
);
948 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
949 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
951 /* a0.0 = surf_index & 0xff */
952 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
953 brw_inst_set_exec_size(p
->brw
, insn_and
, BRW_EXECUTE_1
);
954 brw_set_dest(p
, insn_and
, addr
);
955 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
956 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
959 /* a0.0 |= <descriptor> */
960 brw_inst
*insn_or
= brw_next_insn(p
, BRW_OPCODE_OR
);
961 brw_set_sampler_message(p
, insn_or
,
964 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
968 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
970 brw_inst_set_exec_size(p
->brw
, insn_or
, BRW_EXECUTE_1
);
971 brw_inst_set_src1_reg_type(p
->brw
, insn_or
, BRW_REGISTER_TYPE_UD
);
972 brw_set_src0(p
, insn_or
, addr
);
973 brw_set_dest(p
, insn_or
, addr
);
976 /* dst = send(offset, a0.0) */
977 brw_inst
*insn_send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
978 brw_set_dest(p
, insn_send
, dst
);
979 brw_set_src0(p
, insn_send
, offset
);
980 brw_set_indirect_send_descriptor(p
, insn_send
, BRW_SFID_SAMPLER
, addr
);
982 brw_pop_insn_state(p
);
984 /* visitor knows more than we do about the surface limit required,
985 * so has already done marking.
992 fs_generator::generate_varying_pull_constant_load(fs_inst
*inst
,
994 struct brw_reg index
,
995 struct brw_reg offset
)
997 assert(brw
->gen
< 7); /* Should use the gen7 variant. */
998 assert(inst
->header_present
);
1001 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1002 index
.type
== BRW_REGISTER_TYPE_UD
);
1003 uint32_t surf_index
= index
.dw1
.ud
;
1005 uint32_t simd_mode
, rlen
, msg_type
;
1006 if (dispatch_width
== 16) {
1007 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1010 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1015 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1017 /* We always use the SIMD16 message so that we only have to load U, and
1020 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1021 assert(inst
->mlen
== 3);
1022 assert(inst
->regs_written
== 8);
1024 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1027 struct brw_reg offset_mrf
= retype(brw_message_reg(inst
->base_mrf
+ 1),
1028 BRW_REGISTER_TYPE_D
);
1029 brw_MOV(p
, offset_mrf
, offset
);
1031 struct brw_reg header
= brw_vec8_grf(0, 0);
1032 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1034 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1035 brw_inst_set_qtr_control(brw
, send
, BRW_COMPRESSION_NONE
);
1036 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1037 brw_set_src0(p
, send
, header
);
1039 brw_inst_set_base_mrf(brw
, send
, inst
->base_mrf
);
1041 /* Our surface is set up as floats, regardless of what actual data is
1044 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1045 brw_set_sampler_message(p
, send
,
1047 0, /* sampler (unused) */
1051 inst
->header_present
,
1055 brw_mark_surface_used(prog_data
, surf_index
);
1059 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1061 struct brw_reg index
,
1062 struct brw_reg offset
)
1064 assert(brw
->gen
>= 7);
1065 /* Varying-offset pull constant loads are treated as a normal expression on
1066 * gen7, so the fact that it's a send message is hidden at the IR level.
1068 assert(!inst
->header_present
);
1069 assert(!inst
->mlen
);
1070 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1072 uint32_t simd_mode
, rlen
, mlen
;
1073 if (dispatch_width
== 16) {
1076 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1080 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1083 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1085 uint32_t surf_index
= index
.dw1
.ud
;
1087 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1088 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1089 brw_set_src0(p
, send
, offset
);
1090 brw_set_sampler_message(p
, send
,
1092 0, /* LD message ignores sampler unit */
1093 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1096 false, /* no header */
1100 brw_mark_surface_used(prog_data
, surf_index
);
1104 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1106 brw_push_insn_state(p
);
1107 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1108 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1110 /* a0.0 = surf_index & 0xff */
1111 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1112 brw_inst_set_exec_size(p
->brw
, insn_and
, BRW_EXECUTE_1
);
1113 brw_set_dest(p
, insn_and
, addr
);
1114 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1115 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1118 /* a0.0 |= <descriptor> */
1119 brw_inst
*insn_or
= brw_next_insn(p
, BRW_OPCODE_OR
);
1120 brw_set_sampler_message(p
, insn_or
,
1123 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1129 brw_inst_set_exec_size(p
->brw
, insn_or
, BRW_EXECUTE_1
);
1130 brw_inst_set_src1_reg_type(p
->brw
, insn_or
, BRW_REGISTER_TYPE_UD
);
1131 brw_set_src0(p
, insn_or
, addr
);
1132 brw_set_dest(p
, insn_or
, addr
);
1135 /* dst = send(offset, a0.0) */
1136 brw_inst
*insn_send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1137 brw_set_dest(p
, insn_send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1138 brw_set_src0(p
, insn_send
, offset
);
1139 brw_set_indirect_send_descriptor(p
, insn_send
, BRW_SFID_SAMPLER
, addr
);
1141 brw_pop_insn_state(p
);
1143 /* visitor knows more than we do about the surface limit required,
1144 * so has already done marking.
1150 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1151 * into the flags register (f0.0).
1153 * Used only on Gen6 and above.
1156 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1158 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
1159 struct brw_reg dispatch_mask
;
1162 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1164 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1166 brw_push_insn_state(p
);
1167 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1168 brw_MOV(p
, flags
, dispatch_mask
);
1169 brw_pop_insn_state(p
);
1173 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1176 struct brw_reg msg_data
,
1179 assert(msg_data
.file
== BRW_IMMEDIATE_VALUE
&&
1180 msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1182 brw_pixel_interpolator_query(p
,
1183 retype(dst
, BRW_REGISTER_TYPE_UW
),
1185 inst
->pi_noperspective
,
1189 inst
->regs_written
);
1193 static uint32_t brw_file_from_reg(fs_reg
*reg
)
1195 switch (reg
->file
) {
1197 return BRW_GENERAL_REGISTER_FILE
;
1199 return BRW_MESSAGE_REGISTER_FILE
;
1201 return BRW_IMMEDIATE_VALUE
;
1203 unreachable("not reached");
1208 brw_reg_from_fs_reg(fs_reg
*reg
)
1210 struct brw_reg brw_reg
;
1212 switch (reg
->file
) {
1215 if (reg
->stride
== 0) {
1216 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
1218 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
1219 brw_reg
= stride(brw_reg
, 8 * reg
->stride
, 8, reg
->stride
);
1222 brw_reg
= retype(brw_reg
, reg
->type
);
1223 brw_reg
= byte_offset(brw_reg
, reg
->subreg_offset
);
1226 switch (reg
->type
) {
1227 case BRW_REGISTER_TYPE_F
:
1228 brw_reg
= brw_imm_f(reg
->fixed_hw_reg
.dw1
.f
);
1230 case BRW_REGISTER_TYPE_D
:
1231 brw_reg
= brw_imm_d(reg
->fixed_hw_reg
.dw1
.d
);
1233 case BRW_REGISTER_TYPE_UD
:
1234 brw_reg
= brw_imm_ud(reg
->fixed_hw_reg
.dw1
.ud
);
1237 unreachable("not reached");
1241 assert(reg
->type
== reg
->fixed_hw_reg
.type
);
1242 brw_reg
= reg
->fixed_hw_reg
;
1245 /* Probably unused. */
1246 brw_reg
= brw_null_reg();
1249 unreachable("not reached");
1251 unreachable("not reached");
1254 brw_reg
= brw_abs(brw_reg
);
1256 brw_reg
= negate(brw_reg
);
1262 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1263 * sampler LD messages.
1265 * We don't want to bake it into the send message's code generation because
1266 * that means we don't get a chance to schedule the instructions.
1269 fs_generator::generate_set_simd4x2_offset(fs_inst
*inst
,
1271 struct brw_reg value
)
1273 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1275 brw_push_insn_state(p
);
1276 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1277 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1278 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 0), value
.type
), value
);
1279 brw_pop_insn_state(p
);
1282 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1283 * (when mask is passed as a uniform) of register mask before moving it
1287 fs_generator::generate_set_omask(fs_inst
*inst
,
1289 struct brw_reg mask
)
1292 (mask
.vstride
== BRW_VERTICAL_STRIDE_8
&&
1293 mask
.width
== BRW_WIDTH_8
&&
1294 mask
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
1297 (mask
.vstride
== BRW_VERTICAL_STRIDE_0
&&
1298 mask
.width
== BRW_WIDTH_1
&&
1299 mask
.hstride
== BRW_HORIZONTAL_STRIDE_0
);
1301 assert(stride_8_8_1
|| stride_0_1_0
);
1302 assert(dst
.type
== BRW_REGISTER_TYPE_UW
);
1304 if (dispatch_width
== 16)
1306 brw_push_insn_state(p
);
1307 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1308 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1311 brw_MOV(p
, dst
, retype(stride(mask
, 16, 8, 2), dst
.type
));
1312 } else if (stride_0_1_0
) {
1313 brw_MOV(p
, dst
, retype(mask
, dst
.type
));
1315 brw_pop_insn_state(p
);
1318 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1319 * the ADD instruction.
1322 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1324 struct brw_reg src0
,
1325 struct brw_reg src1
)
1327 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1328 dst
.type
== BRW_REGISTER_TYPE_UD
);
1329 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1330 src0
.type
== BRW_REGISTER_TYPE_UD
);
1332 brw_push_insn_state(p
);
1333 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1334 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1335 struct brw_reg reg
= retype(stride(src1
, 1, 4, 0), BRW_REGISTER_TYPE_UW
);
1336 if (dispatch_width
== 8) {
1337 brw_ADD(p
, dst
, src0
, reg
);
1338 } else if (dispatch_width
== 16) {
1339 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), reg
);
1340 brw_ADD(p
, sechalf(dst
), sechalf(src0
), suboffset(reg
, 2));
1342 brw_pop_insn_state(p
);
1346 * Change the register's data type from UD to W, doubling the strides in order
1347 * to compensate for halving the data type width.
1349 static struct brw_reg
1350 ud_reg_to_w(struct brw_reg r
)
1352 assert(r
.type
== BRW_REGISTER_TYPE_UD
);
1353 r
.type
= BRW_REGISTER_TYPE_W
;
1355 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1356 * doubles the real stride.
1367 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
1372 assert(brw
->gen
>= 7);
1373 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1374 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1375 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1377 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1379 * Because this instruction does not have a 16-bit floating-point type,
1380 * the destination data type must be Word (W).
1382 * The destination must be DWord-aligned and specify a horizontal stride
1383 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1384 * each destination channel and the upper word is not modified.
1386 struct brw_reg dst_w
= ud_reg_to_w(dst
);
1388 /* Give each 32-bit channel of dst the form below , where "." means
1392 brw_F32TO16(p
, dst_w
, y
);
1397 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1399 /* And, finally the form of packHalf2x16's output:
1402 brw_F32TO16(p
, dst_w
, x
);
1406 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1410 assert(brw
->gen
>= 7);
1411 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1412 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1414 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1416 * Because this instruction does not have a 16-bit floating-point type,
1417 * the source data type must be Word (W). The destination type must be
1420 struct brw_reg src_w
= ud_reg_to_w(src
);
1422 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1423 * For the Y case, we wish to access only the upper word; therefore
1424 * a 16-bit subregister offset is needed.
1426 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1427 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1428 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1431 brw_F16TO32(p
, dst
, src_w
);
1435 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1436 struct brw_reg payload
,
1437 struct brw_reg offset
,
1438 struct brw_reg value
)
1440 assert(brw
->gen
>= 7);
1441 brw_push_insn_state(p
);
1442 brw_set_default_mask_control(p
, true);
1444 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1445 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1447 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1450 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1451 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1452 value
.width
= BRW_WIDTH_1
;
1453 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1454 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1456 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1459 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1460 * case, and we don't really care about squeezing every bit of performance
1461 * out of this path, so we just emit the MOVs from here.
1463 brw_MOV(p
, payload_offset
, offset
);
1464 brw_MOV(p
, payload_value
, value
);
1465 brw_shader_time_add(p
, payload
,
1466 prog_data
->binding_table
.shader_time_start
);
1467 brw_pop_insn_state(p
);
1469 brw_mark_surface_used(prog_data
,
1470 prog_data
->binding_table
.shader_time_start
);
1474 fs_generator::generate_untyped_atomic(fs_inst
*inst
, struct brw_reg dst
,
1475 struct brw_reg atomic_op
,
1476 struct brw_reg surf_index
)
1478 assert(atomic_op
.file
== BRW_IMMEDIATE_VALUE
&&
1479 atomic_op
.type
== BRW_REGISTER_TYPE_UD
&&
1480 surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
1481 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
1483 brw_untyped_atomic(p
, dst
, brw_message_reg(inst
->base_mrf
),
1484 atomic_op
.dw1
.ud
, surf_index
.dw1
.ud
,
1485 inst
->mlen
, dispatch_width
/ 8);
1487 brw_mark_surface_used(prog_data
, surf_index
.dw1
.ud
);
1491 fs_generator::generate_untyped_surface_read(fs_inst
*inst
, struct brw_reg dst
,
1492 struct brw_reg surf_index
)
1494 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
1495 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
1497 brw_untyped_surface_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1499 inst
->mlen
, dispatch_width
/ 8);
1501 brw_mark_surface_used(prog_data
, surf_index
.dw1
.ud
);
1505 fs_generator::generate_code(const cfg_t
*cfg
)
1507 int start_offset
= p
->next_insn_offset
;
1510 struct annotation_info annotation
;
1511 memset(&annotation
, 0, sizeof(annotation
));
1513 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1514 struct brw_reg src
[3], dst
;
1515 unsigned int last_insn_offset
= p
->next_insn_offset
;
1517 if (unlikely(debug_flag
))
1518 annotate(brw
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1520 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1521 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1523 /* The accumulator result appears to get used for the
1524 * conditional modifier generation. When negating a UD
1525 * value, there is a 33rd bit generated for the sign in the
1526 * accumulator value, so now you can't check, for example,
1527 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1529 assert(!inst
->conditional_mod
||
1530 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1531 !inst
->src
[i
].negate
);
1533 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1535 brw_set_default_predicate_control(p
, inst
->predicate
);
1536 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1537 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1538 brw_set_default_saturate(p
, inst
->saturate
);
1539 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1540 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1542 if (inst
->force_uncompressed
|| dispatch_width
== 8) {
1543 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1544 } else if (inst
->force_sechalf
) {
1545 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1547 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1550 switch (inst
->opcode
) {
1551 case BRW_OPCODE_MOV
:
1552 brw_MOV(p
, dst
, src
[0]);
1554 case BRW_OPCODE_ADD
:
1555 brw_ADD(p
, dst
, src
[0], src
[1]);
1557 case BRW_OPCODE_MUL
:
1558 brw_MUL(p
, dst
, src
[0], src
[1]);
1560 case BRW_OPCODE_AVG
:
1561 brw_AVG(p
, dst
, src
[0], src
[1]);
1563 case BRW_OPCODE_MACH
:
1564 brw_MACH(p
, dst
, src
[0], src
[1]);
1567 case BRW_OPCODE_MAD
:
1568 assert(brw
->gen
>= 6);
1569 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1570 if (dispatch_width
== 16 && brw
->gen
< 8 && !brw
->is_haswell
) {
1571 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1572 brw_MAD(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1573 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1574 brw_MAD(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1575 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1577 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1579 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1582 case BRW_OPCODE_LRP
:
1583 assert(brw
->gen
>= 6);
1584 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1585 if (dispatch_width
== 16 && brw
->gen
< 8 && !brw
->is_haswell
) {
1586 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1587 brw_LRP(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1588 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1589 brw_LRP(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1590 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1592 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1594 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1597 case BRW_OPCODE_FRC
:
1598 brw_FRC(p
, dst
, src
[0]);
1600 case BRW_OPCODE_RNDD
:
1601 brw_RNDD(p
, dst
, src
[0]);
1603 case BRW_OPCODE_RNDE
:
1604 brw_RNDE(p
, dst
, src
[0]);
1606 case BRW_OPCODE_RNDZ
:
1607 brw_RNDZ(p
, dst
, src
[0]);
1610 case BRW_OPCODE_AND
:
1611 brw_AND(p
, dst
, src
[0], src
[1]);
1614 brw_OR(p
, dst
, src
[0], src
[1]);
1616 case BRW_OPCODE_XOR
:
1617 brw_XOR(p
, dst
, src
[0], src
[1]);
1619 case BRW_OPCODE_NOT
:
1620 brw_NOT(p
, dst
, src
[0]);
1622 case BRW_OPCODE_ASR
:
1623 brw_ASR(p
, dst
, src
[0], src
[1]);
1625 case BRW_OPCODE_SHR
:
1626 brw_SHR(p
, dst
, src
[0], src
[1]);
1628 case BRW_OPCODE_SHL
:
1629 brw_SHL(p
, dst
, src
[0], src
[1]);
1631 case BRW_OPCODE_F32TO16
:
1632 assert(brw
->gen
>= 7);
1633 brw_F32TO16(p
, dst
, src
[0]);
1635 case BRW_OPCODE_F16TO32
:
1636 assert(brw
->gen
>= 7);
1637 brw_F16TO32(p
, dst
, src
[0]);
1639 case BRW_OPCODE_CMP
:
1640 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1642 case BRW_OPCODE_SEL
:
1643 brw_SEL(p
, dst
, src
[0], src
[1]);
1645 case BRW_OPCODE_BFREV
:
1646 assert(brw
->gen
>= 7);
1647 /* BFREV only supports UD type for src and dst. */
1648 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1649 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1651 case BRW_OPCODE_FBH
:
1652 assert(brw
->gen
>= 7);
1653 /* FBH only supports UD type for dst. */
1654 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1656 case BRW_OPCODE_FBL
:
1657 assert(brw
->gen
>= 7);
1658 /* FBL only supports UD type for dst. */
1659 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1661 case BRW_OPCODE_CBIT
:
1662 assert(brw
->gen
>= 7);
1663 /* CBIT only supports UD type for dst. */
1664 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1666 case BRW_OPCODE_ADDC
:
1667 assert(brw
->gen
>= 7);
1668 brw_ADDC(p
, dst
, src
[0], src
[1]);
1670 case BRW_OPCODE_SUBB
:
1671 assert(brw
->gen
>= 7);
1672 brw_SUBB(p
, dst
, src
[0], src
[1]);
1674 case BRW_OPCODE_MAC
:
1675 brw_MAC(p
, dst
, src
[0], src
[1]);
1678 case BRW_OPCODE_BFE
:
1679 assert(brw
->gen
>= 7);
1680 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1681 if (dispatch_width
== 16 && brw
->gen
< 8 && !brw
->is_haswell
) {
1682 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1683 brw_BFE(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1684 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1685 brw_BFE(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1686 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1688 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1690 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1693 case BRW_OPCODE_BFI1
:
1694 assert(brw
->gen
>= 7);
1695 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1698 * "Force BFI instructions to be executed always in SIMD8."
1700 if (dispatch_width
== 16 && brw
->is_haswell
) {
1701 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1702 brw_BFI1(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]));
1703 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1704 brw_BFI1(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]));
1705 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1707 brw_BFI1(p
, dst
, src
[0], src
[1]);
1710 case BRW_OPCODE_BFI2
:
1711 assert(brw
->gen
>= 7);
1712 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1713 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1716 * "Force BFI instructions to be executed always in SIMD8."
1718 * Otherwise we would be able to emit compressed instructions like we
1719 * do for the other three-source instructions.
1721 if (dispatch_width
== 16) {
1722 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1723 brw_BFI2(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1724 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1725 brw_BFI2(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1726 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1728 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1730 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1734 if (inst
->src
[0].file
!= BAD_FILE
) {
1735 /* The instruction has an embedded compare (only allowed on gen6) */
1736 assert(brw
->gen
== 6);
1737 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1739 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1743 case BRW_OPCODE_ELSE
:
1746 case BRW_OPCODE_ENDIF
:
1751 brw_DO(p
, BRW_EXECUTE_8
);
1754 case BRW_OPCODE_BREAK
:
1756 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1758 case BRW_OPCODE_CONTINUE
:
1760 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1763 case BRW_OPCODE_WHILE
:
1768 case SHADER_OPCODE_RCP
:
1769 case SHADER_OPCODE_RSQ
:
1770 case SHADER_OPCODE_SQRT
:
1771 case SHADER_OPCODE_EXP2
:
1772 case SHADER_OPCODE_LOG2
:
1773 case SHADER_OPCODE_SIN
:
1774 case SHADER_OPCODE_COS
:
1775 assert(brw
->gen
< 6 || inst
->mlen
== 0);
1776 if (brw
->gen
>= 7) {
1777 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1779 } else if (brw
->gen
== 6) {
1780 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
1781 } else if (brw
->gen
== 5 || brw
->is_g4x
) {
1782 generate_math_g45(inst
, dst
, src
[0]);
1784 generate_math_gen4(inst
, dst
, src
[0]);
1787 case SHADER_OPCODE_INT_QUOTIENT
:
1788 case SHADER_OPCODE_INT_REMAINDER
:
1789 case SHADER_OPCODE_POW
:
1790 assert(brw
->gen
< 6 || inst
->mlen
== 0);
1791 if (brw
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) {
1792 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1793 } else if (brw
->gen
>= 6) {
1794 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
1796 generate_math_gen4(inst
, dst
, src
[0]);
1799 case FS_OPCODE_PIXEL_X
:
1800 generate_pixel_xy(dst
, true);
1802 case FS_OPCODE_PIXEL_Y
:
1803 generate_pixel_xy(dst
, false);
1805 case FS_OPCODE_CINTERP
:
1806 brw_MOV(p
, dst
, src
[0]);
1808 case FS_OPCODE_LINTERP
:
1809 generate_linterp(inst
, dst
, src
);
1811 case SHADER_OPCODE_TEX
:
1813 case SHADER_OPCODE_TXD
:
1814 case SHADER_OPCODE_TXF
:
1815 case SHADER_OPCODE_TXF_CMS
:
1816 case SHADER_OPCODE_TXF_UMS
:
1817 case SHADER_OPCODE_TXF_MCS
:
1818 case SHADER_OPCODE_TXL
:
1819 case SHADER_OPCODE_TXS
:
1820 case SHADER_OPCODE_LOD
:
1821 case SHADER_OPCODE_TG4
:
1822 case SHADER_OPCODE_TG4_OFFSET
:
1823 generate_tex(inst
, dst
, src
[0], src
[1]);
1826 generate_ddx(inst
, dst
, src
[0], src
[1]);
1829 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1830 * guarantee that key->render_to_fbo is set).
1832 assert(stage
== MESA_SHADER_FRAGMENT
&&
1833 ((gl_fragment_program
*) prog
)->UsesDFdy
);
1834 generate_ddy(inst
, dst
, src
[0], src
[1],
1835 ((brw_wm_prog_key
* const) this->key
)->render_to_fbo
);
1838 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1839 generate_scratch_write(inst
, src
[0]);
1842 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1843 generate_scratch_read(inst
, dst
);
1846 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
1847 generate_scratch_read_gen7(inst
, dst
);
1850 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1851 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1854 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
1855 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1858 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
1859 generate_varying_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1862 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
1863 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1866 case FS_OPCODE_REP_FB_WRITE
:
1867 case FS_OPCODE_FB_WRITE
:
1868 generate_fb_write(inst
);
1871 case FS_OPCODE_BLORP_FB_WRITE
:
1872 generate_blorp_fb_write(inst
);
1875 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
1876 generate_mov_dispatch_to_flags(inst
);
1879 case FS_OPCODE_DISCARD_JUMP
:
1880 generate_discard_jump(inst
);
1883 case SHADER_OPCODE_SHADER_TIME_ADD
:
1884 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
1887 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1888 generate_untyped_atomic(inst
, dst
, src
[0], src
[1]);
1891 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1892 generate_untyped_surface_read(inst
, dst
, src
[0]);
1895 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
1896 generate_set_simd4x2_offset(inst
, dst
, src
[0]);
1899 case FS_OPCODE_SET_OMASK
:
1900 generate_set_omask(inst
, dst
, src
[0]);
1903 case FS_OPCODE_SET_SAMPLE_ID
:
1904 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
1907 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
1908 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
1911 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
1912 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
1913 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
1916 case FS_OPCODE_PLACEHOLDER_HALT
:
1917 /* This is the place where the final HALT needs to be inserted if
1918 * we've emitted any discards. If not, this will emit no code.
1920 if (!patch_discard_jumps_to_fb_writes()) {
1921 if (unlikely(debug_flag
)) {
1922 annotation
.ann_count
--;
1927 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
1928 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
1929 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID
);
1932 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
1933 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
1934 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
1937 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
1938 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
1939 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
1942 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
1943 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
1944 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
1948 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1949 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
1950 opcode_descs
[inst
->opcode
].name
);
1952 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
1956 case SHADER_OPCODE_LOAD_PAYLOAD
:
1957 unreachable("Should be lowered by lower_load_payload()");
1960 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
1961 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
1962 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1963 "emitting more than 1 instruction");
1965 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
1967 brw_inst_set_cond_modifier(brw
, last
, inst
->conditional_mod
);
1968 brw_inst_set_no_dd_clear(brw
, last
, inst
->no_dd_clear
);
1969 brw_inst_set_no_dd_check(brw
, last
, inst
->no_dd_check
);
1974 annotation_finalize(&annotation
, p
->next_insn_offset
);
1976 int before_size
= p
->next_insn_offset
- start_offset
;
1977 brw_compact_instructions(p
, start_offset
, annotation
.ann_count
,
1979 int after_size
= p
->next_insn_offset
- start_offset
;
1981 if (unlikely(debug_flag
)) {
1984 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
1985 shader_prog
->Label
? shader_prog
->Label
: "unnamed",
1986 shader_prog
->Name
, dispatch_width
);
1989 "Native code for fragment program %d (SIMD%d dispatch):\n",
1990 prog
->Id
, dispatch_width
);
1992 fprintf(stderr
, "Native code for blorp program (SIMD%d dispatch):\n",
1995 fprintf(stderr
, "SIMD%d shader: %d instructions. %d loops. Compacted %d to %d"
1996 " bytes (%.0f%%)\n",
1997 dispatch_width
, before_size
/ 16, loop_count
, before_size
, after_size
,
1998 100.0f
* (before_size
- after_size
) / before_size
);
2000 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
, brw
, prog
);
2001 ralloc_free(annotation
.ann
);
2006 fs_generator::generate_assembly(const cfg_t
*simd8_cfg
,
2007 const cfg_t
*simd16_cfg
,
2008 unsigned *assembly_size
)
2010 assert(simd8_cfg
|| simd16_cfg
);
2014 generate_code(simd8_cfg
);
2018 /* align to 64 byte boundary. */
2019 while (p
->next_insn_offset
% 64) {
2023 assert(stage
== MESA_SHADER_FRAGMENT
);
2024 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
2026 /* Save off the start of this SIMD16 program */
2027 prog_data
->prog_offset_16
= p
->next_insn_offset
;
2029 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
2031 dispatch_width
= 16;
2032 generate_code(simd16_cfg
);
2035 return brw_get_program(p
, assembly_size
);