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i965/fs: Emit ADDs for gl_FragCoord, not virtual opcodes.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "main/macros.h"
31 #include "brw_context.h"
32 #include "brw_eu.h"
33 #include "brw_fs.h"
34 #include "brw_cfg.h"
35
36 static uint32_t brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case GRF:
40 return BRW_GENERAL_REGISTER_FILE;
41 case MRF:
42 return BRW_MESSAGE_REGISTER_FILE;
43 case IMM:
44 return BRW_IMMEDIATE_VALUE;
45 default:
46 unreachable("not reached");
47 }
48 }
49
50 static struct brw_reg
51 brw_reg_from_fs_reg(fs_reg *reg)
52 {
53 struct brw_reg brw_reg;
54
55 switch (reg->file) {
56 case GRF:
57 case MRF:
58 if (reg->stride == 0) {
59 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
60 } else if (reg->width < 8) {
61 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
62 brw_reg = stride(brw_reg, reg->width * reg->stride,
63 reg->width, reg->stride);
64 } else {
65 /* From the Haswell PRM:
66 *
67 * VertStride must be used to cross GRF register boundaries. This
68 * rule implies that elements within a 'Width' cannot cross GRF
69 * boundaries.
70 *
71 * So, for registers with width > 8, we have to use a width of 8
72 * and trust the compression state to sort out the exec size.
73 */
74 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
75 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
76 }
77
78 brw_reg = retype(brw_reg, reg->type);
79 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
80 break;
81 case IMM:
82 switch (reg->type) {
83 case BRW_REGISTER_TYPE_F:
84 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
85 break;
86 case BRW_REGISTER_TYPE_D:
87 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
88 break;
89 case BRW_REGISTER_TYPE_UD:
90 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
91 break;
92 case BRW_REGISTER_TYPE_W:
93 brw_reg = brw_imm_w(reg->fixed_hw_reg.dw1.d);
94 break;
95 case BRW_REGISTER_TYPE_UW:
96 brw_reg = brw_imm_uw(reg->fixed_hw_reg.dw1.ud);
97 break;
98 case BRW_REGISTER_TYPE_VF:
99 brw_reg = brw_imm_vf(reg->fixed_hw_reg.dw1.ud);
100 break;
101 default:
102 unreachable("not reached");
103 }
104 break;
105 case HW_REG:
106 assert(reg->type == reg->fixed_hw_reg.type);
107 brw_reg = reg->fixed_hw_reg;
108 break;
109 case BAD_FILE:
110 /* Probably unused. */
111 brw_reg = brw_null_reg();
112 break;
113 default:
114 unreachable("not reached");
115 }
116 if (reg->abs)
117 brw_reg = brw_abs(brw_reg);
118 if (reg->negate)
119 brw_reg = negate(brw_reg);
120
121 return brw_reg;
122 }
123
124 fs_generator::fs_generator(struct brw_context *brw,
125 void *mem_ctx,
126 const void *key,
127 struct brw_stage_prog_data *prog_data,
128 struct gl_program *prog,
129 unsigned promoted_constants,
130 bool runtime_check_aads_emit,
131 const char *stage_abbrev)
132
133 : brw(brw), key(key),
134 prog_data(prog_data),
135 prog(prog), promoted_constants(promoted_constants),
136 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
137 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
138 {
139 ctx = &brw->ctx;
140
141 p = rzalloc(mem_ctx, struct brw_compile);
142 brw_init_compile(brw, p, mem_ctx);
143 }
144
145 fs_generator::~fs_generator()
146 {
147 }
148
149 class ip_record : public exec_node {
150 public:
151 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
152
153 ip_record(int ip)
154 {
155 this->ip = ip;
156 }
157
158 int ip;
159 };
160
161 bool
162 fs_generator::patch_discard_jumps_to_fb_writes()
163 {
164 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
165 return false;
166
167 int scale = brw_jump_scale(brw);
168
169 /* There is a somewhat strange undocumented requirement of using
170 * HALT, according to the simulator. If some channel has HALTed to
171 * a particular UIP, then by the end of the program, every channel
172 * must have HALTed to that UIP. Furthermore, the tracking is a
173 * stack, so you can't do the final halt of a UIP after starting
174 * halting to a new UIP.
175 *
176 * Symptoms of not emitting this instruction on actual hardware
177 * included GPU hangs and sparkly rendering on the piglit discard
178 * tests.
179 */
180 brw_inst *last_halt = gen6_HALT(p);
181 brw_inst_set_uip(brw, last_halt, 1 * scale);
182 brw_inst_set_jip(brw, last_halt, 1 * scale);
183
184 int ip = p->nr_insn;
185
186 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
187 brw_inst *patch = &p->store[patch_ip->ip];
188
189 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
190 /* HALT takes a half-instruction distance from the pre-incremented IP. */
191 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
192 }
193
194 this->discard_halt_patches.make_empty();
195 return true;
196 }
197
198 void
199 fs_generator::fire_fb_write(fs_inst *inst,
200 struct brw_reg payload,
201 struct brw_reg implied_header,
202 GLuint nr)
203 {
204 uint32_t msg_control;
205
206 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
207
208 if (brw->gen < 6) {
209 brw_push_insn_state(p);
210 brw_set_default_exec_size(p, BRW_EXECUTE_8);
211 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
212 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
213 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
214 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
215 brw_pop_insn_state(p);
216 }
217
218 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
219 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
220 else if (prog_data->dual_src_blend) {
221 if (dispatch_width == 8 || !inst->eot)
222 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
223 else
224 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
225 } else if (dispatch_width == 16)
226 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
227 else
228 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
229
230 uint32_t surf_index =
231 prog_data->binding_table.render_target_start + inst->target;
232
233 bool last_render_target = inst->eot ||
234 (prog_data->dual_src_blend && dispatch_width == 16);
235
236
237 brw_fb_WRITE(p,
238 dispatch_width,
239 payload,
240 implied_header,
241 msg_control,
242 surf_index,
243 nr,
244 0,
245 inst->eot,
246 last_render_target,
247 inst->header_present);
248
249 brw_mark_surface_used(&prog_data->base, surf_index);
250 }
251
252 void
253 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
254 {
255 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
256 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
257 struct brw_reg implied_header;
258
259 if (brw->gen < 8 && !brw->is_haswell) {
260 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
261 }
262
263 if (inst->base_mrf >= 0)
264 payload = brw_message_reg(inst->base_mrf);
265
266 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
267 * move, here's g1.
268 */
269 if (inst->header_present) {
270 brw_push_insn_state(p);
271 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
272 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
273 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
274 brw_set_default_flag_reg(p, 0, 0);
275
276 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
277 * present.
278 */
279 if (prog_data->uses_kill) {
280 struct brw_reg pixel_mask;
281
282 if (brw->gen >= 6)
283 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
284 else
285 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
286
287 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
288 }
289
290 if (brw->gen >= 6) {
291 brw_push_insn_state(p);
292 brw_set_default_exec_size(p, BRW_EXECUTE_16);
293 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
294 brw_MOV(p,
295 retype(payload, BRW_REGISTER_TYPE_UD),
296 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
297 brw_pop_insn_state(p);
298
299 if (inst->target > 0 && key->replicate_alpha) {
300 /* Set "Source0 Alpha Present to RenderTarget" bit in message
301 * header.
302 */
303 brw_OR(p,
304 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
305 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
306 brw_imm_ud(0x1 << 11));
307 }
308
309 if (inst->target > 0) {
310 /* Set the render target index for choosing BLEND_STATE. */
311 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
312 BRW_REGISTER_TYPE_UD),
313 brw_imm_ud(inst->target));
314 }
315
316 implied_header = brw_null_reg();
317 } else {
318 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
319 }
320
321 brw_pop_insn_state(p);
322 } else {
323 implied_header = brw_null_reg();
324 }
325
326 if (!runtime_check_aads_emit) {
327 fire_fb_write(inst, payload, implied_header, inst->mlen);
328 } else {
329 /* This can only happen in gen < 6 */
330 assert(brw->gen < 6);
331
332 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
333
334 /* Check runtime bit to detect if we have to send AA data or not */
335 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
336 brw_AND(p,
337 v1_null_ud,
338 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
339 brw_imm_ud(1<<26));
340 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
341
342 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
343 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
344 {
345 /* Don't send AA data */
346 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
347 }
348 brw_land_fwd_jump(p, jmp);
349 fire_fb_write(inst, payload, implied_header, inst->mlen);
350 }
351 }
352
353 void
354 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
355 {
356 brw_inst *insn;
357
358 insn = brw_next_insn(p, BRW_OPCODE_SEND);
359
360 brw_set_dest(p, insn, brw_null_reg());
361 brw_set_src0(p, insn, payload);
362 brw_set_src1(p, insn, brw_imm_d(0));
363
364 brw_inst_set_sfid(brw, insn, BRW_SFID_URB);
365 brw_inst_set_urb_opcode(brw, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
366
367 brw_inst_set_mlen(brw, insn, inst->mlen);
368 brw_inst_set_rlen(brw, insn, 0);
369 brw_inst_set_eot(brw, insn, inst->eot);
370 brw_inst_set_header_present(brw, insn, true);
371 brw_inst_set_urb_global_offset(brw, insn, inst->offset);
372 }
373
374 void
375 fs_generator::generate_blorp_fb_write(fs_inst *inst)
376 {
377 brw_fb_WRITE(p,
378 16 /* dispatch_width */,
379 brw_message_reg(inst->base_mrf),
380 brw_reg_from_fs_reg(&inst->src[0]),
381 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
382 inst->target,
383 inst->mlen,
384 0,
385 true,
386 true,
387 inst->header_present);
388 }
389
390 void
391 fs_generator::generate_linterp(fs_inst *inst,
392 struct brw_reg dst, struct brw_reg *src)
393 {
394 struct brw_reg delta_x = src[0];
395 struct brw_reg delta_y = src[1];
396 struct brw_reg interp = src[2];
397
398 if (brw->has_pln &&
399 delta_y.nr == delta_x.nr + 1 &&
400 (brw->gen >= 7 || (delta_x.nr & 1) == 0)) {
401 brw_PLN(p, dst, interp, delta_x);
402 } else {
403 brw_LINE(p, brw_null_reg(), interp, delta_x);
404 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
405 }
406 }
407
408 void
409 fs_generator::generate_math_gen6(fs_inst *inst,
410 struct brw_reg dst,
411 struct brw_reg src0,
412 struct brw_reg src1)
413 {
414 int op = brw_math_function(inst->opcode);
415 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
416
417 if (dispatch_width == 8) {
418 gen6_math(p, dst, op, src0, src1);
419 } else if (dispatch_width == 16) {
420 brw_push_insn_state(p);
421 brw_set_default_exec_size(p, BRW_EXECUTE_8);
422 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
423 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
424 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
425 gen6_math(p, sechalf(dst), op, sechalf(src0),
426 binop ? sechalf(src1) : brw_null_reg());
427 brw_pop_insn_state(p);
428 }
429 }
430
431 void
432 fs_generator::generate_math_gen4(fs_inst *inst,
433 struct brw_reg dst,
434 struct brw_reg src)
435 {
436 int op = brw_math_function(inst->opcode);
437
438 assert(inst->mlen >= 1);
439
440 if (dispatch_width == 8) {
441 gen4_math(p, dst,
442 op,
443 inst->base_mrf, src,
444 BRW_MATH_PRECISION_FULL);
445 } else if (dispatch_width == 16) {
446 brw_set_default_exec_size(p, BRW_EXECUTE_8);
447 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
448 gen4_math(p, firsthalf(dst),
449 op,
450 inst->base_mrf, firsthalf(src),
451 BRW_MATH_PRECISION_FULL);
452 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
453 gen4_math(p, sechalf(dst),
454 op,
455 inst->base_mrf + 1, sechalf(src),
456 BRW_MATH_PRECISION_FULL);
457
458 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
459 }
460 }
461
462 void
463 fs_generator::generate_math_g45(fs_inst *inst,
464 struct brw_reg dst,
465 struct brw_reg src)
466 {
467 if (inst->opcode == SHADER_OPCODE_POW ||
468 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
469 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
470 generate_math_gen4(inst, dst, src);
471 return;
472 }
473
474 int op = brw_math_function(inst->opcode);
475
476 assert(inst->mlen >= 1);
477
478 gen4_math(p, dst,
479 op,
480 inst->base_mrf, src,
481 BRW_MATH_PRECISION_FULL);
482 }
483
484 void
485 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
486 struct brw_reg sampler_index)
487 {
488 int msg_type = -1;
489 int rlen = 4;
490 uint32_t simd_mode;
491 uint32_t return_format;
492 bool is_combined_send = inst->eot;
493
494 switch (dst.type) {
495 case BRW_REGISTER_TYPE_D:
496 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
497 break;
498 case BRW_REGISTER_TYPE_UD:
499 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
500 break;
501 default:
502 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
503 break;
504 }
505
506 switch (inst->exec_size) {
507 case 8:
508 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
509 break;
510 case 16:
511 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
512 break;
513 default:
514 unreachable("Invalid width for texture instruction");
515 }
516
517 if (brw->gen >= 5) {
518 switch (inst->opcode) {
519 case SHADER_OPCODE_TEX:
520 if (inst->shadow_compare) {
521 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
522 } else {
523 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
524 }
525 break;
526 case FS_OPCODE_TXB:
527 if (inst->shadow_compare) {
528 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
529 } else {
530 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
531 }
532 break;
533 case SHADER_OPCODE_TXL:
534 if (inst->shadow_compare) {
535 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
536 } else {
537 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
538 }
539 break;
540 case SHADER_OPCODE_TXS:
541 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
542 break;
543 case SHADER_OPCODE_TXD:
544 if (inst->shadow_compare) {
545 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
546 assert(brw->gen >= 8 || brw->is_haswell);
547 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
548 } else {
549 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
550 }
551 break;
552 case SHADER_OPCODE_TXF:
553 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
554 break;
555 case SHADER_OPCODE_TXF_CMS:
556 if (brw->gen >= 7)
557 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
558 else
559 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
560 break;
561 case SHADER_OPCODE_TXF_UMS:
562 assert(brw->gen >= 7);
563 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
564 break;
565 case SHADER_OPCODE_TXF_MCS:
566 assert(brw->gen >= 7);
567 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
568 break;
569 case SHADER_OPCODE_LOD:
570 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
571 break;
572 case SHADER_OPCODE_TG4:
573 if (inst->shadow_compare) {
574 assert(brw->gen >= 7);
575 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
576 } else {
577 assert(brw->gen >= 6);
578 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
579 }
580 break;
581 case SHADER_OPCODE_TG4_OFFSET:
582 assert(brw->gen >= 7);
583 if (inst->shadow_compare) {
584 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
585 } else {
586 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
587 }
588 break;
589 default:
590 unreachable("not reached");
591 }
592 } else {
593 switch (inst->opcode) {
594 case SHADER_OPCODE_TEX:
595 /* Note that G45 and older determines shadow compare and dispatch width
596 * from message length for most messages.
597 */
598 if (dispatch_width == 8) {
599 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
600 if (inst->shadow_compare) {
601 assert(inst->mlen == 6);
602 } else {
603 assert(inst->mlen <= 4);
604 }
605 } else {
606 if (inst->shadow_compare) {
607 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
608 assert(inst->mlen == 9);
609 } else {
610 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
611 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
612 }
613 }
614 break;
615 case FS_OPCODE_TXB:
616 if (inst->shadow_compare) {
617 assert(dispatch_width == 8);
618 assert(inst->mlen == 6);
619 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
620 } else {
621 assert(inst->mlen == 9);
622 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
623 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
624 }
625 break;
626 case SHADER_OPCODE_TXL:
627 if (inst->shadow_compare) {
628 assert(dispatch_width == 8);
629 assert(inst->mlen == 6);
630 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
631 } else {
632 assert(inst->mlen == 9);
633 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
634 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
635 }
636 break;
637 case SHADER_OPCODE_TXD:
638 /* There is no sample_d_c message; comparisons are done manually */
639 assert(dispatch_width == 8);
640 assert(inst->mlen == 7 || inst->mlen == 10);
641 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
642 break;
643 case SHADER_OPCODE_TXF:
644 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
645 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
646 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
647 break;
648 case SHADER_OPCODE_TXS:
649 assert(inst->mlen == 3);
650 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
651 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
652 break;
653 default:
654 unreachable("not reached");
655 }
656 }
657 assert(msg_type != -1);
658
659 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
660 rlen = 8;
661 dst = vec16(dst);
662 }
663
664 if (is_combined_send) {
665 assert(brw->gen >= 9 || brw->is_cherryview);
666 rlen = 0;
667 }
668
669 assert(brw->gen < 7 || !inst->header_present ||
670 src.file == BRW_GENERAL_REGISTER_FILE);
671
672 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
673
674 /* Load the message header if present. If there's a texture offset,
675 * we need to set it up explicitly and load the offset bitfield.
676 * Otherwise, we can use an implied move from g0 to the first message reg.
677 */
678 if (inst->header_present) {
679 if (brw->gen < 6 && !inst->offset) {
680 /* Set up an implied move from g0 to the MRF. */
681 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
682 } else {
683 struct brw_reg header_reg;
684
685 if (brw->gen >= 7) {
686 header_reg = src;
687 } else {
688 assert(inst->base_mrf != -1);
689 header_reg = brw_message_reg(inst->base_mrf);
690 }
691
692 brw_push_insn_state(p);
693 brw_set_default_exec_size(p, BRW_EXECUTE_8);
694 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
695 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
696 /* Explicitly set up the message header by copying g0 to the MRF. */
697 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
698
699 if (inst->offset) {
700 /* Set the offset bits in DWord 2. */
701 brw_MOV(p, get_element_ud(header_reg, 2),
702 brw_imm_ud(inst->offset));
703 }
704
705 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
706 brw_pop_insn_state(p);
707 }
708 }
709
710 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
711 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
712 ? prog_data->binding_table.gather_texture_start
713 : prog_data->binding_table.texture_start;
714
715 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
716 uint32_t sampler = sampler_index.dw1.ud;
717
718 brw_SAMPLE(p,
719 retype(dst, BRW_REGISTER_TYPE_UW),
720 inst->base_mrf,
721 src,
722 sampler + base_binding_table_index,
723 sampler % 16,
724 msg_type,
725 rlen,
726 inst->mlen,
727 inst->header_present,
728 simd_mode,
729 return_format);
730
731 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
732 } else {
733 /* Non-const sampler index */
734 /* Note: this clobbers `dst` as a temporary before emitting the send */
735
736 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
737 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
738
739 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
740
741 brw_push_insn_state(p);
742 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
743 brw_set_default_access_mode(p, BRW_ALIGN_1);
744
745 /* Some care required: `sampler` and `temp` may alias:
746 * addr = sampler & 0xff
747 * temp = (sampler << 8) & 0xf00
748 * addr = addr | temp
749 */
750 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
751 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
752 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
753 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
754 brw_OR(p, addr, addr, temp);
755
756 brw_pop_insn_state(p);
757
758 /* dst = send(offset, a0.0 | <descriptor>) */
759 brw_inst *insn = brw_send_indirect_message(
760 p, BRW_SFID_SAMPLER, dst, src, addr);
761 brw_set_sampler_message(p, insn,
762 0 /* surface */,
763 0 /* sampler */,
764 msg_type,
765 rlen,
766 inst->mlen /* mlen */,
767 inst->header_present /* header */,
768 simd_mode,
769 return_format);
770
771 /* visitor knows more than we do about the surface limit required,
772 * so has already done marking.
773 */
774 }
775
776 if (is_combined_send) {
777 brw_inst_set_eot(brw, brw_last_inst, true);
778 brw_inst_set_opcode(brw, brw_last_inst, BRW_OPCODE_SENDC);
779 }
780 }
781
782
783 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
784 * looking like:
785 *
786 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
787 *
788 * Ideally, we want to produce:
789 *
790 * DDX DDY
791 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
792 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
793 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
794 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
795 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
796 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
797 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
798 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
799 *
800 * and add another set of two more subspans if in 16-pixel dispatch mode.
801 *
802 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
803 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
804 * pair. But the ideal approximation may impose a huge performance cost on
805 * sample_d. On at least Haswell, sample_d instruction does some
806 * optimizations if the same LOD is used for all pixels in the subspan.
807 *
808 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
809 * appropriate swizzling.
810 */
811 void
812 fs_generator::generate_ddx(enum opcode opcode,
813 struct brw_reg dst, struct brw_reg src)
814 {
815 unsigned vstride, width;
816
817 if (opcode == FS_OPCODE_DDX_FINE) {
818 /* produce accurate derivatives */
819 vstride = BRW_VERTICAL_STRIDE_2;
820 width = BRW_WIDTH_2;
821 } else {
822 /* replicate the derivative at the top-left pixel to other pixels */
823 vstride = BRW_VERTICAL_STRIDE_4;
824 width = BRW_WIDTH_4;
825 }
826
827 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
828 src.negate, src.abs,
829 BRW_REGISTER_TYPE_F,
830 vstride,
831 width,
832 BRW_HORIZONTAL_STRIDE_0,
833 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
834 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
835 src.negate, src.abs,
836 BRW_REGISTER_TYPE_F,
837 vstride,
838 width,
839 BRW_HORIZONTAL_STRIDE_0,
840 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
841 brw_ADD(p, dst, src0, negate(src1));
842 }
843
844 /* The negate_value boolean is used to negate the derivative computation for
845 * FBOs, since they place the origin at the upper left instead of the lower
846 * left.
847 */
848 void
849 fs_generator::generate_ddy(enum opcode opcode,
850 struct brw_reg dst, struct brw_reg src,
851 bool negate_value)
852 {
853 if (opcode == FS_OPCODE_DDY_FINE) {
854 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
855 * Region Restrictions):
856 *
857 * In Align16 access mode, SIMD16 is not allowed for DW operations
858 * and SIMD8 is not allowed for DF operations.
859 *
860 * In this context, "DW operations" means "operations acting on 32-bit
861 * values", so it includes operations on floats.
862 *
863 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
864 * (Instruction Compression -> Rules and Restrictions):
865 *
866 * A compressed instruction must be in Align1 access mode. Align16
867 * mode instructions cannot be compressed.
868 *
869 * Similar text exists in the g45 PRM.
870 *
871 * On these platforms, if we're building a SIMD16 shader, we need to
872 * manually unroll to a pair of SIMD8 instructions.
873 */
874 bool unroll_to_simd8 =
875 (dispatch_width == 16 &&
876 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
877
878 /* produce accurate derivatives */
879 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
880 src.negate, src.abs,
881 BRW_REGISTER_TYPE_F,
882 BRW_VERTICAL_STRIDE_4,
883 BRW_WIDTH_4,
884 BRW_HORIZONTAL_STRIDE_1,
885 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
886 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
887 src.negate, src.abs,
888 BRW_REGISTER_TYPE_F,
889 BRW_VERTICAL_STRIDE_4,
890 BRW_WIDTH_4,
891 BRW_HORIZONTAL_STRIDE_1,
892 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
893 brw_push_insn_state(p);
894 brw_set_default_access_mode(p, BRW_ALIGN_16);
895 if (unroll_to_simd8) {
896 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
897 if (negate_value) {
898 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
899 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
900 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
901 } else {
902 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
903 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
904 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
905 }
906 } else {
907 if (negate_value)
908 brw_ADD(p, dst, src1, negate(src0));
909 else
910 brw_ADD(p, dst, src0, negate(src1));
911 }
912 brw_pop_insn_state(p);
913 } else {
914 /* replicate the derivative at the top-left pixel to other pixels */
915 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
916 src.negate, src.abs,
917 BRW_REGISTER_TYPE_F,
918 BRW_VERTICAL_STRIDE_4,
919 BRW_WIDTH_4,
920 BRW_HORIZONTAL_STRIDE_0,
921 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
922 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
923 src.negate, src.abs,
924 BRW_REGISTER_TYPE_F,
925 BRW_VERTICAL_STRIDE_4,
926 BRW_WIDTH_4,
927 BRW_HORIZONTAL_STRIDE_0,
928 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
929 if (negate_value)
930 brw_ADD(p, dst, src1, negate(src0));
931 else
932 brw_ADD(p, dst, src0, negate(src1));
933 }
934 }
935
936 void
937 fs_generator::generate_discard_jump(fs_inst *inst)
938 {
939 assert(brw->gen >= 6);
940
941 /* This HALT will be patched up at FB write time to point UIP at the end of
942 * the program, and at brw_uip_jip() JIP will be set to the end of the
943 * current block (or the program).
944 */
945 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
946
947 brw_push_insn_state(p);
948 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
949 gen6_HALT(p);
950 brw_pop_insn_state(p);
951 }
952
953 void
954 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
955 {
956 assert(inst->mlen != 0);
957
958 brw_MOV(p,
959 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
960 retype(src, BRW_REGISTER_TYPE_UD));
961 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
962 inst->exec_size / 8, inst->offset);
963 }
964
965 void
966 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
967 {
968 assert(inst->mlen != 0);
969
970 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
971 inst->exec_size / 8, inst->offset);
972 }
973
974 void
975 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
976 {
977 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
978 }
979
980 void
981 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
982 struct brw_reg dst,
983 struct brw_reg index,
984 struct brw_reg offset)
985 {
986 assert(inst->mlen != 0);
987
988 assert(index.file == BRW_IMMEDIATE_VALUE &&
989 index.type == BRW_REGISTER_TYPE_UD);
990 uint32_t surf_index = index.dw1.ud;
991
992 assert(offset.file == BRW_IMMEDIATE_VALUE &&
993 offset.type == BRW_REGISTER_TYPE_UD);
994 uint32_t read_offset = offset.dw1.ud;
995
996 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
997 read_offset, surf_index);
998
999 brw_mark_surface_used(prog_data, surf_index);
1000 }
1001
1002 void
1003 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1004 struct brw_reg dst,
1005 struct brw_reg index,
1006 struct brw_reg offset)
1007 {
1008 assert(inst->mlen == 0);
1009 assert(index.type == BRW_REGISTER_TYPE_UD);
1010
1011 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1012 /* Reference just the dword we need, to avoid angering validate_reg(). */
1013 offset = brw_vec1_grf(offset.nr, 0);
1014
1015 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1016 * the destination loaded consecutively from the same offset (which appears
1017 * in the first component, and the rest are ignored).
1018 */
1019 dst.width = BRW_WIDTH_4;
1020
1021 struct brw_reg src = offset;
1022 bool header_present = false;
1023 int mlen = 1;
1024
1025 if (brw->gen >= 9) {
1026 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1027 src = retype(brw_vec4_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD);
1028 mlen = 2;
1029 header_present = true;
1030
1031 brw_push_insn_state(p);
1032 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1033 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1034 brw_set_default_access_mode(p, BRW_ALIGN_1);
1035
1036 brw_MOV(p, get_element_ud(src, 2),
1037 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1038 brw_pop_insn_state(p);
1039 }
1040
1041 if (index.file == BRW_IMMEDIATE_VALUE) {
1042
1043 uint32_t surf_index = index.dw1.ud;
1044
1045 brw_push_insn_state(p);
1046 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1047 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1048 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1049 brw_pop_insn_state(p);
1050
1051 brw_set_dest(p, send, dst);
1052 brw_set_src0(p, send, src);
1053 brw_set_sampler_message(p, send,
1054 surf_index,
1055 0, /* LD message ignores sampler unit */
1056 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1057 1, /* rlen */
1058 mlen,
1059 header_present,
1060 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1061 0);
1062
1063 brw_mark_surface_used(prog_data, surf_index);
1064
1065 } else {
1066
1067 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1068
1069 brw_push_insn_state(p);
1070 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1071 brw_set_default_access_mode(p, BRW_ALIGN_1);
1072
1073 /* a0.0 = surf_index & 0xff */
1074 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1075 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1076 brw_set_dest(p, insn_and, addr);
1077 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1078 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1079
1080 /* dst = send(payload, a0.0 | <descriptor>) */
1081 brw_inst *insn = brw_send_indirect_message(
1082 p, BRW_SFID_SAMPLER, dst, src, addr);
1083 brw_set_sampler_message(p, insn,
1084 0,
1085 0, /* LD message ignores sampler unit */
1086 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1087 1, /* rlen */
1088 mlen,
1089 header_present,
1090 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1091 0);
1092
1093 brw_pop_insn_state(p);
1094
1095 /* visitor knows more than we do about the surface limit required,
1096 * so has already done marking.
1097 */
1098
1099 }
1100 }
1101
1102 void
1103 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1104 struct brw_reg dst,
1105 struct brw_reg index,
1106 struct brw_reg offset)
1107 {
1108 assert(brw->gen < 7); /* Should use the gen7 variant. */
1109 assert(inst->header_present);
1110 assert(inst->mlen);
1111
1112 assert(index.file == BRW_IMMEDIATE_VALUE &&
1113 index.type == BRW_REGISTER_TYPE_UD);
1114 uint32_t surf_index = index.dw1.ud;
1115
1116 uint32_t simd_mode, rlen, msg_type;
1117 if (dispatch_width == 16) {
1118 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1119 rlen = 8;
1120 } else {
1121 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1122 rlen = 4;
1123 }
1124
1125 if (brw->gen >= 5)
1126 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1127 else {
1128 /* We always use the SIMD16 message so that we only have to load U, and
1129 * not V or R.
1130 */
1131 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1132 assert(inst->mlen == 3);
1133 assert(inst->regs_written == 8);
1134 rlen = 8;
1135 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1136 }
1137
1138 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1139 BRW_REGISTER_TYPE_D);
1140 brw_MOV(p, offset_mrf, offset);
1141
1142 struct brw_reg header = brw_vec8_grf(0, 0);
1143 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1144
1145 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1146 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
1147 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1148 brw_set_src0(p, send, header);
1149 if (brw->gen < 6)
1150 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
1151
1152 /* Our surface is set up as floats, regardless of what actual data is
1153 * stored in it.
1154 */
1155 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1156 brw_set_sampler_message(p, send,
1157 surf_index,
1158 0, /* sampler (unused) */
1159 msg_type,
1160 rlen,
1161 inst->mlen,
1162 inst->header_present,
1163 simd_mode,
1164 return_format);
1165
1166 brw_mark_surface_used(prog_data, surf_index);
1167 }
1168
1169 void
1170 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1171 struct brw_reg dst,
1172 struct brw_reg index,
1173 struct brw_reg offset)
1174 {
1175 assert(brw->gen >= 7);
1176 /* Varying-offset pull constant loads are treated as a normal expression on
1177 * gen7, so the fact that it's a send message is hidden at the IR level.
1178 */
1179 assert(!inst->header_present);
1180 assert(!inst->mlen);
1181 assert(index.type == BRW_REGISTER_TYPE_UD);
1182
1183 uint32_t simd_mode, rlen, mlen;
1184 if (dispatch_width == 16) {
1185 mlen = 2;
1186 rlen = 8;
1187 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1188 } else {
1189 mlen = 1;
1190 rlen = 4;
1191 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1192 }
1193
1194 if (index.file == BRW_IMMEDIATE_VALUE) {
1195
1196 uint32_t surf_index = index.dw1.ud;
1197
1198 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1199 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1200 brw_set_src0(p, send, offset);
1201 brw_set_sampler_message(p, send,
1202 surf_index,
1203 0, /* LD message ignores sampler unit */
1204 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1205 rlen,
1206 mlen,
1207 false, /* no header */
1208 simd_mode,
1209 0);
1210
1211 brw_mark_surface_used(prog_data, surf_index);
1212
1213 } else {
1214
1215 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1216
1217 brw_push_insn_state(p);
1218 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1219 brw_set_default_access_mode(p, BRW_ALIGN_1);
1220
1221 /* a0.0 = surf_index & 0xff */
1222 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1223 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1224 brw_set_dest(p, insn_and, addr);
1225 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1226 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1227
1228 brw_pop_insn_state(p);
1229
1230 /* dst = send(offset, a0.0 | <descriptor>) */
1231 brw_inst *insn = brw_send_indirect_message(
1232 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1233 offset, addr);
1234 brw_set_sampler_message(p, insn,
1235 0 /* surface */,
1236 0 /* sampler */,
1237 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1238 rlen /* rlen */,
1239 mlen /* mlen */,
1240 false /* header */,
1241 simd_mode,
1242 0);
1243
1244 /* visitor knows more than we do about the surface limit required,
1245 * so has already done marking.
1246 */
1247 }
1248 }
1249
1250 /**
1251 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1252 * into the flags register (f0.0).
1253 *
1254 * Used only on Gen6 and above.
1255 */
1256 void
1257 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1258 {
1259 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1260 struct brw_reg dispatch_mask;
1261
1262 if (brw->gen >= 6)
1263 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1264 else
1265 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1266
1267 brw_push_insn_state(p);
1268 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1269 brw_MOV(p, flags, dispatch_mask);
1270 brw_pop_insn_state(p);
1271 }
1272
1273 void
1274 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1275 struct brw_reg dst,
1276 struct brw_reg src,
1277 struct brw_reg msg_data,
1278 unsigned msg_type)
1279 {
1280 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1281 msg_data.type == BRW_REGISTER_TYPE_UD);
1282
1283 brw_pixel_interpolator_query(p,
1284 retype(dst, BRW_REGISTER_TYPE_UW),
1285 src,
1286 inst->pi_noperspective,
1287 msg_type,
1288 msg_data.dw1.ud,
1289 inst->mlen,
1290 inst->regs_written);
1291 }
1292
1293
1294 /**
1295 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1296 * sampler LD messages.
1297 *
1298 * We don't want to bake it into the send message's code generation because
1299 * that means we don't get a chance to schedule the instructions.
1300 */
1301 void
1302 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1303 struct brw_reg dst,
1304 struct brw_reg value)
1305 {
1306 assert(value.file == BRW_IMMEDIATE_VALUE);
1307
1308 brw_push_insn_state(p);
1309 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1310 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1311 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1312 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1313 brw_pop_insn_state(p);
1314 }
1315
1316 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1317 * (when mask is passed as a uniform) of register mask before moving it
1318 * to register dst.
1319 */
1320 void
1321 fs_generator::generate_set_omask(fs_inst *inst,
1322 struct brw_reg dst,
1323 struct brw_reg mask)
1324 {
1325 bool stride_8_8_1 =
1326 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1327 mask.width == BRW_WIDTH_8 &&
1328 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1329
1330 bool stride_0_1_0 = has_scalar_region(mask);
1331
1332 assert(stride_8_8_1 || stride_0_1_0);
1333 assert(dst.type == BRW_REGISTER_TYPE_UW);
1334
1335 brw_push_insn_state(p);
1336 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1337 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1338
1339 if (stride_8_8_1) {
1340 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1341 } else if (stride_0_1_0) {
1342 brw_MOV(p, dst, retype(mask, dst.type));
1343 }
1344 brw_pop_insn_state(p);
1345 }
1346
1347 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1348 * the ADD instruction.
1349 */
1350 void
1351 fs_generator::generate_set_sample_id(fs_inst *inst,
1352 struct brw_reg dst,
1353 struct brw_reg src0,
1354 struct brw_reg src1)
1355 {
1356 assert(dst.type == BRW_REGISTER_TYPE_D ||
1357 dst.type == BRW_REGISTER_TYPE_UD);
1358 assert(src0.type == BRW_REGISTER_TYPE_D ||
1359 src0.type == BRW_REGISTER_TYPE_UD);
1360
1361 brw_push_insn_state(p);
1362 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1363 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1364 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1365 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1366 if (dispatch_width == 8) {
1367 brw_ADD(p, dst, src0, reg);
1368 } else if (dispatch_width == 16) {
1369 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1370 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1371 }
1372 brw_pop_insn_state(p);
1373 }
1374
1375 void
1376 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1377 struct brw_reg dst,
1378 struct brw_reg x,
1379 struct brw_reg y)
1380 {
1381 assert(brw->gen >= 7);
1382 assert(dst.type == BRW_REGISTER_TYPE_UD);
1383 assert(x.type == BRW_REGISTER_TYPE_F);
1384 assert(y.type == BRW_REGISTER_TYPE_F);
1385
1386 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1387 *
1388 * Because this instruction does not have a 16-bit floating-point type,
1389 * the destination data type must be Word (W).
1390 *
1391 * The destination must be DWord-aligned and specify a horizontal stride
1392 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1393 * each destination channel and the upper word is not modified.
1394 */
1395 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1396
1397 /* Give each 32-bit channel of dst the form below, where "." means
1398 * unchanged.
1399 * 0x....hhhh
1400 */
1401 brw_F32TO16(p, dst_w, y);
1402
1403 /* Now the form:
1404 * 0xhhhh0000
1405 */
1406 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1407
1408 /* And, finally the form of packHalf2x16's output:
1409 * 0xhhhhllll
1410 */
1411 brw_F32TO16(p, dst_w, x);
1412 }
1413
1414 void
1415 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1416 struct brw_reg dst,
1417 struct brw_reg src)
1418 {
1419 assert(brw->gen >= 7);
1420 assert(dst.type == BRW_REGISTER_TYPE_F);
1421 assert(src.type == BRW_REGISTER_TYPE_UD);
1422
1423 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1424 *
1425 * Because this instruction does not have a 16-bit floating-point type,
1426 * the source data type must be Word (W). The destination type must be
1427 * F (Float).
1428 */
1429 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1430
1431 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1432 * For the Y case, we wish to access only the upper word; therefore
1433 * a 16-bit subregister offset is needed.
1434 */
1435 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1436 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1437 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1438 src_w.subnr += 2;
1439
1440 brw_F16TO32(p, dst, src_w);
1441 }
1442
1443 void
1444 fs_generator::generate_shader_time_add(fs_inst *inst,
1445 struct brw_reg payload,
1446 struct brw_reg offset,
1447 struct brw_reg value)
1448 {
1449 assert(brw->gen >= 7);
1450 brw_push_insn_state(p);
1451 brw_set_default_mask_control(p, true);
1452
1453 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1454 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1455 offset.type);
1456 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1457 value.type);
1458
1459 assert(offset.file == BRW_IMMEDIATE_VALUE);
1460 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1461 value.width = BRW_WIDTH_1;
1462 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1463 value.vstride = BRW_VERTICAL_STRIDE_0;
1464 } else {
1465 assert(value.file == BRW_IMMEDIATE_VALUE);
1466 }
1467
1468 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1469 * case, and we don't really care about squeezing every bit of performance
1470 * out of this path, so we just emit the MOVs from here.
1471 */
1472 brw_MOV(p, payload_offset, offset);
1473 brw_MOV(p, payload_value, value);
1474 brw_shader_time_add(p, payload,
1475 prog_data->binding_table.shader_time_start);
1476 brw_pop_insn_state(p);
1477
1478 brw_mark_surface_used(prog_data,
1479 prog_data->binding_table.shader_time_start);
1480 }
1481
1482 void
1483 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1484 struct brw_reg payload,
1485 struct brw_reg atomic_op,
1486 struct brw_reg surf_index)
1487 {
1488 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1489 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1490 surf_index.file == BRW_IMMEDIATE_VALUE &&
1491 surf_index.type == BRW_REGISTER_TYPE_UD);
1492
1493 brw_untyped_atomic(p, dst, payload,
1494 atomic_op.dw1.ud, surf_index.dw1.ud,
1495 inst->mlen, true);
1496
1497 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1498 }
1499
1500 void
1501 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1502 struct brw_reg payload,
1503 struct brw_reg surf_index)
1504 {
1505 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1506 surf_index.type == BRW_REGISTER_TYPE_UD);
1507
1508 brw_untyped_surface_read(p, dst, payload, surf_index.dw1.ud, inst->mlen, 1);
1509
1510 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1511 }
1512
1513 void
1514 fs_generator::enable_debug(const char *shader_name)
1515 {
1516 debug_flag = true;
1517 this->shader_name = shader_name;
1518 }
1519
1520 /**
1521 * Some hardware doesn't support SIMD16 instructions with 3 sources.
1522 */
1523 static bool
1524 brw_supports_simd16_3src(const struct brw_context *brw)
1525 {
1526 /* WaDisableSIMD16On3SrcInstr: 3-source instructions don't work in SIMD16
1527 * on a few steppings of Skylake.
1528 */
1529 if (brw->gen == 9)
1530 return brw->revision != 2 && brw->revision != 3 && brw->revision != -1;
1531
1532 return brw->is_haswell || brw->gen >= 8;
1533 }
1534
1535 int
1536 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1537 {
1538 /* align to 64 byte boundary. */
1539 while (p->next_insn_offset % 64)
1540 brw_NOP(p);
1541
1542 this->dispatch_width = dispatch_width;
1543 if (dispatch_width == 16)
1544 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1545
1546 int start_offset = p->next_insn_offset;
1547 int spill_count = 0, fill_count = 0;
1548 int loop_count = 0;
1549
1550 struct annotation_info annotation;
1551 memset(&annotation, 0, sizeof(annotation));
1552
1553 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1554 struct brw_reg src[3], dst;
1555 unsigned int last_insn_offset = p->next_insn_offset;
1556 bool multiple_instructions_emitted = false;
1557
1558 if (unlikely(debug_flag))
1559 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1560
1561 for (unsigned int i = 0; i < inst->sources; i++) {
1562 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1563
1564 /* The accumulator result appears to get used for the
1565 * conditional modifier generation. When negating a UD
1566 * value, there is a 33rd bit generated for the sign in the
1567 * accumulator value, so now you can't check, for example,
1568 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1569 */
1570 assert(!inst->conditional_mod ||
1571 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1572 !inst->src[i].negate);
1573 }
1574 dst = brw_reg_from_fs_reg(&inst->dst);
1575
1576 brw_set_default_predicate_control(p, inst->predicate);
1577 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1578 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1579 brw_set_default_saturate(p, inst->saturate);
1580 brw_set_default_mask_control(p, inst->force_writemask_all);
1581 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1582 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1583
1584 switch (inst->exec_size) {
1585 case 1:
1586 case 2:
1587 case 4:
1588 assert(inst->force_writemask_all);
1589 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1590 break;
1591 case 8:
1592 if (inst->force_sechalf) {
1593 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1594 } else {
1595 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1596 }
1597 break;
1598 case 16:
1599 case 32:
1600 if (type_sz(inst->dst.type) < sizeof(float))
1601 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1602 else
1603 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1604 break;
1605 default:
1606 unreachable("Invalid instruction width");
1607 }
1608
1609 switch (inst->opcode) {
1610 case BRW_OPCODE_MOV:
1611 brw_MOV(p, dst, src[0]);
1612 break;
1613 case BRW_OPCODE_ADD:
1614 brw_ADD(p, dst, src[0], src[1]);
1615 break;
1616 case BRW_OPCODE_MUL:
1617 brw_MUL(p, dst, src[0], src[1]);
1618 break;
1619 case BRW_OPCODE_AVG:
1620 brw_AVG(p, dst, src[0], src[1]);
1621 break;
1622 case BRW_OPCODE_MACH:
1623 brw_MACH(p, dst, src[0], src[1]);
1624 break;
1625
1626 case BRW_OPCODE_LINE:
1627 brw_LINE(p, dst, src[0], src[1]);
1628 break;
1629
1630 case BRW_OPCODE_MAD:
1631 assert(brw->gen >= 6);
1632 brw_set_default_access_mode(p, BRW_ALIGN_16);
1633 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1634 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1635 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1636 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1637 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1638 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1639 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1640
1641 if (inst->conditional_mod) {
1642 brw_inst_set_cond_modifier(brw, f, inst->conditional_mod);
1643 brw_inst_set_cond_modifier(brw, s, inst->conditional_mod);
1644 multiple_instructions_emitted = true;
1645 }
1646 } else {
1647 brw_MAD(p, dst, src[0], src[1], src[2]);
1648 }
1649 brw_set_default_access_mode(p, BRW_ALIGN_1);
1650 break;
1651
1652 case BRW_OPCODE_LRP:
1653 assert(brw->gen >= 6);
1654 brw_set_default_access_mode(p, BRW_ALIGN_16);
1655 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1656 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1657 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1658 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1659 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1660 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1661 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1662
1663 if (inst->conditional_mod) {
1664 brw_inst_set_cond_modifier(brw, f, inst->conditional_mod);
1665 brw_inst_set_cond_modifier(brw, s, inst->conditional_mod);
1666 multiple_instructions_emitted = true;
1667 }
1668 } else {
1669 brw_LRP(p, dst, src[0], src[1], src[2]);
1670 }
1671 brw_set_default_access_mode(p, BRW_ALIGN_1);
1672 break;
1673
1674 case BRW_OPCODE_FRC:
1675 brw_FRC(p, dst, src[0]);
1676 break;
1677 case BRW_OPCODE_RNDD:
1678 brw_RNDD(p, dst, src[0]);
1679 break;
1680 case BRW_OPCODE_RNDE:
1681 brw_RNDE(p, dst, src[0]);
1682 break;
1683 case BRW_OPCODE_RNDZ:
1684 brw_RNDZ(p, dst, src[0]);
1685 break;
1686
1687 case BRW_OPCODE_AND:
1688 brw_AND(p, dst, src[0], src[1]);
1689 break;
1690 case BRW_OPCODE_OR:
1691 brw_OR(p, dst, src[0], src[1]);
1692 break;
1693 case BRW_OPCODE_XOR:
1694 brw_XOR(p, dst, src[0], src[1]);
1695 break;
1696 case BRW_OPCODE_NOT:
1697 brw_NOT(p, dst, src[0]);
1698 break;
1699 case BRW_OPCODE_ASR:
1700 brw_ASR(p, dst, src[0], src[1]);
1701 break;
1702 case BRW_OPCODE_SHR:
1703 brw_SHR(p, dst, src[0], src[1]);
1704 break;
1705 case BRW_OPCODE_SHL:
1706 brw_SHL(p, dst, src[0], src[1]);
1707 break;
1708 case BRW_OPCODE_F32TO16:
1709 assert(brw->gen >= 7);
1710 brw_F32TO16(p, dst, src[0]);
1711 break;
1712 case BRW_OPCODE_F16TO32:
1713 assert(brw->gen >= 7);
1714 brw_F16TO32(p, dst, src[0]);
1715 break;
1716 case BRW_OPCODE_CMP:
1717 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1718 * that when the destination is a GRF that the dependency-clear bit on
1719 * the flag register is cleared early.
1720 *
1721 * Suggested workarounds are to disable coissuing CMP instructions
1722 * or to split CMP(16) instructions into two CMP(8) instructions.
1723 *
1724 * We choose to split into CMP(8) instructions since disabling
1725 * coissuing would affect CMP instructions not otherwise affected by
1726 * the errata.
1727 */
1728 if (dispatch_width == 16 && brw->gen == 7 && !brw->is_haswell) {
1729 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1730 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1731 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1732 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1733 firsthalf(src[0]), firsthalf(src[1]));
1734 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1735 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1736 sechalf(src[0]), sechalf(src[1]));
1737 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1738
1739 multiple_instructions_emitted = true;
1740 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1741 /* For unknown reasons, the aforementioned workaround is not
1742 * sufficient. Overriding the type when the destination is the
1743 * null register is necessary but not sufficient by itself.
1744 */
1745 assert(dst.nr == BRW_ARF_NULL);
1746 dst.type = BRW_REGISTER_TYPE_D;
1747 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1748 } else {
1749 unreachable("not reached");
1750 }
1751 } else {
1752 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1753 }
1754 break;
1755 case BRW_OPCODE_SEL:
1756 brw_SEL(p, dst, src[0], src[1]);
1757 break;
1758 case BRW_OPCODE_BFREV:
1759 assert(brw->gen >= 7);
1760 /* BFREV only supports UD type for src and dst. */
1761 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1762 retype(src[0], BRW_REGISTER_TYPE_UD));
1763 break;
1764 case BRW_OPCODE_FBH:
1765 assert(brw->gen >= 7);
1766 /* FBH only supports UD type for dst. */
1767 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1768 break;
1769 case BRW_OPCODE_FBL:
1770 assert(brw->gen >= 7);
1771 /* FBL only supports UD type for dst. */
1772 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1773 break;
1774 case BRW_OPCODE_CBIT:
1775 assert(brw->gen >= 7);
1776 /* CBIT only supports UD type for dst. */
1777 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1778 break;
1779 case BRW_OPCODE_ADDC:
1780 assert(brw->gen >= 7);
1781 brw_ADDC(p, dst, src[0], src[1]);
1782 break;
1783 case BRW_OPCODE_SUBB:
1784 assert(brw->gen >= 7);
1785 brw_SUBB(p, dst, src[0], src[1]);
1786 break;
1787 case BRW_OPCODE_MAC:
1788 brw_MAC(p, dst, src[0], src[1]);
1789 break;
1790
1791 case BRW_OPCODE_BFE:
1792 assert(brw->gen >= 7);
1793 brw_set_default_access_mode(p, BRW_ALIGN_16);
1794 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1795 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1796 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1797 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1798 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1799 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1800 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1801 } else {
1802 brw_BFE(p, dst, src[0], src[1], src[2]);
1803 }
1804 brw_set_default_access_mode(p, BRW_ALIGN_1);
1805 break;
1806
1807 case BRW_OPCODE_BFI1:
1808 assert(brw->gen >= 7);
1809 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1810 * should
1811 *
1812 * "Force BFI instructions to be executed always in SIMD8."
1813 */
1814 if (dispatch_width == 16 && brw->is_haswell) {
1815 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1816 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1817 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1818 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1819 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1820 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1821 } else {
1822 brw_BFI1(p, dst, src[0], src[1]);
1823 }
1824 break;
1825 case BRW_OPCODE_BFI2:
1826 assert(brw->gen >= 7);
1827 brw_set_default_access_mode(p, BRW_ALIGN_16);
1828 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1829 * should
1830 *
1831 * "Force BFI instructions to be executed always in SIMD8."
1832 *
1833 * Otherwise we would be able to emit compressed instructions like we
1834 * do for the other three-source instructions.
1835 */
1836 if (dispatch_width == 16 &&
1837 (brw->is_haswell || !brw_supports_simd16_3src(brw))) {
1838 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1839 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1840 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1841 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1842 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1843 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1844 } else {
1845 brw_BFI2(p, dst, src[0], src[1], src[2]);
1846 }
1847 brw_set_default_access_mode(p, BRW_ALIGN_1);
1848 break;
1849
1850 case BRW_OPCODE_IF:
1851 if (inst->src[0].file != BAD_FILE) {
1852 /* The instruction has an embedded compare (only allowed on gen6) */
1853 assert(brw->gen == 6);
1854 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1855 } else {
1856 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1857 }
1858 break;
1859
1860 case BRW_OPCODE_ELSE:
1861 brw_ELSE(p);
1862 break;
1863 case BRW_OPCODE_ENDIF:
1864 brw_ENDIF(p);
1865 break;
1866
1867 case BRW_OPCODE_DO:
1868 brw_DO(p, BRW_EXECUTE_8);
1869 break;
1870
1871 case BRW_OPCODE_BREAK:
1872 brw_BREAK(p);
1873 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1874 break;
1875 case BRW_OPCODE_CONTINUE:
1876 brw_CONT(p);
1877 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1878 break;
1879
1880 case BRW_OPCODE_WHILE:
1881 brw_WHILE(p);
1882 loop_count++;
1883 break;
1884
1885 case SHADER_OPCODE_RCP:
1886 case SHADER_OPCODE_RSQ:
1887 case SHADER_OPCODE_SQRT:
1888 case SHADER_OPCODE_EXP2:
1889 case SHADER_OPCODE_LOG2:
1890 case SHADER_OPCODE_SIN:
1891 case SHADER_OPCODE_COS:
1892 assert(brw->gen < 6 || inst->mlen == 0);
1893 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1894 if (brw->gen >= 7) {
1895 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1896 brw_null_reg());
1897 } else if (brw->gen == 6) {
1898 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1899 } else if (brw->gen == 5 || brw->is_g4x) {
1900 generate_math_g45(inst, dst, src[0]);
1901 } else {
1902 generate_math_gen4(inst, dst, src[0]);
1903 }
1904 break;
1905 case SHADER_OPCODE_INT_QUOTIENT:
1906 case SHADER_OPCODE_INT_REMAINDER:
1907 case SHADER_OPCODE_POW:
1908 assert(brw->gen < 6 || inst->mlen == 0);
1909 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1910 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1911 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1912 } else if (brw->gen >= 6) {
1913 generate_math_gen6(inst, dst, src[0], src[1]);
1914 } else {
1915 generate_math_gen4(inst, dst, src[0]);
1916 }
1917 break;
1918 case FS_OPCODE_CINTERP:
1919 brw_MOV(p, dst, src[0]);
1920 break;
1921 case FS_OPCODE_LINTERP:
1922 generate_linterp(inst, dst, src);
1923 break;
1924 case SHADER_OPCODE_TEX:
1925 case FS_OPCODE_TXB:
1926 case SHADER_OPCODE_TXD:
1927 case SHADER_OPCODE_TXF:
1928 case SHADER_OPCODE_TXF_CMS:
1929 case SHADER_OPCODE_TXF_UMS:
1930 case SHADER_OPCODE_TXF_MCS:
1931 case SHADER_OPCODE_TXL:
1932 case SHADER_OPCODE_TXS:
1933 case SHADER_OPCODE_LOD:
1934 case SHADER_OPCODE_TG4:
1935 case SHADER_OPCODE_TG4_OFFSET:
1936 generate_tex(inst, dst, src[0], src[1]);
1937 break;
1938 case FS_OPCODE_DDX_COARSE:
1939 case FS_OPCODE_DDX_FINE:
1940 generate_ddx(inst->opcode, dst, src[0]);
1941 break;
1942 case FS_OPCODE_DDY_COARSE:
1943 case FS_OPCODE_DDY_FINE:
1944 assert(src[1].file == BRW_IMMEDIATE_VALUE);
1945 generate_ddy(inst->opcode, dst, src[0], src[1].dw1.ud);
1946 break;
1947
1948 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1949 generate_scratch_write(inst, src[0]);
1950 spill_count++;
1951 break;
1952
1953 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1954 generate_scratch_read(inst, dst);
1955 fill_count++;
1956 break;
1957
1958 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1959 generate_scratch_read_gen7(inst, dst);
1960 fill_count++;
1961 break;
1962
1963 case SHADER_OPCODE_URB_WRITE_SIMD8:
1964 generate_urb_write(inst, src[0]);
1965 break;
1966
1967 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1968 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1969 break;
1970
1971 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1972 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1973 break;
1974
1975 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1976 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1977 break;
1978
1979 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1980 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1981 break;
1982
1983 case FS_OPCODE_REP_FB_WRITE:
1984 case FS_OPCODE_FB_WRITE:
1985 generate_fb_write(inst, src[0]);
1986 break;
1987
1988 case FS_OPCODE_BLORP_FB_WRITE:
1989 generate_blorp_fb_write(inst);
1990 break;
1991
1992 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1993 generate_mov_dispatch_to_flags(inst);
1994 break;
1995
1996 case FS_OPCODE_DISCARD_JUMP:
1997 generate_discard_jump(inst);
1998 break;
1999
2000 case SHADER_OPCODE_SHADER_TIME_ADD:
2001 generate_shader_time_add(inst, src[0], src[1], src[2]);
2002 break;
2003
2004 case SHADER_OPCODE_UNTYPED_ATOMIC:
2005 generate_untyped_atomic(inst, dst, src[0], src[1], src[2]);
2006 break;
2007
2008 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2009 generate_untyped_surface_read(inst, dst, src[0], src[1]);
2010 break;
2011
2012 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2013 generate_set_simd4x2_offset(inst, dst, src[0]);
2014 break;
2015
2016 case FS_OPCODE_SET_OMASK:
2017 generate_set_omask(inst, dst, src[0]);
2018 break;
2019
2020 case FS_OPCODE_SET_SAMPLE_ID:
2021 generate_set_sample_id(inst, dst, src[0], src[1]);
2022 break;
2023
2024 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2025 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2026 break;
2027
2028 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2029 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2030 generate_unpack_half_2x16_split(inst, dst, src[0]);
2031 break;
2032
2033 case FS_OPCODE_PLACEHOLDER_HALT:
2034 /* This is the place where the final HALT needs to be inserted if
2035 * we've emitted any discards. If not, this will emit no code.
2036 */
2037 if (!patch_discard_jumps_to_fb_writes()) {
2038 if (unlikely(debug_flag)) {
2039 annotation.ann_count--;
2040 }
2041 }
2042 break;
2043
2044 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2045 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2046 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2047 break;
2048
2049 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2050 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2051 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2052 break;
2053
2054 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2055 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2056 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2057 break;
2058
2059 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2060 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2061 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2062 break;
2063
2064 default:
2065 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
2066 _mesa_problem(ctx, "Unsupported opcode `%s' in %s",
2067 opcode_descs[inst->opcode].name, stage_abbrev);
2068 } else {
2069 _mesa_problem(ctx, "Unsupported opcode %d in %s", inst->opcode,
2070 stage_abbrev);
2071 }
2072 abort();
2073
2074 case SHADER_OPCODE_LOAD_PAYLOAD:
2075 unreachable("Should be lowered by lower_load_payload()");
2076 }
2077
2078 if (multiple_instructions_emitted)
2079 continue;
2080
2081 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2082 assert(p->next_insn_offset == last_insn_offset + 16 ||
2083 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2084 "emitting more than 1 instruction");
2085
2086 brw_inst *last = &p->store[last_insn_offset / 16];
2087
2088 if (inst->conditional_mod)
2089 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
2090 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
2091 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
2092 }
2093 }
2094
2095 brw_set_uip_jip(p);
2096 annotation_finalize(&annotation, p->next_insn_offset);
2097
2098 int before_size = p->next_insn_offset - start_offset;
2099 brw_compact_instructions(p, start_offset, annotation.ann_count,
2100 annotation.ann);
2101 int after_size = p->next_insn_offset - start_offset;
2102
2103 if (unlikely(debug_flag)) {
2104 fprintf(stderr, "Native code for %s\n"
2105 "SIMD%d shader: %d instructions. %d loops. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2106 " bytes (%.0f%%)\n",
2107 shader_name, dispatch_width, before_size / 16, loop_count,
2108 spill_count, fill_count, promoted_constants, before_size, after_size,
2109 100.0f * (before_size - after_size) / before_size);
2110
2111 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
2112 ralloc_free(annotation.ann);
2113 }
2114
2115 static GLuint msg_id = 0;
2116 _mesa_gl_debug(&brw->ctx, &msg_id,
2117 MESA_DEBUG_SOURCE_SHADER_COMPILER,
2118 MESA_DEBUG_TYPE_OTHER,
2119 MESA_DEBUG_SEVERITY_NOTIFICATION,
2120 "%s SIMD%d shader: %d inst, %d loops, %d:%d spills:fills, "
2121 "Promoted %u constants, compacted %d to %d bytes.\n",
2122 stage_abbrev, dispatch_width, before_size / 16, loop_count,
2123 spill_count, fill_count, promoted_constants, before_size, after_size);
2124
2125 return start_offset;
2126 }
2127
2128 const unsigned *
2129 fs_generator::get_assembly(unsigned int *assembly_size)
2130 {
2131 return brw_get_program(p, assembly_size);
2132 }