2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
30 #include "main/macros.h"
31 #include "brw_context.h"
36 static uint32_t brw_file_from_reg(fs_reg
*reg
)
40 return BRW_GENERAL_REGISTER_FILE
;
42 return BRW_MESSAGE_REGISTER_FILE
;
44 return BRW_IMMEDIATE_VALUE
;
46 unreachable("not reached");
51 brw_reg_from_fs_reg(fs_inst
*inst
, fs_reg
*reg
, unsigned gen
)
53 struct brw_reg brw_reg
;
57 assert((reg
->reg
& ~(1 << 7)) < BRW_MAX_MRF(gen
));
60 if (reg
->stride
== 0) {
61 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
62 } else if (inst
->exec_size
< 8) {
63 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
64 brw_reg
= stride(brw_reg
, inst
->exec_size
* reg
->stride
,
65 inst
->exec_size
, reg
->stride
);
67 /* From the Haswell PRM:
69 * VertStride must be used to cross GRF register boundaries. This
70 * rule implies that elements within a 'Width' cannot cross GRF
73 * So, for registers with width > 8, we have to use a width of 8
74 * and trust the compression state to sort out the exec size.
76 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
77 brw_reg
= stride(brw_reg
, 8 * reg
->stride
, 8, reg
->stride
);
80 brw_reg
= retype(brw_reg
, reg
->type
);
81 brw_reg
= byte_offset(brw_reg
, reg
->subreg_offset
);
84 assert(reg
->stride
== ((reg
->type
== BRW_REGISTER_TYPE_V
||
85 reg
->type
== BRW_REGISTER_TYPE_UV
||
86 reg
->type
== BRW_REGISTER_TYPE_VF
) ? 1 : 0));
89 case BRW_REGISTER_TYPE_F
:
90 brw_reg
= brw_imm_f(reg
->fixed_hw_reg
.dw1
.f
);
92 case BRW_REGISTER_TYPE_D
:
93 brw_reg
= brw_imm_d(reg
->fixed_hw_reg
.dw1
.d
);
95 case BRW_REGISTER_TYPE_UD
:
96 brw_reg
= brw_imm_ud(reg
->fixed_hw_reg
.dw1
.ud
);
98 case BRW_REGISTER_TYPE_W
:
99 brw_reg
= brw_imm_w(reg
->fixed_hw_reg
.dw1
.d
);
101 case BRW_REGISTER_TYPE_UW
:
102 brw_reg
= brw_imm_uw(reg
->fixed_hw_reg
.dw1
.ud
);
104 case BRW_REGISTER_TYPE_VF
:
105 brw_reg
= brw_imm_vf(reg
->fixed_hw_reg
.dw1
.ud
);
108 unreachable("not reached");
112 assert(reg
->type
== reg
->fixed_hw_reg
.type
);
113 brw_reg
= reg
->fixed_hw_reg
;
116 /* Probably unused. */
117 brw_reg
= brw_null_reg();
120 unreachable("not reached");
123 brw_reg
= brw_abs(brw_reg
);
125 brw_reg
= negate(brw_reg
);
130 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
133 struct brw_stage_prog_data
*prog_data
,
134 unsigned promoted_constants
,
135 bool runtime_check_aads_emit
,
136 const char *stage_abbrev
)
138 : compiler(compiler
), log_data(log_data
),
139 devinfo(compiler
->devinfo
), key(key
),
140 prog_data(prog_data
),
141 promoted_constants(promoted_constants
),
142 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
143 stage_abbrev(stage_abbrev
), mem_ctx(mem_ctx
)
145 p
= rzalloc(mem_ctx
, struct brw_codegen
);
146 brw_init_codegen(devinfo
, p
, mem_ctx
);
149 fs_generator::~fs_generator()
153 class ip_record
: public exec_node
{
155 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
166 fs_generator::patch_discard_jumps_to_fb_writes()
168 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
171 int scale
= brw_jump_scale(p
->devinfo
);
173 /* There is a somewhat strange undocumented requirement of using
174 * HALT, according to the simulator. If some channel has HALTed to
175 * a particular UIP, then by the end of the program, every channel
176 * must have HALTed to that UIP. Furthermore, the tracking is a
177 * stack, so you can't do the final halt of a UIP after starting
178 * halting to a new UIP.
180 * Symptoms of not emitting this instruction on actual hardware
181 * included GPU hangs and sparkly rendering on the piglit discard
184 brw_inst
*last_halt
= gen6_HALT(p
);
185 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
186 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
190 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
191 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
193 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
194 /* HALT takes a half-instruction distance from the pre-incremented IP. */
195 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
198 this->discard_halt_patches
.make_empty();
203 fs_generator::fire_fb_write(fs_inst
*inst
,
204 struct brw_reg payload
,
205 struct brw_reg implied_header
,
208 uint32_t msg_control
;
210 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
212 if (devinfo
->gen
< 6) {
213 brw_push_insn_state(p
);
214 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
215 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
216 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
217 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
218 brw_MOV(p
, offset(payload
, 1), brw_vec8_grf(1, 0));
219 brw_pop_insn_state(p
);
222 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
)
223 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
224 else if (prog_data
->dual_src_blend
) {
225 if (!inst
->force_sechalf
)
226 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
228 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
229 } else if (inst
->exec_size
== 16)
230 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
232 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
234 uint32_t surf_index
=
235 prog_data
->binding_table
.render_target_start
+ inst
->target
;
237 bool last_render_target
= inst
->eot
||
238 (prog_data
->dual_src_blend
&& dispatch_width
== 16);
251 inst
->header_size
!= 0);
253 brw_mark_surface_used(&prog_data
->base
, surf_index
);
257 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
259 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
260 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
261 struct brw_reg implied_header
;
263 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
264 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
267 if (inst
->base_mrf
>= 0)
268 payload
= brw_message_reg(inst
->base_mrf
);
270 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
273 if (inst
->header_size
!= 0) {
274 brw_push_insn_state(p
);
275 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
276 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
277 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
278 brw_set_default_flag_reg(p
, 0, 0);
280 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
283 if (prog_data
->uses_kill
) {
284 struct brw_reg pixel_mask
;
286 if (devinfo
->gen
>= 6)
287 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
289 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
291 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
294 if (devinfo
->gen
>= 6) {
295 brw_push_insn_state(p
);
296 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
297 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
299 retype(payload
, BRW_REGISTER_TYPE_UD
),
300 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
301 brw_pop_insn_state(p
);
303 if (inst
->target
> 0 && key
->replicate_alpha
) {
304 /* Set "Source0 Alpha Present to RenderTarget" bit in message
308 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
309 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
310 brw_imm_ud(0x1 << 11));
313 if (inst
->target
> 0) {
314 /* Set the render target index for choosing BLEND_STATE. */
315 brw_MOV(p
, retype(vec1(suboffset(payload
, 2)),
316 BRW_REGISTER_TYPE_UD
),
317 brw_imm_ud(inst
->target
));
320 implied_header
= brw_null_reg();
322 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
325 brw_pop_insn_state(p
);
327 implied_header
= brw_null_reg();
330 if (!runtime_check_aads_emit
) {
331 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
333 /* This can only happen in gen < 6 */
334 assert(devinfo
->gen
< 6);
336 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
338 /* Check runtime bit to detect if we have to send AA data or not */
339 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
342 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
344 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
346 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
347 brw_inst_set_exec_size(p
->devinfo
, brw_last_inst
, BRW_EXECUTE_1
);
349 /* Don't send AA data */
350 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
352 brw_land_fwd_jump(p
, jmp
);
353 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
358 fs_generator::generate_urb_read(fs_inst
*inst
,
360 struct brw_reg header
)
362 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
363 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
365 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
366 brw_set_dest(p
, send
, dst
);
367 brw_set_src0(p
, send
, header
);
368 brw_set_src1(p
, send
, brw_imm_ud(0u));
370 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
371 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
373 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
374 brw_inst_set_rlen(p
->devinfo
, send
, inst
->regs_written
);
375 brw_inst_set_header_present(p
->devinfo
, send
, true);
376 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
380 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
384 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
386 brw_set_dest(p
, insn
, brw_null_reg());
387 brw_set_src0(p
, insn
, payload
);
388 brw_set_src1(p
, insn
, brw_imm_d(0));
390 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
391 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
393 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
394 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
395 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
397 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
398 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
399 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
401 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
402 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
403 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
404 brw_inst_set_header_present(p
->devinfo
, insn
, true);
405 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
409 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
411 struct brw_inst
*insn
;
413 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
415 brw_set_dest(p
, insn
, brw_null_reg());
416 brw_set_src0(p
, insn
, payload
);
417 brw_set_src1(p
, insn
, brw_imm_d(0));
419 /* Terminate a compute shader by sending a message to the thread spawner.
421 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
422 brw_inst_set_mlen(devinfo
, insn
, 1);
423 brw_inst_set_rlen(devinfo
, insn
, 0);
424 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
425 brw_inst_set_header_present(devinfo
, insn
, false);
427 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
428 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
430 /* Note that even though the thread has a URB resource associated with it,
431 * we set the "do not dereference URB" bit, because the URB resource is
432 * managed by the fixed-function unit, so it will free it automatically.
434 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
436 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
440 fs_generator::generate_barrier(fs_inst
*inst
, struct brw_reg src
)
447 fs_generator::generate_blorp_fb_write(fs_inst
*inst
)
450 16 /* dispatch_width */,
451 brw_message_reg(inst
->base_mrf
),
452 brw_reg_from_fs_reg(inst
, &inst
->src
[0], devinfo
->gen
),
453 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
459 inst
->header_size
!= 0);
463 fs_generator::generate_linterp(fs_inst
*inst
,
464 struct brw_reg dst
, struct brw_reg
*src
)
468 * -----------------------------------
469 * | src1+0 | src1+1 | src1+2 | src1+3 |
470 * |-----------------------------------|
471 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
472 * -----------------------------------
474 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
476 * -----------------------------------
477 * | src1+0 | src1+1 | src1+2 | src1+3 |
478 * |-----------------------------------|
479 * |(x0, x1)|(y0, y1)| | | in SIMD8
480 * |-----------------------------------|
481 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
482 * -----------------------------------
484 * See also: emit_interpolation_setup_gen4().
486 struct brw_reg delta_x
= src
[0];
487 struct brw_reg delta_y
= offset(src
[0], dispatch_width
/ 8);
488 struct brw_reg interp
= src
[1];
490 if (devinfo
->has_pln
&&
491 (devinfo
->gen
>= 7 || (delta_x
.nr
& 1) == 0)) {
492 brw_PLN(p
, dst
, interp
, delta_x
);
494 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
495 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
500 fs_generator::generate_math_gen6(fs_inst
*inst
,
505 int op
= brw_math_function(inst
->opcode
);
506 bool binop
= src1
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
;
508 if (dispatch_width
== 8) {
509 gen6_math(p
, dst
, op
, src0
, src1
);
510 } else if (dispatch_width
== 16) {
511 brw_push_insn_state(p
);
512 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
513 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
514 gen6_math(p
, firsthalf(dst
), op
, firsthalf(src0
), firsthalf(src1
));
515 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
516 gen6_math(p
, sechalf(dst
), op
, sechalf(src0
),
517 binop
? sechalf(src1
) : brw_null_reg());
518 brw_pop_insn_state(p
);
523 fs_generator::generate_math_gen4(fs_inst
*inst
,
527 int op
= brw_math_function(inst
->opcode
);
529 assert(inst
->mlen
>= 1);
531 if (dispatch_width
== 8) {
535 BRW_MATH_PRECISION_FULL
);
536 } else if (dispatch_width
== 16) {
537 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
538 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
539 gen4_math(p
, firsthalf(dst
),
541 inst
->base_mrf
, firsthalf(src
),
542 BRW_MATH_PRECISION_FULL
);
543 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
544 gen4_math(p
, sechalf(dst
),
546 inst
->base_mrf
+ 1, sechalf(src
),
547 BRW_MATH_PRECISION_FULL
);
549 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
554 fs_generator::generate_math_g45(fs_inst
*inst
,
558 if (inst
->opcode
== SHADER_OPCODE_POW
||
559 inst
->opcode
== SHADER_OPCODE_INT_QUOTIENT
||
560 inst
->opcode
== SHADER_OPCODE_INT_REMAINDER
) {
561 generate_math_gen4(inst
, dst
, src
);
565 int op
= brw_math_function(inst
->opcode
);
567 assert(inst
->mlen
>= 1);
572 BRW_MATH_PRECISION_FULL
);
576 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
579 struct brw_reg surf_index
)
581 assert(devinfo
->gen
>= 7);
582 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
587 switch (inst
->exec_size
) {
589 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
592 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
595 unreachable("Invalid width for texture instruction");
598 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
604 retype(dst
, BRW_REGISTER_TYPE_UW
),
609 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
610 rlen
, /* response length */
612 inst
->header_size
> 0,
614 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
616 brw_mark_surface_used(prog_data
, surf_index
.dw1
.ud
);
620 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
621 struct brw_reg sampler_index
)
626 uint32_t return_format
;
627 bool is_combined_send
= inst
->eot
;
630 case BRW_REGISTER_TYPE_D
:
631 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
633 case BRW_REGISTER_TYPE_UD
:
634 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
637 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
641 switch (inst
->exec_size
) {
643 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
646 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
649 unreachable("Invalid width for texture instruction");
652 if (devinfo
->gen
>= 5) {
653 switch (inst
->opcode
) {
654 case SHADER_OPCODE_TEX
:
655 if (inst
->shadow_compare
) {
656 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
658 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
662 if (inst
->shadow_compare
) {
663 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
665 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
668 case SHADER_OPCODE_TXL
:
669 if (inst
->shadow_compare
) {
670 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
672 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
675 case SHADER_OPCODE_TXS
:
676 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
678 case SHADER_OPCODE_TXD
:
679 if (inst
->shadow_compare
) {
680 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
681 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
682 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
684 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
687 case SHADER_OPCODE_TXF
:
688 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
690 case SHADER_OPCODE_TXF_CMS
:
691 if (devinfo
->gen
>= 7)
692 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
694 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
696 case SHADER_OPCODE_TXF_UMS
:
697 assert(devinfo
->gen
>= 7);
698 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
700 case SHADER_OPCODE_TXF_MCS
:
701 assert(devinfo
->gen
>= 7);
702 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
704 case SHADER_OPCODE_LOD
:
705 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
707 case SHADER_OPCODE_TG4
:
708 if (inst
->shadow_compare
) {
709 assert(devinfo
->gen
>= 7);
710 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
712 assert(devinfo
->gen
>= 6);
713 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
716 case SHADER_OPCODE_TG4_OFFSET
:
717 assert(devinfo
->gen
>= 7);
718 if (inst
->shadow_compare
) {
719 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
721 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
724 case SHADER_OPCODE_SAMPLEINFO
:
725 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
728 unreachable("not reached");
731 switch (inst
->opcode
) {
732 case SHADER_OPCODE_TEX
:
733 /* Note that G45 and older determines shadow compare and dispatch width
734 * from message length for most messages.
736 if (inst
->exec_size
== 8) {
737 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
738 if (inst
->shadow_compare
) {
739 assert(inst
->mlen
== 6);
741 assert(inst
->mlen
<= 4);
744 if (inst
->shadow_compare
) {
745 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
746 assert(inst
->mlen
== 9);
748 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
749 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
754 if (inst
->shadow_compare
) {
755 assert(inst
->exec_size
== 8);
756 assert(inst
->mlen
== 6);
757 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
759 assert(inst
->mlen
== 9);
760 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
761 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
764 case SHADER_OPCODE_TXL
:
765 if (inst
->shadow_compare
) {
766 assert(inst
->exec_size
== 8);
767 assert(inst
->mlen
== 6);
768 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
770 assert(inst
->mlen
== 9);
771 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
772 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
775 case SHADER_OPCODE_TXD
:
776 /* There is no sample_d_c message; comparisons are done manually */
777 assert(inst
->exec_size
== 8);
778 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
779 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
781 case SHADER_OPCODE_TXF
:
782 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
783 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
784 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
786 case SHADER_OPCODE_TXS
:
787 assert(inst
->mlen
== 3);
788 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
789 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
792 unreachable("not reached");
795 assert(msg_type
!= -1);
797 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
802 if (is_combined_send
) {
803 assert(devinfo
->gen
>= 9 || devinfo
->is_cherryview
);
807 assert(devinfo
->gen
< 7 || inst
->header_size
== 0 ||
808 src
.file
== BRW_GENERAL_REGISTER_FILE
);
810 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
812 /* Load the message header if present. If there's a texture offset,
813 * we need to set it up explicitly and load the offset bitfield.
814 * Otherwise, we can use an implied move from g0 to the first message reg.
816 if (inst
->header_size
!= 0) {
817 if (devinfo
->gen
< 6 && !inst
->offset
) {
818 /* Set up an implied move from g0 to the MRF. */
819 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
821 struct brw_reg header_reg
;
823 if (devinfo
->gen
>= 7) {
826 assert(inst
->base_mrf
!= -1);
827 header_reg
= brw_message_reg(inst
->base_mrf
);
830 brw_push_insn_state(p
);
831 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
832 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
833 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
834 /* Explicitly set up the message header by copying g0 to the MRF. */
835 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
838 /* Set the offset bits in DWord 2. */
839 brw_MOV(p
, get_element_ud(header_reg
, 2),
840 brw_imm_ud(inst
->offset
));
843 brw_adjust_sampler_state_pointer(p
, header_reg
, sampler_index
);
844 brw_pop_insn_state(p
);
848 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
849 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
850 ? prog_data
->binding_table
.gather_texture_start
851 : prog_data
->binding_table
.texture_start
;
853 if (sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
854 uint32_t sampler
= sampler_index
.dw1
.ud
;
857 retype(dst
, BRW_REGISTER_TYPE_UW
),
860 sampler
+ base_binding_table_index
,
865 inst
->header_size
!= 0,
869 brw_mark_surface_used(prog_data
, sampler
+ base_binding_table_index
);
871 /* Non-const sampler index */
873 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
874 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
876 brw_push_insn_state(p
);
877 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
878 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
880 /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
881 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
882 if (base_binding_table_index
)
883 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
884 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
886 brw_pop_insn_state(p
);
888 /* dst = send(offset, a0.0 | <descriptor>) */
889 brw_inst
*insn
= brw_send_indirect_message(
890 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
891 brw_set_sampler_message(p
, insn
,
896 inst
->mlen
/* mlen */,
897 inst
->header_size
!= 0 /* header */,
901 /* visitor knows more than we do about the surface limit required,
902 * so has already done marking.
906 if (is_combined_send
) {
907 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, true);
908 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
913 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
916 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
918 * Ideally, we want to produce:
921 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
922 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
923 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
924 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
925 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
926 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
927 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
928 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
930 * and add another set of two more subspans if in 16-pixel dispatch mode.
932 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
933 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
934 * pair. But the ideal approximation may impose a huge performance cost on
935 * sample_d. On at least Haswell, sample_d instruction does some
936 * optimizations if the same LOD is used for all pixels in the subspan.
938 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
939 * appropriate swizzling.
942 fs_generator::generate_ddx(enum opcode opcode
,
943 struct brw_reg dst
, struct brw_reg src
)
945 unsigned vstride
, width
;
947 if (opcode
== FS_OPCODE_DDX_FINE
) {
948 /* produce accurate derivatives */
949 vstride
= BRW_VERTICAL_STRIDE_2
;
952 /* replicate the derivative at the top-left pixel to other pixels */
953 vstride
= BRW_VERTICAL_STRIDE_4
;
957 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
962 BRW_HORIZONTAL_STRIDE_0
,
963 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
964 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
969 BRW_HORIZONTAL_STRIDE_0
,
970 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
971 brw_ADD(p
, dst
, src0
, negate(src1
));
974 /* The negate_value boolean is used to negate the derivative computation for
975 * FBOs, since they place the origin at the upper left instead of the lower
979 fs_generator::generate_ddy(enum opcode opcode
,
980 struct brw_reg dst
, struct brw_reg src
,
983 if (opcode
== FS_OPCODE_DDY_FINE
) {
984 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
985 * Region Restrictions):
987 * In Align16 access mode, SIMD16 is not allowed for DW operations
988 * and SIMD8 is not allowed for DF operations.
990 * In this context, "DW operations" means "operations acting on 32-bit
991 * values", so it includes operations on floats.
993 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
994 * (Instruction Compression -> Rules and Restrictions):
996 * A compressed instruction must be in Align1 access mode. Align16
997 * mode instructions cannot be compressed.
999 * Similar text exists in the g45 PRM.
1001 * On these platforms, if we're building a SIMD16 shader, we need to
1002 * manually unroll to a pair of SIMD8 instructions.
1004 bool unroll_to_simd8
=
1005 (dispatch_width
== 16 &&
1006 (devinfo
->gen
== 4 || (devinfo
->gen
== 7 && !devinfo
->is_haswell
)));
1008 /* produce accurate derivatives */
1009 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1010 src
.negate
, src
.abs
,
1011 BRW_REGISTER_TYPE_F
,
1012 BRW_VERTICAL_STRIDE_4
,
1014 BRW_HORIZONTAL_STRIDE_1
,
1015 BRW_SWIZZLE_XYXY
, WRITEMASK_XYZW
);
1016 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1017 src
.negate
, src
.abs
,
1018 BRW_REGISTER_TYPE_F
,
1019 BRW_VERTICAL_STRIDE_4
,
1021 BRW_HORIZONTAL_STRIDE_1
,
1022 BRW_SWIZZLE_ZWZW
, WRITEMASK_XYZW
);
1023 brw_push_insn_state(p
);
1024 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1025 if (unroll_to_simd8
) {
1026 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1027 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1029 brw_ADD(p
, firsthalf(dst
), firsthalf(src1
), negate(firsthalf(src0
)));
1030 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1031 brw_ADD(p
, sechalf(dst
), sechalf(src1
), negate(sechalf(src0
)));
1033 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), negate(firsthalf(src1
)));
1034 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1035 brw_ADD(p
, sechalf(dst
), sechalf(src0
), negate(sechalf(src1
)));
1039 brw_ADD(p
, dst
, src1
, negate(src0
));
1041 brw_ADD(p
, dst
, src0
, negate(src1
));
1043 brw_pop_insn_state(p
);
1045 /* replicate the derivative at the top-left pixel to other pixels */
1046 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1047 src
.negate
, src
.abs
,
1048 BRW_REGISTER_TYPE_F
,
1049 BRW_VERTICAL_STRIDE_4
,
1051 BRW_HORIZONTAL_STRIDE_0
,
1052 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1053 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
1054 src
.negate
, src
.abs
,
1055 BRW_REGISTER_TYPE_F
,
1056 BRW_VERTICAL_STRIDE_4
,
1058 BRW_HORIZONTAL_STRIDE_0
,
1059 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1061 brw_ADD(p
, dst
, src1
, negate(src0
));
1063 brw_ADD(p
, dst
, src0
, negate(src1
));
1068 fs_generator::generate_discard_jump(fs_inst
*inst
)
1070 assert(devinfo
->gen
>= 6);
1072 /* This HALT will be patched up at FB write time to point UIP at the end of
1073 * the program, and at brw_uip_jip() JIP will be set to the end of the
1074 * current block (or the program).
1076 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1078 brw_push_insn_state(p
);
1079 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1081 brw_pop_insn_state(p
);
1085 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1087 assert(inst
->mlen
!= 0);
1090 brw_uvec_mrf(inst
->exec_size
, (inst
->base_mrf
+ 1), 0),
1091 retype(src
, BRW_REGISTER_TYPE_UD
));
1092 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1093 inst
->exec_size
/ 8, inst
->offset
);
1097 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1099 assert(inst
->mlen
!= 0);
1101 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1102 inst
->exec_size
/ 8, inst
->offset
);
1106 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1108 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1112 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1114 struct brw_reg index
,
1115 struct brw_reg offset
)
1117 assert(inst
->mlen
!= 0);
1119 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1120 index
.type
== BRW_REGISTER_TYPE_UD
);
1121 uint32_t surf_index
= index
.dw1
.ud
;
1123 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1124 offset
.type
== BRW_REGISTER_TYPE_UD
);
1125 uint32_t read_offset
= offset
.dw1
.ud
;
1127 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1128 read_offset
, surf_index
);
1130 brw_mark_surface_used(prog_data
, surf_index
);
1134 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1136 struct brw_reg index
,
1137 struct brw_reg offset
)
1139 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1141 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
1142 /* Reference just the dword we need, to avoid angering validate_reg(). */
1143 offset
= brw_vec1_grf(offset
.nr
, 0);
1145 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1146 * the destination loaded consecutively from the same offset (which appears
1147 * in the first component, and the rest are ignored).
1149 dst
.width
= BRW_WIDTH_4
;
1151 struct brw_reg src
= offset
;
1152 bool header_present
= false;
1154 if (devinfo
->gen
>= 9) {
1155 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1156 src
= retype(brw_vec4_grf(offset
.nr
, 0), BRW_REGISTER_TYPE_UD
);
1157 header_present
= true;
1159 brw_push_insn_state(p
);
1160 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1161 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1162 brw_MOV(p
, vec8(src
), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1163 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1165 brw_MOV(p
, get_element_ud(src
, 2),
1166 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
));
1167 brw_pop_insn_state(p
);
1170 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1172 uint32_t surf_index
= index
.dw1
.ud
;
1174 brw_push_insn_state(p
);
1175 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1176 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1177 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1178 brw_pop_insn_state(p
);
1180 brw_set_dest(p
, send
, dst
);
1181 brw_set_src0(p
, send
, src
);
1182 brw_set_sampler_message(p
, send
,
1184 0, /* LD message ignores sampler unit */
1185 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1189 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1192 brw_mark_surface_used(prog_data
, surf_index
);
1196 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1198 brw_push_insn_state(p
);
1199 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1200 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1202 /* a0.0 = surf_index & 0xff */
1203 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1204 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1205 brw_set_dest(p
, insn_and
, addr
);
1206 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1207 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1209 /* dst = send(payload, a0.0 | <descriptor>) */
1210 brw_inst
*insn
= brw_send_indirect_message(
1211 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1212 brw_set_sampler_message(p
, insn
,
1214 0, /* LD message ignores sampler unit */
1215 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1219 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1222 brw_pop_insn_state(p
);
1224 /* visitor knows more than we do about the surface limit required,
1225 * so has already done marking.
1232 fs_generator::generate_varying_pull_constant_load(fs_inst
*inst
,
1234 struct brw_reg index
,
1235 struct brw_reg offset
)
1237 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1238 assert(inst
->header_size
!= 0);
1241 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1242 index
.type
== BRW_REGISTER_TYPE_UD
);
1243 uint32_t surf_index
= index
.dw1
.ud
;
1245 uint32_t simd_mode
, rlen
, msg_type
;
1246 if (dispatch_width
== 16) {
1247 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1250 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1254 if (devinfo
->gen
>= 5)
1255 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1257 /* We always use the SIMD16 message so that we only have to load U, and
1260 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1261 assert(inst
->mlen
== 3);
1262 assert(inst
->regs_written
== 8);
1264 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1267 struct brw_reg offset_mrf
= retype(brw_message_reg(inst
->base_mrf
+ 1),
1268 BRW_REGISTER_TYPE_D
);
1269 brw_MOV(p
, offset_mrf
, offset
);
1271 struct brw_reg header
= brw_vec8_grf(0, 0);
1272 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1274 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1275 brw_inst_set_qtr_control(p
->devinfo
, send
, BRW_COMPRESSION_NONE
);
1276 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1277 brw_set_src0(p
, send
, header
);
1278 if (devinfo
->gen
< 6)
1279 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1281 /* Our surface is set up as floats, regardless of what actual data is
1284 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1285 brw_set_sampler_message(p
, send
,
1287 0, /* sampler (unused) */
1291 inst
->header_size
!= 0,
1295 brw_mark_surface_used(prog_data
, surf_index
);
1299 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1301 struct brw_reg index
,
1302 struct brw_reg offset
)
1304 assert(devinfo
->gen
>= 7);
1305 /* Varying-offset pull constant loads are treated as a normal expression on
1306 * gen7, so the fact that it's a send message is hidden at the IR level.
1308 assert(inst
->header_size
== 0);
1309 assert(!inst
->mlen
);
1310 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1312 uint32_t simd_mode
, rlen
, mlen
;
1313 if (dispatch_width
== 16) {
1316 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1320 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1323 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1325 uint32_t surf_index
= index
.dw1
.ud
;
1327 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1328 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1329 brw_set_src0(p
, send
, offset
);
1330 brw_set_sampler_message(p
, send
,
1332 0, /* LD message ignores sampler unit */
1333 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1336 false, /* no header */
1340 brw_mark_surface_used(prog_data
, surf_index
);
1344 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1346 brw_push_insn_state(p
);
1347 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1348 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1350 /* a0.0 = surf_index & 0xff */
1351 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1352 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1353 brw_set_dest(p
, insn_and
, addr
);
1354 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1355 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1357 brw_pop_insn_state(p
);
1359 /* dst = send(offset, a0.0 | <descriptor>) */
1360 brw_inst
*insn
= brw_send_indirect_message(
1361 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1363 brw_set_sampler_message(p
, insn
,
1366 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1373 /* visitor knows more than we do about the surface limit required,
1374 * so has already done marking.
1380 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1381 * into the flags register (f0.0).
1383 * Used only on Gen6 and above.
1386 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1388 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
1389 struct brw_reg dispatch_mask
;
1391 if (devinfo
->gen
>= 6)
1392 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1394 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1396 brw_push_insn_state(p
);
1397 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1398 brw_MOV(p
, flags
, dispatch_mask
);
1399 brw_pop_insn_state(p
);
1403 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1406 struct brw_reg msg_data
,
1409 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1411 brw_pixel_interpolator_query(p
,
1412 retype(dst
, BRW_REGISTER_TYPE_UW
),
1414 inst
->pi_noperspective
,
1418 inst
->regs_written
);
1423 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1424 * sampler LD messages.
1426 * We don't want to bake it into the send message's code generation because
1427 * that means we don't get a chance to schedule the instructions.
1430 fs_generator::generate_set_simd4x2_offset(fs_inst
*inst
,
1432 struct brw_reg value
)
1434 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1436 brw_push_insn_state(p
);
1437 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1438 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1439 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1440 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 0), value
.type
), value
);
1441 brw_pop_insn_state(p
);
1444 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1445 * the ADD instruction.
1448 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1450 struct brw_reg src0
,
1451 struct brw_reg src1
)
1453 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1454 dst
.type
== BRW_REGISTER_TYPE_UD
);
1455 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1456 src0
.type
== BRW_REGISTER_TYPE_UD
);
1458 brw_push_insn_state(p
);
1459 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1460 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1461 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1462 struct brw_reg reg
= retype(stride(src1
, 1, 4, 0), BRW_REGISTER_TYPE_UW
);
1463 if (dispatch_width
== 8) {
1464 brw_ADD(p
, dst
, src0
, reg
);
1465 } else if (dispatch_width
== 16) {
1466 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), reg
);
1467 brw_ADD(p
, sechalf(dst
), sechalf(src0
), suboffset(reg
, 2));
1469 brw_pop_insn_state(p
);
1473 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
1478 assert(devinfo
->gen
>= 7);
1479 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1480 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1481 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1483 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1485 * Because this instruction does not have a 16-bit floating-point type,
1486 * the destination data type must be Word (W).
1488 * The destination must be DWord-aligned and specify a horizontal stride
1489 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1490 * each destination channel and the upper word is not modified.
1492 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1494 /* Give each 32-bit channel of dst the form below, where "." means
1498 brw_F32TO16(p
, dst_w
, y
);
1503 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1505 /* And, finally the form of packHalf2x16's output:
1508 brw_F32TO16(p
, dst_w
, x
);
1512 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1516 assert(devinfo
->gen
>= 7);
1517 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1518 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1520 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1522 * Because this instruction does not have a 16-bit floating-point type,
1523 * the source data type must be Word (W). The destination type must be
1526 struct brw_reg src_w
= spread(retype(src
, BRW_REGISTER_TYPE_W
), 2);
1528 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1529 * For the Y case, we wish to access only the upper word; therefore
1530 * a 16-bit subregister offset is needed.
1532 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1533 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1534 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1537 brw_F16TO32(p
, dst
, src_w
);
1541 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1542 struct brw_reg payload
,
1543 struct brw_reg offset
,
1544 struct brw_reg value
)
1546 assert(devinfo
->gen
>= 7);
1547 brw_push_insn_state(p
);
1548 brw_set_default_mask_control(p
, true);
1550 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1551 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1553 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1556 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1557 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1558 value
.width
= BRW_WIDTH_1
;
1559 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1560 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1562 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1565 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1566 * case, and we don't really care about squeezing every bit of performance
1567 * out of this path, so we just emit the MOVs from here.
1569 brw_MOV(p
, payload_offset
, offset
);
1570 brw_MOV(p
, payload_value
, value
);
1571 brw_shader_time_add(p
, payload
,
1572 prog_data
->binding_table
.shader_time_start
);
1573 brw_pop_insn_state(p
);
1575 brw_mark_surface_used(prog_data
,
1576 prog_data
->binding_table
.shader_time_start
);
1580 fs_generator::enable_debug(const char *shader_name
)
1583 this->shader_name
= shader_name
;
1587 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1589 /* align to 64 byte boundary. */
1590 while (p
->next_insn_offset
% 64)
1593 this->dispatch_width
= dispatch_width
;
1594 if (dispatch_width
== 16)
1595 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1597 int start_offset
= p
->next_insn_offset
;
1598 int spill_count
= 0, fill_count
= 0;
1601 struct annotation_info annotation
;
1602 memset(&annotation
, 0, sizeof(annotation
));
1604 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1605 struct brw_reg src
[3], dst
;
1606 unsigned int last_insn_offset
= p
->next_insn_offset
;
1607 bool multiple_instructions_emitted
= false;
1609 if (unlikely(debug_flag
))
1610 annotate(p
->devinfo
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1612 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1613 src
[i
] = brw_reg_from_fs_reg(inst
, &inst
->src
[i
], devinfo
->gen
);
1615 /* The accumulator result appears to get used for the
1616 * conditional modifier generation. When negating a UD
1617 * value, there is a 33rd bit generated for the sign in the
1618 * accumulator value, so now you can't check, for example,
1619 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1621 assert(!inst
->conditional_mod
||
1622 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1623 !inst
->src
[i
].negate
);
1625 dst
= brw_reg_from_fs_reg(inst
, &inst
->dst
, devinfo
->gen
);
1627 brw_set_default_predicate_control(p
, inst
->predicate
);
1628 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1629 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1630 brw_set_default_saturate(p
, inst
->saturate
);
1631 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1632 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1633 brw_set_default_exec_size(p
, cvt(inst
->exec_size
) - 1);
1635 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1636 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1638 switch (inst
->exec_size
) {
1642 assert(inst
->force_writemask_all
);
1643 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1646 if (inst
->force_sechalf
) {
1647 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1649 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1654 /* If the instruction writes to more than one register, it needs to
1655 * be a "compressed" instruction on Gen <= 5.
1657 if (inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
)
1658 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1660 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1663 unreachable("Invalid instruction width");
1666 switch (inst
->opcode
) {
1667 case BRW_OPCODE_MOV
:
1668 brw_MOV(p
, dst
, src
[0]);
1670 case BRW_OPCODE_ADD
:
1671 brw_ADD(p
, dst
, src
[0], src
[1]);
1673 case BRW_OPCODE_MUL
:
1674 brw_MUL(p
, dst
, src
[0], src
[1]);
1676 case BRW_OPCODE_AVG
:
1677 brw_AVG(p
, dst
, src
[0], src
[1]);
1679 case BRW_OPCODE_MACH
:
1680 brw_MACH(p
, dst
, src
[0], src
[1]);
1683 case BRW_OPCODE_LINE
:
1684 brw_LINE(p
, dst
, src
[0], src
[1]);
1687 case BRW_OPCODE_MAD
:
1688 assert(devinfo
->gen
>= 6);
1689 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1690 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1691 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1692 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1693 brw_inst
*f
= brw_MAD(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1694 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1695 brw_inst
*s
= brw_MAD(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1696 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1698 if (inst
->conditional_mod
) {
1699 brw_inst_set_cond_modifier(p
->devinfo
, f
, inst
->conditional_mod
);
1700 brw_inst_set_cond_modifier(p
->devinfo
, s
, inst
->conditional_mod
);
1701 multiple_instructions_emitted
= true;
1704 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1706 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1709 case BRW_OPCODE_LRP
:
1710 assert(devinfo
->gen
>= 6);
1711 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1712 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1713 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1714 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1715 brw_inst
*f
= brw_LRP(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1716 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1717 brw_inst
*s
= brw_LRP(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1718 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1720 if (inst
->conditional_mod
) {
1721 brw_inst_set_cond_modifier(p
->devinfo
, f
, inst
->conditional_mod
);
1722 brw_inst_set_cond_modifier(p
->devinfo
, s
, inst
->conditional_mod
);
1723 multiple_instructions_emitted
= true;
1726 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1728 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1731 case BRW_OPCODE_FRC
:
1732 brw_FRC(p
, dst
, src
[0]);
1734 case BRW_OPCODE_RNDD
:
1735 brw_RNDD(p
, dst
, src
[0]);
1737 case BRW_OPCODE_RNDE
:
1738 brw_RNDE(p
, dst
, src
[0]);
1740 case BRW_OPCODE_RNDZ
:
1741 brw_RNDZ(p
, dst
, src
[0]);
1744 case BRW_OPCODE_AND
:
1745 brw_AND(p
, dst
, src
[0], src
[1]);
1748 brw_OR(p
, dst
, src
[0], src
[1]);
1750 case BRW_OPCODE_XOR
:
1751 brw_XOR(p
, dst
, src
[0], src
[1]);
1753 case BRW_OPCODE_NOT
:
1754 brw_NOT(p
, dst
, src
[0]);
1756 case BRW_OPCODE_ASR
:
1757 brw_ASR(p
, dst
, src
[0], src
[1]);
1759 case BRW_OPCODE_SHR
:
1760 brw_SHR(p
, dst
, src
[0], src
[1]);
1762 case BRW_OPCODE_SHL
:
1763 brw_SHL(p
, dst
, src
[0], src
[1]);
1765 case BRW_OPCODE_F32TO16
:
1766 assert(devinfo
->gen
>= 7);
1767 brw_F32TO16(p
, dst
, src
[0]);
1769 case BRW_OPCODE_F16TO32
:
1770 assert(devinfo
->gen
>= 7);
1771 brw_F16TO32(p
, dst
, src
[0]);
1773 case BRW_OPCODE_CMP
:
1774 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1775 * that when the destination is a GRF that the dependency-clear bit on
1776 * the flag register is cleared early.
1778 * Suggested workarounds are to disable coissuing CMP instructions
1779 * or to split CMP(16) instructions into two CMP(8) instructions.
1781 * We choose to split into CMP(8) instructions since disabling
1782 * coissuing would affect CMP instructions not otherwise affected by
1785 if (dispatch_width
== 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1786 if (dst
.file
== BRW_GENERAL_REGISTER_FILE
) {
1787 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1788 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1789 brw_CMP(p
, firsthalf(dst
), inst
->conditional_mod
,
1790 firsthalf(src
[0]), firsthalf(src
[1]));
1791 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1792 brw_CMP(p
, sechalf(dst
), inst
->conditional_mod
,
1793 sechalf(src
[0]), sechalf(src
[1]));
1794 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1796 multiple_instructions_emitted
= true;
1797 } else if (dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1798 /* For unknown reasons, the aforementioned workaround is not
1799 * sufficient. Overriding the type when the destination is the
1800 * null register is necessary but not sufficient by itself.
1802 assert(dst
.nr
== BRW_ARF_NULL
);
1803 dst
.type
= BRW_REGISTER_TYPE_D
;
1804 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1806 unreachable("not reached");
1809 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1812 case BRW_OPCODE_SEL
:
1813 brw_SEL(p
, dst
, src
[0], src
[1]);
1815 case BRW_OPCODE_BFREV
:
1816 assert(devinfo
->gen
>= 7);
1817 /* BFREV only supports UD type for src and dst. */
1818 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1819 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1821 case BRW_OPCODE_FBH
:
1822 assert(devinfo
->gen
>= 7);
1823 /* FBH only supports UD type for dst. */
1824 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1826 case BRW_OPCODE_FBL
:
1827 assert(devinfo
->gen
>= 7);
1828 /* FBL only supports UD type for dst. */
1829 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1831 case BRW_OPCODE_CBIT
:
1832 assert(devinfo
->gen
>= 7);
1833 /* CBIT only supports UD type for dst. */
1834 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1836 case BRW_OPCODE_ADDC
:
1837 assert(devinfo
->gen
>= 7);
1838 brw_ADDC(p
, dst
, src
[0], src
[1]);
1840 case BRW_OPCODE_SUBB
:
1841 assert(devinfo
->gen
>= 7);
1842 brw_SUBB(p
, dst
, src
[0], src
[1]);
1844 case BRW_OPCODE_MAC
:
1845 brw_MAC(p
, dst
, src
[0], src
[1]);
1848 case BRW_OPCODE_BFE
:
1849 assert(devinfo
->gen
>= 7);
1850 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1851 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1852 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1853 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1854 brw_BFE(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1855 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1856 brw_BFE(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1857 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1859 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1861 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1864 case BRW_OPCODE_BFI1
:
1865 assert(devinfo
->gen
>= 7);
1866 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1869 * "Force BFI instructions to be executed always in SIMD8."
1871 if (dispatch_width
== 16 && devinfo
->is_haswell
) {
1872 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1873 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1874 brw_BFI1(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]));
1875 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1876 brw_BFI1(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]));
1877 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1879 brw_BFI1(p
, dst
, src
[0], src
[1]);
1882 case BRW_OPCODE_BFI2
:
1883 assert(devinfo
->gen
>= 7);
1884 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1885 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1888 * "Force BFI instructions to be executed always in SIMD8."
1890 * Otherwise we would be able to emit compressed instructions like we
1891 * do for the other three-source instructions.
1893 if (dispatch_width
== 16 &&
1894 (devinfo
->is_haswell
|| !devinfo
->supports_simd16_3src
)) {
1895 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1896 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1897 brw_BFI2(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1898 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1899 brw_BFI2(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1900 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1902 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1904 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1908 if (inst
->src
[0].file
!= BAD_FILE
) {
1909 /* The instruction has an embedded compare (only allowed on gen6) */
1910 assert(devinfo
->gen
== 6);
1911 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1913 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1917 case BRW_OPCODE_ELSE
:
1920 case BRW_OPCODE_ENDIF
:
1925 brw_DO(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1928 case BRW_OPCODE_BREAK
:
1930 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1932 case BRW_OPCODE_CONTINUE
:
1934 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1937 case BRW_OPCODE_WHILE
:
1942 case SHADER_OPCODE_RCP
:
1943 case SHADER_OPCODE_RSQ
:
1944 case SHADER_OPCODE_SQRT
:
1945 case SHADER_OPCODE_EXP2
:
1946 case SHADER_OPCODE_LOG2
:
1947 case SHADER_OPCODE_SIN
:
1948 case SHADER_OPCODE_COS
:
1949 assert(devinfo
->gen
< 6 || inst
->mlen
== 0);
1950 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1951 if (devinfo
->gen
>= 7) {
1952 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1954 } else if (devinfo
->gen
== 6) {
1955 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
1956 } else if (devinfo
->gen
== 5 || devinfo
->is_g4x
) {
1957 generate_math_g45(inst
, dst
, src
[0]);
1959 generate_math_gen4(inst
, dst
, src
[0]);
1962 case SHADER_OPCODE_INT_QUOTIENT
:
1963 case SHADER_OPCODE_INT_REMAINDER
:
1964 case SHADER_OPCODE_POW
:
1965 assert(devinfo
->gen
< 6 || inst
->mlen
== 0);
1966 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1967 if (devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) {
1968 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1969 } else if (devinfo
->gen
>= 6) {
1970 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
1972 generate_math_gen4(inst
, dst
, src
[0]);
1975 case FS_OPCODE_CINTERP
:
1976 brw_MOV(p
, dst
, src
[0]);
1978 case FS_OPCODE_LINTERP
:
1979 generate_linterp(inst
, dst
, src
);
1981 case FS_OPCODE_PIXEL_X
:
1982 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1983 src
[0].subnr
= 0 * type_sz(src
[0].type
);
1984 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1986 case FS_OPCODE_PIXEL_Y
:
1987 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1988 src
[0].subnr
= 4 * type_sz(src
[0].type
);
1989 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1991 case FS_OPCODE_GET_BUFFER_SIZE
:
1992 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
1994 case SHADER_OPCODE_TEX
:
1996 case SHADER_OPCODE_TXD
:
1997 case SHADER_OPCODE_TXF
:
1998 case SHADER_OPCODE_TXF_CMS
:
1999 case SHADER_OPCODE_TXF_UMS
:
2000 case SHADER_OPCODE_TXF_MCS
:
2001 case SHADER_OPCODE_TXL
:
2002 case SHADER_OPCODE_TXS
:
2003 case SHADER_OPCODE_LOD
:
2004 case SHADER_OPCODE_TG4
:
2005 case SHADER_OPCODE_TG4_OFFSET
:
2006 case SHADER_OPCODE_SAMPLEINFO
:
2007 generate_tex(inst
, dst
, src
[0], src
[1]);
2009 case FS_OPCODE_DDX_COARSE
:
2010 case FS_OPCODE_DDX_FINE
:
2011 generate_ddx(inst
->opcode
, dst
, src
[0]);
2013 case FS_OPCODE_DDY_COARSE
:
2014 case FS_OPCODE_DDY_FINE
:
2015 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2016 generate_ddy(inst
->opcode
, dst
, src
[0], src
[1].dw1
.ud
);
2019 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2020 generate_scratch_write(inst
, src
[0]);
2024 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2025 generate_scratch_read(inst
, dst
);
2029 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2030 generate_scratch_read_gen7(inst
, dst
);
2034 case SHADER_OPCODE_URB_READ_SIMD8
:
2035 generate_urb_read(inst
, dst
, src
[0]);
2038 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2039 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2040 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2041 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2042 generate_urb_write(inst
, src
[0]);
2045 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2046 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2049 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2050 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2053 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
2054 generate_varying_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2057 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
2058 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2061 case FS_OPCODE_REP_FB_WRITE
:
2062 case FS_OPCODE_FB_WRITE
:
2063 generate_fb_write(inst
, src
[0]);
2066 case FS_OPCODE_BLORP_FB_WRITE
:
2067 generate_blorp_fb_write(inst
);
2070 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
2071 generate_mov_dispatch_to_flags(inst
);
2074 case FS_OPCODE_DISCARD_JUMP
:
2075 generate_discard_jump(inst
);
2078 case SHADER_OPCODE_SHADER_TIME_ADD
:
2079 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2082 case SHADER_OPCODE_UNTYPED_ATOMIC
:
2083 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2084 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].dw1
.ud
,
2085 inst
->mlen
, !inst
->dst
.is_null());
2088 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
2089 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2090 brw_untyped_surface_read(p
, dst
, src
[0], src
[1],
2091 inst
->mlen
, src
[2].dw1
.ud
);
2094 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
2095 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2096 brw_untyped_surface_write(p
, src
[0], src
[1],
2097 inst
->mlen
, src
[2].dw1
.ud
);
2100 case SHADER_OPCODE_TYPED_ATOMIC
:
2101 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2102 brw_typed_atomic(p
, dst
, src
[0], src
[1],
2103 src
[2].dw1
.ud
, inst
->mlen
, !inst
->dst
.is_null());
2106 case SHADER_OPCODE_TYPED_SURFACE_READ
:
2107 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2108 brw_typed_surface_read(p
, dst
, src
[0], src
[1],
2109 inst
->mlen
, src
[2].dw1
.ud
);
2112 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
2113 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2114 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
, src
[2].dw1
.ud
);
2117 case SHADER_OPCODE_MEMORY_FENCE
:
2118 brw_memory_fence(p
, dst
);
2121 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
2122 generate_set_simd4x2_offset(inst
, dst
, src
[0]);
2125 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2126 brw_find_live_channel(p
, dst
);
2129 case SHADER_OPCODE_BROADCAST
:
2130 brw_broadcast(p
, dst
, src
[0], src
[1]);
2133 case FS_OPCODE_SET_SAMPLE_ID
:
2134 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2137 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2138 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2141 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
2142 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
2143 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
2146 case FS_OPCODE_PLACEHOLDER_HALT
:
2147 /* This is the place where the final HALT needs to be inserted if
2148 * we've emitted any discards. If not, this will emit no code.
2150 if (!patch_discard_jumps_to_fb_writes()) {
2151 if (unlikely(debug_flag
)) {
2152 annotation
.ann_count
--;
2157 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
2158 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2159 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID
);
2162 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2163 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2164 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2167 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2168 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2169 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2172 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2173 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2174 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2177 case CS_OPCODE_CS_TERMINATE
:
2178 generate_cs_terminate(inst
, src
[0]);
2181 case SHADER_OPCODE_BARRIER
:
2182 generate_barrier(inst
, src
[0]);
2186 unreachable("Unsupported opcode");
2188 case SHADER_OPCODE_LOAD_PAYLOAD
:
2189 unreachable("Should be lowered by lower_load_payload()");
2192 if (multiple_instructions_emitted
)
2195 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2196 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2197 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2198 "emitting more than 1 instruction");
2200 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2202 if (inst
->conditional_mod
)
2203 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2204 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2205 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2210 annotation_finalize(&annotation
, p
->next_insn_offset
);
2212 int before_size
= p
->next_insn_offset
- start_offset
;
2213 brw_compact_instructions(p
, start_offset
, annotation
.ann_count
,
2215 int after_size
= p
->next_insn_offset
- start_offset
;
2217 if (unlikely(debug_flag
)) {
2218 fprintf(stderr
, "Native code for %s\n"
2219 "SIMD%d shader: %d instructions. %d loops. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2220 " bytes (%.0f%%)\n",
2221 shader_name
, dispatch_width
, before_size
/ 16, loop_count
,
2222 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2223 100.0f
* (before_size
- after_size
) / before_size
);
2225 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
,
2227 ralloc_free(annotation
.ann
);
2230 compiler
->shader_debug_log(log_data
,
2231 "%s SIMD%d shader: %d inst, %d loops, "
2232 "%d:%d spills:fills, Promoted %u constants, "
2233 "compacted %d to %d bytes.\n",
2234 stage_abbrev
, dispatch_width
, before_size
/ 16,
2235 loop_count
, spill_count
, fill_count
,
2236 promoted_constants
, before_size
, after_size
);
2238 return start_offset
;
2242 fs_generator::get_assembly(unsigned int *assembly_size
)
2244 return brw_get_program(p
, assembly_size
);