src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_cfg.h"
  29 #include "brw_fs_live_variables.h"
  30
  31 using namespace brw;
  32
  33 #define MAX_INSTRUCTION (1 << 30)
  34
  35 /** @file brw_fs_live_variables.cpp
  36  *
  37  * Support for calculating liveness information about virtual GRFs.
  38  *
  39  * This produces a live interval for each whole virtual GRF.  We could
  40  * choose to expose per-component live intervals for VGRFs of size > 1,
  41  * but we currently do not.  It is easier for the consumers of this
  42  * information to work with whole VGRFs.
  43  *
  44  * However, we internally track use/def information at the per-component
  45  * (reg_offset) level for greater accuracy.  Large VGRFs may be accessed
  46  * piecemeal over many (possibly non-adjacent) instructions.  In this case,
  47  * examining a single instruction is insufficient to decide whether a whole
  48  * VGRF is ultimately used or defined.  Tracking individual components
  49  * allows us to easily assemble this information.
  50  *
  51  * See Muchnick's Advanced Compiler Design and Implementation, section
  52  * 14.1 (p444).
  53  */
  54
  55 void
  56 fs_live_variables::setup_one_read(bblock_t *block, fs_inst *inst,
  57                                   int ip, fs_reg reg)
  58 {
  59    int var = var_from_vgrf[reg.reg] + reg.reg_offset;
  60    assert(var < num_vars);
  61
  62    /* In most cases, a register can be written over safely by the
  63     * same instruction that is its last use.  For a single
  64     * instruction, the sources are dereferenced before writing of the
  65     * destination starts (naturally).  This gets more complicated for
  66     * simd16, because the instruction:
  67     *
  68     * add(16)      g4<1>F      g4<8,8,1>F   g6<8,8,1>F
  69     *
  70     * is actually decoded in hardware as:
  71     *
  72     * add(8)       g4<1>F      g4<8,8,1>F   g6<8,8,1>F
  73     * add(8)       g5<1>F      g5<8,8,1>F   g7<8,8,1>F
  74     *
  75     * Which is safe.  However, if we have uniform accesses
  76     * happening, we get into trouble:
  77     *
  78     * add(8)       g4<1>F      g4<0,1,0>F   g6<8,8,1>F
  79     * add(8)       g5<1>F      g4<0,1,0>F   g7<8,8,1>F
  80     *
  81     * Now our destination for the first instruction overwrote the
  82     * second instruction's src0, and we get garbage for those 8
  83     * pixels.  There's a similar issue for the pre-gen6
  84     * pixel_x/pixel_y, which are registers of 16-bit values and thus
  85     * would get stomped by the first decode as well.
  86     */
  87    int end_ip = ip;
  88    if (v->dispatch_width == 16 && (reg.stride == 0 ||
  89                                    ((v->pixel_x.file == GRF &&
  90                                      v->pixel_x.reg == reg.reg) ||
  91                                     (v->pixel_y.file == GRF &&
  92                                      v->pixel_y.reg == reg.reg)))) {
  93       end_ip++;
  94    }
  95
  96    start[var] = MIN2(start[var], ip);
  97    end[var] = MAX2(end[var], end_ip);
  98
  99    /* The use[] bitset marks when the block makes use of a variable (VGRF
 100     * channel) without having completely defined that variable within the
 101     * block.
 102     */
 103    if (!BITSET_TEST(bd[block->block_num].def, var))
 104       BITSET_SET(bd[block->block_num].use, var);
 105 }
 106
 107 void
 108 fs_live_variables::setup_one_write(bblock_t *block, fs_inst *inst,
 109                                    int ip, fs_reg reg)
 110 {
 111    int var = var_from_vgrf[reg.reg] + reg.reg_offset;
 112    assert(var < num_vars);
 113
 114    start[var] = MIN2(start[var], ip);
 115    end[var] = MAX2(end[var], ip);
 116
 117    /* The def[] bitset marks when an initialization in a block completely
 118     * screens off previous updates of that variable (VGRF channel).
 119     */
 120    if (inst->dst.file == GRF && !inst->is_partial_write()) {
 121       if (!BITSET_TEST(bd[block->block_num].use, var))
 122          BITSET_SET(bd[block->block_num].def, var);
 123    }
 124 }
 125
 126 /**
 127  * Sets up the use[] and def[] bitsets.
 128  *
 129  * The basic-block-level live variable analysis needs to know which
 130  * variables get used before they're completely defined, and which
 131  * variables are completely defined before they're used.
 132  *
 133  * These are tracked at the per-component level, rather than whole VGRFs.
 134  */
 135 void
 136 fs_live_variables::setup_def_use()
 137 {
 138    int ip = 0;
 139
 140    for (int b = 0; b < cfg->num_blocks; b++) {
 141       bblock_t *block = cfg->blocks[b];
 142
 143       assert(ip == block->start_ip);
 144       if (b > 0)
 145          assert(cfg->blocks[b - 1]->end_ip == ip - 1);
 146
 147       for (fs_inst *inst = (fs_inst *)block->start;
 148            inst != block->end->next;
 149            inst = (fs_inst *)inst->next) {
 150
 151          /* Set use[] for this instruction */
 152          for (unsigned int i = 0; i < 3; i++) {
 153             fs_reg reg = inst->src[i];
 154
 155             if (reg.file != GRF)
 156                continue;
 157
 158             for (int j = 0; j < inst->regs_read(v, i); j++) {
 159                setup_one_read(block, inst, ip, reg);
 160                reg.reg_offset++;
 161             }
 162          }
 163
 164          /* Set def[] for this instruction */
 165          if (inst->dst.file == GRF) {
 166             fs_reg reg = inst->dst;
 167             for (int j = 0; j < inst->regs_written; j++) {
 168                setup_one_write(block, inst, ip, reg);
 169                reg.reg_offset++;
 170             }
 171          }
 172
 173          ip++;
 174       }
 175    }
 176 }
 177
 178 /**
 179  * The algorithm incrementally sets bits in liveout and livein,
 180  * propagating it through control flow.  It will eventually terminate
 181  * because it only ever adds bits, and stops when no bits are added in
 182  * a pass.
 183  */
 184 void
 185 fs_live_variables::compute_live_variables()
 186 {
 187    bool cont = true;
 188
 189    while (cont) {
 190       cont = false;
 191
 192       for (int b = 0; b < cfg->num_blocks; b++) {
 193          /* Update livein */
 194          for (int i = 0; i < bitset_words; i++) {
 195             BITSET_WORD new_livein = (bd[b].use[i] |
 196                                       (bd[b].liveout[i] & ~bd[b].def[i]));
 197             if (new_livein & ~bd[b].livein[i]) {
 198                bd[b].livein[i] |= new_livein;
 199                cont = true;
 200             }
 201          }
 202
 203          /* Update liveout */
 204          foreach_list(block_node, &cfg->blocks[b]->children) {
 205             bblock_link *link = (bblock_link *)block_node;
 206             bblock_t *block = link->block;
 207
 208             for (int i = 0; i < bitset_words; i++) {
 209                BITSET_WORD new_liveout = (bd[block->block_num].livein[i] &
 210                                           ~bd[b].liveout[i]);
 211                if (new_liveout) {
 212                   bd[b].liveout[i] |= new_liveout;
 213                   cont = true;
 214                }
 215             }
 216          }
 217       }
 218    }
 219 }
 220
 221 /**
 222  * Extend the start/end ranges for each variable to account for the
 223  * new information calculated from control flow.
 224  */
 225 void
 226 fs_live_variables::compute_start_end()
 227 {
 228    for (int b = 0; b < cfg->num_blocks; b++) {
 229       for (int i = 0; i < num_vars; i++) {
 230          if (BITSET_TEST(bd[b].livein, i)) {
 231             start[i] = MIN2(start[i], cfg->blocks[b]->start_ip);
 232             end[i] = MAX2(end[i], cfg->blocks[b]->start_ip);
 233          }
 234
 235          if (BITSET_TEST(bd[b].liveout, i)) {
 236             start[i] = MIN2(start[i], cfg->blocks[b]->end_ip);
 237             end[i] = MAX2(end[i], cfg->blocks[b]->end_ip);
 238          }
 239
 240       }
 241    }
 242 }
 243
 244 int
 245 fs_live_variables::var_from_reg(fs_reg *reg)
 246 {
 247    return var_from_vgrf[reg->reg] + reg->reg_offset;
 248 }
 249
 250 fs_live_variables::fs_live_variables(fs_visitor *v, cfg_t *cfg)
 251    : v(v), cfg(cfg)
 252 {
 253    mem_ctx = ralloc_context(NULL);
 254
 255    num_vgrfs = v->virtual_grf_count;
 256    num_vars = 0;
 257    var_from_vgrf = rzalloc_array(mem_ctx, int, num_vgrfs);
 258    for (int i = 0; i < num_vgrfs; i++) {
 259       var_from_vgrf[i] = num_vars;
 260       num_vars += v->virtual_grf_sizes[i];
 261    }
 262
 263    vgrf_from_var = rzalloc_array(mem_ctx, int, num_vars);
 264    for (int i = 0; i < num_vgrfs; i++) {
 265       for (int j = 0; j < v->virtual_grf_sizes[i]; j++) {
 266          vgrf_from_var[var_from_vgrf[i] + j] = i;
 267       }
 268    }
 269
 270    start = ralloc_array(mem_ctx, int, num_vars);
 271    end = rzalloc_array(mem_ctx, int, num_vars);
 272    for (int i = 0; i < num_vars; i++) {
 273       start[i] = MAX_INSTRUCTION;
 274       end[i] = -1;
 275    }
 276
 277    bd = rzalloc_array(mem_ctx, struct block_data, cfg->num_blocks);
 278
 279    bitset_words = BITSET_WORDS(num_vars);
 280    for (int i = 0; i < cfg->num_blocks; i++) {
 281       bd[i].def = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 282       bd[i].use = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 283       bd[i].livein = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 284       bd[i].liveout = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 285    }
 286
 287    setup_def_use();
 288    compute_live_variables();
 289    compute_start_end();
 290 }
 291
 292 fs_live_variables::~fs_live_variables()
 293 {
 294    ralloc_free(mem_ctx);
 295 }
 296
 297 void
 298 fs_visitor::invalidate_live_intervals()
 299 {
 300    ralloc_free(live_intervals);
 301    live_intervals = NULL;
 302 }
 303
 304 /**
 305  * Compute the live intervals for each virtual GRF.
 306  *
 307  * This uses the per-component use/def data, but combines it to produce
 308  * information about whole VGRFs.
 309  */
 310 void
 311 fs_visitor::calculate_live_intervals()
 312 {
 313    if (this->live_intervals)
 314       return;
 315
 316    int num_vgrfs = this->virtual_grf_count;
 317    ralloc_free(this->virtual_grf_start);
 318    ralloc_free(this->virtual_grf_end);
 319    virtual_grf_start = ralloc_array(mem_ctx, int, num_vgrfs);
 320    virtual_grf_end = ralloc_array(mem_ctx, int, num_vgrfs);
 321
 322    for (int i = 0; i < num_vgrfs; i++) {
 323       virtual_grf_start[i] = MAX_INSTRUCTION;
 324       virtual_grf_end[i] = -1;
 325    }
 326
 327    cfg_t cfg(&instructions);
 328    this->live_intervals = new(mem_ctx) fs_live_variables(this, &cfg);
 329
 330    /* Merge the per-component live ranges to whole VGRF live ranges. */
 331    for (int i = 0; i < live_intervals->num_vars; i++) {
 332       int vgrf = live_intervals->vgrf_from_var[i];
 333       virtual_grf_start[vgrf] = MIN2(virtual_grf_start[vgrf],
 334                                      live_intervals->start[i]);
 335       virtual_grf_end[vgrf] = MAX2(virtual_grf_end[vgrf],
 336                                    live_intervals->end[i]);
 337    }
 338 }
 339
 340 bool
 341 fs_live_variables::vars_interfere(int a, int b)
 342 {
 343    return !(end[b] <= start[a] ||
 344             end[a] <= start[b]);
 345 }
 346
 347 bool
 348 fs_visitor::virtual_grf_interferes(int a, int b)
 349 {
 350    return !(virtual_grf_end[a] <= virtual_grf_start[b] ||
 351             virtual_grf_end[b] <= virtual_grf_start[a]);
 352 }