src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_cfg.h"
  29 #include "brw_fs_live_variables.h"
  30
  31 using namespace brw;
  32
  33 /** @file brw_fs_live_variables.cpp
  34  *
  35  * Support for calculating liveness information about virtual GRFs.
  36  *
  37  * This produces a live interval for each whole virtual GRF.  We could
  38  * choose to expose per-component live intervals for VGRFs of size > 1,
  39  * but we currently do not.  It is easier for the consumers of this
  40  * information to work with whole VGRFs.
  41  *
  42  * However, we internally track use/def information at the per-component
  43  * (reg_offset) level for greater accuracy.  Large VGRFs may be accessed
  44  * piecemeal over many (possibly non-adjacent) instructions.  In this case,
  45  * examining a single instruction is insufficient to decide whether a whole
  46  * VGRF is ultimately used or defined.  Tracking individual components
  47  * allows us to easily assemble this information.
  48  *
  49  * See Muchnik's Advanced Compiler Design and Implementation, section
  50  * 14.1 (p444).
  51  */
  52
  53 void
  54 fs_live_variables::setup_one_read(bblock_t *block, fs_inst *inst,
  55                                   int ip, fs_reg reg)
  56 {
  57    int var = var_from_vgrf[reg.reg] + reg.reg_offset;
  58
  59    /* The use[] bitset marks when the block makes use of a variable (VGRF
  60     * channel) without having completely defined that variable within the
  61     * block.
  62     */
  63    if (!BITSET_TEST(bd[block->block_num].def, var))
  64       BITSET_SET(bd[block->block_num].use, var);
  65 }
  66
  67 void
  68 fs_live_variables::setup_one_write(bblock_t *block, fs_inst *inst,
  69                                    int ip, fs_reg reg)
  70 {
  71    int var = var_from_vgrf[reg.reg] + reg.reg_offset;
  72
  73    /* The def[] bitset marks when an initialization in a block completely
  74     * screens off previous updates of that variable (VGRF channel).
  75     */
  76    if (inst->dst.file == GRF && !inst->is_partial_write()) {
  77       if (!BITSET_TEST(bd[block->block_num].use, var))
  78          BITSET_SET(bd[block->block_num].def, var);
  79    }
  80 }
  81
  82 /**
  83  * Sets up the use[] and def[] bitsets.
  84  *
  85  * The basic-block-level live variable analysis needs to know which
  86  * variables get used before they're completely defined, and which
  87  * variables are completely defined before they're used.
  88  *
  89  * These are tracked at the per-component level, rather than whole VGRFs.
  90  */
  91 void
  92 fs_live_variables::setup_def_use()
  93 {
  94    int ip = 0;
  95
  96    for (int b = 0; b < cfg->num_blocks; b++) {
  97       bblock_t *block = cfg->blocks[b];
  98
  99       assert(ip == block->start_ip);
 100       if (b > 0)
 101          assert(cfg->blocks[b - 1]->end_ip == ip - 1);
 102
 103       for (fs_inst *inst = (fs_inst *)block->start;
 104            inst != block->end->next;
 105            inst = (fs_inst *)inst->next) {
 106
 107          /* Set use[] for this instruction */
 108          for (unsigned int i = 0; i < 3; i++) {
 109             fs_reg reg = inst->src[i];
 110
 111             if (reg.file != GRF)
 112                continue;
 113
 114             int regs_read = 1;
 115             /* We don't know how many components are read in a send-from-grf,
 116              * so just assume "all of them."
 117              */
 118             if (inst->is_send_from_grf())
 119                regs_read = v->virtual_grf_sizes[reg.reg];
 120
 121             for (int i = 0; i < regs_read; i++) {
 122                setup_one_read(block, inst, ip, reg);
 123                reg.reg_offset++;
 124             }
 125          }
 126
 127          /* Set def[] for this instruction */
 128          if (inst->dst.file == GRF) {
 129             fs_reg reg = inst->dst;
 130             for (int j = 0; j < inst->regs_written; j++) {
 131                setup_one_write(block, inst, ip, reg);
 132                reg.reg_offset++;
 133             }
 134          }
 135
 136          ip++;
 137       }
 138    }
 139 }
 140
 141 /**
 142  * The algorithm incrementally sets bits in liveout and livein,
 143  * propagating it through control flow.  It will eventually terminate
 144  * because it only ever adds bits, and stops when no bits are added in
 145  * a pass.
 146  */
 147 void
 148 fs_live_variables::compute_live_variables()
 149 {
 150    bool cont = true;
 151
 152    while (cont) {
 153       cont = false;
 154
 155       for (int b = 0; b < cfg->num_blocks; b++) {
 156          /* Update livein */
 157          for (int i = 0; i < bitset_words; i++) {
 158             BITSET_WORD new_livein = (bd[b].use[i] |
 159                                       (bd[b].liveout[i] & ~bd[b].def[i]));
 160             if (new_livein & ~bd[b].livein[i]) {
 161                bd[b].livein[i] |= new_livein;
 162                cont = true;
 163             }
 164          }
 165
 166          /* Update liveout */
 167          foreach_list(block_node, &cfg->blocks[b]->children) {
 168             bblock_link *link = (bblock_link *)block_node;
 169             bblock_t *block = link->block;
 170
 171             for (int i = 0; i < bitset_words; i++) {
 172                BITSET_WORD new_liveout = (bd[block->block_num].livein[i] &
 173                                           ~bd[b].liveout[i]);
 174                if (new_liveout) {
 175                   bd[b].liveout[i] |= new_liveout;
 176                   cont = true;
 177                }
 178             }
 179          }
 180       }
 181    }
 182 }
 183
 184 fs_live_variables::fs_live_variables(fs_visitor *v, cfg_t *cfg)
 185    : v(v), cfg(cfg)
 186 {
 187    mem_ctx = ralloc_context(cfg->mem_ctx);
 188
 189    num_vgrfs = v->virtual_grf_count;
 190    num_vars = 0;
 191    var_from_vgrf = rzalloc_array(mem_ctx, int, num_vgrfs);
 192    for (int i = 0; i < num_vgrfs; i++) {
 193       var_from_vgrf[i] = num_vars;
 194       num_vars += v->virtual_grf_sizes[i];
 195    }
 196
 197    vgrf_from_var = rzalloc_array(mem_ctx, int, num_vars);
 198    for (int i = 0; i < num_vgrfs; i++) {
 199       for (int j = 0; j < v->virtual_grf_sizes[i]; j++) {
 200          vgrf_from_var[var_from_vgrf[i] + j] = i;
 201       }
 202    }
 203
 204    bd = rzalloc_array(mem_ctx, struct block_data, cfg->num_blocks);
 205
 206    bitset_words = BITSET_WORDS(num_vars);
 207    for (int i = 0; i < cfg->num_blocks; i++) {
 208       bd[i].def = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 209       bd[i].use = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 210       bd[i].livein = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 211       bd[i].liveout = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 212    }
 213
 214    setup_def_use();
 215    compute_live_variables();
 216 }
 217
 218 fs_live_variables::~fs_live_variables()
 219 {
 220    ralloc_free(mem_ctx);
 221 }
 222
 223 #define MAX_INSTRUCTION (1 << 30)
 224
 225 void
 226 fs_visitor::invalidate_live_intervals()
 227 {
 228    this->live_intervals_valid = false;
 229 }
 230
 231 /**
 232  * Compute the live intervals for each virtual GRF.
 233  *
 234  * This uses the per-component use/def data, but combines it to produce
 235  * information about whole VGRFs.
 236  */
 237 void
 238 fs_visitor::calculate_live_intervals()
 239 {
 240    if (this->live_intervals_valid)
 241       return;
 242
 243    int num_vgrfs = this->virtual_grf_count;
 244    int *start = ralloc_array(mem_ctx, int, num_vgrfs);
 245    int *end = ralloc_array(mem_ctx, int, num_vgrfs);
 246    ralloc_free(this->virtual_grf_start);
 247    ralloc_free(this->virtual_grf_end);
 248    this->virtual_grf_start = start;
 249    this->virtual_grf_end = end;
 250
 251    for (int i = 0; i < num_vgrfs; i++) {
 252       start[i] = MAX_INSTRUCTION;
 253       end[i] = -1;
 254    }
 255
 256    /* Start by setting up the intervals with no knowledge of control
 257     * flow.
 258     */
 259    int ip = 0;
 260    foreach_list(node, &this->instructions) {
 261       fs_inst *inst = (fs_inst *)node;
 262
 263       for (unsigned int i = 0; i < 3; i++) {
 264          if (inst->src[i].file == GRF) {
 265             int reg = inst->src[i].reg;
 266             int end_ip = ip;
 267
 268             /* In most cases, a register can be written over safely by the
 269              * same instruction that is its last use.  For a single
 270              * instruction, the sources are dereferenced before writing of the
 271              * destination starts (naturally).  This gets more complicated for
 272              * simd16, because the instruction:
 273              *
 274              * mov(16)      g4<1>F      g4<8,8,1>F   g6<8,8,1>F
 275              *
 276              * is actually decoded in hardware as:
 277              *
 278              * mov(8)       g4<1>F      g4<8,8,1>F   g6<8,8,1>F
 279              * mov(8)       g5<1>F      g5<8,8,1>F   g7<8,8,1>F
 280              *
 281              * Which is safe.  However, if we have uniform accesses
 282              * happening, we get into trouble:
 283              *
 284              * mov(8)       g4<1>F      g4<0,1,0>F   g6<8,8,1>F
 285              * mov(8)       g5<1>F      g4<0,1,0>F   g7<8,8,1>F
 286              *
 287              * Now our destination for the first instruction overwrote the
 288              * second instruction's src0, and we get garbage for those 8
 289              * pixels.  There's a similar issue for the pre-gen6
 290              * pixel_x/pixel_y, which are registers of 16-bit values and thus
 291              * would get stomped by the first decode as well.
 292              */
 293             if (dispatch_width == 16 && (inst->src[i].smear >= 0 ||
 294                                          (this->pixel_x.reg == reg ||
 295                                           this->pixel_y.reg == reg))) {
 296                end_ip++;
 297             }
 298
 299             start[reg] = MIN2(start[reg], ip);
 300             end[reg] = MAX2(end[reg], end_ip);
 301          }
 302       }
 303
 304       if (inst->dst.file == GRF) {
 305          int reg = inst->dst.reg;
 306
 307          start[reg] = MIN2(start[reg], ip);
 308          end[reg] = MAX2(end[reg], ip);
 309       }
 310
 311       ip++;
 312    }
 313
 314    /* Now, extend those intervals using our analysis of control flow. */
 315    cfg_t cfg(this);
 316    fs_live_variables livevars(this, &cfg);
 317
 318    for (int b = 0; b < cfg.num_blocks; b++) {
 319       for (int i = 0; i < livevars.num_vars; i++) {
 320          int vgrf = livevars.vgrf_from_var[i];
 321          if (BITSET_TEST(livevars.bd[b].livein, i)) {
 322             start[vgrf] = MIN2(start[vgrf], cfg.blocks[b]->start_ip);
 323             end[vgrf] = MAX2(end[vgrf], cfg.blocks[b]->start_ip);
 324          }
 325
 326          if (BITSET_TEST(livevars.bd[b].liveout, i)) {
 327             start[vgrf] = MIN2(start[vgrf], cfg.blocks[b]->end_ip);
 328             end[vgrf] = MAX2(end[vgrf], cfg.blocks[b]->end_ip);
 329          }
 330       }
 331    }
 332
 333    this->live_intervals_valid = true;
 334 }
 335
 336 bool
 337 fs_visitor::virtual_grf_interferes(int a, int b)
 338 {
 339    return !(virtual_grf_end[a] <= virtual_grf_start[b] ||
 340             virtual_grf_end[b] <= virtual_grf_start[a]);
 341 }