i965: Move the old live interval analysis code next to the new live vars code.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_live_variables.cpp
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "brw_fs_cfg.h"
29 #include "brw_fs_live_variables.h"
30
31 using namespace brw;
32
33 /** @file brw_fs_live_variables.cpp
34 *
35 * Support for computing at the basic block level which variables
36 * (virtual GRFs in our case) are live at entry and exit.
37 *
38 * See Muchnik's Advanced Compiler Design and Implementation, section
39 * 14.1 (p444).
40 */
41
42 /**
43 * Sets up the use[] and def[] arrays.
44 *
45 * The basic-block-level live variable analysis needs to know which
46 * variables get used before they're completely defined, and which
47 * variables are completely defined before they're used.
48 */
49 void
50 fs_live_variables::setup_def_use()
51 {
52 int ip = 0;
53
54 for (int b = 0; b < cfg->num_blocks; b++) {
55 fs_bblock *block = cfg->blocks[b];
56
57 assert(ip == block->start_ip);
58 if (b > 0)
59 assert(cfg->blocks[b - 1]->end_ip == ip - 1);
60
61 for (fs_inst *inst = block->start;
62 inst != block->end->next;
63 inst = (fs_inst *)inst->next) {
64
65 /* Set use[] for this instruction */
66 for (unsigned int i = 0; i < 3; i++) {
67 if (inst->src[i].file == GRF) {
68 int reg = inst->src[i].reg;
69
70 if (!bd[b].def[reg])
71 bd[b].use[reg] = true;
72 }
73 }
74
75 /* Check for unconditional writes to whole registers. These
76 * are the things that screen off preceding definitions of a
77 * variable, and thus qualify for being in def[].
78 */
79 if (inst->dst.file == GRF &&
80 inst->regs_written() == v->virtual_grf_sizes[inst->dst.reg] &&
81 !inst->predicated &&
82 !inst->force_uncompressed &&
83 !inst->force_sechalf) {
84 int reg = inst->dst.reg;
85 if (!bd[b].use[reg])
86 bd[b].def[reg] = true;
87 }
88
89 ip++;
90 }
91 }
92 }
93
94 /**
95 * The algorithm incrementally sets bits in liveout and livein,
96 * propagating it through control flow. It will eventually terminate
97 * because it only ever adds bits, and stops when no bits are added in
98 * a pass.
99 */
100 void
101 fs_live_variables::compute_live_variables()
102 {
103 bool cont = true;
104
105 while (cont) {
106 cont = false;
107
108 for (int b = 0; b < cfg->num_blocks; b++) {
109 /* Update livein */
110 for (int i = 0; i < num_vars; i++) {
111 if (bd[b].use[i] || (bd[b].liveout[i] && !bd[b].def[i])) {
112 if (!bd[b].livein[i]) {
113 bd[b].livein[i] = true;
114 cont = true;
115 }
116 }
117 }
118
119 /* Update liveout */
120 foreach_list(block_node, &cfg->blocks[b]->children) {
121 fs_bblock_link *link = (fs_bblock_link *)block_node;
122 fs_bblock *block = link->block;
123
124 for (int i = 0; i < num_vars; i++) {
125 if (bd[block->block_num].livein[i] && !bd[b].liveout[i]) {
126 bd[b].liveout[i] = true;
127 cont = true;
128 }
129 }
130 }
131 }
132 }
133 }
134
135 fs_live_variables::fs_live_variables(fs_visitor *v, fs_cfg *cfg)
136 : v(v), cfg(cfg)
137 {
138 mem_ctx = ralloc_context(cfg->mem_ctx);
139
140 num_vars = v->virtual_grf_next;
141 bd = rzalloc_array(mem_ctx, struct block_data, cfg->num_blocks);
142 vars = rzalloc_array(mem_ctx, struct var, num_vars);
143
144 for (int i = 0; i < cfg->num_blocks; i++) {
145 bd[i].def = rzalloc_array(mem_ctx, bool, num_vars);
146 bd[i].use = rzalloc_array(mem_ctx, bool, num_vars);
147 bd[i].livein = rzalloc_array(mem_ctx, bool, num_vars);
148 bd[i].liveout = rzalloc_array(mem_ctx, bool, num_vars);
149 }
150
151 setup_def_use();
152 compute_live_variables();
153 }
154
155 fs_live_variables::~fs_live_variables()
156 {
157 ralloc_free(mem_ctx);
158 }
159
160 #define MAX_INSTRUCTION (1 << 30)
161
162 void
163 fs_visitor::calculate_live_intervals()
164 {
165 int num_vars = this->virtual_grf_next;
166 int *def = ralloc_array(mem_ctx, int, num_vars);
167 int *use = ralloc_array(mem_ctx, int, num_vars);
168 int loop_depth = 0;
169 int loop_start = 0;
170
171 if (this->live_intervals_valid)
172 return;
173
174 for (int i = 0; i < num_vars; i++) {
175 def[i] = MAX_INSTRUCTION;
176 use[i] = -1;
177 }
178
179 int ip = 0;
180 foreach_list(node, &this->instructions) {
181 fs_inst *inst = (fs_inst *)node;
182
183 if (inst->opcode == BRW_OPCODE_DO) {
184 if (loop_depth++ == 0)
185 loop_start = ip;
186 } else if (inst->opcode == BRW_OPCODE_WHILE) {
187 loop_depth--;
188
189 if (loop_depth == 0) {
190 /* Patches up the use of vars marked for being live across
191 * the whole loop.
192 */
193 for (int i = 0; i < num_vars; i++) {
194 if (use[i] == loop_start) {
195 use[i] = ip;
196 }
197 }
198 }
199 } else {
200 for (unsigned int i = 0; i < 3; i++) {
201 if (inst->src[i].file == GRF) {
202 int reg = inst->src[i].reg;
203
204 if (!loop_depth) {
205 use[reg] = ip;
206 } else {
207 def[reg] = MIN2(loop_start, def[reg]);
208 use[reg] = loop_start;
209
210 /* Nobody else is going to go smash our start to
211 * later in the loop now, because def[reg] now
212 * points before the bb header.
213 */
214 }
215 }
216 }
217 if (inst->dst.file == GRF) {
218 int reg = inst->dst.reg;
219
220 if (!loop_depth) {
221 def[reg] = MIN2(def[reg], ip);
222 } else {
223 def[reg] = MIN2(def[reg], loop_start);
224 }
225 }
226 }
227
228 ip++;
229 }
230
231 ralloc_free(this->virtual_grf_def);
232 ralloc_free(this->virtual_grf_use);
233 this->virtual_grf_def = def;
234 this->virtual_grf_use = use;
235
236 this->live_intervals_valid = true;
237 }
238
239 bool
240 fs_visitor::virtual_grf_interferes(int a, int b)
241 {
242 int start = MAX2(this->virtual_grf_def[a], this->virtual_grf_def[b]);
243 int end = MIN2(this->virtual_grf_use[a], this->virtual_grf_use[b]);
244
245 /* We can't handle dead register writes here, without iterating
246 * over the whole instruction stream to find every single dead
247 * write to that register to compare to the live interval of the
248 * other register. Just assert that dead_code_eliminate() has been
249 * called.
250 */
251 assert((this->virtual_grf_use[a] != -1 ||
252 this->virtual_grf_def[a] == MAX_INSTRUCTION) &&
253 (this->virtual_grf_use[b] != -1 ||
254 this->virtual_grf_def[b] == MAX_INSTRUCTION));
255
256 /* If the register is used to store 16 values of less than float
257 * size (only the case for pixel_[xy]), then we can't allocate
258 * another dword-sized thing to that register that would be used in
259 * the same instruction. This is because when the GPU decodes (for
260 * example):
261 *
262 * (declare (in ) vec4 gl_FragCoord@0x97766a0)
263 * add(16) g6<1>F g6<8,8,1>UW 0.5F { align1 compr };
264 *
265 * it's actually processed as:
266 * add(8) g6<1>F g6<8,8,1>UW 0.5F { align1 };
267 * add(8) g7<1>F g6.8<8,8,1>UW 0.5F { align1 sechalf };
268 *
269 * so our second half values in g6 got overwritten in the first
270 * half.
271 */
272 if (c->dispatch_width == 16 && (this->pixel_x.reg == a ||
273 this->pixel_x.reg == b ||
274 this->pixel_y.reg == a ||
275 this->pixel_y.reg == b)) {
276 return start <= end;
277 }
278
279 return start < end;
280 }