2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include "brw_fs_cfg.h"
29 #include "brw_fs_live_variables.h"
33 /** @file brw_fs_live_variables.cpp
35 * Support for computing at the basic block level which variables
36 * (virtual GRFs in our case) are live at entry and exit.
38 * See Muchnik's Advanced Compiler Design and Implementation, section
43 * Sets up the use[] and def[] arrays.
45 * The basic-block-level live variable analysis needs to know which
46 * variables get used before they're completely defined, and which
47 * variables are completely defined before they're used.
50 fs_live_variables::setup_def_use()
54 for (int b
= 0; b
< cfg
->num_blocks
; b
++) {
55 fs_bblock
*block
= cfg
->blocks
[b
];
57 assert(ip
== block
->start_ip
);
59 assert(cfg
->blocks
[b
- 1]->end_ip
== ip
- 1);
61 for (fs_inst
*inst
= block
->start
;
62 inst
!= block
->end
->next
;
63 inst
= (fs_inst
*)inst
->next
) {
65 /* Set use[] for this instruction */
66 for (unsigned int i
= 0; i
< 3; i
++) {
67 if (inst
->src
[i
].file
== GRF
) {
68 int reg
= inst
->src
[i
].reg
;
71 bd
[b
].use
[reg
] = true;
75 /* Check for unconditional writes to whole registers. These
76 * are the things that screen off preceding definitions of a
77 * variable, and thus qualify for being in def[].
79 if (inst
->dst
.file
== GRF
&&
80 inst
->regs_written() == v
->virtual_grf_sizes
[inst
->dst
.reg
] &&
82 !inst
->force_uncompressed
&&
83 !inst
->force_sechalf
) {
84 int reg
= inst
->dst
.reg
;
86 bd
[b
].def
[reg
] = true;
95 * The algorithm incrementally sets bits in liveout and livein,
96 * propagating it through control flow. It will eventually terminate
97 * because it only ever adds bits, and stops when no bits are added in
101 fs_live_variables::compute_live_variables()
108 for (int b
= 0; b
< cfg
->num_blocks
; b
++) {
110 for (int i
= 0; i
< num_vars
; i
++) {
111 if (bd
[b
].use
[i
] || (bd
[b
].liveout
[i
] && !bd
[b
].def
[i
])) {
112 if (!bd
[b
].livein
[i
]) {
113 bd
[b
].livein
[i
] = true;
120 foreach_list(block_node
, &cfg
->blocks
[b
]->children
) {
121 fs_bblock_link
*link
= (fs_bblock_link
*)block_node
;
122 fs_bblock
*block
= link
->block
;
124 for (int i
= 0; i
< num_vars
; i
++) {
125 if (bd
[block
->block_num
].livein
[i
] && !bd
[b
].liveout
[i
]) {
126 bd
[b
].liveout
[i
] = true;
135 fs_live_variables::fs_live_variables(fs_visitor
*v
, fs_cfg
*cfg
)
138 mem_ctx
= ralloc_context(cfg
->mem_ctx
);
140 num_vars
= v
->virtual_grf_next
;
141 bd
= rzalloc_array(mem_ctx
, struct block_data
, cfg
->num_blocks
);
142 vars
= rzalloc_array(mem_ctx
, struct var
, num_vars
);
144 for (int i
= 0; i
< cfg
->num_blocks
; i
++) {
145 bd
[i
].def
= rzalloc_array(mem_ctx
, bool, num_vars
);
146 bd
[i
].use
= rzalloc_array(mem_ctx
, bool, num_vars
);
147 bd
[i
].livein
= rzalloc_array(mem_ctx
, bool, num_vars
);
148 bd
[i
].liveout
= rzalloc_array(mem_ctx
, bool, num_vars
);
152 compute_live_variables();
155 fs_live_variables::~fs_live_variables()
157 ralloc_free(mem_ctx
);
160 #define MAX_INSTRUCTION (1 << 30)
163 fs_visitor::calculate_live_intervals()
165 int num_vars
= this->virtual_grf_next
;
167 if (this->live_intervals_valid
)
170 int *def
= ralloc_array(mem_ctx
, int, num_vars
);
171 int *use
= ralloc_array(mem_ctx
, int, num_vars
);
172 ralloc_free(this->virtual_grf_def
);
173 ralloc_free(this->virtual_grf_use
);
174 this->virtual_grf_def
= def
;
175 this->virtual_grf_use
= use
;
177 for (int i
= 0; i
< num_vars
; i
++) {
178 def
[i
] = MAX_INSTRUCTION
;
182 /* Start by setting up the intervals with no knowledge of control
186 foreach_list(node
, &this->instructions
) {
187 fs_inst
*inst
= (fs_inst
*)node
;
189 for (unsigned int i
= 0; i
< 3; i
++) {
190 if (inst
->src
[i
].file
== GRF
) {
191 int reg
= inst
->src
[i
].reg
;
195 if (inst
->dst
.file
== GRF
) {
196 int reg
= inst
->dst
.reg
;
198 def
[reg
] = MIN2(def
[reg
], ip
);
205 /* Now, extend those intervals using our analysis of control flow. */
207 fs_live_variables
livevars(this, &cfg
);
209 for (int b
= 0; b
< cfg
.num_blocks
; b
++) {
210 for (int i
= 0; i
< num_vars
; i
++) {
211 if (livevars
.bd
[b
].livein
[i
]) {
212 def
[i
] = MIN2(def
[i
], cfg
.blocks
[b
]->start_ip
);
213 use
[i
] = MAX2(use
[i
], cfg
.blocks
[b
]->start_ip
);
216 if (livevars
.bd
[b
].liveout
[i
]) {
217 def
[i
] = MIN2(def
[i
], cfg
.blocks
[b
]->end_ip
);
218 use
[i
] = MAX2(use
[i
], cfg
.blocks
[b
]->end_ip
);
223 this->live_intervals_valid
= true;
227 fs_visitor::virtual_grf_interferes(int a
, int b
)
229 int a_def
= this->virtual_grf_def
[a
], a_use
= this->virtual_grf_use
[a
];
230 int b_def
= this->virtual_grf_def
[b
], b_use
= this->virtual_grf_use
[b
];
232 /* If there's dead code (def but not use), it would break our test
233 * unless we consider it used.
235 if ((a_use
== -1 && a_def
!= MAX_INSTRUCTION
) ||
236 (b_use
== -1 && b_def
!= MAX_INSTRUCTION
)) {
240 int start
= MAX2(a_def
, b_def
);
241 int end
= MIN2(a_use
, b_use
);
243 /* If the register is used to store 16 values of less than float
244 * size (only the case for pixel_[xy]), then we can't allocate
245 * another dword-sized thing to that register that would be used in
246 * the same instruction. This is because when the GPU decodes (for
249 * (declare (in ) vec4 gl_FragCoord@0x97766a0)
250 * add(16) g6<1>F g6<8,8,1>UW 0.5F { align1 compr };
252 * it's actually processed as:
253 * add(8) g6<1>F g6<8,8,1>UW 0.5F { align1 };
254 * add(8) g7<1>F g6.8<8,8,1>UW 0.5F { align1 sechalf };
256 * so our second half values in g6 got overwritten in the first
259 if (c
->dispatch_width
== 16 && (this->pixel_x
.reg
== a
||
260 this->pixel_x
.reg
== b
||
261 this->pixel_y
.reg
== a
||
262 this->pixel_y
.reg
== b
)) {