2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 /* get the main function and emit it */
45 nir_foreach_function(function
, nir
) {
46 assert(strcmp(function
->name
, "main") == 0);
47 assert(function
->impl
);
48 nir_emit_impl(function
->impl
);
53 fs_visitor::nir_setup_inputs()
55 if (stage
!= MESA_SHADER_FRAGMENT
)
58 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
60 nir_foreach_variable(var
, &nir
->inputs
) {
61 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
64 if (var
->data
.location
== VARYING_SLOT_POS
) {
65 reg
= *emit_fragcoord_interpolation();
66 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
68 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
69 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
70 reg
.type
= BRW_REGISTER_TYPE_D
;
71 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
72 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
73 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
74 reg
.type
= BRW_REGISTER_TYPE_D
;
75 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
77 int location
= var
->data
.location
;
78 emit_general_interpolation(&input
, var
->name
, var
->type
,
79 (glsl_interp_qualifier
) var
->data
.interpolation
,
80 &location
, var
->data
.centroid
,
87 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
88 const glsl_type
*type
,
91 if (type
->is_array() || type
->is_matrix()) {
92 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
93 const unsigned length
= glsl_get_length(type
);
95 for (unsigned i
= 0; i
< length
; i
++) {
96 nir_setup_single_output_varying(reg
, elem_type
, location
);
98 } else if (type
->is_record()) {
99 for (unsigned i
= 0; i
< type
->length
; i
++) {
100 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
101 nir_setup_single_output_varying(reg
, field_type
, location
);
104 assert(type
->is_scalar() || type
->is_vector());
105 unsigned num_elements
= type
->vector_elements
;
106 if (type
->is_double())
108 for (unsigned count
= 0; count
< num_elements
; count
+= 4) {
109 this->outputs
[*location
] = *reg
;
110 this->output_components
[*location
] = MIN2(4, num_elements
- count
);
111 *reg
= offset(*reg
, bld
, this->output_components
[*location
]);
118 fs_visitor::nir_setup_outputs()
120 if (stage
== MESA_SHADER_TESS_CTRL
)
123 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
125 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
127 nir_foreach_variable(var
, &nir
->outputs
) {
128 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
131 case MESA_SHADER_VERTEX
:
132 case MESA_SHADER_TESS_EVAL
:
133 case MESA_SHADER_GEOMETRY
: {
134 unsigned location
= var
->data
.location
;
135 nir_setup_single_output_varying(®
, var
->type
, &location
);
138 case MESA_SHADER_FRAGMENT
:
139 if (key
->force_dual_color_blend
&&
140 var
->data
.location
== FRAG_RESULT_DATA1
) {
141 this->dual_src_output
= reg
;
142 this->do_dual_src
= true;
143 } else if (var
->data
.index
> 0) {
144 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
145 assert(var
->data
.index
== 1);
146 this->dual_src_output
= reg
;
147 this->do_dual_src
= true;
148 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
149 /* Writing gl_FragColor outputs to all color regions. */
150 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
151 this->outputs
[i
] = reg
;
152 this->output_components
[i
] = 4;
154 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
155 this->frag_depth
= reg
;
156 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
157 this->frag_stencil
= reg
;
158 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
159 this->sample_mask
= reg
;
161 int vector_elements
= var
->type
->without_array()->vector_elements
;
163 /* gl_FragData or a user-defined FS output */
164 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
165 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
167 /* General color output. */
168 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
169 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
170 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
171 this->output_components
[output
] = vector_elements
;
176 unreachable("unhandled shader stage");
182 fs_visitor::nir_setup_uniforms()
184 if (dispatch_width
!= min_dispatch_width
)
187 uniforms
= nir
->num_uniforms
/ 4;
191 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
195 nir_foreach_instr(instr
, block
) {
196 if (instr
->type
!= nir_instr_type_intrinsic
)
199 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
200 switch (intrin
->intrinsic
) {
201 case nir_intrinsic_load_vertex_id
:
202 unreachable("should be lowered by lower_vertex_id().");
204 case nir_intrinsic_load_vertex_id_zero_base
:
205 assert(v
->stage
== MESA_SHADER_VERTEX
);
206 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
207 if (reg
->file
== BAD_FILE
)
208 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
211 case nir_intrinsic_load_base_vertex
:
212 assert(v
->stage
== MESA_SHADER_VERTEX
);
213 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
214 if (reg
->file
== BAD_FILE
)
215 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
218 case nir_intrinsic_load_instance_id
:
219 assert(v
->stage
== MESA_SHADER_VERTEX
);
220 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
221 if (reg
->file
== BAD_FILE
)
222 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
225 case nir_intrinsic_load_base_instance
:
226 assert(v
->stage
== MESA_SHADER_VERTEX
);
227 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
228 if (reg
->file
== BAD_FILE
)
229 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
232 case nir_intrinsic_load_draw_id
:
233 assert(v
->stage
== MESA_SHADER_VERTEX
);
234 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
235 if (reg
->file
== BAD_FILE
)
236 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
239 case nir_intrinsic_load_invocation_id
:
240 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
242 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
243 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
244 if (reg
->file
== BAD_FILE
) {
245 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
246 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
247 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
248 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
253 case nir_intrinsic_load_sample_pos
:
254 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
255 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
256 if (reg
->file
== BAD_FILE
)
257 *reg
= *v
->emit_samplepos_setup();
260 case nir_intrinsic_load_sample_id
:
261 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
262 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
263 if (reg
->file
== BAD_FILE
)
264 *reg
= *v
->emit_sampleid_setup();
267 case nir_intrinsic_load_sample_mask_in
:
268 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
269 assert(v
->devinfo
->gen
>= 7);
270 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
271 if (reg
->file
== BAD_FILE
)
272 *reg
= *v
->emit_samplemaskin_setup();
275 case nir_intrinsic_load_work_group_id
:
276 assert(v
->stage
== MESA_SHADER_COMPUTE
);
277 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
278 if (reg
->file
== BAD_FILE
)
279 *reg
= *v
->emit_cs_work_group_id_setup();
282 case nir_intrinsic_load_helper_invocation
:
283 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
284 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
285 if (reg
->file
== BAD_FILE
) {
286 const fs_builder abld
=
287 v
->bld
.annotate("gl_HelperInvocation", NULL
);
289 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
290 * pixel mask is in g1.7 of the thread payload.
292 * We move the per-channel pixel enable bit to the low bit of each
293 * channel by shifting the byte containing the pixel mask by the
294 * vector immediate 0x76543210UV.
296 * The region of <1,8,0> reads only 1 byte (the pixel masks for
297 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
298 * masks for 2 and 3) in SIMD16.
300 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
302 stride(byte_offset(retype(brw_vec1_grf(1, 0),
303 BRW_REGISTER_TYPE_UB
), 28),
305 brw_imm_v(0x76543210));
307 /* A set bit in the pixel mask means the channel is enabled, but
308 * that is the opposite of gl_HelperInvocation so we need to invert
311 * The negate source-modifier bit of logical instructions on Gen8+
312 * performs 1's complement negation, so we can use that instead of
315 fs_reg inverted
= negate(shifted
);
316 if (v
->devinfo
->gen
< 8) {
317 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
318 abld
.NOT(inverted
, shifted
);
321 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
322 * with 1 and negating.
324 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
325 abld
.AND(anded
, inverted
, brw_imm_uw(1));
327 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
328 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
342 fs_visitor::nir_emit_system_values()
344 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
345 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
346 nir_system_values
[i
] = fs_reg();
349 nir_foreach_function(function
, nir
) {
350 assert(strcmp(function
->name
, "main") == 0);
351 assert(function
->impl
);
352 nir_foreach_block(block
, function
->impl
) {
353 emit_system_values_block(block
, this);
359 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
361 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
362 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
363 nir_locals
[i
] = fs_reg();
366 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
367 unsigned array_elems
=
368 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
369 unsigned size
= array_elems
* reg
->num_components
;
370 const brw_reg_type reg_type
=
371 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
372 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
375 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
378 nir_emit_cf_list(&impl
->body
);
382 fs_visitor::nir_emit_cf_list(exec_list
*list
)
384 exec_list_validate(list
);
385 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
386 switch (node
->type
) {
388 nir_emit_if(nir_cf_node_as_if(node
));
391 case nir_cf_node_loop
:
392 nir_emit_loop(nir_cf_node_as_loop(node
));
395 case nir_cf_node_block
:
396 nir_emit_block(nir_cf_node_as_block(node
));
400 unreachable("Invalid CFG node block");
406 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
408 /* first, put the condition into f0 */
409 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
410 retype(get_nir_src(if_stmt
->condition
),
411 BRW_REGISTER_TYPE_D
));
412 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
414 bld
.IF(BRW_PREDICATE_NORMAL
);
416 nir_emit_cf_list(&if_stmt
->then_list
);
418 /* note: if the else is empty, dead CF elimination will remove it */
419 bld
.emit(BRW_OPCODE_ELSE
);
421 nir_emit_cf_list(&if_stmt
->else_list
);
423 bld
.emit(BRW_OPCODE_ENDIF
);
427 fs_visitor::nir_emit_loop(nir_loop
*loop
)
429 bld
.emit(BRW_OPCODE_DO
);
431 nir_emit_cf_list(&loop
->body
);
433 bld
.emit(BRW_OPCODE_WHILE
);
437 fs_visitor::nir_emit_block(nir_block
*block
)
439 nir_foreach_instr(instr
, block
) {
440 nir_emit_instr(instr
);
445 fs_visitor::nir_emit_instr(nir_instr
*instr
)
447 const fs_builder abld
= bld
.annotate(NULL
, instr
);
449 switch (instr
->type
) {
450 case nir_instr_type_alu
:
451 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
454 case nir_instr_type_intrinsic
:
456 case MESA_SHADER_VERTEX
:
457 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
459 case MESA_SHADER_TESS_CTRL
:
460 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
462 case MESA_SHADER_TESS_EVAL
:
463 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 case MESA_SHADER_GEOMETRY
:
466 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_FRAGMENT
:
469 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
471 case MESA_SHADER_COMPUTE
:
472 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
475 unreachable("unsupported shader stage");
479 case nir_instr_type_tex
:
480 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
483 case nir_instr_type_load_const
:
484 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
487 case nir_instr_type_ssa_undef
:
488 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
491 case nir_instr_type_jump
:
492 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
496 unreachable("unknown instruction type");
501 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
505 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
506 const fs_reg
&result
)
508 if (!instr
->src
[0].src
.is_ssa
||
509 !instr
->src
[0].src
.ssa
->parent_instr
)
512 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
515 nir_alu_instr
*src0
=
516 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
518 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
519 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
522 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
523 assert(element
!= NULL
);
525 /* Element type to extract.*/
526 const brw_reg_type type
= brw_int_type(
527 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
528 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
530 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
531 op0
.type
= brw_type_for_nir_type(
532 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
533 nir_src_bit_size(src0
->src
[0].src
)));
534 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
536 set_saturate(instr
->dest
.saturate
,
537 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
542 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
543 const fs_reg
&result
)
545 if (!instr
->src
[0].src
.is_ssa
||
546 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
549 nir_intrinsic_instr
*src0
=
550 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
552 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
555 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
556 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
559 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
560 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
563 fs_reg tmp
= vgrf(glsl_type::int_type
);
565 if (devinfo
->gen
>= 6) {
566 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
567 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
569 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
571 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
572 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
574 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
576 * This negation looks like it's safe in practice, because bits 0:4 will
577 * surely be TRIANGLES
580 if (value1
->f32
[0] == -1.0f
) {
584 tmp
.type
= BRW_REGISTER_TYPE_W
;
585 tmp
.subreg_offset
= 2;
588 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
590 tmp
.type
= BRW_REGISTER_TYPE_D
;
591 tmp
.subreg_offset
= 0;
594 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
595 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
597 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
599 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
600 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
602 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
604 * This negation looks like it's safe in practice, because bits 0:4 will
605 * surely be TRIANGLES
608 if (value1
->f32
[0] == -1.0f
) {
612 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
614 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
620 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
622 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
625 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
626 result
.type
= brw_type_for_nir_type(
627 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
628 nir_dest_bit_size(instr
->dest
.dest
)));
631 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
632 op
[i
] = get_nir_src(instr
->src
[i
].src
);
633 op
[i
].type
= brw_type_for_nir_type(
634 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
635 nir_src_bit_size(instr
->src
[i
].src
)));
636 op
[i
].abs
= instr
->src
[i
].abs
;
637 op
[i
].negate
= instr
->src
[i
].negate
;
640 /* We get a bunch of mov's out of the from_ssa pass and they may still
641 * be vectorized. We'll handle them as a special-case. We'll also
642 * handle vecN here because it's basically the same thing.
650 fs_reg temp
= result
;
651 bool need_extra_copy
= false;
652 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
653 if (!instr
->src
[i
].src
.is_ssa
&&
654 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
655 need_extra_copy
= true;
656 temp
= bld
.vgrf(result
.type
, 4);
661 for (unsigned i
= 0; i
< 4; i
++) {
662 if (!(instr
->dest
.write_mask
& (1 << i
)))
665 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
666 inst
= bld
.MOV(offset(temp
, bld
, i
),
667 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
669 inst
= bld
.MOV(offset(temp
, bld
, i
),
670 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
672 inst
->saturate
= instr
->dest
.saturate
;
675 /* In this case the source and destination registers were the same,
676 * so we need to insert an extra set of moves in order to deal with
679 if (need_extra_copy
) {
680 for (unsigned i
= 0; i
< 4; i
++) {
681 if (!(instr
->dest
.write_mask
& (1 << i
)))
684 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
693 /* At this point, we have dealt with any instruction that operates on
694 * more than a single channel. Therefore, we can just adjust the source
695 * and destination registers for that channel and emit the instruction.
697 unsigned channel
= 0;
698 if (nir_op_infos
[instr
->op
].output_size
== 0) {
699 /* Since NIR is doing the scalarizing for us, we should only ever see
700 * vectorized operations with a single channel.
702 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
703 channel
= ffs(instr
->dest
.write_mask
) - 1;
705 result
= offset(result
, bld
, channel
);
708 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
709 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
710 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
716 if (optimize_extract_to_float(instr
, result
))
718 inst
= bld
.MOV(result
, op
[0]);
719 inst
->saturate
= instr
->dest
.saturate
;
725 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
727 * "When source or destination is 64b (...), regioning in Align1
728 * must follow these rules:
730 * 1. Source and destination horizontal stride must be aligned to
734 * This means that 32-bit to 64-bit conversions need to have the 32-bit
735 * data elements aligned to 64-bit. This restriction does not apply to
738 if (devinfo
->is_cherryview
|| devinfo
->is_broxton
) {
739 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
740 tmp
= subscript(tmp
, op
[0].type
, 0);
741 inst
= bld
.MOV(tmp
, op
[0]);
742 inst
= bld
.MOV(result
, tmp
);
743 inst
->saturate
= instr
->dest
.saturate
;
750 inst
= bld
.MOV(result
, op
[0]);
751 inst
->saturate
= instr
->dest
.saturate
;
756 bld
.MOV(result
, op
[0]);
760 if (type_sz(op
[0].type
) < 8) {
761 /* AND(val, 0x80000000) gives the sign bit.
763 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
766 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
768 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
769 op
[0].type
= BRW_REGISTER_TYPE_UD
;
770 result
.type
= BRW_REGISTER_TYPE_UD
;
771 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
773 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
774 inst
->predicate
= BRW_PREDICATE_NORMAL
;
775 if (instr
->dest
.saturate
) {
776 inst
= bld
.MOV(result
, result
);
777 inst
->saturate
= true;
780 /* For doubles we do the same but we need to consider:
782 * - 2-src instructions can't operate with 64-bit immediates
783 * - The sign is encoded in the high 32-bit of each DF
784 * - CMP with DF requires special handling in SIMD16
785 * - We need to produce a DF result.
788 /* 2-src instructions can't have 64-bit immediates, so put 0.0 in
789 * a register and compare with that.
791 fs_reg tmp
= vgrf(glsl_type::double_type
);
792 bld
.MOV(tmp
, setup_imm_df(bld
, 0.0));
794 /* A direct DF CMP using the flag register (null dst) won't work in
795 * SIMD16 because the CMP will be split in two by lower_simd_width,
796 * resulting in two CMP instructions with the same dst (NULL),
797 * leading to dead code elimination of the first one. In SIMD8,
798 * however, there is no need to split the CMP and we can save some
801 fs_reg dst_tmp
= vgrf(glsl_type::double_type
);
802 bld
.CMP(dst_tmp
, op
[0], tmp
, BRW_CONDITIONAL_NZ
);
804 /* In SIMD16 we want to avoid using a NULL dst register with DF CMP,
805 * so we store the result of the comparison in a vgrf instead and
806 * then we generate a UD comparison from that that won't have to
807 * be split by lower_simd_width. This is what NIR does to handle
808 * double comparisons in the general case.
810 if (bld
.dispatch_width() == 16 ) {
811 fs_reg dst_tmp_ud
= retype(dst_tmp
, BRW_REGISTER_TYPE_UD
);
812 bld
.MOV(dst_tmp_ud
, subscript(dst_tmp
, BRW_REGISTER_TYPE_UD
, 0));
813 bld
.CMP(bld
.null_reg_ud(),
814 dst_tmp_ud
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
817 /* Get the high 32-bit of each double component where the sign is */
818 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
819 bld
.MOV(result_int
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
821 /* Get the sign bit */
822 bld
.AND(result_int
, result_int
, brw_imm_ud(0x80000000u
));
824 /* Add 1.0 to the sign, predicated to skip the case of op[0] == 0.0 */
825 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
826 inst
->predicate
= BRW_PREDICATE_NORMAL
;
828 /* Convert from 32-bit float to 64-bit double */
829 result
.type
= BRW_REGISTER_TYPE_DF
;
830 inst
= bld
.MOV(result
, retype(result_int
, BRW_REGISTER_TYPE_F
));
832 if (instr
->dest
.saturate
) {
833 inst
= bld
.MOV(result
, result
);
834 inst
->saturate
= true;
841 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
842 * -> non-negative val generates 0x00000000.
843 * Predicated OR sets 1 if val is positive.
845 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
846 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
847 bld
.ASR(result
, op
[0], brw_imm_d(31));
848 inst
= bld
.OR(result
, result
, brw_imm_d(1));
849 inst
->predicate
= BRW_PREDICATE_NORMAL
;
853 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
854 inst
->saturate
= instr
->dest
.saturate
;
858 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
859 inst
->saturate
= instr
->dest
.saturate
;
863 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
864 inst
->saturate
= instr
->dest
.saturate
;
868 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
869 inst
->saturate
= instr
->dest
.saturate
;
873 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
874 inst
->saturate
= instr
->dest
.saturate
;
878 if (fs_key
->high_quality_derivatives
) {
879 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
881 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
883 inst
->saturate
= instr
->dest
.saturate
;
885 case nir_op_fddx_fine
:
886 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
887 inst
->saturate
= instr
->dest
.saturate
;
889 case nir_op_fddx_coarse
:
890 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
891 inst
->saturate
= instr
->dest
.saturate
;
894 if (fs_key
->high_quality_derivatives
) {
895 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
897 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
899 inst
->saturate
= instr
->dest
.saturate
;
901 case nir_op_fddy_fine
:
902 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
903 inst
->saturate
= instr
->dest
.saturate
;
905 case nir_op_fddy_coarse
:
906 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
907 inst
->saturate
= instr
->dest
.saturate
;
911 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
913 inst
= bld
.ADD(result
, op
[0], op
[1]);
914 inst
->saturate
= instr
->dest
.saturate
;
918 inst
= bld
.MUL(result
, op
[0], op
[1]);
919 inst
->saturate
= instr
->dest
.saturate
;
923 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
924 bld
.MUL(result
, op
[0], op
[1]);
927 case nir_op_imul_high
:
928 case nir_op_umul_high
:
929 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
930 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
935 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
936 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
939 case nir_op_uadd_carry
:
940 unreachable("Should have been lowered by carry_to_arith().");
942 case nir_op_usub_borrow
:
943 unreachable("Should have been lowered by borrow_to_arith().");
947 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
948 * appears that our hardware just does the right thing for signed
951 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
952 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
956 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
957 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
959 /* Math instructions don't support conditional mod */
960 inst
= bld
.MOV(bld
.null_reg_d(), result
);
961 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
963 /* Now, we need to determine if signs of the sources are different.
964 * When we XOR the sources, the top bit is 0 if they are the same and 1
965 * if they are different. We can then use a conditional modifier to
966 * turn that into a predicate. This leads us to an XOR.l instruction.
968 * Technically, according to the PRM, you're not allowed to use .l on a
969 * XOR instruction. However, emperical experiments and Curro's reading
970 * of the simulator source both indicate that it's safe.
972 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
973 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
974 inst
->predicate
= BRW_PREDICATE_NORMAL
;
975 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
977 /* If the result of the initial remainder operation is non-zero and the
978 * two sources have different signs, add in a copy of op[1] to get the
979 * final integer modulus value.
981 inst
= bld
.ADD(result
, result
, op
[1]);
982 inst
->predicate
= BRW_PREDICATE_NORMAL
;
990 fs_reg dest
= result
;
991 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
992 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
994 brw_conditional_mod cond
;
997 cond
= BRW_CONDITIONAL_L
;
1000 cond
= BRW_CONDITIONAL_GE
;
1003 cond
= BRW_CONDITIONAL_Z
;
1006 cond
= BRW_CONDITIONAL_NZ
;
1009 unreachable("bad opcode");
1011 bld
.CMP(dest
, op
[0], op
[1], cond
);
1012 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1013 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1020 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1021 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1026 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1027 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1031 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1032 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
1036 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1037 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
1041 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1042 if (devinfo
->gen
>= 8) {
1043 op
[0] = resolve_source_modifiers(op
[0]);
1045 bld
.NOT(result
, op
[0]);
1048 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1049 if (devinfo
->gen
>= 8) {
1050 op
[0] = resolve_source_modifiers(op
[0]);
1051 op
[1] = resolve_source_modifiers(op
[1]);
1053 bld
.XOR(result
, op
[0], op
[1]);
1056 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1057 if (devinfo
->gen
>= 8) {
1058 op
[0] = resolve_source_modifiers(op
[0]);
1059 op
[1] = resolve_source_modifiers(op
[1]);
1061 bld
.OR(result
, op
[0], op
[1]);
1064 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1065 if (devinfo
->gen
>= 8) {
1066 op
[0] = resolve_source_modifiers(op
[0]);
1067 op
[1] = resolve_source_modifiers(op
[1]);
1069 bld
.AND(result
, op
[0], op
[1]);
1075 case nir_op_ball_fequal2
:
1076 case nir_op_ball_iequal2
:
1077 case nir_op_ball_fequal3
:
1078 case nir_op_ball_iequal3
:
1079 case nir_op_ball_fequal4
:
1080 case nir_op_ball_iequal4
:
1081 case nir_op_bany_fnequal2
:
1082 case nir_op_bany_inequal2
:
1083 case nir_op_bany_fnequal3
:
1084 case nir_op_bany_inequal3
:
1085 case nir_op_bany_fnequal4
:
1086 case nir_op_bany_inequal4
:
1087 unreachable("Lowered by nir_lower_alu_reductions");
1089 case nir_op_fnoise1_1
:
1090 case nir_op_fnoise1_2
:
1091 case nir_op_fnoise1_3
:
1092 case nir_op_fnoise1_4
:
1093 case nir_op_fnoise2_1
:
1094 case nir_op_fnoise2_2
:
1095 case nir_op_fnoise2_3
:
1096 case nir_op_fnoise2_4
:
1097 case nir_op_fnoise3_1
:
1098 case nir_op_fnoise3_2
:
1099 case nir_op_fnoise3_3
:
1100 case nir_op_fnoise3_4
:
1101 case nir_op_fnoise4_1
:
1102 case nir_op_fnoise4_2
:
1103 case nir_op_fnoise4_3
:
1104 case nir_op_fnoise4_4
:
1105 unreachable("not reached: should be handled by lower_noise");
1108 unreachable("not reached: should be handled by ldexp_to_arith()");
1111 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1112 inst
->saturate
= instr
->dest
.saturate
;
1116 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1117 inst
->saturate
= instr
->dest
.saturate
;
1122 bld
.MOV(result
, negate(op
[0]));
1126 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1129 /* two-argument instructions can't take 64-bit immediates */
1130 fs_reg zero
= vgrf(glsl_type::double_type
);
1131 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1132 /* A SIMD16 execution needs to be split in two instructions, so use
1133 * a vgrf instead of the flag register as dst so instruction splitting
1136 fs_reg tmp
= vgrf(glsl_type::double_type
);
1137 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1138 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1142 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1146 inst
= bld
.RNDZ(result
, op
[0]);
1147 inst
->saturate
= instr
->dest
.saturate
;
1150 case nir_op_fceil
: {
1151 op
[0].negate
= !op
[0].negate
;
1152 fs_reg temp
= vgrf(glsl_type::float_type
);
1153 bld
.RNDD(temp
, op
[0]);
1155 inst
= bld
.MOV(result
, temp
);
1156 inst
->saturate
= instr
->dest
.saturate
;
1160 inst
= bld
.RNDD(result
, op
[0]);
1161 inst
->saturate
= instr
->dest
.saturate
;
1164 inst
= bld
.FRC(result
, op
[0]);
1165 inst
->saturate
= instr
->dest
.saturate
;
1167 case nir_op_fround_even
:
1168 inst
= bld
.RNDE(result
, op
[0]);
1169 inst
->saturate
= instr
->dest
.saturate
;
1172 case nir_op_fquantize2f16
: {
1173 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1174 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1175 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1177 /* The destination stride must be at least as big as the source stride. */
1178 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1181 /* Check for denormal */
1182 fs_reg abs_src0
= op
[0];
1183 abs_src0
.abs
= true;
1184 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1186 /* Get the appropriately signed zero */
1187 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1188 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1189 brw_imm_ud(0x80000000));
1190 /* Do the actual F32 -> F16 -> F32 conversion */
1191 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1192 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1193 /* Select that or zero based on normal status */
1194 inst
= bld
.SEL(result
, zero
, tmp32
);
1195 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1196 inst
->saturate
= instr
->dest
.saturate
;
1202 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1204 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1205 inst
->saturate
= instr
->dest
.saturate
;
1210 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1212 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1213 inst
->saturate
= instr
->dest
.saturate
;
1216 case nir_op_pack_snorm_2x16
:
1217 case nir_op_pack_snorm_4x8
:
1218 case nir_op_pack_unorm_2x16
:
1219 case nir_op_pack_unorm_4x8
:
1220 case nir_op_unpack_snorm_2x16
:
1221 case nir_op_unpack_snorm_4x8
:
1222 case nir_op_unpack_unorm_2x16
:
1223 case nir_op_unpack_unorm_4x8
:
1224 case nir_op_unpack_half_2x16
:
1225 case nir_op_pack_half_2x16
:
1226 unreachable("not reached: should be handled by lower_packing_builtins");
1228 case nir_op_unpack_half_2x16_split_x
:
1229 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1230 inst
->saturate
= instr
->dest
.saturate
;
1232 case nir_op_unpack_half_2x16_split_y
:
1233 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1234 inst
->saturate
= instr
->dest
.saturate
;
1237 case nir_op_pack_double_2x32_split
:
1238 /* Optimize the common case where we are re-packing a double with
1239 * the result of a previous double unpack. In this case we can take the
1240 * 32-bit value to use in the re-pack from the original double and bypass
1241 * the unpack operation.
1243 for (int i
= 0; i
< 2; i
++) {
1244 if (instr
->src
[i
].src
.is_ssa
)
1247 const nir_instr
*parent_instr
= instr
->src
[i
].src
.ssa
->parent_instr
;
1248 if (parent_instr
->type
== nir_instr_type_alu
)
1251 const nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1252 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_x
||
1253 alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1256 if (!alu_parent
->src
[0].src
.is_ssa
)
1259 op
[i
] = get_nir_src(alu_parent
->src
[0].src
);
1260 op
[i
] = offset(retype(op
[i
], BRW_REGISTER_TYPE_DF
), bld
,
1261 alu_parent
->src
[0].swizzle
[channel
]);
1262 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1263 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 1);
1265 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 0);
1267 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1270 case nir_op_unpack_double_2x32_split_x
:
1271 case nir_op_unpack_double_2x32_split_y
: {
1272 /* Optimize the common case where we are unpacking from a double we have
1273 * previously packed. In this case we can just bypass the pack operation
1274 * and source directly from its arguments.
1276 unsigned index
= (instr
->op
== nir_op_unpack_double_2x32_split_x
) ? 0 : 1;
1277 if (instr
->src
[0].src
.is_ssa
) {
1278 nir_instr
*parent_instr
= instr
->src
[0].src
.ssa
->parent_instr
;
1279 if (parent_instr
->type
== nir_instr_type_alu
) {
1280 nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1281 if (alu_parent
->op
== nir_op_pack_double_2x32_split
&&
1282 alu_parent
->src
[index
].src
.is_ssa
) {
1283 op
[0] = retype(get_nir_src(alu_parent
->src
[index
].src
),
1284 BRW_REGISTER_TYPE_UD
);
1286 offset(op
[0], bld
, alu_parent
->src
[index
].swizzle
[channel
]);
1287 bld
.MOV(result
, op
[0]);
1293 if (instr
->op
== nir_op_unpack_double_2x32_split_x
)
1294 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1296 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1301 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1302 inst
->saturate
= instr
->dest
.saturate
;
1305 case nir_op_bitfield_reverse
:
1306 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1307 bld
.BFREV(result
, op
[0]);
1310 case nir_op_bit_count
:
1311 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1312 bld
.CBIT(result
, op
[0]);
1315 case nir_op_ufind_msb
:
1316 case nir_op_ifind_msb
: {
1317 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1318 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1320 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1321 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1322 * subtract the result from 31 to convert the MSB count into an LSB count.
1324 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1326 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1327 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1328 inst
->src
[0].negate
= true;
1332 case nir_op_find_lsb
:
1333 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1334 bld
.FBL(result
, op
[0]);
1337 case nir_op_ubitfield_extract
:
1338 case nir_op_ibitfield_extract
:
1339 unreachable("should have been lowered");
1342 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1343 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1346 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1347 bld
.BFI1(result
, op
[0], op
[1]);
1350 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1351 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1354 case nir_op_bitfield_insert
:
1355 unreachable("not reached: should have been lowered");
1358 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1359 bld
.SHL(result
, op
[0], op
[1]);
1362 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1363 bld
.ASR(result
, op
[0], op
[1]);
1366 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1367 bld
.SHR(result
, op
[0], op
[1]);
1370 case nir_op_pack_half_2x16_split
:
1371 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1375 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1376 inst
->saturate
= instr
->dest
.saturate
;
1380 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1381 inst
->saturate
= instr
->dest
.saturate
;
1385 if (optimize_frontfacing_ternary(instr
, result
))
1388 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1389 inst
= bld
.SEL(result
, op
[1], op
[2]);
1390 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1393 case nir_op_extract_u8
:
1394 case nir_op_extract_i8
: {
1395 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1396 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1397 assert(byte
!= NULL
);
1398 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1402 case nir_op_extract_u16
:
1403 case nir_op_extract_i16
: {
1404 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1405 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1406 assert(word
!= NULL
);
1407 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1412 unreachable("unhandled instruction");
1415 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1416 * to sign extend the low bit to 0/~0
1418 if (devinfo
->gen
<= 5 &&
1419 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1420 fs_reg masked
= vgrf(glsl_type::int_type
);
1421 bld
.AND(masked
, result
, brw_imm_d(1));
1422 masked
.negate
= true;
1423 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1428 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1429 nir_load_const_instr
*instr
)
1431 const brw_reg_type reg_type
=
1432 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1433 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1435 switch (instr
->def
.bit_size
) {
1437 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1438 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1442 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1443 bld
.MOV(offset(reg
, bld
, i
),
1444 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1448 unreachable("Invalid bit size");
1451 nir_ssa_values
[instr
->def
.index
] = reg
;
1455 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1457 const brw_reg_type reg_type
=
1458 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1459 nir_ssa_values
[instr
->def
.index
] =
1460 bld
.vgrf(reg_type
, instr
->def
.num_components
);
1464 fs_visitor::get_nir_src(const nir_src
&src
)
1468 reg
= nir_ssa_values
[src
.ssa
->index
];
1470 /* We don't handle indirects on locals */
1471 assert(src
.reg
.indirect
== NULL
);
1472 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1473 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1476 /* to avoid floating-point denorm flushing problems, set the type by
1477 * default to D - instructions that need floating point semantics will set
1478 * this to F if they need to
1480 return retype(reg
, BRW_REGISTER_TYPE_D
);
1484 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1487 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1489 nir_const_value
*val
= nir_src_as_const_value(src
);
1490 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1494 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1497 const brw_reg_type reg_type
=
1498 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1499 nir_ssa_values
[dest
.ssa
.index
] =
1500 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1501 return nir_ssa_values
[dest
.ssa
.index
];
1503 /* We don't handle indirects on locals */
1504 assert(dest
.reg
.indirect
== NULL
);
1505 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1506 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1511 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1513 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1514 BRW_REGISTER_TYPE_UD
);
1516 unsigned indirect_max
= 0;
1518 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1519 tail
= tail
->child
) {
1520 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1521 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1522 const unsigned size
= glsl_get_length(tail
->type
);
1523 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1524 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1525 image
= offset(image
, bld
, base
* element_size
);
1527 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1528 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1530 /* Accessing an invalid surface index with the dataport can result
1531 * in a hang. According to the spec "if the index used to
1532 * select an individual element is negative or greater than or
1533 * equal to the size of the array, the results of the operation
1534 * are undefined but may not lead to termination" -- which is one
1535 * of the possible outcomes of the hang. Clamp the index to
1536 * prevent access outside of the array bounds.
1538 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1539 BRW_REGISTER_TYPE_UD
),
1540 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1542 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1544 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1545 if (indirect
.file
== BAD_FILE
) {
1548 bld
.ADD(indirect
, indirect
, tmp
);
1553 if (indirect
.file
== BAD_FILE
) {
1556 /* Emit a pile of MOVs to load the uniform into a temporary. The
1557 * dead-code elimination pass will get rid of what we don't use.
1559 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1560 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1561 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1562 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1563 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1570 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1573 for (unsigned i
= 0; i
< 4; i
++) {
1574 if (!((wr_mask
>> i
) & 1))
1577 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1578 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1579 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1580 if (new_inst
->src
[j
].file
== VGRF
)
1581 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1588 * Get the matching channel register datatype for an image intrinsic of the
1589 * specified GLSL image type.
1592 get_image_base_type(const glsl_type
*type
)
1594 switch ((glsl_base_type
)type
->sampled_type
) {
1595 case GLSL_TYPE_UINT
:
1596 return BRW_REGISTER_TYPE_UD
;
1598 return BRW_REGISTER_TYPE_D
;
1599 case GLSL_TYPE_FLOAT
:
1600 return BRW_REGISTER_TYPE_F
;
1602 unreachable("Not reached.");
1607 * Get the appropriate atomic op for an image atomic intrinsic.
1610 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1613 case nir_intrinsic_image_atomic_add
:
1615 case nir_intrinsic_image_atomic_min
:
1616 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1617 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1618 case nir_intrinsic_image_atomic_max
:
1619 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1620 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1621 case nir_intrinsic_image_atomic_and
:
1623 case nir_intrinsic_image_atomic_or
:
1625 case nir_intrinsic_image_atomic_xor
:
1627 case nir_intrinsic_image_atomic_exchange
:
1629 case nir_intrinsic_image_atomic_comp_swap
:
1630 return BRW_AOP_CMPWR
;
1632 unreachable("Not reachable.");
1637 emit_pixel_interpolater_send(const fs_builder
&bld
,
1642 glsl_interp_qualifier interpolation
)
1648 if (src
.file
== BAD_FILE
) {
1650 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1654 mlen
= 2 * bld
.dispatch_width() / 8;
1657 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1659 /* 2 floats per slot returned */
1660 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1661 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1667 * Computes 1 << x, given a D/UD register containing some value x.
1670 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1672 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1674 fs_reg result
= bld
.vgrf(x
.type
, 1);
1675 fs_reg one
= bld
.vgrf(x
.type
, 1);
1677 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1678 bld
.SHL(result
, one
, x
);
1683 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1685 assert(stage
== MESA_SHADER_GEOMETRY
);
1687 struct brw_gs_prog_data
*gs_prog_data
=
1688 (struct brw_gs_prog_data
*) prog_data
;
1690 if (gs_compile
->control_data_header_size_bits
== 0)
1693 /* We can only do EndPrimitive() functionality when the control data
1694 * consists of cut bits. Fortunately, the only time it isn't is when the
1695 * output type is points, in which case EndPrimitive() is a no-op.
1697 if (gs_prog_data
->control_data_format
!=
1698 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1702 /* Cut bits use one bit per vertex. */
1703 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1705 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1706 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1708 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1709 * vertex n, 0 otherwise. So all we need to do here is mark bit
1710 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1711 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1712 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1714 * Note that if EndPrimitive() is called before emitting any vertices, this
1715 * will cause us to set bit 31 of the control_data_bits register to 1.
1716 * That's fine because:
1718 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1719 * output, so the hardware will ignore cut bit 31.
1721 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1722 * last vertex, so setting cut bit 31 has no effect (since the primitive
1723 * is automatically ended when the GS terminates).
1725 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1726 * control_data_bits register to 0 when the first vertex is emitted.
1729 const fs_builder abld
= bld
.annotate("end primitive");
1731 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1732 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1733 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1734 fs_reg mask
= intexp2(abld
, prev_count
);
1735 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1736 * attention to the lower 5 bits of its second source argument, so on this
1737 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1738 * ((vertex_count - 1) % 32).
1740 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1744 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1746 assert(stage
== MESA_SHADER_GEOMETRY
);
1747 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1749 struct brw_gs_prog_data
*gs_prog_data
=
1750 (struct brw_gs_prog_data
*) prog_data
;
1752 const fs_builder abld
= bld
.annotate("emit control data bits");
1753 const fs_builder fwa_bld
= bld
.exec_all();
1755 /* We use a single UD register to accumulate control data bits (32 bits
1756 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1759 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1760 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1761 * use the Channel Mask phase to enable/disable which DWord within that
1762 * group to write. (Remember, different SIMD8 channels may have emitted
1763 * different numbers of vertices, so we may need per-slot offsets.)
1765 * Channel masking presents an annoying problem: we may have to replicate
1766 * the data up to 4 times:
1768 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1770 * To avoid penalizing shaders that emit a small number of vertices, we
1771 * can avoid these sometimes: if the size of the control data header is
1772 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1773 * land in the same 128-bit group, so we can skip per-slot offsets.
1775 * Similarly, if the control data header is <= 32 bits, there is only one
1776 * DWord, so we can skip channel masks.
1778 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1780 fs_reg channel_mask
, per_slot_offset
;
1782 if (gs_compile
->control_data_header_size_bits
> 32) {
1783 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1784 channel_mask
= vgrf(glsl_type::uint_type
);
1787 if (gs_compile
->control_data_header_size_bits
> 128) {
1788 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1789 per_slot_offset
= vgrf(glsl_type::uint_type
);
1792 /* Figure out which DWord we're trying to write to using the formula:
1794 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1796 * Since bits_per_vertex is a power of two, and is known at compile
1797 * time, this can be optimized to:
1799 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1801 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1802 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1803 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1804 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1805 unsigned log2_bits_per_vertex
=
1806 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1807 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1809 if (per_slot_offset
.file
!= BAD_FILE
) {
1810 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1811 * the appropriate OWord within the control data header.
1813 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1816 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1817 * write to the appropriate DWORD within the OWORD.
1819 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1820 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1821 channel_mask
= intexp2(fwa_bld
, channel
);
1822 /* Then the channel masks need to be in bits 23:16. */
1823 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1826 /* Store the control data bits in the message payload and send it. */
1828 if (channel_mask
.file
!= BAD_FILE
)
1829 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1830 if (per_slot_offset
.file
!= BAD_FILE
)
1833 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1834 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1836 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1837 if (per_slot_offset
.file
!= BAD_FILE
)
1838 sources
[i
++] = per_slot_offset
;
1839 if (channel_mask
.file
!= BAD_FILE
)
1840 sources
[i
++] = channel_mask
;
1842 sources
[i
++] = this->control_data_bits
;
1845 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1846 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1848 /* We need to increment Global Offset by 256-bits to make room for
1849 * Broadwell's extra "Vertex Count" payload at the beginning of the
1850 * URB entry. Since this is an OWord message, Global Offset is counted
1851 * in 128-bit units, so we must set it to 2.
1853 if (gs_prog_data
->static_vertex_count
== -1)
1858 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1861 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1863 /* Note: we are calling this *before* increasing vertex_count, so
1864 * this->vertex_count == vertex_count - 1 in the formula above.
1867 /* Stream mode uses 2 bits per vertex */
1868 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1870 /* Must be a valid stream */
1871 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1873 /* Control data bits are initialized to 0 so we don't have to set any
1874 * bits when sending vertices to stream 0.
1879 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1881 /* reg::sid = stream_id */
1882 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1883 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1885 /* reg:shift_count = 2 * (vertex_count - 1) */
1886 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1887 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1889 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1890 * attention to the lower 5 bits of its second source argument, so on this
1891 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1892 * stream_id << ((2 * (vertex_count - 1)) % 32).
1894 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1895 abld
.SHL(mask
, sid
, shift_count
);
1896 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1900 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1903 assert(stage
== MESA_SHADER_GEOMETRY
);
1905 struct brw_gs_prog_data
*gs_prog_data
=
1906 (struct brw_gs_prog_data
*) prog_data
;
1908 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1909 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1911 /* Haswell and later hardware ignores the "Render Stream Select" bits
1912 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1913 * and instead sends all primitives down the pipeline for rasterization.
1914 * If the SOL stage is enabled, "Render Stream Select" is honored and
1915 * primitives bound to non-zero streams are discarded after stream output.
1917 * Since the only purpose of primives sent to non-zero streams is to
1918 * be recorded by transform feedback, we can simply discard all geometry
1919 * bound to these streams when transform feedback is disabled.
1921 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1924 /* If we're outputting 32 control data bits or less, then we can wait
1925 * until the shader is over to output them all. Otherwise we need to
1926 * output them as we go. Now is the time to do it, since we're about to
1927 * output the vertex_count'th vertex, so it's guaranteed that the
1928 * control data bits associated with the (vertex_count - 1)th vertex are
1931 if (gs_compile
->control_data_header_size_bits
> 32) {
1932 const fs_builder abld
=
1933 bld
.annotate("emit vertex: emit control data bits");
1935 /* Only emit control data bits if we've finished accumulating a batch
1936 * of 32 bits. This is the case when:
1938 * (vertex_count * bits_per_vertex) % 32 == 0
1940 * (in other words, when the last 5 bits of vertex_count *
1941 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1942 * integer n (which is always the case, since bits_per_vertex is
1943 * always 1 or 2), this is equivalent to requiring that the last 5-n
1944 * bits of vertex_count are 0:
1946 * vertex_count & (2^(5-n) - 1) == 0
1948 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1951 * vertex_count & (32 / bits_per_vertex - 1) == 0
1953 * TODO: If vertex_count is an immediate, we could do some of this math
1954 * at compile time...
1957 abld
.AND(bld
.null_reg_d(), vertex_count
,
1958 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1959 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1961 abld
.IF(BRW_PREDICATE_NORMAL
);
1962 /* If vertex_count is 0, then no control data bits have been
1963 * accumulated yet, so we can skip emitting them.
1965 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1966 BRW_CONDITIONAL_NEQ
);
1967 abld
.IF(BRW_PREDICATE_NORMAL
);
1968 emit_gs_control_data_bits(vertex_count
);
1969 abld
.emit(BRW_OPCODE_ENDIF
);
1971 /* Reset control_data_bits to 0 so we can start accumulating a new
1974 * Note: in the case where vertex_count == 0, this neutralizes the
1975 * effect of any call to EndPrimitive() that the shader may have
1976 * made before outputting its first vertex.
1978 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1979 inst
->force_writemask_all
= true;
1980 abld
.emit(BRW_OPCODE_ENDIF
);
1983 emit_urb_writes(vertex_count
);
1985 /* In stream mode we have to set control data bits for all vertices
1986 * unless we have disabled control data bits completely (which we do
1987 * do for GL_POINTS outputs that don't use streams).
1989 if (gs_compile
->control_data_header_size_bits
> 0 &&
1990 gs_prog_data
->control_data_format
==
1991 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1992 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1997 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1998 const nir_src
&vertex_src
,
1999 unsigned base_offset
,
2000 const nir_src
&offset_src
,
2001 unsigned num_components
,
2002 unsigned first_component
)
2004 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
2006 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2007 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2008 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2010 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
2011 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
2012 * gl_PointSize is available as a GS input, however, so it must be that.
2014 const bool is_point_size
= (base_offset
== 0);
2016 /* TODO: figure out push input layout for invocations == 1 */
2017 if (gs_prog_data
->invocations
== 1 &&
2018 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2019 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2020 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2021 vertex_const
->u32
[0] * push_reg_count
;
2022 /* This input was pushed into registers. */
2023 if (is_point_size
) {
2024 /* gl_PointSize comes in .w */
2025 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
2027 for (unsigned i
= 0; i
< num_components
; i
++) {
2028 bld
.MOV(offset(dst
, bld
, i
),
2029 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
2035 /* Resort to the pull model. Ensure the VUE handles are provided. */
2036 gs_prog_data
->base
.include_vue_handles
= true;
2038 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2039 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2041 if (gs_prog_data
->invocations
== 1) {
2043 /* The vertex index is constant; just select the proper URB handle. */
2045 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2046 BRW_REGISTER_TYPE_UD
);
2048 /* The vertex index is non-constant. We need to use indirect
2049 * addressing to fetch the proper URB handle.
2051 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2052 * indicating that channel <n> should read the handle from
2053 * DWord <n>. We convert that to bytes by multiplying by 4.
2055 * Next, we convert the vertex index to bytes by multiplying
2056 * by 32 (shifting by 5), and add the two together. This is
2057 * the final indirect byte offset.
2059 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
2060 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2061 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2062 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2064 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2065 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2066 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2067 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2068 /* Convert vertex_index to bytes (multiply by 32) */
2069 bld
.SHL(vertex_offset_bytes
,
2070 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2072 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2074 /* Use first_icp_handle as the base offset. There is one register
2075 * of URB handles per vertex, so inform the register allocator that
2076 * we might read up to nir->info.gs.vertices_in registers.
2078 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2079 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2080 fs_reg(icp_offset_bytes
),
2081 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2084 assert(gs_prog_data
->invocations
> 1);
2087 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2089 retype(brw_vec1_grf(first_icp_handle
+
2090 vertex_const
->i32
[0] / 8,
2091 vertex_const
->i32
[0] % 8),
2092 BRW_REGISTER_TYPE_UD
));
2094 /* The vertex index is non-constant. We need to use indirect
2095 * addressing to fetch the proper URB handle.
2098 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2100 /* Convert vertex_index to bytes (multiply by 4) */
2101 bld
.SHL(icp_offset_bytes
,
2102 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2105 /* Use first_icp_handle as the base offset. There is one DWord
2106 * of URB handles per vertex, so inform the register allocator that
2107 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2109 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2110 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2111 fs_reg(icp_offset_bytes
),
2112 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2119 fs_reg tmp_dst
= dst
;
2120 fs_reg indirect_offset
= get_nir_src(offset_src
);
2121 unsigned num_iterations
= 1;
2122 unsigned orig_num_components
= num_components
;
2124 if (type_sz(dst
.type
) == 8) {
2125 if (num_components
> 2) {
2129 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2131 first_component
= first_component
/ 2;
2134 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2136 /* Constant indexing - use global offset. */
2137 if (first_component
!= 0) {
2138 unsigned read_components
= num_components
+ first_component
;
2139 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2140 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2141 inst
->regs_written
= read_components
* type_sz(tmp_dst
.type
) / 4;
2142 for (unsigned i
= 0; i
< num_components
; i
++) {
2143 bld
.MOV(offset(tmp_dst
, bld
, i
),
2144 offset(tmp
, bld
, i
+ first_component
));
2147 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2149 inst
->regs_written
= num_components
* type_sz(tmp_dst
.type
) / 4;
2151 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2154 /* Indirect indexing - use per-slot offsets as well. */
2155 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2156 unsigned read_components
= num_components
+ first_component
;
2157 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2158 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2159 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2160 if (first_component
!= 0) {
2161 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2163 inst
->regs_written
= read_components
* type_sz(tmp_dst
.type
) / 4;
2164 for (unsigned i
= 0; i
< num_components
; i
++) {
2165 bld
.MOV(offset(tmp_dst
, bld
, i
),
2166 offset(tmp
, bld
, i
+ first_component
));
2169 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2171 inst
->regs_written
= num_components
* type_sz(tmp_dst
.type
) / 4;
2173 inst
->offset
= base_offset
;
2177 if (type_sz(dst
.type
) == 8) {
2178 shuffle_32bit_load_result_to_64bit_data(
2179 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2181 for (unsigned c
= 0; c
< num_components
; c
++)
2182 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2185 if (num_iterations
> 1) {
2186 num_components
= orig_num_components
- 2;
2190 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2191 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2192 indirect_offset
= new_indirect
;
2197 if (is_point_size
) {
2198 /* Read the whole VUE header (because of alignment) and read .w. */
2199 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
2201 inst
->regs_written
= 4;
2202 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2207 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2209 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2210 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2213 /* The only constant offset we should find is 0. brw_nir.c's
2214 * add_const_offset_to_base() will fold other constant offsets
2215 * into instr->const_index[0].
2217 assert(const_value
->u32
[0] == 0);
2221 return get_nir_src(*offset_src
);
2225 do_untyped_vector_read(const fs_builder
&bld
,
2227 const fs_reg surf_index
,
2228 const fs_reg offset_reg
,
2229 unsigned num_components
)
2231 if (type_sz(dest
.type
) == 4) {
2232 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2235 BRW_PREDICATE_NONE
);
2236 read_result
.type
= dest
.type
;
2237 for (unsigned i
= 0; i
< num_components
; i
++)
2238 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2239 } else if (type_sz(dest
.type
) == 8) {
2240 /* Reading a dvec, so we need to:
2242 * 1. Multiply num_components by 2, to account for the fact that we
2243 * need to read 64-bit components.
2244 * 2. Shuffle the result of the load to form valid 64-bit elements
2245 * 3. Emit a second load (for components z/w) if needed.
2247 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2248 bld
.MOV(read_offset
, offset_reg
);
2250 int iters
= num_components
<= 2 ? 1 : 2;
2252 /* Load the dvec, the first iteration loads components x/y, the second
2253 * iteration, if needed, loads components z/w
2255 for (int it
= 0; it
< iters
; it
++) {
2256 /* Compute number of components to read in this iteration */
2257 int iter_components
= MIN2(2, num_components
);
2258 num_components
-= iter_components
;
2260 /* Read. Since this message reads 32-bit components, we need to
2261 * read twice as many components.
2263 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2265 iter_components
* 2,
2266 BRW_PREDICATE_NONE
);
2268 /* Shuffle the 32-bit load result into valid 64-bit data */
2269 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2270 shuffle_32bit_load_result_to_64bit_data(
2271 bld
, packed_result
, read_result
, iter_components
);
2273 /* Move each component to its destination */
2274 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2275 for (int c
= 0; c
< iter_components
; c
++) {
2276 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2277 offset(packed_result
, bld
, c
));
2280 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2283 unreachable("Unsupported type");
2288 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2289 nir_intrinsic_instr
*instr
)
2291 assert(stage
== MESA_SHADER_VERTEX
);
2294 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2295 dest
= get_nir_dest(instr
->dest
);
2297 switch (instr
->intrinsic
) {
2298 case nir_intrinsic_load_vertex_id
:
2299 unreachable("should be lowered by lower_vertex_id()");
2301 case nir_intrinsic_load_vertex_id_zero_base
:
2302 case nir_intrinsic_load_base_vertex
:
2303 case nir_intrinsic_load_instance_id
:
2304 case nir_intrinsic_load_base_instance
:
2305 case nir_intrinsic_load_draw_id
: {
2306 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2307 fs_reg val
= nir_system_values
[sv
];
2308 assert(val
.file
!= BAD_FILE
);
2309 dest
.type
= val
.type
;
2315 nir_emit_intrinsic(bld
, instr
);
2321 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2322 nir_intrinsic_instr
*instr
)
2324 assert(stage
== MESA_SHADER_TESS_CTRL
);
2325 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2326 struct brw_tcs_prog_data
*tcs_prog_data
=
2327 (struct brw_tcs_prog_data
*) prog_data
;
2330 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2331 dst
= get_nir_dest(instr
->dest
);
2333 switch (instr
->intrinsic
) {
2334 case nir_intrinsic_load_primitive_id
:
2335 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2337 case nir_intrinsic_load_invocation_id
:
2338 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2340 case nir_intrinsic_load_patch_vertices_in
:
2341 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2342 brw_imm_d(tcs_key
->input_vertices
));
2345 case nir_intrinsic_barrier
: {
2346 if (tcs_prog_data
->instances
== 1)
2349 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2350 fs_reg m0_2
= byte_offset(m0
, 2 * sizeof(uint32_t));
2352 const fs_builder fwa_bld
= bld
.exec_all();
2354 /* Zero the message header */
2355 fwa_bld
.MOV(m0
, brw_imm_ud(0u));
2357 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2358 fwa_bld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2359 brw_imm_ud(INTEL_MASK(16, 13)));
2361 /* Shift it up to bits 27:24. */
2362 fwa_bld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2364 /* Set the Barrier Count and the enable bit */
2365 fwa_bld
.OR(m0_2
, m0_2
,
2366 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2368 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2372 case nir_intrinsic_load_input
:
2373 unreachable("nir_lower_io should never give us these.");
2376 case nir_intrinsic_load_per_vertex_input
: {
2377 fs_reg indirect_offset
= get_indirect_offset(instr
);
2378 unsigned imm_offset
= instr
->const_index
[0];
2380 const nir_src
&vertex_src
= instr
->src
[0];
2381 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2388 /* Emit a MOV to resolve <0,1,0> regioning. */
2389 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2391 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2392 vertex_const
->i32
[0] & 7),
2393 BRW_REGISTER_TYPE_UD
));
2394 } else if (tcs_prog_data
->instances
== 1 &&
2395 vertex_src
.is_ssa
&&
2396 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2397 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2398 /* For the common case of only 1 instance, an array index of
2399 * gl_InvocationID means reading g1. Skip all the indirect work.
2401 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2403 /* The vertex index is non-constant. We need to use indirect
2404 * addressing to fetch the proper URB handle.
2406 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2408 /* Each ICP handle is a single DWord (4 bytes) */
2409 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2410 bld
.SHL(vertex_offset_bytes
,
2411 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2414 /* Start at g1. We might read up to 4 registers. */
2415 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2416 fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes
,
2417 brw_imm_ud(4 * REG_SIZE
));
2420 /* We can only read two double components with each URB read, so
2421 * we send two read messages in that case, each one loading up to
2422 * two double components.
2424 unsigned num_iterations
= 1;
2425 unsigned num_components
= instr
->num_components
;
2426 unsigned first_component
= nir_intrinsic_component(instr
);
2427 fs_reg orig_dst
= dst
;
2428 if (type_sz(dst
.type
) == 8) {
2429 first_component
= first_component
/ 2;
2430 if (instr
->num_components
> 2) {
2435 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2439 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2440 if (indirect_offset
.file
== BAD_FILE
) {
2441 /* Constant indexing - use global offset. */
2442 if (first_component
!= 0) {
2443 unsigned read_components
= num_components
+ first_component
;
2444 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2445 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2446 for (unsigned i
= 0; i
< num_components
; i
++) {
2447 bld
.MOV(offset(dst
, bld
, i
),
2448 offset(tmp
, bld
, i
+ first_component
));
2451 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2453 inst
->offset
= imm_offset
;
2456 /* Indirect indexing - use per-slot offsets as well. */
2457 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2458 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2459 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2460 if (first_component
!= 0) {
2461 unsigned read_components
= num_components
+ first_component
;
2462 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2463 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2465 for (unsigned i
= 0; i
< num_components
; i
++) {
2466 bld
.MOV(offset(dst
, bld
, i
),
2467 offset(tmp
, bld
, i
+ first_component
));
2470 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2473 inst
->offset
= imm_offset
;
2476 inst
->regs_written
=
2477 ((num_components
+ first_component
) * type_sz(dst
.type
) / 4);
2479 /* If we are reading 64-bit data using 32-bit read messages we need
2480 * build proper 64-bit data elements by shuffling the low and high
2481 * 32-bit components around like we do for other things like UBOs
2484 if (type_sz(dst
.type
) == 8) {
2485 shuffle_32bit_load_result_to_64bit_data(
2486 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2488 for (unsigned c
= 0; c
< num_components
; c
++) {
2489 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2490 offset(dst
, bld
, c
));
2494 /* Copy the temporary to the destination to deal with writemasking.
2496 * Also attempt to deal with gl_PointSize being in the .w component.
2498 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2499 assert(type_sz(dst
.type
) < 8);
2500 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2501 inst
->regs_written
= 4;
2502 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2505 /* If we are loading double data and we need a second read message
2506 * adjust the write offset
2508 if (num_iterations
> 1) {
2509 num_components
= instr
->num_components
- 2;
2510 if (indirect_offset
.file
== BAD_FILE
) {
2513 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2514 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2515 indirect_offset
= new_indirect
;
2522 case nir_intrinsic_load_output
:
2523 case nir_intrinsic_load_per_vertex_output
: {
2524 fs_reg indirect_offset
= get_indirect_offset(instr
);
2525 unsigned imm_offset
= instr
->const_index
[0];
2528 if (indirect_offset
.file
== BAD_FILE
) {
2529 /* Replicate the patch handle to all enabled channels */
2530 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2531 bld
.MOV(patch_handle
,
2532 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2534 if (imm_offset
== 0) {
2535 /* This is a read of gl_TessLevelInner[], which lives in the
2536 * Patch URB header. The layout depends on the domain.
2538 dst
.type
= BRW_REGISTER_TYPE_F
;
2539 switch (tcs_key
->tes_primitive_mode
) {
2541 /* DWords 3-2 (reversed) */
2542 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2544 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2547 inst
->regs_written
= 4;
2549 /* dst.xy = tmp.wz */
2550 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2551 bld
.MOV(offset(dst
, bld
, 1), offset(tmp
, bld
, 2));
2555 /* DWord 4; hardcode offset = 1 and regs_written = 1 */
2556 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2559 inst
->regs_written
= 1;
2562 /* All channels are undefined. */
2565 unreachable("Bogus tessellation domain");
2567 } else if (imm_offset
== 1) {
2568 /* This is a read of gl_TessLevelOuter[], which lives in the
2569 * Patch URB header. The layout depends on the domain.
2571 dst
.type
= BRW_REGISTER_TYPE_F
;
2573 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2574 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2577 inst
->regs_written
= 4;
2579 /* Reswizzle: WZYX */
2581 offset(tmp
, bld
, 3),
2582 offset(tmp
, bld
, 2),
2583 offset(tmp
, bld
, 1),
2584 offset(tmp
, bld
, 0),
2587 unsigned num_components
;
2588 switch (tcs_key
->tes_primitive_mode
) {
2596 /* Isolines are not reversed; swizzle .zw -> .xy */
2597 srcs
[0] = offset(tmp
, bld
, 2);
2598 srcs
[1] = offset(tmp
, bld
, 3);
2602 unreachable("Bogus tessellation domain");
2604 bld
.LOAD_PAYLOAD(dst
, srcs
, num_components
, 0);
2606 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2607 inst
->offset
= imm_offset
;
2609 inst
->regs_written
= instr
->num_components
;
2612 /* Indirect indexing - use per-slot offsets as well. */
2613 const fs_reg srcs
[] = {
2614 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2617 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2618 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2620 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2621 inst
->offset
= imm_offset
;
2623 inst
->regs_written
= instr
->num_components
;
2628 case nir_intrinsic_store_output
:
2629 case nir_intrinsic_store_per_vertex_output
: {
2630 fs_reg value
= get_nir_src(instr
->src
[0]);
2631 bool is_64bit
= (instr
->src
[0].is_ssa
?
2632 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2633 fs_reg indirect_offset
= get_indirect_offset(instr
);
2634 unsigned imm_offset
= instr
->const_index
[0];
2635 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2636 unsigned mask
= instr
->const_index
[1];
2637 unsigned header_regs
= 0;
2639 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2641 if (indirect_offset
.file
!= BAD_FILE
) {
2642 srcs
[header_regs
++] = indirect_offset
;
2643 } else if (!is_passthrough_shader
) {
2644 if (imm_offset
== 0) {
2645 value
.type
= BRW_REGISTER_TYPE_F
;
2647 mask
&= (1 << tesslevel_inner_components(tcs_key
->tes_primitive_mode
)) - 1;
2649 /* This is a write to gl_TessLevelInner[], which lives in the
2650 * Patch URB header. The layout depends on the domain.
2652 switch (tcs_key
->tes_primitive_mode
) {
2654 /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
2655 * We use an XXYX swizzle to reverse put .xy in the .wz
2656 * channels, and use a .zw writemask.
2658 mask
= writemask_for_backwards_vector(mask
);
2659 swiz
= BRW_SWIZZLE4(0, 0, 1, 0);
2662 /* gl_TessLevelInner[].x lives at DWord 4, so we set the
2663 * writemask to X and bump the URB offset by 1.
2668 /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
2671 unreachable("Bogus tessellation domain");
2673 } else if (imm_offset
== 1) {
2674 /* This is a write to gl_TessLevelOuter[] which lives in the
2675 * Patch URB Header at DWords 4-7. However, it's reversed, so
2676 * instead of .xyzw we have .wzyx.
2678 value
.type
= BRW_REGISTER_TYPE_F
;
2680 mask
&= (1 << tesslevel_outer_components(tcs_key
->tes_primitive_mode
)) - 1;
2682 if (tcs_key
->tes_primitive_mode
== GL_ISOLINES
) {
2683 /* Isolines .xy should be stored in .zw, in order. */
2684 swiz
= BRW_SWIZZLE4(0, 0, 0, 1);
2687 /* Other domains are reversed; store .wzyx instead of .xyzw */
2688 swiz
= BRW_SWIZZLE_WZYX
;
2689 mask
= writemask_for_backwards_vector(mask
);
2697 unsigned num_components
= _mesa_fls(mask
);
2700 /* We can only pack two 64-bit components in a single message, so send
2701 * 2 messages if we have more components
2703 unsigned num_iterations
= 1;
2704 unsigned iter_components
= num_components
;
2705 unsigned first_component
= nir_intrinsic_component(instr
);
2707 first_component
= first_component
/ 2;
2708 if (instr
->num_components
> 2) {
2710 iter_components
= 2;
2714 /* 64-bit data needs to me shuffled before we can write it to the URB.
2715 * We will use this temporary to shuffle the components in each
2719 fs_reg(VGRF
, alloc
.allocate(2 * iter_components
), value
.type
);
2721 mask
= mask
<< first_component
;
2723 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2724 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2725 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2726 opcode
= indirect_offset
.file
!= BAD_FILE
?
2727 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2728 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2729 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2730 /* Expand the 64-bit mask to 32-bit channels. We only handle
2731 * two channels in each iteration, so we only care about X/Y.
2733 unsigned mask32
= 0;
2734 if (mask
& WRITEMASK_X
)
2735 mask32
|= WRITEMASK_XY
;
2736 if (mask
& WRITEMASK_Y
)
2737 mask32
|= WRITEMASK_ZW
;
2739 /* If the mask does not include any of the channels X or Y there
2740 * is nothing to do in this iteration. Move on to the next couple
2741 * of 64-bit channels.
2749 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2750 opcode
= indirect_offset
.file
!= BAD_FILE
?
2751 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2752 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2754 opcode
= indirect_offset
.file
!= BAD_FILE
?
2755 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2756 SHADER_OPCODE_URB_WRITE_SIMD8
;
2759 for (unsigned i
= 0; i
< iter_components
; i
++) {
2760 if (!(mask
& (1 << (i
+ first_component
))))
2764 srcs
[header_regs
+ i
+ first_component
] =
2765 offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2767 /* We need to shuffle the 64-bit data to match the layout
2768 * expected by our 32-bit URB write messages. We use a temporary
2771 unsigned channel
= BRW_GET_SWZ(swiz
, iter
* 2 + i
);
2772 shuffle_64bit_data_for_32bit_write(bld
,
2773 retype(offset(tmp
, bld
, 2 * i
), BRW_REGISTER_TYPE_F
),
2774 retype(offset(value
, bld
, 2 * channel
), BRW_REGISTER_TYPE_DF
),
2777 /* Now copy the data to the destination */
2778 fs_reg dest
= fs_reg(VGRF
, alloc
.allocate(2), value
.type
);
2779 unsigned idx
= 2 * i
;
2780 bld
.MOV(dest
, offset(tmp
, bld
, idx
));
2781 bld
.MOV(offset(dest
, bld
, 1), offset(tmp
, bld
, idx
+ 1));
2782 srcs
[header_regs
+ idx
+ first_component
* 2] = dest
;
2783 srcs
[header_regs
+ idx
+ 1 + first_component
* 2] =
2784 offset(dest
, bld
, 1);
2789 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2790 (is_64bit
? 2 * first_component
: first_component
);
2792 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2793 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2795 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2796 inst
->offset
= imm_offset
;
2799 /* If this is a 64-bit attribute, select the next two 64-bit channels
2800 * to be handled in the next iteration.
2811 nir_emit_intrinsic(bld
, instr
);
2817 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2818 nir_intrinsic_instr
*instr
)
2820 assert(stage
== MESA_SHADER_TESS_EVAL
);
2821 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
2824 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2825 dest
= get_nir_dest(instr
->dest
);
2827 switch (instr
->intrinsic
) {
2828 case nir_intrinsic_load_primitive_id
:
2829 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2831 case nir_intrinsic_load_tess_coord
:
2832 /* gl_TessCoord is part of the payload in g1-3 */
2833 for (unsigned i
= 0; i
< 3; i
++) {
2834 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2838 case nir_intrinsic_load_tess_level_outer
:
2839 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
2840 * appears as a push-model input. So, we can simply use the ATTR file
2841 * rather than issuing URB read messages. The data is stored in the
2842 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
2845 switch (tes_prog_data
->domain
) {
2846 case BRW_TESS_DOMAIN_QUAD
:
2847 for (unsigned i
= 0; i
< 4; i
++)
2848 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2850 case BRW_TESS_DOMAIN_TRI
:
2851 for (unsigned i
= 0; i
< 3; i
++)
2852 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2854 case BRW_TESS_DOMAIN_ISOLINE
:
2855 for (unsigned i
= 0; i
< 2; i
++)
2856 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 6 + i
));
2861 case nir_intrinsic_load_tess_level_inner
:
2862 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
2863 * appears as a push-model input. So, we can simply use the ATTR file
2864 * rather than issuing URB read messages.
2866 switch (tes_prog_data
->domain
) {
2867 case BRW_TESS_DOMAIN_QUAD
:
2868 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
2869 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
2871 case BRW_TESS_DOMAIN_TRI
:
2872 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
2874 case BRW_TESS_DOMAIN_ISOLINE
:
2875 /* ignore - value is undefined */
2880 case nir_intrinsic_load_input
:
2881 case nir_intrinsic_load_per_vertex_input
: {
2882 fs_reg indirect_offset
= get_indirect_offset(instr
);
2883 unsigned imm_offset
= instr
->const_index
[0];
2884 unsigned first_component
= nir_intrinsic_component(instr
);
2886 if (type_sz(dest
.type
) == 8) {
2887 first_component
= first_component
/ 2;
2891 if (indirect_offset
.file
== BAD_FILE
) {
2892 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2893 * which is 16 registers (since each holds 2 vec4 slots).
2895 const unsigned max_push_slots
= 32;
2896 if (imm_offset
< max_push_slots
) {
2897 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2898 for (int i
= 0; i
< instr
->num_components
; i
++) {
2899 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2900 i
+ first_component
;
2901 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2903 tes_prog_data
->base
.urb_read_length
=
2904 MAX2(tes_prog_data
->base
.urb_read_length
,
2905 DIV_ROUND_UP(imm_offset
+ 1, 2));
2907 /* Replicate the patch handle to all enabled channels */
2908 const fs_reg srcs
[] = {
2909 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2911 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2912 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2914 if (first_component
!= 0) {
2915 unsigned read_components
=
2916 instr
->num_components
+ first_component
;
2917 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2918 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2920 inst
->regs_written
= read_components
;
2921 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2922 bld
.MOV(offset(dest
, bld
, i
),
2923 offset(tmp
, bld
, i
+ first_component
));
2926 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2928 inst
->regs_written
= instr
->num_components
;
2931 inst
->offset
= imm_offset
;
2934 /* Indirect indexing - use per-slot offsets as well. */
2935 const fs_reg srcs
[] = {
2936 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2939 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2940 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2942 if (first_component
!= 0) {
2943 unsigned read_components
=
2944 instr
->num_components
+ first_component
;
2945 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2946 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2948 inst
->regs_written
= read_components
;
2949 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2950 bld
.MOV(offset(dest
, bld
, i
),
2951 offset(tmp
, bld
, i
+ first_component
));
2954 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2956 inst
->regs_written
= instr
->num_components
;
2959 inst
->offset
= imm_offset
;
2964 nir_emit_intrinsic(bld
, instr
);
2970 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2971 nir_intrinsic_instr
*instr
)
2973 assert(stage
== MESA_SHADER_GEOMETRY
);
2974 fs_reg indirect_offset
;
2977 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2978 dest
= get_nir_dest(instr
->dest
);
2980 switch (instr
->intrinsic
) {
2981 case nir_intrinsic_load_primitive_id
:
2982 assert(stage
== MESA_SHADER_GEOMETRY
);
2983 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
2984 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2985 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2988 case nir_intrinsic_load_input
:
2989 unreachable("load_input intrinsics are invalid for the GS stage");
2991 case nir_intrinsic_load_per_vertex_input
:
2992 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2993 instr
->src
[1], instr
->num_components
,
2994 nir_intrinsic_component(instr
));
2997 case nir_intrinsic_emit_vertex_with_counter
:
2998 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3001 case nir_intrinsic_end_primitive_with_counter
:
3002 emit_gs_end_primitive(instr
->src
[0]);
3005 case nir_intrinsic_set_vertex_count
:
3006 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3009 case nir_intrinsic_load_invocation_id
: {
3010 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3011 assert(val
.file
!= BAD_FILE
);
3012 dest
.type
= val
.type
;
3018 nir_emit_intrinsic(bld
, instr
);
3024 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3025 nir_intrinsic_instr
*instr
)
3027 assert(stage
== MESA_SHADER_FRAGMENT
);
3028 struct brw_wm_prog_data
*wm_prog_data
=
3029 (struct brw_wm_prog_data
*) prog_data
;
3030 const struct brw_wm_prog_key
*wm_key
= (const struct brw_wm_prog_key
*) key
;
3033 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3034 dest
= get_nir_dest(instr
->dest
);
3036 switch (instr
->intrinsic
) {
3037 case nir_intrinsic_load_front_face
:
3038 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3039 *emit_frontfacing_interpolation());
3042 case nir_intrinsic_load_sample_pos
: {
3043 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3044 assert(sample_pos
.file
!= BAD_FILE
);
3045 dest
.type
= sample_pos
.type
;
3046 bld
.MOV(dest
, sample_pos
);
3047 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3051 case nir_intrinsic_load_helper_invocation
:
3052 case nir_intrinsic_load_sample_mask_in
:
3053 case nir_intrinsic_load_sample_id
: {
3054 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3055 fs_reg val
= nir_system_values
[sv
];
3056 assert(val
.file
!= BAD_FILE
);
3057 dest
.type
= val
.type
;
3062 case nir_intrinsic_discard
:
3063 case nir_intrinsic_discard_if
: {
3064 /* We track our discarded pixels in f0.1. By predicating on it, we can
3065 * update just the flag bits that aren't yet discarded. If there's no
3066 * condition, we emit a CMP of g0 != g0, so all currently executing
3067 * channels will get turned off.
3070 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3071 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3072 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3074 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3075 BRW_REGISTER_TYPE_UW
));
3076 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3078 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3079 cmp
->flag_subreg
= 1;
3081 if (devinfo
->gen
>= 6) {
3082 emit_discard_jump();
3087 case nir_intrinsic_interp_var_at_centroid
:
3088 case nir_intrinsic_interp_var_at_sample
:
3089 case nir_intrinsic_interp_var_at_offset
: {
3090 /* Handle ARB_gpu_shader5 interpolation intrinsics
3092 * It's worth a quick word of explanation as to why we handle the full
3093 * variable-based interpolation intrinsic rather than a lowered version
3094 * with like we do for other inputs. We have to do that because the way
3095 * we set up inputs doesn't allow us to use the already setup inputs for
3096 * interpolation. At the beginning of the shader, we go through all of
3097 * the input variables and do the initial interpolation and put it in
3098 * the nir_inputs array based on its location as determined in
3099 * nir_lower_io. If the input isn't used, dead code cleans up and
3100 * everything works fine. However, when we get to the ARB_gpu_shader5
3101 * interpolation intrinsics, we need to reinterpolate the input
3102 * differently. If we used an intrinsic that just had an index it would
3103 * only give us the offset into the nir_inputs array. However, this is
3104 * useless because that value is post-interpolation and we need
3105 * pre-interpolation. In order to get the actual location of the bits
3106 * we get from the vertex fetching hardware, we need the variable.
3108 wm_prog_data
->pulls_bary
= true;
3110 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3111 const glsl_interp_qualifier interpolation
=
3112 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
3114 switch (instr
->intrinsic
) {
3115 case nir_intrinsic_interp_var_at_centroid
:
3116 emit_pixel_interpolater_send(bld
,
3117 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
3124 case nir_intrinsic_interp_var_at_sample
: {
3125 if (!wm_key
->multisample_fbo
) {
3126 /* From the ARB_gpu_shader5 specification:
3127 * "If multisample buffers are not available, the input varying
3128 * will be evaluated at the center of the pixel."
3130 emit_pixel_interpolater_send(bld
,
3131 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
3139 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3142 unsigned msg_data
= const_sample
->i32
[0] << 4;
3144 emit_pixel_interpolater_send(bld
,
3145 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3148 brw_imm_ud(msg_data
),
3151 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3152 BRW_REGISTER_TYPE_UD
);
3154 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3155 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3156 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3157 bld
.exec_all().group(1, 0)
3158 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3159 emit_pixel_interpolater_send(bld
,
3160 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3166 /* Make a loop that sends a message to the pixel interpolater
3167 * for the sample number in each live channel. If there are
3168 * multiple channels with the same sample number then these
3169 * will be handled simultaneously with a single interation of
3172 bld
.emit(BRW_OPCODE_DO
);
3174 /* Get the next live sample number into sample_id_reg */
3175 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3177 /* Set the flag register so that we can perform the send
3178 * message on all channels that have the same sample number
3180 bld
.CMP(bld
.null_reg_ud(),
3181 sample_src
, sample_id
,
3182 BRW_CONDITIONAL_EQ
);
3183 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3184 bld
.exec_all().group(1, 0)
3185 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3187 emit_pixel_interpolater_send(bld
,
3188 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3193 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3195 /* Continue the loop if there are any live channels left */
3196 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3198 bld
.emit(BRW_OPCODE_WHILE
));
3205 case nir_intrinsic_interp_var_at_offset
: {
3206 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3209 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3210 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3212 emit_pixel_interpolater_send(bld
,
3213 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3216 brw_imm_ud(off_x
| (off_y
<< 4)),
3219 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3220 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3221 BRW_REGISTER_TYPE_F
);
3222 for (int i
= 0; i
< 2; i
++) {
3223 fs_reg temp
= vgrf(glsl_type::float_type
);
3224 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3225 fs_reg itemp
= vgrf(glsl_type::int_type
);
3227 bld
.MOV(itemp
, temp
);
3229 /* Clamp the upper end of the range to +7/16.
3230 * ARB_gpu_shader5 requires that we support a maximum offset
3231 * of +0.5, which isn't representable in a S0.4 value -- if
3232 * we didn't clamp it, we'd end up with -8/16, which is the
3233 * opposite of what the shader author wanted.
3235 * This is legal due to ARB_gpu_shader5's quantization
3238 * "Not all values of <offset> may be supported; x and y
3239 * offsets may be rounded to fixed-point values with the
3240 * number of fraction bits given by the
3241 * implementation-dependent constant
3242 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3244 set_condmod(BRW_CONDITIONAL_L
,
3245 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3248 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3249 emit_pixel_interpolater_send(bld
,
3260 unreachable("Invalid intrinsic");
3263 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3264 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
3265 src
.type
= dest
.type
;
3267 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
3268 dest
= offset(dest
, bld
, 1);
3273 nir_emit_intrinsic(bld
, instr
);
3279 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3280 nir_intrinsic_instr
*instr
)
3282 assert(stage
== MESA_SHADER_COMPUTE
);
3283 struct brw_cs_prog_data
*cs_prog_data
=
3284 (struct brw_cs_prog_data
*) prog_data
;
3287 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3288 dest
= get_nir_dest(instr
->dest
);
3290 switch (instr
->intrinsic
) {
3291 case nir_intrinsic_barrier
:
3293 cs_prog_data
->uses_barrier
= true;
3296 case nir_intrinsic_load_local_invocation_id
:
3297 case nir_intrinsic_load_work_group_id
: {
3298 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3299 fs_reg val
= nir_system_values
[sv
];
3300 assert(val
.file
!= BAD_FILE
);
3301 dest
.type
= val
.type
;
3302 for (unsigned i
= 0; i
< 3; i
++)
3303 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3307 case nir_intrinsic_load_num_work_groups
: {
3308 const unsigned surface
=
3309 cs_prog_data
->binding_table
.work_groups_start
;
3311 cs_prog_data
->uses_num_work_groups
= true;
3313 fs_reg surf_index
= brw_imm_ud(surface
);
3314 brw_mark_surface_used(prog_data
, surface
);
3316 /* Read the 3 GLuint components of gl_NumWorkGroups */
3317 for (unsigned i
= 0; i
< 3; i
++) {
3318 fs_reg read_result
=
3319 emit_untyped_read(bld
, surf_index
,
3321 1 /* dims */, 1 /* size */,
3322 BRW_PREDICATE_NONE
);
3323 read_result
.type
= dest
.type
;
3324 bld
.MOV(dest
, read_result
);
3325 dest
= offset(dest
, bld
, 1);
3330 case nir_intrinsic_shared_atomic_add
:
3331 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3333 case nir_intrinsic_shared_atomic_imin
:
3334 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3336 case nir_intrinsic_shared_atomic_umin
:
3337 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3339 case nir_intrinsic_shared_atomic_imax
:
3340 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3342 case nir_intrinsic_shared_atomic_umax
:
3343 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3345 case nir_intrinsic_shared_atomic_and
:
3346 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3348 case nir_intrinsic_shared_atomic_or
:
3349 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3351 case nir_intrinsic_shared_atomic_xor
:
3352 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3354 case nir_intrinsic_shared_atomic_exchange
:
3355 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3357 case nir_intrinsic_shared_atomic_comp_swap
:
3358 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3361 case nir_intrinsic_load_shared
: {
3362 assert(devinfo
->gen
>= 7);
3364 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3366 /* Get the offset to read from */
3368 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3370 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3372 offset_reg
= vgrf(glsl_type::uint_type
);
3374 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3375 brw_imm_ud(instr
->const_index
[0]));
3378 /* Read the vector */
3379 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3380 instr
->num_components
);
3384 case nir_intrinsic_store_shared
: {
3385 assert(devinfo
->gen
>= 7);
3388 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3391 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3394 unsigned writemask
= instr
->const_index
[1];
3396 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3397 * since the untyped writes below operate in units of 32-bits, which
3398 * means that we need to write twice as many components each time.
3399 * Also, we have to suffle 64-bit data to be in the appropriate layout
3400 * expected by our 32-bit write messages.
3402 unsigned type_size
= 4;
3403 unsigned bit_size
= instr
->src
[0].is_ssa
?
3404 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3405 if (bit_size
== 64) {
3408 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3409 shuffle_64bit_data_for_32bit_write(
3411 retype(tmp
, BRW_REGISTER_TYPE_F
),
3412 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3413 instr
->num_components
);
3417 unsigned type_slots
= type_size
/ 4;
3419 /* Combine groups of consecutive enabled channels in one write
3420 * message. We use ffs to find the first enabled channel and then ffs on
3421 * the bit-inverse, down-shifted writemask to determine the length of
3422 * the block of enabled bits.
3425 unsigned first_component
= ffs(writemask
) - 1;
3426 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3428 /* We can't write more than 2 64-bit components at once. Limit the
3429 * length of the write to what we can do and let the next iteration
3433 length
= MIN2(2, length
);
3436 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3438 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3439 type_size
* first_component
);
3441 offset_reg
= vgrf(glsl_type::uint_type
);
3443 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3444 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3447 emit_untyped_write(bld
, surf_index
, offset_reg
,
3448 offset(val_reg
, bld
, first_component
* type_slots
),
3449 1 /* dims */, length
* type_slots
,
3450 BRW_PREDICATE_NONE
);
3452 /* Clear the bits in the writemask that we just wrote, then try
3453 * again to see if more channels are left.
3455 writemask
&= (15 << (first_component
+ length
));
3462 nir_emit_intrinsic(bld
, instr
);
3468 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3471 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3472 dest
= get_nir_dest(instr
->dest
);
3474 switch (instr
->intrinsic
) {
3475 case nir_intrinsic_atomic_counter_inc
:
3476 case nir_intrinsic_atomic_counter_dec
:
3477 case nir_intrinsic_atomic_counter_read
: {
3478 if (stage
== MESA_SHADER_FRAGMENT
&&
3479 instr
->intrinsic
!= nir_intrinsic_atomic_counter_read
)
3480 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
3482 /* Get the arguments of the atomic intrinsic. */
3483 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3484 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3485 instr
->const_index
[0]);
3488 /* Emit a surface read or atomic op. */
3489 switch (instr
->intrinsic
) {
3490 case nir_intrinsic_atomic_counter_read
:
3491 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3494 case nir_intrinsic_atomic_counter_inc
:
3495 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
3496 fs_reg(), 1, 1, BRW_AOP_INC
);
3499 case nir_intrinsic_atomic_counter_dec
:
3500 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
3501 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
3505 unreachable("Unreachable");
3508 /* Assign the result. */
3509 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3511 /* Mark the surface as used. */
3512 brw_mark_surface_used(stage_prog_data
, surface
);
3516 case nir_intrinsic_image_load
:
3517 case nir_intrinsic_image_store
:
3518 case nir_intrinsic_image_atomic_add
:
3519 case nir_intrinsic_image_atomic_min
:
3520 case nir_intrinsic_image_atomic_max
:
3521 case nir_intrinsic_image_atomic_and
:
3522 case nir_intrinsic_image_atomic_or
:
3523 case nir_intrinsic_image_atomic_xor
:
3524 case nir_intrinsic_image_atomic_exchange
:
3525 case nir_intrinsic_image_atomic_comp_swap
: {
3526 using namespace image_access
;
3528 if (stage
== MESA_SHADER_FRAGMENT
&&
3529 instr
->intrinsic
!= nir_intrinsic_image_load
)
3530 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
3532 /* Get the referenced image variable and type. */
3533 const nir_variable
*var
= instr
->variables
[0]->var
;
3534 const glsl_type
*type
= var
->type
->without_array();
3535 const brw_reg_type base_type
= get_image_base_type(type
);
3537 /* Get some metadata from the image intrinsic. */
3538 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3539 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3540 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3541 const unsigned format
= var
->data
.image
.format
;
3543 /* Get the arguments of the image intrinsic. */
3544 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3545 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3546 BRW_REGISTER_TYPE_UD
);
3547 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3548 retype(get_nir_src(instr
->src
[2]), base_type
) :
3550 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3551 retype(get_nir_src(instr
->src
[3]), base_type
) :
3555 /* Emit an image load, store or atomic op. */
3556 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3557 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3559 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3560 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3561 var
->data
.image
.write_only
? GL_NONE
: format
);
3564 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3565 surf_dims
, arr_dims
, info
->dest_components
,
3566 get_image_atomic_op(instr
->intrinsic
, type
));
3568 /* Assign the result. */
3569 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3570 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3571 offset(tmp
, bld
, c
));
3575 case nir_intrinsic_memory_barrier_atomic_counter
:
3576 case nir_intrinsic_memory_barrier_buffer
:
3577 case nir_intrinsic_memory_barrier_image
:
3578 case nir_intrinsic_memory_barrier
: {
3579 const fs_builder ubld
= bld
.group(8, 0);
3580 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3581 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3586 case nir_intrinsic_group_memory_barrier
:
3587 case nir_intrinsic_memory_barrier_shared
:
3588 /* We treat these workgroup-level barriers as no-ops. This should be
3589 * safe at present and as long as:
3591 * - Memory access instructions are not subsequently reordered by the
3592 * compiler back-end.
3594 * - All threads from a given compute shader workgroup fit within a
3595 * single subslice and therefore talk to the same HDC shared unit
3596 * what supposedly guarantees ordering and coherency between threads
3597 * from the same workgroup. This may change in the future when we
3598 * start splitting workgroups across multiple subslices.
3600 * - The context is not in fault-and-stream mode, which could cause
3601 * memory transactions (including to SLM) prior to the barrier to be
3602 * replayed after the barrier if a pagefault occurs. This shouldn't
3603 * be a problem up to and including SKL because fault-and-stream is
3604 * not usable due to hardware issues, but that's likely to change in
3609 case nir_intrinsic_shader_clock
: {
3610 /* We cannot do anything if there is an event, so ignore it for now */
3611 fs_reg shader_clock
= get_timestamp(bld
);
3612 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
3614 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3618 case nir_intrinsic_image_size
: {
3619 /* Get the referenced image variable and type. */
3620 const nir_variable
*var
= instr
->variables
[0]->var
;
3621 const glsl_type
*type
= var
->type
->without_array();
3623 /* Get the size of the image. */
3624 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3625 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3627 /* For 1DArray image types, the array index is stored in the Z component.
3628 * Fix this by swizzling the Z component to the Y component.
3630 const bool is_1d_array_image
=
3631 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3632 type
->sampler_array
;
3634 /* For CubeArray images, we should count the number of cubes instead
3635 * of the number of faces. Fix it by dividing the (Z component) by 6.
3637 const bool is_cube_array_image
=
3638 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3639 type
->sampler_array
;
3641 /* Copy all the components. */
3642 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3643 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
3644 if ((int)c
>= type
->coordinate_components()) {
3645 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3647 } else if (c
== 1 && is_1d_array_image
) {
3648 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3649 offset(size
, bld
, 2));
3650 } else if (c
== 2 && is_cube_array_image
) {
3651 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3652 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3653 offset(size
, bld
, c
), brw_imm_d(6));
3655 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3656 offset(size
, bld
, c
));
3663 case nir_intrinsic_image_samples
:
3664 /* The driver does not support multi-sampled images. */
3665 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3668 case nir_intrinsic_load_uniform
: {
3669 /* Offsets are in bytes but they should always be multiples of 4 */
3670 assert(instr
->const_index
[0] % 4 == 0);
3672 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3674 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3676 /* Offsets are in bytes but they should always be multiples of 4 */
3677 assert(const_offset
->u32
[0] % 4 == 0);
3678 src
.reg_offset
= const_offset
->u32
[0] / 4;
3680 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3681 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3684 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3685 BRW_REGISTER_TYPE_UD
);
3687 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3688 * go past the end of the uniform. In order to keep the n'th
3689 * component from running past, we subtract off the size of all but
3690 * one component of the vector.
3692 assert(instr
->const_index
[1] >=
3693 instr
->num_components
* (int) type_sz(dest
.type
));
3694 unsigned read_size
= instr
->const_index
[1] -
3695 (instr
->num_components
- 1) * type_sz(dest
.type
);
3697 fs_reg indirect_chv_high_32bit
;
3698 bool is_chv_bxt_64bit
=
3699 (devinfo
->is_cherryview
|| devinfo
->is_broxton
) &&
3700 type_sz(dest
.type
) == 8;
3701 if (is_chv_bxt_64bit
) {
3702 indirect_chv_high_32bit
= vgrf(glsl_type::uint_type
);
3703 /* Calculate indirect address to read high 32 bits */
3704 bld
.ADD(indirect_chv_high_32bit
, indirect
, brw_imm_ud(4));
3707 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3708 if (!is_chv_bxt_64bit
) {
3709 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3710 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3711 indirect
, brw_imm_ud(read_size
));
3713 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3714 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, 0),
3715 offset(src
, bld
, j
),
3716 indirect
, brw_imm_ud(read_size
));
3718 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3719 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, 1),
3720 offset(src
, bld
, j
),
3721 indirect_chv_high_32bit
, brw_imm_ud(read_size
));
3728 case nir_intrinsic_load_ubo
: {
3729 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3733 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3734 const_index
->u32
[0];
3735 surf_index
= brw_imm_ud(index
);
3736 brw_mark_surface_used(prog_data
, index
);
3738 /* The block index is not a constant. Evaluate the index expression
3739 * per-channel and add the base UBO index; we have to select a value
3740 * from any live channel.
3742 surf_index
= vgrf(glsl_type::uint_type
);
3743 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3744 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3745 surf_index
= bld
.emit_uniformize(surf_index
);
3747 /* Assume this may touch any UBO. It would be nice to provide
3748 * a tighter bound, but the array information is already lowered away.
3750 brw_mark_surface_used(prog_data
,
3751 stage_prog_data
->binding_table
.ubo_start
+
3752 nir
->info
.num_ubos
- 1);
3755 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3756 if (const_offset
== NULL
) {
3757 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3758 BRW_REGISTER_TYPE_UD
);
3760 for (int i
= 0; i
< instr
->num_components
; i
++)
3761 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3762 base_offset
, i
* type_sz(dest
.type
));
3764 /* Even if we are loading doubles, a pull constant load will load
3765 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3766 * need to load a full dvec4 we will have to emit 2 loads. This is
3767 * similar to demote_pull_constants(), except that in that case we
3768 * see individual accesses to each component of the vector and then
3769 * we let CSE deal with duplicate loads. Here we see a vector access
3770 * and we have to split it if necessary.
3772 const unsigned type_size
= type_sz(dest
.type
);
3773 const fs_reg packed_consts
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
3774 for (unsigned c
= 0; c
< instr
->num_components
;) {
3775 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
3777 /* Number of usable components in the next 16B-aligned load */
3778 const unsigned count
= MIN2(instr
->num_components
- c
,
3779 (16 - base
% 16) / type_size
);
3782 .emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3783 packed_consts
, surf_index
, brw_imm_ud(base
& ~15));
3785 const fs_reg consts
=
3786 retype(byte_offset(packed_consts
, base
& 15), dest
.type
);
3788 for (unsigned d
= 0; d
< count
; d
++)
3789 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3797 case nir_intrinsic_load_ssbo
: {
3798 assert(devinfo
->gen
>= 7);
3800 nir_const_value
*const_uniform_block
=
3801 nir_src_as_const_value(instr
->src
[0]);
3804 if (const_uniform_block
) {
3805 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3806 const_uniform_block
->u32
[0];
3807 surf_index
= brw_imm_ud(index
);
3808 brw_mark_surface_used(prog_data
, index
);
3810 surf_index
= vgrf(glsl_type::uint_type
);
3811 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3812 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3814 /* Assume this may touch any UBO. It would be nice to provide
3815 * a tighter bound, but the array information is already lowered away.
3817 brw_mark_surface_used(prog_data
,
3818 stage_prog_data
->binding_table
.ssbo_start
+
3819 nir
->info
.num_ssbos
- 1);
3823 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3825 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3827 offset_reg
= get_nir_src(instr
->src
[1]);
3830 /* Read the vector */
3831 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3832 instr
->num_components
);
3837 case nir_intrinsic_load_input
: {
3839 unsigned num_components
= instr
->num_components
;
3840 enum brw_reg_type type
= dest
.type
;
3842 if (stage
== MESA_SHADER_VERTEX
) {
3843 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
3845 assert(type_sz(type
) >= 4);
3846 if (type
== BRW_REGISTER_TYPE_DF
) {
3847 /* const_index is in 32-bit type size units that could not be aligned
3848 * with DF. We need to read the double vector as if it was a float
3849 * vector of twice the number of components to fetch the right data.
3851 dest
= retype(dest
, BRW_REGISTER_TYPE_F
);
3852 num_components
*= 2;
3854 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
3855 instr
->const_index
[0]);
3858 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3859 assert(const_offset
&& "Indirect input loads not allowed");
3860 src
= offset(src
, bld
, const_offset
->u32
[0]);
3862 for (unsigned j
= 0; j
< num_components
; j
++) {
3863 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3866 if (type
== BRW_REGISTER_TYPE_DF
) {
3867 /* Once the double vector is read, set again its original register
3868 * type to continue with normal execution.
3870 src
= retype(src
, type
);
3871 dest
= retype(dest
, type
);
3874 if (type_sz(src
.type
) == 8) {
3875 shuffle_32bit_load_result_to_64bit_data(bld
,
3877 retype(dest
, BRW_REGISTER_TYPE_F
),
3878 instr
->num_components
);
3884 case nir_intrinsic_store_ssbo
: {
3885 assert(devinfo
->gen
>= 7);
3887 if (stage
== MESA_SHADER_FRAGMENT
)
3888 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
3892 nir_const_value
*const_uniform_block
=
3893 nir_src_as_const_value(instr
->src
[1]);
3894 if (const_uniform_block
) {
3895 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3896 const_uniform_block
->u32
[0];
3897 surf_index
= brw_imm_ud(index
);
3898 brw_mark_surface_used(prog_data
, index
);
3900 surf_index
= vgrf(glsl_type::uint_type
);
3901 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
3902 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3904 brw_mark_surface_used(prog_data
,
3905 stage_prog_data
->binding_table
.ssbo_start
+
3906 nir
->info
.num_ssbos
- 1);
3910 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3913 unsigned writemask
= instr
->const_index
[0];
3915 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3916 * since the untyped writes below operate in units of 32-bits, which
3917 * means that we need to write twice as many components each time.
3918 * Also, we have to suffle 64-bit data to be in the appropriate layout
3919 * expected by our 32-bit write messages.
3921 unsigned type_size
= 4;
3922 unsigned bit_size
= instr
->src
[0].is_ssa
?
3923 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3924 if (bit_size
== 64) {
3927 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3928 shuffle_64bit_data_for_32bit_write(bld
,
3929 retype(tmp
, BRW_REGISTER_TYPE_F
),
3930 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3931 instr
->num_components
);
3935 unsigned type_slots
= type_size
/ 4;
3937 /* Combine groups of consecutive enabled channels in one write
3938 * message. We use ffs to find the first enabled channel and then ffs on
3939 * the bit-inverse, down-shifted writemask to determine the length of
3940 * the block of enabled bits.
3943 unsigned first_component
= ffs(writemask
) - 1;
3944 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3946 /* We can't write more than 2 64-bit components at once. Limit the
3947 * length of the write to what we can do and let the next iteration
3951 length
= MIN2(2, length
);
3954 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
3956 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
3957 type_size
* first_component
);
3959 offset_reg
= vgrf(glsl_type::uint_type
);
3961 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
3962 brw_imm_ud(type_size
* first_component
));
3966 emit_untyped_write(bld
, surf_index
, offset_reg
,
3967 offset(val_reg
, bld
, first_component
* type_slots
),
3968 1 /* dims */, length
* type_slots
,
3969 BRW_PREDICATE_NONE
);
3971 /* Clear the bits in the writemask that we just wrote, then try
3972 * again to see if more channels are left.
3974 writemask
&= (15 << (first_component
+ length
));
3979 case nir_intrinsic_store_output
: {
3980 fs_reg src
= get_nir_src(instr
->src
[0]);
3981 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
3982 instr
->const_index
[0]);
3984 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3985 assert(const_offset
&& "Indirect output stores not allowed");
3986 new_dest
= offset(new_dest
, bld
, const_offset
->u32
[0]);
3988 unsigned num_components
= instr
->num_components
;
3989 unsigned bit_size
= instr
->src
[0].is_ssa
?
3990 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3991 if (bit_size
== 64) {
3993 fs_reg(VGRF
, alloc
.allocate(2 * num_components
),
3994 BRW_REGISTER_TYPE_F
);
3995 shuffle_64bit_data_for_32bit_write(
3996 bld
, tmp
, retype(src
, BRW_REGISTER_TYPE_DF
), num_components
);
3997 src
= retype(tmp
, src
.type
);
3998 num_components
*= 2;
4001 for (unsigned j
= 0; j
< num_components
; j
++) {
4002 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
4007 case nir_intrinsic_ssbo_atomic_add
:
4008 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4010 case nir_intrinsic_ssbo_atomic_imin
:
4011 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4013 case nir_intrinsic_ssbo_atomic_umin
:
4014 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4016 case nir_intrinsic_ssbo_atomic_imax
:
4017 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4019 case nir_intrinsic_ssbo_atomic_umax
:
4020 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4022 case nir_intrinsic_ssbo_atomic_and
:
4023 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4025 case nir_intrinsic_ssbo_atomic_or
:
4026 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4028 case nir_intrinsic_ssbo_atomic_xor
:
4029 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4031 case nir_intrinsic_ssbo_atomic_exchange
:
4032 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4034 case nir_intrinsic_ssbo_atomic_comp_swap
:
4035 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4038 case nir_intrinsic_get_buffer_size
: {
4039 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4040 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4042 /* A resinfo's sampler message is used to get the buffer size. The
4043 * SIMD8's writeback message consists of four registers and SIMD16's
4044 * writeback message consists of 8 destination registers (two per each
4045 * component). Because we are only interested on the first channel of
4046 * the first returned component, where resinfo returns the buffer size
4047 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4048 * the dispatch width.
4050 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4051 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4052 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4055 ubld
.MOV(src_payload
, brw_imm_d(0));
4057 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4058 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4059 src_payload
, brw_imm_ud(index
));
4060 inst
->header_size
= 0;
4062 inst
->regs_written
= 4;
4064 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4065 brw_mark_surface_used(prog_data
, index
);
4069 case nir_intrinsic_load_channel_num
: {
4070 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
4071 dest
= retype(dest
, BRW_REGISTER_TYPE_UD
);
4072 const fs_builder allbld8
= bld
.group(8, 0).exec_all();
4073 allbld8
.MOV(tmp
, brw_imm_v(0x76543210));
4074 if (dispatch_width
> 8)
4075 allbld8
.ADD(byte_offset(tmp
, 16), tmp
, brw_imm_uw(8u));
4076 if (dispatch_width
> 16) {
4077 const fs_builder allbld16
= bld
.group(16, 0).exec_all();
4078 allbld16
.ADD(byte_offset(tmp
, 32), tmp
, brw_imm_uw(16u));
4085 unreachable("unknown intrinsic");
4090 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4091 int op
, nir_intrinsic_instr
*instr
)
4093 if (stage
== MESA_SHADER_FRAGMENT
)
4094 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
4097 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4098 dest
= get_nir_dest(instr
->dest
);
4101 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4102 if (const_surface
) {
4103 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4104 const_surface
->u32
[0];
4105 surface
= brw_imm_ud(surf_index
);
4106 brw_mark_surface_used(prog_data
, surf_index
);
4108 surface
= vgrf(glsl_type::uint_type
);
4109 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4110 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4112 /* Assume this may touch any SSBO. This is the same we do for other
4113 * UBO/SSBO accesses with non-constant surface.
4115 brw_mark_surface_used(prog_data
,
4116 stage_prog_data
->binding_table
.ssbo_start
+
4117 nir
->info
.num_ssbos
- 1);
4120 fs_reg offset
= get_nir_src(instr
->src
[1]);
4121 fs_reg data1
= get_nir_src(instr
->src
[2]);
4123 if (op
== BRW_AOP_CMPWR
)
4124 data2
= get_nir_src(instr
->src
[3]);
4126 /* Emit the actual atomic operation operation */
4128 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4130 1 /* dims */, 1 /* rsize */,
4132 BRW_PREDICATE_NONE
);
4133 dest
.type
= atomic_result
.type
;
4134 bld
.MOV(dest
, atomic_result
);
4138 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4139 int op
, nir_intrinsic_instr
*instr
)
4142 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4143 dest
= get_nir_dest(instr
->dest
);
4145 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4146 fs_reg offset
= get_nir_src(instr
->src
[0]);
4147 fs_reg data1
= get_nir_src(instr
->src
[1]);
4149 if (op
== BRW_AOP_CMPWR
)
4150 data2
= get_nir_src(instr
->src
[2]);
4152 /* Emit the actual atomic operation operation */
4154 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4156 1 /* dims */, 1 /* rsize */,
4158 BRW_PREDICATE_NONE
);
4159 dest
.type
= atomic_result
.type
;
4160 bld
.MOV(dest
, atomic_result
);
4164 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4166 unsigned texture
= instr
->texture_index
;
4167 unsigned sampler
= instr
->sampler_index
;
4169 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4171 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4172 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4174 int lod_components
= 0;
4176 /* The hardware requires a LOD for buffer textures */
4177 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4178 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4180 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4181 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4182 switch (instr
->src
[i
].src_type
) {
4183 case nir_tex_src_bias
:
4184 srcs
[TEX_LOGICAL_SRC_LOD
] =
4185 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4187 case nir_tex_src_comparitor
:
4188 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4190 case nir_tex_src_coord
:
4191 switch (instr
->op
) {
4193 case nir_texop_txf_ms
:
4194 case nir_texop_txf_ms_mcs
:
4195 case nir_texop_samples_identical
:
4196 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4199 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4203 case nir_tex_src_ddx
:
4204 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4205 lod_components
= nir_tex_instr_src_size(instr
, i
);
4207 case nir_tex_src_ddy
:
4208 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4210 case nir_tex_src_lod
:
4211 switch (instr
->op
) {
4213 srcs
[TEX_LOGICAL_SRC_LOD
] =
4214 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4217 srcs
[TEX_LOGICAL_SRC_LOD
] =
4218 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4221 srcs
[TEX_LOGICAL_SRC_LOD
] =
4222 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4226 case nir_tex_src_ms_index
:
4227 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4230 case nir_tex_src_offset
: {
4231 nir_const_value
*const_offset
=
4232 nir_src_as_const_value(instr
->src
[i
].src
);
4234 unsigned header_bits
= brw_texture_offset(const_offset
->i32
, 3);
4235 if (header_bits
!= 0)
4236 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] = brw_imm_ud(header_bits
);
4238 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] =
4239 retype(src
, BRW_REGISTER_TYPE_D
);
4244 case nir_tex_src_projector
:
4245 unreachable("should be lowered");
4247 case nir_tex_src_texture_offset
: {
4248 /* Figure out the highest possible texture index and mark it as used */
4249 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4250 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4251 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4253 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4255 brw_mark_surface_used(prog_data
, max_used
);
4257 /* Emit code to evaluate the actual indexing expression */
4258 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4259 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4260 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4264 case nir_tex_src_sampler_offset
: {
4265 /* Emit code to evaluate the actual indexing expression */
4266 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4267 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4268 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4272 case nir_tex_src_ms_mcs
:
4273 assert(instr
->op
== nir_texop_txf_ms
);
4274 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4277 case nir_tex_src_plane
: {
4278 nir_const_value
*const_plane
=
4279 nir_src_as_const_value(instr
->src
[i
].src
);
4280 const uint32_t plane
= const_plane
->u32
[0];
4281 const uint32_t texture_index
=
4282 instr
->texture_index
+
4283 stage_prog_data
->binding_table
.plane_start
[plane
] -
4284 stage_prog_data
->binding_table
.texture_start
;
4286 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4291 unreachable("unknown texture source");
4295 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4296 (instr
->op
== nir_texop_txf_ms
||
4297 instr
->op
== nir_texop_samples_identical
)) {
4298 if (devinfo
->gen
>= 7 &&
4299 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4300 srcs
[TEX_LOGICAL_SRC_MCS
] =
4301 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4302 instr
->coord_components
,
4303 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4305 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4309 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4310 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4312 if (instr
->op
== nir_texop_query_levels
) {
4313 /* textureQueryLevels() is implemented in terms of TXS so we need to
4314 * pass a valid LOD argument.
4316 assert(srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
);
4317 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
4321 switch (instr
->op
) {
4323 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
4326 opcode
= FS_OPCODE_TXB_LOGICAL
;
4329 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4332 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4335 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4337 case nir_texop_txf_ms
:
4338 if ((key_tex
->msaa_16
& (1 << sampler
)))
4339 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4341 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4343 case nir_texop_txf_ms_mcs
:
4344 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4346 case nir_texop_query_levels
:
4348 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4351 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4354 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= BAD_FILE
&&
4355 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= IMM
)
4356 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4358 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4360 case nir_texop_texture_samples
:
4361 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4363 case nir_texop_samples_identical
: {
4364 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4366 /* If mcs is an immediate value, it means there is no MCS. In that case
4367 * just return false.
4369 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4370 bld
.MOV(dst
, brw_imm_ud(0u));
4371 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4372 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4373 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4374 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4375 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4377 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4378 BRW_CONDITIONAL_EQ
);
4383 unreachable("unknown texture opcode");
4386 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(instr
->dest_type
), 4);
4387 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4389 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4390 if (devinfo
->gen
>= 9 &&
4391 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4392 unsigned write_mask
= instr
->dest
.is_ssa
?
4393 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4394 (1 << dest_size
) - 1;
4395 assert(write_mask
!= 0); /* dead code should have been eliminated */
4396 inst
->regs_written
= _mesa_fls(write_mask
) * dispatch_width
/ 8;
4398 inst
->regs_written
= 4 * dispatch_width
/ 8;
4401 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4402 inst
->shadow_compare
= true;
4404 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
== IMM
)
4405 inst
->offset
= srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].ud
;
4407 if (instr
->op
== nir_texop_tg4
) {
4408 if (instr
->component
== 1 &&
4409 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4410 /* gather4 sampler is broken for green channel on RG32F --
4411 * we must ask for blue instead.
4413 inst
->offset
|= 2 << 16;
4415 inst
->offset
|= instr
->component
<< 16;
4418 if (devinfo
->gen
== 6)
4419 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4423 for (unsigned i
= 0; i
< dest_size
; i
++)
4424 nir_dest
[i
] = offset(dst
, bld
, i
);
4426 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
4429 if (instr
->op
== nir_texop_query_levels
) {
4430 /* # levels is in .w */
4431 nir_dest
[0] = offset(dst
, bld
, 3);
4432 } else if (instr
->op
== nir_texop_txs
&& dest_size
>= 3 &&
4433 (devinfo
->gen
< 7 || is_cube_array
)) {
4434 fs_reg depth
= offset(dst
, bld
, 2);
4435 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
4437 if (is_cube_array
) {
4438 /* fixup #layers for cube map arrays */
4439 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, brw_imm_d(6));
4440 } else if (devinfo
->gen
< 7) {
4441 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4442 bld
.emit_minmax(fixed_depth
, depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4445 nir_dest
[2] = fixed_depth
;
4448 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4452 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4454 switch (instr
->type
) {
4455 case nir_jump_break
:
4456 bld
.emit(BRW_OPCODE_BREAK
);
4458 case nir_jump_continue
:
4459 bld
.emit(BRW_OPCODE_CONTINUE
);
4461 case nir_jump_return
:
4463 unreachable("unknown jump");
4468 * This helper takes the result of a load operation that reads 32-bit elements
4476 * and shuffles the data to get this:
4483 * Which is exactly what we want if the load is reading 64-bit components
4484 * like doubles, where x represents the low 32-bit of the x double component
4485 * and y represents the high 32-bit of the x double component (likewise with
4486 * z and w for double component y). The parameter @components represents
4487 * the number of 64-bit components present in @src. This would typically be
4488 * 2 at most, since we can only fit 2 double elements in the result of a
4491 * Notice that @dst and @src can be the same register.
4494 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4497 uint32_t components
)
4499 assert(type_sz(src
.type
) == 4);
4500 assert(type_sz(dst
.type
) == 8);
4502 /* A temporary that we will use to shuffle the 32-bit data of each
4503 * component in the vector into valid 64-bit data. We can't write directly
4504 * to dst because dst can be (and would usually be) the same as src
4505 * and in that case the first MOV in the loop below would overwrite the
4506 * data read in the second MOV.
4508 fs_reg tmp
= bld
.vgrf(dst
.type
);
4510 for (unsigned i
= 0; i
< components
; i
++) {
4511 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4513 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4514 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4516 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4521 * This helper does the inverse operation of
4522 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4524 * We need to do this when we are going to use untyped write messsages that
4525 * operate with 32-bit components in order to arrange our 64-bit data to be
4526 * in the expected layout.
4528 * Notice that callers of this function, unlike in the case of the inverse
4529 * operation, would typically need to call this with dst and src being
4530 * different registers, since they would otherwise corrupt the original
4531 * 64-bit data they are about to write. Because of this the function checks
4532 * that the src and dst regions involved in the operation do not overlap.
4535 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4538 uint32_t components
)
4540 assert(type_sz(src
.type
) == 8);
4541 assert(type_sz(dst
.type
) == 4);
4543 assert(!src
.in_range(dst
, 2 * components
* bld
.dispatch_width() / 8));
4545 for (unsigned i
= 0; i
< components
; i
++) {
4546 const fs_reg component_i
= offset(src
, bld
, i
);
4547 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4548 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4553 setup_imm_df(const fs_builder
&bld
, double v
)
4555 const struct brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4556 assert(devinfo
->gen
>= 7);
4558 if (devinfo
->gen
>= 8)
4559 return brw_imm_df(v
);
4561 /* gen7.5 does not support DF immediates straighforward but the DIM
4562 * instruction allows to set the 64-bit immediate value.
4564 if (devinfo
->is_haswell
) {
4565 const fs_builder ubld
= bld
.exec_all();
4566 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4567 ubld
.DIM(dst
, brw_imm_df(v
));
4568 return component(dst
, 0);
4571 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4572 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4573 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4575 * Alternatively, we could also produce a normal VGRF (without stride 0)
4576 * by writing to all the channels in the VGRF, however, that would hit the
4577 * gen7 bug where we have to split writes that span more than 1 register
4578 * into instructions with a width of 4 (otherwise the write to the second
4579 * register written runs into an execmask hardware bug) which isn't very
4592 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4593 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4594 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4595 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4597 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);