2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "program/prog_to_nir.h"
34 fs_visitor::emit_nir_code()
36 nir_shader
*nir
= prog
->nir
;
38 /* emit the arrays used for inputs and outputs - load/store intrinsics will
39 * be converted to reads/writes of these arrays
42 if (nir
->num_inputs
> 0) {
43 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
44 nir_setup_inputs(nir
);
47 if (nir
->num_outputs
> 0) {
48 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
49 nir_setup_outputs(nir
);
52 if (nir
->num_uniforms
> 0) {
53 nir_setup_uniforms(nir
);
56 nir_emit_system_values(nir
);
58 nir_globals
= ralloc_array(mem_ctx
, fs_reg
, nir
->reg_alloc
);
59 foreach_list_typed(nir_register
, reg
, node
, &nir
->registers
) {
60 unsigned array_elems
=
61 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
62 unsigned size
= array_elems
* reg
->num_components
;
63 nir_globals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
66 /* get the main function and emit it */
67 nir_foreach_overload(nir
, overload
) {
68 assert(strcmp(overload
->function
->name
, "main") == 0);
69 assert(overload
->impl
);
70 nir_emit_impl(overload
->impl
);
75 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
77 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
78 enum brw_reg_type type
= brw_type_for_base_type(var
->type
);
79 fs_reg input
= offset(nir_inputs
, var
->data
.driver_location
);
83 case MESA_SHADER_VERTEX
: {
84 /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
85 * stored in nir_variable::location.
87 * However, NIR's load_input intrinsics use a different index - an
88 * offset into a single contiguous array containing all inputs.
89 * This index corresponds to the nir_variable::driver_location field.
91 * So, we need to copy from fs_reg(ATTR, var->location) to
92 * offset(nir_inputs, var->data.driver_location).
94 unsigned components
= var
->type
->without_array()->components();
95 unsigned array_length
= var
->type
->is_array() ? var
->type
->length
: 1;
96 for (unsigned i
= 0; i
< array_length
; i
++) {
97 for (unsigned j
= 0; j
< components
; j
++) {
98 bld
.MOV(retype(offset(input
, components
* i
+ j
), type
),
99 offset(fs_reg(ATTR
, var
->data
.location
+ i
, type
), j
));
104 case MESA_SHADER_GEOMETRY
:
105 case MESA_SHADER_COMPUTE
:
106 unreachable("fs_visitor not used for these stages yet.");
108 case MESA_SHADER_FRAGMENT
:
109 if (var
->data
.location
== VARYING_SLOT_POS
) {
110 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
111 var
->data
.origin_upper_left
);
112 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, input
, reg
), 0xF);
114 emit_general_interpolation(input
, var
->name
, var
->type
,
115 (glsl_interp_qualifier
) var
->data
.interpolation
,
116 var
->data
.location
, var
->data
.centroid
,
125 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
127 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
129 foreach_list_typed(nir_variable
, var
, node
, &shader
->outputs
) {
130 fs_reg reg
= offset(nir_outputs
, var
->data
.driver_location
);
132 int vector_elements
=
133 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
134 : var
->type
->vector_elements
;
136 if (stage
== MESA_SHADER_VERTEX
) {
137 for (int i
= 0; i
< ALIGN(type_size(var
->type
), 4) / 4; i
++) {
138 int output
= var
->data
.location
+ i
;
139 this->outputs
[output
] = offset(reg
, 4 * i
);
140 this->output_components
[output
] = vector_elements
;
142 } else if (var
->data
.index
> 0) {
143 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
144 assert(var
->data
.index
== 1);
145 this->dual_src_output
= reg
;
146 this->do_dual_src
= true;
147 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
148 /* Writing gl_FragColor outputs to all color regions. */
149 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
150 this->outputs
[i
] = reg
;
151 this->output_components
[i
] = 4;
153 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
154 this->frag_depth
= reg
;
155 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
156 this->sample_mask
= reg
;
158 /* gl_FragData or a user-defined FS output */
159 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
160 var
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
162 /* General color output. */
163 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
164 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
165 this->outputs
[output
] = offset(reg
, vector_elements
* i
);
166 this->output_components
[output
] = vector_elements
;
173 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
175 uniforms
= shader
->num_uniforms
;
176 num_direct_uniforms
= shader
->num_direct_uniforms
;
178 /* We split the uniform register file in half. The first half is
179 * entirely direct uniforms. The second half is indirect.
181 param_size
[0] = num_direct_uniforms
;
182 if (shader
->num_uniforms
> num_direct_uniforms
)
183 param_size
[num_direct_uniforms
] = shader
->num_uniforms
- num_direct_uniforms
;
185 if (dispatch_width
!= 8)
189 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
190 /* UBO's and atomics don't take up space in the uniform file */
191 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
194 if (strncmp(var
->name
, "gl_", 3) == 0)
195 nir_setup_builtin_uniform(var
);
197 nir_setup_uniform(var
);
200 /* prog_to_nir doesn't create uniform variables; set param up directly. */
201 for (unsigned p
= 0; p
< prog
->Parameters
->NumParameters
; p
++) {
202 for (unsigned int i
= 0; i
< 4; i
++) {
203 stage_prog_data
->param
[4 * p
+ i
] =
204 &prog
->Parameters
->ParameterValues
[p
][i
];
211 fs_visitor::nir_setup_uniform(nir_variable
*var
)
213 int namelen
= strlen(var
->name
);
215 /* The data for our (non-builtin) uniforms is stored in a series of
216 * gl_uniform_driver_storage structs for each subcomponent that
217 * glGetUniformLocation() could name. We know it's been set up in the
218 * same order we'd walk the type, so walk the list of storage and find
219 * anything with our name, or the prefix of a component that starts with
222 unsigned index
= var
->data
.driver_location
;
223 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
224 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
226 if (storage
->builtin
)
229 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
230 (storage
->name
[namelen
] != 0 &&
231 storage
->name
[namelen
] != '.' &&
232 storage
->name
[namelen
] != '[')) {
236 unsigned slots
= storage
->type
->component_slots();
237 if (storage
->array_elements
)
238 slots
*= storage
->array_elements
;
240 for (unsigned i
= 0; i
< slots
; i
++) {
241 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
245 /* Make sure we actually initialized the right amount of stuff here. */
246 assert(var
->data
.driver_location
+ var
->type
->component_slots() == index
);
250 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
252 const nir_state_slot
*const slots
= var
->state_slots
;
253 assert(var
->state_slots
!= NULL
);
255 unsigned uniform_index
= var
->data
.driver_location
;
256 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
257 /* This state reference has already been setup by ir_to_mesa, but we'll
258 * get the same index back here.
260 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
261 (gl_state_index
*)slots
[i
].tokens
);
263 /* Add each of the unique swizzles of the element as a parameter.
264 * This'll end up matching the expected layout of the
265 * array/matrix/structure we're trying to fill in.
268 for (unsigned int j
= 0; j
< 4; j
++) {
269 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
270 if (swiz
== last_swiz
)
274 stage_prog_data
->param
[uniform_index
++] =
275 &prog
->Parameters
->ParameterValues
[index
][swiz
];
281 emit_system_values_block(nir_block
*block
, void *void_visitor
)
283 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
286 nir_foreach_instr(block
, instr
) {
287 if (instr
->type
!= nir_instr_type_intrinsic
)
290 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
291 switch (intrin
->intrinsic
) {
292 case nir_intrinsic_load_vertex_id
:
293 unreachable("should be lowered by lower_vertex_id().");
295 case nir_intrinsic_load_vertex_id_zero_base
:
296 assert(v
->stage
== MESA_SHADER_VERTEX
);
297 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
298 if (reg
->file
== BAD_FILE
)
299 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
302 case nir_intrinsic_load_base_vertex
:
303 assert(v
->stage
== MESA_SHADER_VERTEX
);
304 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
305 if (reg
->file
== BAD_FILE
)
306 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
309 case nir_intrinsic_load_instance_id
:
310 assert(v
->stage
== MESA_SHADER_VERTEX
);
311 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
312 if (reg
->file
== BAD_FILE
)
313 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
316 case nir_intrinsic_load_sample_pos
:
317 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
318 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
319 if (reg
->file
== BAD_FILE
)
320 *reg
= *v
->emit_samplepos_setup();
323 case nir_intrinsic_load_sample_id
:
324 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
325 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
326 if (reg
->file
== BAD_FILE
)
327 *reg
= *v
->emit_sampleid_setup();
330 case nir_intrinsic_load_sample_mask_in
:
331 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
332 assert(v
->devinfo
->gen
>= 7);
333 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
334 if (reg
->file
== BAD_FILE
)
335 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
336 BRW_REGISTER_TYPE_D
));
348 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
350 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
351 nir_foreach_overload(shader
, overload
) {
352 assert(strcmp(overload
->function
->name
, "main") == 0);
353 assert(overload
->impl
);
354 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
359 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
361 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
362 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
363 unsigned array_elems
=
364 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
365 unsigned size
= array_elems
* reg
->num_components
;
366 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
369 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
372 nir_emit_cf_list(&impl
->body
);
376 fs_visitor::nir_emit_cf_list(exec_list
*list
)
378 exec_list_validate(list
);
379 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
380 switch (node
->type
) {
382 nir_emit_if(nir_cf_node_as_if(node
));
385 case nir_cf_node_loop
:
386 nir_emit_loop(nir_cf_node_as_loop(node
));
389 case nir_cf_node_block
:
390 nir_emit_block(nir_cf_node_as_block(node
));
394 unreachable("Invalid CFG node block");
400 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
402 /* first, put the condition into f0 */
403 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
404 retype(get_nir_src(if_stmt
->condition
),
405 BRW_REGISTER_TYPE_D
));
406 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
408 bld
.IF(BRW_PREDICATE_NORMAL
);
410 nir_emit_cf_list(&if_stmt
->then_list
);
412 /* note: if the else is empty, dead CF elimination will remove it */
413 bld
.emit(BRW_OPCODE_ELSE
);
415 nir_emit_cf_list(&if_stmt
->else_list
);
417 bld
.emit(BRW_OPCODE_ENDIF
);
419 if (!try_replace_with_sel() && devinfo
->gen
< 6) {
420 no16("Can't support (non-uniform) control flow on SIMD16\n");
425 fs_visitor::nir_emit_loop(nir_loop
*loop
)
427 if (devinfo
->gen
< 6) {
428 no16("Can't support (non-uniform) control flow on SIMD16\n");
431 bld
.emit(BRW_OPCODE_DO
);
433 nir_emit_cf_list(&loop
->body
);
435 bld
.emit(BRW_OPCODE_WHILE
);
439 fs_visitor::nir_emit_block(nir_block
*block
)
441 nir_foreach_instr(block
, instr
) {
442 nir_emit_instr(instr
);
447 fs_visitor::nir_emit_instr(nir_instr
*instr
)
449 const fs_builder abld
= bld
.annotate(NULL
, instr
);
451 switch (instr
->type
) {
452 case nir_instr_type_alu
:
453 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
456 case nir_instr_type_intrinsic
:
457 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
460 case nir_instr_type_tex
:
461 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
464 case nir_instr_type_load_const
:
465 /* We can hit these, but we do nothing now and use them as
470 case nir_instr_type_ssa_undef
:
471 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
474 case nir_instr_type_jump
:
475 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
479 unreachable("unknown instruction type");
484 brw_type_for_nir_type(nir_alu_type type
)
487 case nir_type_unsigned
:
488 return BRW_REGISTER_TYPE_UD
;
491 return BRW_REGISTER_TYPE_D
;
493 return BRW_REGISTER_TYPE_F
;
495 unreachable("unknown type");
498 return BRW_REGISTER_TYPE_F
;
502 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
503 const fs_reg
&result
)
505 if (!instr
->src
[0].src
.is_ssa
||
506 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
509 nir_intrinsic_instr
*src0
=
510 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
512 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
515 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
516 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
519 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
520 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
523 fs_reg tmp
= vgrf(glsl_type::int_type
);
525 if (devinfo
->gen
>= 6) {
526 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
527 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
529 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
531 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
532 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
534 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
536 * This negation looks like it's safe in practice, because bits 0:4 will
537 * surely be TRIANGLES
540 if (value1
->f
[0] == -1.0f
) {
544 tmp
.type
= BRW_REGISTER_TYPE_W
;
545 tmp
.subreg_offset
= 2;
548 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
549 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
551 tmp
.type
= BRW_REGISTER_TYPE_D
;
552 tmp
.subreg_offset
= 0;
555 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
556 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
558 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
560 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
561 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
563 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
565 * This negation looks like it's safe in practice, because bits 0:4 will
566 * surely be TRIANGLES
569 if (value1
->f
[0] == -1.0f
) {
573 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
575 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
581 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
583 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
586 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
587 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
590 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
591 op
[i
] = get_nir_src(instr
->src
[i
].src
);
592 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
593 op
[i
].abs
= instr
->src
[i
].abs
;
594 op
[i
].negate
= instr
->src
[i
].negate
;
597 /* We get a bunch of mov's out of the from_ssa pass and they may still
598 * be vectorized. We'll handle them as a special-case. We'll also
599 * handle vecN here because it's basically the same thing.
607 fs_reg temp
= result
;
608 bool need_extra_copy
= false;
609 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
610 if (!instr
->src
[i
].src
.is_ssa
&&
611 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
612 need_extra_copy
= true;
613 temp
= bld
.vgrf(result
.type
, 4);
618 for (unsigned i
= 0; i
< 4; i
++) {
619 if (!(instr
->dest
.write_mask
& (1 << i
)))
622 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
623 inst
= bld
.MOV(offset(temp
, i
),
624 offset(op
[0], instr
->src
[0].swizzle
[i
]));
626 inst
= bld
.MOV(offset(temp
, i
),
627 offset(op
[i
], instr
->src
[i
].swizzle
[0]));
629 inst
->saturate
= instr
->dest
.saturate
;
632 /* In this case the source and destination registers were the same,
633 * so we need to insert an extra set of moves in order to deal with
636 if (need_extra_copy
) {
637 for (unsigned i
= 0; i
< 4; i
++) {
638 if (!(instr
->dest
.write_mask
& (1 << i
)))
641 bld
.MOV(offset(result
, i
), offset(temp
, i
));
650 /* At this point, we have dealt with any instruction that operates on
651 * more than a single channel. Therefore, we can just adjust the source
652 * and destination registers for that channel and emit the instruction.
654 unsigned channel
= 0;
655 if (nir_op_infos
[instr
->op
].output_size
== 0) {
656 /* Since NIR is doing the scalarizing for us, we should only ever see
657 * vectorized operations with a single channel.
659 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
660 channel
= ffs(instr
->dest
.write_mask
) - 1;
662 result
= offset(result
, channel
);
665 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
666 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
667 op
[i
] = offset(op
[i
], instr
->src
[i
].swizzle
[channel
]);
673 inst
= bld
.MOV(result
, op
[0]);
674 inst
->saturate
= instr
->dest
.saturate
;
679 bld
.MOV(result
, op
[0]);
683 /* AND(val, 0x80000000) gives the sign bit.
685 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
688 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
690 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
691 op
[0].type
= BRW_REGISTER_TYPE_UD
;
692 result
.type
= BRW_REGISTER_TYPE_UD
;
693 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
695 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
696 inst
->predicate
= BRW_PREDICATE_NORMAL
;
697 if (instr
->dest
.saturate
) {
698 inst
= bld
.MOV(result
, result
);
699 inst
->saturate
= true;
705 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
706 * -> non-negative val generates 0x00000000.
707 * Predicated OR sets 1 if val is positive.
709 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
710 bld
.ASR(result
, op
[0], fs_reg(31));
711 inst
= bld
.OR(result
, result
, fs_reg(1));
712 inst
->predicate
= BRW_PREDICATE_NORMAL
;
716 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
717 inst
->saturate
= instr
->dest
.saturate
;
721 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
722 inst
->saturate
= instr
->dest
.saturate
;
726 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
727 inst
->saturate
= instr
->dest
.saturate
;
731 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
732 inst
->saturate
= instr
->dest
.saturate
;
736 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
737 inst
->saturate
= instr
->dest
.saturate
;
741 if (fs_key
->high_quality_derivatives
) {
742 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
744 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
746 inst
->saturate
= instr
->dest
.saturate
;
748 case nir_op_fddx_fine
:
749 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
750 inst
->saturate
= instr
->dest
.saturate
;
752 case nir_op_fddx_coarse
:
753 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
754 inst
->saturate
= instr
->dest
.saturate
;
757 if (fs_key
->high_quality_derivatives
) {
758 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
759 fs_reg(fs_key
->render_to_fbo
));
761 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
762 fs_reg(fs_key
->render_to_fbo
));
764 inst
->saturate
= instr
->dest
.saturate
;
766 case nir_op_fddy_fine
:
767 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
768 fs_reg(fs_key
->render_to_fbo
));
769 inst
->saturate
= instr
->dest
.saturate
;
771 case nir_op_fddy_coarse
:
772 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
773 fs_reg(fs_key
->render_to_fbo
));
774 inst
->saturate
= instr
->dest
.saturate
;
779 inst
= bld
.ADD(result
, op
[0], op
[1]);
780 inst
->saturate
= instr
->dest
.saturate
;
784 inst
= bld
.MUL(result
, op
[0], op
[1]);
785 inst
->saturate
= instr
->dest
.saturate
;
789 bld
.MUL(result
, op
[0], op
[1]);
792 case nir_op_imul_high
:
793 case nir_op_umul_high
: {
794 if (devinfo
->gen
>= 7)
795 no16("SIMD16 explicit accumulator operands unsupported\n");
797 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
799 fs_inst
*mul
= bld
.MUL(acc
, op
[0], op
[1]);
800 bld
.MACH(result
, op
[0], op
[1]);
802 /* Until Gen8, integer multiplies read 32-bits from one source, and
803 * 16-bits from the other, and relying on the MACH instruction to
804 * generate the high bits of the result.
806 * On Gen8, the multiply instruction does a full 32x32-bit multiply,
807 * but in order to do a 64x64-bit multiply we have to simulate the
808 * previous behavior and then use a MACH instruction.
810 * FINISHME: Don't use source modifiers on src1.
812 if (devinfo
->gen
>= 8) {
813 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
814 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
815 if (mul
->src
[1].type
== BRW_REGISTER_TYPE_D
) {
816 mul
->src
[1].type
= BRW_REGISTER_TYPE_W
;
817 mul
->src
[1].stride
= 2;
819 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
820 mul
->src
[1].stride
= 2;
828 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
831 case nir_op_uadd_carry
: {
832 if (devinfo
->gen
>= 7)
833 no16("SIMD16 explicit accumulator operands unsupported\n");
835 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
836 BRW_REGISTER_TYPE_UD
);
838 bld
.ADDC(bld
.null_reg_ud(), op
[0], op
[1]);
839 bld
.MOV(result
, fs_reg(acc
));
843 case nir_op_usub_borrow
: {
844 if (devinfo
->gen
>= 7)
845 no16("SIMD16 explicit accumulator operands unsupported\n");
847 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
848 BRW_REGISTER_TYPE_UD
);
850 bld
.SUBB(bld
.null_reg_ud(), op
[0], op
[1]);
851 bld
.MOV(result
, fs_reg(acc
));
856 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
862 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
868 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
873 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
878 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
882 if (devinfo
->gen
>= 8) {
883 resolve_source_modifiers(&op
[0]);
885 bld
.NOT(result
, op
[0]);
888 if (devinfo
->gen
>= 8) {
889 resolve_source_modifiers(&op
[0]);
890 resolve_source_modifiers(&op
[1]);
892 bld
.XOR(result
, op
[0], op
[1]);
895 if (devinfo
->gen
>= 8) {
896 resolve_source_modifiers(&op
[0]);
897 resolve_source_modifiers(&op
[1]);
899 bld
.OR(result
, op
[0], op
[1]);
902 if (devinfo
->gen
>= 8) {
903 resolve_source_modifiers(&op
[0]);
904 resolve_source_modifiers(&op
[1]);
906 bld
.AND(result
, op
[0], op
[1]);
918 case nir_op_ball_fequal2
:
919 case nir_op_ball_iequal2
:
920 case nir_op_ball_fequal3
:
921 case nir_op_ball_iequal3
:
922 case nir_op_ball_fequal4
:
923 case nir_op_ball_iequal4
:
924 case nir_op_bany_fnequal2
:
925 case nir_op_bany_inequal2
:
926 case nir_op_bany_fnequal3
:
927 case nir_op_bany_inequal3
:
928 case nir_op_bany_fnequal4
:
929 case nir_op_bany_inequal4
:
930 unreachable("Lowered by nir_lower_alu_reductions");
932 case nir_op_fnoise1_1
:
933 case nir_op_fnoise1_2
:
934 case nir_op_fnoise1_3
:
935 case nir_op_fnoise1_4
:
936 case nir_op_fnoise2_1
:
937 case nir_op_fnoise2_2
:
938 case nir_op_fnoise2_3
:
939 case nir_op_fnoise2_4
:
940 case nir_op_fnoise3_1
:
941 case nir_op_fnoise3_2
:
942 case nir_op_fnoise3_3
:
943 case nir_op_fnoise3_4
:
944 case nir_op_fnoise4_1
:
945 case nir_op_fnoise4_2
:
946 case nir_op_fnoise4_3
:
947 case nir_op_fnoise4_4
:
948 unreachable("not reached: should be handled by lower_noise");
951 unreachable("not reached: should be handled by ldexp_to_arith()");
954 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
955 inst
->saturate
= instr
->dest
.saturate
;
959 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
960 inst
->saturate
= instr
->dest
.saturate
;
964 bld
.AND(result
, op
[0], fs_reg(1));
967 bld
.AND(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0], fs_reg(0x3f800000u
));
971 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
974 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
978 inst
= bld
.RNDZ(result
, op
[0]);
979 inst
->saturate
= instr
->dest
.saturate
;
983 op
[0].negate
= !op
[0].negate
;
984 fs_reg temp
= vgrf(glsl_type::float_type
);
985 bld
.RNDD(temp
, op
[0]);
987 inst
= bld
.MOV(result
, temp
);
988 inst
->saturate
= instr
->dest
.saturate
;
992 inst
= bld
.RNDD(result
, op
[0]);
993 inst
->saturate
= instr
->dest
.saturate
;
996 inst
= bld
.FRC(result
, op
[0]);
997 inst
->saturate
= instr
->dest
.saturate
;
999 case nir_op_fround_even
:
1000 inst
= bld
.RNDE(result
, op
[0]);
1001 inst
->saturate
= instr
->dest
.saturate
;
1007 if (devinfo
->gen
>= 6) {
1008 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1009 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1011 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
1012 inst
= bld
.SEL(result
, op
[0], op
[1]);
1013 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1015 inst
->saturate
= instr
->dest
.saturate
;
1021 if (devinfo
->gen
>= 6) {
1022 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1023 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1025 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
1026 inst
= bld
.SEL(result
, op
[0], op
[1]);
1027 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1029 inst
->saturate
= instr
->dest
.saturate
;
1032 case nir_op_pack_snorm_2x16
:
1033 case nir_op_pack_snorm_4x8
:
1034 case nir_op_pack_unorm_2x16
:
1035 case nir_op_pack_unorm_4x8
:
1036 case nir_op_unpack_snorm_2x16
:
1037 case nir_op_unpack_snorm_4x8
:
1038 case nir_op_unpack_unorm_2x16
:
1039 case nir_op_unpack_unorm_4x8
:
1040 case nir_op_unpack_half_2x16
:
1041 case nir_op_pack_half_2x16
:
1042 unreachable("not reached: should be handled by lower_packing_builtins");
1044 case nir_op_unpack_half_2x16_split_x
:
1045 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1046 inst
->saturate
= instr
->dest
.saturate
;
1048 case nir_op_unpack_half_2x16_split_y
:
1049 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1050 inst
->saturate
= instr
->dest
.saturate
;
1054 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1055 inst
->saturate
= instr
->dest
.saturate
;
1058 case nir_op_bitfield_reverse
:
1059 bld
.BFREV(result
, op
[0]);
1062 case nir_op_bit_count
:
1063 bld
.CBIT(result
, op
[0]);
1066 case nir_op_ufind_msb
:
1067 case nir_op_ifind_msb
: {
1068 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1070 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1071 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1072 * subtract the result from 31 to convert the MSB count into an LSB count.
1075 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
1076 fs_reg
neg_result(result
);
1077 neg_result
.negate
= true;
1078 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
1079 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1083 case nir_op_find_lsb
:
1084 bld
.FBL(result
, op
[0]);
1087 case nir_op_ubitfield_extract
:
1088 case nir_op_ibitfield_extract
:
1089 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1092 bld
.BFI1(result
, op
[0], op
[1]);
1095 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1098 case nir_op_bitfield_insert
:
1099 unreachable("not reached: should be handled by "
1100 "lower_instructions::bitfield_insert_to_bfm_bfi");
1103 bld
.SHL(result
, op
[0], op
[1]);
1106 bld
.ASR(result
, op
[0], op
[1]);
1109 bld
.SHR(result
, op
[0], op
[1]);
1112 case nir_op_pack_half_2x16_split
:
1113 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1117 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1118 inst
->saturate
= instr
->dest
.saturate
;
1122 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1123 inst
->saturate
= instr
->dest
.saturate
;
1127 if (optimize_frontfacing_ternary(instr
, result
))
1130 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
1131 inst
= bld
.SEL(result
, op
[1], op
[2]);
1132 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1136 unreachable("unhandled instruction");
1139 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1140 * to sign extend the low bit to 0/~0
1142 if (devinfo
->gen
<= 5 &&
1143 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1144 fs_reg masked
= vgrf(glsl_type::int_type
);
1145 bld
.AND(masked
, result
, fs_reg(1));
1146 masked
.negate
= true;
1147 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1152 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1154 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1155 instr
->def
.num_components
);
1159 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1160 unsigned base_offset
, nir_src
*indirect
)
1163 if (nir_reg
->is_global
)
1164 reg
= v
->nir_globals
[nir_reg
->index
];
1166 reg
= v
->nir_locals
[nir_reg
->index
];
1168 reg
= offset(reg
, base_offset
* nir_reg
->num_components
);
1170 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1172 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1173 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1174 fs_reg(multiplier
));
1181 fs_visitor::get_nir_src(nir_src src
)
1185 if (src
.ssa
->parent_instr
->type
== nir_instr_type_load_const
) {
1186 nir_load_const_instr
*load
=
1187 nir_instr_as_load_const(src
.ssa
->parent_instr
);
1188 reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, src
.ssa
->num_components
);
1190 for (unsigned i
= 0; i
< src
.ssa
->num_components
; ++i
)
1191 bld
.MOV(offset(reg
, i
), fs_reg(load
->value
.i
[i
]));
1193 reg
= nir_ssa_values
[src
.ssa
->index
];
1196 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1200 /* to avoid floating-point denorm flushing problems, set the type by
1201 * default to D - instructions that need floating point semantics will set
1202 * this to F if they need to
1204 return retype(reg
, BRW_REGISTER_TYPE_D
);
1208 fs_visitor::get_nir_dest(nir_dest dest
)
1211 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1212 dest
.ssa
.num_components
);
1213 return nir_ssa_values
[dest
.ssa
.index
];
1216 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1221 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1224 for (unsigned i
= 0; i
< 4; i
++) {
1225 if (!((wr_mask
>> i
) & 1))
1228 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1229 new_inst
->dst
= offset(new_inst
->dst
, i
);
1230 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1231 if (new_inst
->src
[j
].file
== GRF
)
1232 new_inst
->src
[j
] = offset(new_inst
->src
[j
], i
);
1239 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1242 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1243 dest
= get_nir_dest(instr
->dest
);
1245 bool has_indirect
= false;
1247 switch (instr
->intrinsic
) {
1248 case nir_intrinsic_discard
:
1249 case nir_intrinsic_discard_if
: {
1250 /* We track our discarded pixels in f0.1. By predicating on it, we can
1251 * update just the flag bits that aren't yet discarded. If there's no
1252 * condition, we emit a CMP of g0 != g0, so all currently executing
1253 * channels will get turned off.
1256 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1257 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1258 fs_reg(0), BRW_CONDITIONAL_Z
);
1260 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1261 BRW_REGISTER_TYPE_UW
));
1262 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1264 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1265 cmp
->flag_subreg
= 1;
1267 if (devinfo
->gen
>= 6) {
1268 emit_discard_jump();
1273 case nir_intrinsic_atomic_counter_inc
:
1274 case nir_intrinsic_atomic_counter_dec
:
1275 case nir_intrinsic_atomic_counter_read
: {
1276 unsigned surf_index
= prog_data
->binding_table
.abo_start
+
1277 (unsigned) instr
->const_index
[0];
1278 fs_reg offset
= fs_reg(get_nir_src(instr
->src
[0]));
1280 switch (instr
->intrinsic
) {
1281 case nir_intrinsic_atomic_counter_inc
:
1282 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
1283 fs_reg(), fs_reg());
1285 case nir_intrinsic_atomic_counter_dec
:
1286 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
1287 fs_reg(), fs_reg());
1289 case nir_intrinsic_atomic_counter_read
:
1290 emit_untyped_surface_read(surf_index
, dest
, offset
);
1293 unreachable("Unreachable");
1298 case nir_intrinsic_load_front_face
:
1299 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1300 *emit_frontfacing_interpolation());
1303 case nir_intrinsic_load_vertex_id
:
1304 unreachable("should be lowered by lower_vertex_id()");
1306 case nir_intrinsic_load_vertex_id_zero_base
: {
1307 fs_reg vertex_id
= nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
1308 assert(vertex_id
.file
!= BAD_FILE
);
1309 dest
.type
= vertex_id
.type
;
1310 bld
.MOV(dest
, vertex_id
);
1314 case nir_intrinsic_load_base_vertex
: {
1315 fs_reg base_vertex
= nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
1316 assert(base_vertex
.file
!= BAD_FILE
);
1317 dest
.type
= base_vertex
.type
;
1318 bld
.MOV(dest
, base_vertex
);
1322 case nir_intrinsic_load_instance_id
: {
1323 fs_reg instance_id
= nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
1324 assert(instance_id
.file
!= BAD_FILE
);
1325 dest
.type
= instance_id
.type
;
1326 bld
.MOV(dest
, instance_id
);
1330 case nir_intrinsic_load_sample_mask_in
: {
1331 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1332 assert(sample_mask_in
.file
!= BAD_FILE
);
1333 dest
.type
= sample_mask_in
.type
;
1334 bld
.MOV(dest
, sample_mask_in
);
1338 case nir_intrinsic_load_sample_pos
: {
1339 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1340 assert(sample_pos
.file
!= BAD_FILE
);
1341 dest
.type
= sample_pos
.type
;
1342 bld
.MOV(dest
, sample_pos
);
1343 bld
.MOV(offset(dest
, 1), offset(sample_pos
, 1));
1347 case nir_intrinsic_load_sample_id
: {
1348 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1349 assert(sample_id
.file
!= BAD_FILE
);
1350 dest
.type
= sample_id
.type
;
1351 bld
.MOV(dest
, sample_id
);
1355 case nir_intrinsic_load_uniform_indirect
:
1356 has_indirect
= true;
1358 case nir_intrinsic_load_uniform
: {
1359 unsigned index
= instr
->const_index
[0];
1362 if (index
< num_direct_uniforms
) {
1363 uniform_reg
= fs_reg(UNIFORM
, 0);
1365 uniform_reg
= fs_reg(UNIFORM
, num_direct_uniforms
);
1366 index
-= num_direct_uniforms
;
1369 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1370 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), index
);
1372 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1376 dest
= offset(dest
, 1);
1381 case nir_intrinsic_load_ubo_indirect
:
1382 has_indirect
= true;
1384 case nir_intrinsic_load_ubo
: {
1385 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1389 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1392 /* The block index is not a constant. Evaluate the index expression
1393 * per-channel and add the base UBO index; we have to select a value
1394 * from any live channel.
1396 surf_index
= vgrf(glsl_type::uint_type
);
1397 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1398 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1399 bld
.emit_uniformize(surf_index
, surf_index
);
1401 /* Assume this may touch any UBO. It would be nice to provide
1402 * a tighter bound, but the array information is already lowered away.
1404 brw_mark_surface_used(prog_data
,
1405 stage_prog_data
->binding_table
.ubo_start
+
1406 shader_prog
->NumUniformBlocks
- 1);
1410 /* Turn the byte offset into a dword offset. */
1411 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1412 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1413 BRW_REGISTER_TYPE_D
),
1416 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1417 for (int i
= 0; i
< instr
->num_components
; i
++)
1418 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, i
), surf_index
,
1419 base_offset
, vec4_offset
+ i
);
1421 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1422 packed_consts
.type
= dest
.type
;
1424 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1425 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1426 surf_index
, const_offset_reg
);
1428 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1429 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1431 /* The std140 packing rules don't allow vectors to cross 16-byte
1432 * boundaries, and a reg is 32 bytes.
1434 assert(packed_consts
.subreg_offset
< 32);
1436 bld
.MOV(dest
, packed_consts
);
1437 dest
= offset(dest
, 1);
1443 case nir_intrinsic_load_input_indirect
:
1444 has_indirect
= true;
1446 case nir_intrinsic_load_input
: {
1448 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1449 fs_reg src
= offset(retype(nir_inputs
, dest
.type
),
1450 instr
->const_index
[0] + index
);
1452 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1456 dest
= offset(dest
, 1);
1461 /* Handle ARB_gpu_shader5 interpolation intrinsics
1463 * It's worth a quick word of explanation as to why we handle the full
1464 * variable-based interpolation intrinsic rather than a lowered version
1465 * with like we do for other inputs. We have to do that because the way
1466 * we set up inputs doesn't allow us to use the already setup inputs for
1467 * interpolation. At the beginning of the shader, we go through all of
1468 * the input variables and do the initial interpolation and put it in
1469 * the nir_inputs array based on its location as determined in
1470 * nir_lower_io. If the input isn't used, dead code cleans up and
1471 * everything works fine. However, when we get to the ARB_gpu_shader5
1472 * interpolation intrinsics, we need to reinterpolate the input
1473 * differently. If we used an intrinsic that just had an index it would
1474 * only give us the offset into the nir_inputs array. However, this is
1475 * useless because that value is post-interpolation and we need
1476 * pre-interpolation. In order to get the actual location of the bits
1477 * we get from the vertex fetching hardware, we need the variable.
1479 case nir_intrinsic_interp_var_at_centroid
:
1480 case nir_intrinsic_interp_var_at_sample
:
1481 case nir_intrinsic_interp_var_at_offset
: {
1482 /* in SIMD16 mode, the pixel interpolator returns coords interleaved
1483 * 8 channels at a time, same as the barycentric coords presented in
1484 * the FS payload. this requires a bit of extra work to support.
1486 no16("interpolate_at_* not yet supported in SIMD16 mode.");
1488 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1490 /* For most messages, we need one reg of ignored data; the hardware
1491 * requires mlen==1 even when there is no payload. in the per-slot
1492 * offset case, we'll replace this with the proper source data.
1494 fs_reg src
= vgrf(glsl_type::float_type
);
1495 int mlen
= 1; /* one reg unless overriden */
1498 switch (instr
->intrinsic
) {
1499 case nir_intrinsic_interp_var_at_centroid
:
1500 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1501 dst_xy
, src
, fs_reg(0u));
1504 case nir_intrinsic_interp_var_at_sample
: {
1505 /* XXX: We should probably handle non-constant sample id's */
1506 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1507 assert(const_sample
);
1508 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1509 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_xy
, src
,
1514 case nir_intrinsic_interp_var_at_offset
: {
1515 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1518 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1519 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1521 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_xy
, src
,
1522 fs_reg(off_x
| (off_y
<< 4)));
1524 src
= vgrf(glsl_type::ivec2_type
);
1525 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1526 BRW_REGISTER_TYPE_F
);
1527 for (int i
= 0; i
< 2; i
++) {
1528 fs_reg temp
= vgrf(glsl_type::float_type
);
1529 bld
.MUL(temp
, offset(offset_src
, i
), fs_reg(16.0f
));
1530 fs_reg itemp
= vgrf(glsl_type::int_type
);
1531 bld
.MOV(itemp
, temp
); /* float to int */
1533 /* Clamp the upper end of the range to +7/16.
1534 * ARB_gpu_shader5 requires that we support a maximum offset
1535 * of +0.5, which isn't representable in a S0.4 value -- if
1536 * we didn't clamp it, we'd end up with -8/16, which is the
1537 * opposite of what the shader author wanted.
1539 * This is legal due to ARB_gpu_shader5's quantization
1542 * "Not all values of <offset> may be supported; x and y
1543 * offsets may be rounded to fixed-point values with the
1544 * number of fraction bits given by the
1545 * implementation-dependent constant
1546 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1548 set_condmod(BRW_CONDITIONAL_L
,
1549 bld
.SEL(offset(src
, i
), itemp
, fs_reg(7)));
1553 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_xy
, src
,
1560 unreachable("Invalid intrinsic");
1564 inst
->regs_written
= 2; /* 2 floats per slot returned */
1565 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1566 INTERP_QUALIFIER_NOPERSPECTIVE
;
1568 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1569 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1570 src
.type
= dest
.type
;
1572 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1573 dest
= offset(dest
, 1);
1578 case nir_intrinsic_store_output_indirect
:
1579 has_indirect
= true;
1581 case nir_intrinsic_store_output
: {
1582 fs_reg src
= get_nir_src(instr
->src
[0]);
1584 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1585 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
),
1586 instr
->const_index
[0] + index
);
1588 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1590 bld
.MOV(new_dest
, src
);
1591 src
= offset(src
, 1);
1596 case nir_intrinsic_barrier
:
1601 unreachable("unknown intrinsic");
1606 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1608 unsigned sampler
= instr
->sampler_index
;
1609 fs_reg
sampler_reg(sampler
);
1611 /* FINISHME: We're failing to recompile our programs when the sampler is
1612 * updated. This only matters for the texture rectangle scale parameters
1613 * (pre-gen6, or gen6+ with GL_CLAMP).
1615 int texunit
= prog
->SamplerUnits
[sampler
];
1617 int gather_component
= instr
->component
;
1619 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1621 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1624 int lod_components
= 0;
1625 int UNUSED offset_components
= 0;
1627 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1629 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1630 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1631 switch (instr
->src
[i
].src_type
) {
1632 case nir_tex_src_bias
:
1633 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1635 case nir_tex_src_comparitor
:
1636 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1638 case nir_tex_src_coord
:
1639 switch (instr
->op
) {
1641 case nir_texop_txf_ms
:
1642 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1645 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1649 case nir_tex_src_ddx
:
1650 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1651 lod_components
= nir_tex_instr_src_size(instr
, i
);
1653 case nir_tex_src_ddy
:
1654 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1656 case nir_tex_src_lod
:
1657 switch (instr
->op
) {
1659 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1662 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1665 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1669 case nir_tex_src_ms_index
:
1670 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1672 case nir_tex_src_offset
:
1673 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1674 if (instr
->is_array
)
1675 offset_components
= instr
->coord_components
- 1;
1677 offset_components
= instr
->coord_components
;
1679 case nir_tex_src_projector
:
1680 unreachable("should be lowered");
1682 case nir_tex_src_sampler_offset
: {
1683 /* Figure out the highest possible sampler index and mark it as used */
1684 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1685 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
1686 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1688 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1690 brw_mark_surface_used(prog_data
, max_used
);
1692 /* Emit code to evaluate the actual indexing expression */
1693 sampler_reg
= vgrf(glsl_type::uint_type
);
1694 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
1695 bld
.emit_uniformize(sampler_reg
, sampler_reg
);
1700 unreachable("unknown texture source");
1704 if (instr
->op
== nir_texop_txf_ms
) {
1705 if (devinfo
->gen
>= 7 &&
1706 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1707 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1713 for (unsigned i
= 0; i
< 3; i
++) {
1714 if (instr
->const_offset
[i
] != 0) {
1715 assert(offset_components
== 0);
1716 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
1721 enum glsl_base_type dest_base_type
;
1722 switch (instr
->dest_type
) {
1723 case nir_type_float
:
1724 dest_base_type
= GLSL_TYPE_FLOAT
;
1727 dest_base_type
= GLSL_TYPE_INT
;
1729 case nir_type_unsigned
:
1730 dest_base_type
= GLSL_TYPE_UINT
;
1733 unreachable("bad type");
1736 const glsl_type
*dest_type
=
1737 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1740 ir_texture_opcode op
;
1741 switch (instr
->op
) {
1742 case nir_texop_lod
: op
= ir_lod
; break;
1743 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1744 case nir_texop_tex
: op
= ir_tex
; break;
1745 case nir_texop_tg4
: op
= ir_tg4
; break;
1746 case nir_texop_txb
: op
= ir_txb
; break;
1747 case nir_texop_txd
: op
= ir_txd
; break;
1748 case nir_texop_txf
: op
= ir_txf
; break;
1749 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1750 case nir_texop_txl
: op
= ir_txl
; break;
1751 case nir_texop_txs
: op
= ir_txs
; break;
1753 unreachable("unknown texture opcode");
1756 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1757 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1758 tex_offset
, mcs
, gather_component
,
1759 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1761 fs_reg dest
= get_nir_dest(instr
->dest
);
1762 dest
.type
= this->result
.type
;
1763 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1764 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, dest
, this->result
),
1765 (1 << num_components
) - 1);
1769 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
1771 switch (instr
->type
) {
1772 case nir_jump_break
:
1773 bld
.emit(BRW_OPCODE_BREAK
);
1775 case nir_jump_continue
:
1776 bld
.emit(BRW_OPCODE_CONTINUE
);
1778 case nir_jump_return
:
1780 unreachable("unknown jump");