2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "program/prog_to_nir.h"
32 nir_optimize(nir_shader
*nir
)
37 nir_lower_vars_to_ssa(nir
);
38 nir_validate_shader(nir
);
39 nir_lower_alu_to_scalar(nir
);
40 nir_validate_shader(nir
);
41 progress
|= nir_copy_prop(nir
);
42 nir_validate_shader(nir
);
43 nir_lower_phis_to_scalar(nir
);
44 nir_validate_shader(nir
);
45 progress
|= nir_copy_prop(nir
);
46 nir_validate_shader(nir
);
47 progress
|= nir_opt_dce(nir
);
48 nir_validate_shader(nir
);
49 progress
|= nir_opt_cse(nir
);
50 nir_validate_shader(nir
);
51 progress
|= nir_opt_peephole_select(nir
);
52 nir_validate_shader(nir
);
53 progress
|= nir_opt_algebraic(nir
);
54 nir_validate_shader(nir
);
55 progress
|= nir_opt_constant_folding(nir
);
56 nir_validate_shader(nir
);
57 progress
|= nir_opt_remove_phis(nir
);
58 nir_validate_shader(nir
);
63 count_nir_instrs_in_block(nir_block
*block
, void *state
)
65 int *count
= (int *) state
;
66 nir_foreach_instr(block
, instr
) {
73 count_nir_instrs(nir_shader
*nir
)
76 nir_foreach_overload(nir
, overload
) {
79 nir_foreach_block(overload
->impl
, count_nir_instrs_in_block
, &count
);
85 fs_visitor::emit_nir_code()
87 const nir_shader_compiler_options
*options
=
88 ctx
->Const
.ShaderCompilerOptions
[stage
].NirOptions
;
91 /* First, lower the GLSL IR or Mesa IR to NIR */
93 lower_output_reads(shader
->base
.ir
);
94 nir
= glsl_to_nir(&shader
->base
, options
);
96 nir
= prog_to_nir(prog
, options
);
97 nir_convert_to_ssa(nir
); /* turn registers into SSA */
99 nir_validate_shader(nir
);
101 nir_lower_global_vars_to_local(nir
);
102 nir_validate_shader(nir
);
104 nir_split_var_copies(nir
);
105 nir_validate_shader(nir
);
109 /* Lower a bunch of stuff */
110 nir_lower_var_copies(nir
);
111 nir_validate_shader(nir
);
113 /* Get rid of split copies */
117 nir_assign_var_locations_scalar_direct_first(nir
, &nir
->uniforms
,
118 &num_direct_uniforms
,
121 /* ARB programs generally create a giant array of "uniform" data, and allow
122 * indirect addressing without any boundaries. In the absence of bounds
123 * analysis, it's all or nothing. num_direct_uniforms is only useful when
124 * we have some direct and some indirect access; it doesn't matter here.
126 num_direct_uniforms
= 0;
128 nir_assign_var_locations_scalar(&nir
->inputs
, &nir
->num_inputs
);
129 nir_assign_var_locations_scalar(&nir
->outputs
, &nir
->num_outputs
);
132 nir_validate_shader(nir
);
134 nir_remove_dead_variables(nir
);
135 nir_validate_shader(nir
);
138 nir_lower_samplers(nir
, shader_prog
, shader
->base
.Program
);
139 nir_validate_shader(nir
);
142 nir_lower_system_values(nir
);
143 nir_validate_shader(nir
);
145 nir_lower_atomics(nir
);
146 nir_validate_shader(nir
);
150 nir_lower_locals_to_regs(nir
);
151 nir_validate_shader(nir
);
153 nir_lower_to_source_mods(nir
);
154 nir_validate_shader(nir
);
156 nir_validate_shader(nir
);
158 if (unlikely(debug_enabled
)) {
159 fprintf(stderr
, "NIR (SSA form) for %s shader:\n", stage_name
);
160 nir_print_shader(nir
, stderr
);
163 if (dispatch_width
== 8) {
164 static GLuint msg_id
= 0;
165 _mesa_gl_debug(&brw
->ctx
, &msg_id
,
166 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
167 MESA_DEBUG_TYPE_OTHER
,
168 MESA_DEBUG_SEVERITY_NOTIFICATION
,
169 "%s NIR shader: %d inst\n",
171 count_nir_instrs(nir
));
174 nir_convert_from_ssa(nir
);
175 nir_validate_shader(nir
);
177 /* This is the last pass we run before we start emitting stuff. It
178 * determines when we need to insert boolean resolves on Gen <= 5. We
179 * run it last because it stashes data in instr->pass_flags and we don't
180 * want that to be squashed by other NIR passes.
183 brw_nir_analyze_boolean_resolves(nir
);
185 /* emit the arrays used for inputs and outputs - load/store intrinsics will
186 * be converted to reads/writes of these arrays
189 if (nir
->num_inputs
> 0) {
190 nir_inputs
= vgrf(nir
->num_inputs
);
191 nir_setup_inputs(nir
);
194 if (nir
->num_outputs
> 0) {
195 nir_outputs
= vgrf(nir
->num_outputs
);
196 nir_setup_outputs(nir
);
199 if (nir
->num_uniforms
> 0) {
200 nir_setup_uniforms(nir
);
203 nir_emit_system_values(nir
);
205 nir_globals
= ralloc_array(mem_ctx
, fs_reg
, nir
->reg_alloc
);
206 foreach_list_typed(nir_register
, reg
, node
, &nir
->registers
) {
207 unsigned array_elems
=
208 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
209 unsigned size
= array_elems
* reg
->num_components
;
210 nir_globals
[reg
->index
] = vgrf(size
);
213 /* get the main function and emit it */
214 nir_foreach_overload(nir
, overload
) {
215 assert(strcmp(overload
->function
->name
, "main") == 0);
216 assert(overload
->impl
);
217 nir_emit_impl(overload
->impl
);
220 if (unlikely(debug_enabled
)) {
221 fprintf(stderr
, "NIR (final form) for %s shader:\n", stage_name
);
222 nir_print_shader(nir
, stderr
);
229 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
231 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
232 enum brw_reg_type type
= brw_type_for_base_type(var
->type
);
233 fs_reg input
= offset(nir_inputs
, var
->data
.driver_location
);
237 case MESA_SHADER_VERTEX
: {
238 /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
239 * stored in nir_variable::location.
241 * However, NIR's load_input intrinsics use a different index - an
242 * offset into a single contiguous array containing all inputs.
243 * This index corresponds to the nir_variable::driver_location field.
245 * So, we need to copy from fs_reg(ATTR, var->location) to
246 * offset(nir_inputs, var->data.driver_location).
248 unsigned components
= var
->type
->without_array()->components();
249 unsigned array_length
= var
->type
->is_array() ? var
->type
->length
: 1;
250 for (unsigned i
= 0; i
< array_length
; i
++) {
251 for (unsigned j
= 0; j
< components
; j
++) {
252 emit(MOV(retype(offset(input
, components
* i
+ j
), type
),
253 offset(fs_reg(ATTR
, var
->data
.location
+ i
, type
), j
)));
258 case MESA_SHADER_GEOMETRY
:
259 case MESA_SHADER_COMPUTE
:
260 unreachable("fs_visitor not used for these stages yet.");
262 case MESA_SHADER_FRAGMENT
:
263 if (var
->data
.location
== VARYING_SLOT_POS
) {
264 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
265 var
->data
.origin_upper_left
);
266 emit_percomp(MOV(input
, reg
), 0xF);
268 emit_general_interpolation(input
, var
->name
, var
->type
,
269 (glsl_interp_qualifier
) var
->data
.interpolation
,
270 var
->data
.location
, var
->data
.centroid
,
279 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
281 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
283 foreach_list_typed(nir_variable
, var
, node
, &shader
->outputs
) {
284 fs_reg reg
= offset(nir_outputs
, var
->data
.driver_location
);
286 int vector_elements
=
287 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
288 : var
->type
->vector_elements
;
290 if (stage
== MESA_SHADER_VERTEX
) {
291 for (int i
= 0; i
< ALIGN(type_size(var
->type
), 4) / 4; i
++) {
292 int output
= var
->data
.location
+ i
;
293 this->outputs
[output
] = offset(reg
, 4 * i
);
294 this->output_components
[output
] = vector_elements
;
296 } else if (var
->data
.index
> 0) {
297 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
298 assert(var
->data
.index
== 1);
299 this->dual_src_output
= reg
;
300 this->do_dual_src
= true;
301 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
302 /* Writing gl_FragColor outputs to all color regions. */
303 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
304 this->outputs
[i
] = reg
;
305 this->output_components
[i
] = 4;
307 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
308 this->frag_depth
= reg
;
309 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
310 this->sample_mask
= reg
;
312 /* gl_FragData or a user-defined FS output */
313 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
314 var
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
316 /* General color output. */
317 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
318 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
319 this->outputs
[output
] = offset(reg
, vector_elements
* i
);
320 this->output_components
[output
] = vector_elements
;
327 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
329 uniforms
= shader
->num_uniforms
;
331 /* We split the uniform register file in half. The first half is
332 * entirely direct uniforms. The second half is indirect.
334 param_size
[0] = num_direct_uniforms
;
335 if (shader
->num_uniforms
> num_direct_uniforms
)
336 param_size
[num_direct_uniforms
] = shader
->num_uniforms
- num_direct_uniforms
;
338 if (dispatch_width
!= 8)
342 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
343 /* UBO's and atomics don't take up space in the uniform file */
344 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
347 if (strncmp(var
->name
, "gl_", 3) == 0)
348 nir_setup_builtin_uniform(var
);
350 nir_setup_uniform(var
);
353 /* prog_to_nir doesn't create uniform variables; set param up directly. */
354 for (unsigned p
= 0; p
< prog
->Parameters
->NumParameters
; p
++) {
355 for (unsigned int i
= 0; i
< 4; i
++) {
356 stage_prog_data
->param
[4 * p
+ i
] =
357 &prog
->Parameters
->ParameterValues
[p
][i
];
364 fs_visitor::nir_setup_uniform(nir_variable
*var
)
366 int namelen
= strlen(var
->name
);
368 /* The data for our (non-builtin) uniforms is stored in a series of
369 * gl_uniform_driver_storage structs for each subcomponent that
370 * glGetUniformLocation() could name. We know it's been set up in the
371 * same order we'd walk the type, so walk the list of storage and find
372 * anything with our name, or the prefix of a component that starts with
375 unsigned index
= var
->data
.driver_location
;
376 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
377 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
379 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
380 (storage
->name
[namelen
] != 0 &&
381 storage
->name
[namelen
] != '.' &&
382 storage
->name
[namelen
] != '[')) {
386 unsigned slots
= storage
->type
->component_slots();
387 if (storage
->array_elements
)
388 slots
*= storage
->array_elements
;
390 for (unsigned i
= 0; i
< slots
; i
++) {
391 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
395 /* Make sure we actually initialized the right amount of stuff here. */
396 assert(var
->data
.driver_location
+ var
->type
->component_slots() == index
);
400 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
402 const nir_state_slot
*const slots
= var
->state_slots
;
403 assert(var
->state_slots
!= NULL
);
405 unsigned uniform_index
= var
->data
.driver_location
;
406 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
407 /* This state reference has already been setup by ir_to_mesa, but we'll
408 * get the same index back here.
410 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
411 (gl_state_index
*)slots
[i
].tokens
);
413 /* Add each of the unique swizzles of the element as a parameter.
414 * This'll end up matching the expected layout of the
415 * array/matrix/structure we're trying to fill in.
418 for (unsigned int j
= 0; j
< 4; j
++) {
419 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
420 if (swiz
== last_swiz
)
424 stage_prog_data
->param
[uniform_index
++] =
425 &prog
->Parameters
->ParameterValues
[index
][swiz
];
431 emit_system_values_block(nir_block
*block
, void *void_visitor
)
433 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
436 nir_foreach_instr(block
, instr
) {
437 if (instr
->type
!= nir_instr_type_intrinsic
)
440 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
441 switch (intrin
->intrinsic
) {
442 case nir_intrinsic_load_vertex_id
:
443 unreachable("should be lowered by lower_vertex_id().");
445 case nir_intrinsic_load_vertex_id_zero_base
:
446 assert(v
->stage
== MESA_SHADER_VERTEX
);
447 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
448 if (reg
->file
== BAD_FILE
)
449 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
452 case nir_intrinsic_load_base_vertex
:
453 assert(v
->stage
== MESA_SHADER_VERTEX
);
454 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
455 if (reg
->file
== BAD_FILE
)
456 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
459 case nir_intrinsic_load_instance_id
:
460 assert(v
->stage
== MESA_SHADER_VERTEX
);
461 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
462 if (reg
->file
== BAD_FILE
)
463 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
466 case nir_intrinsic_load_sample_pos
:
467 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
468 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
469 if (reg
->file
== BAD_FILE
)
470 *reg
= *v
->emit_samplepos_setup();
473 case nir_intrinsic_load_sample_id
:
474 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
475 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
476 if (reg
->file
== BAD_FILE
)
477 *reg
= *v
->emit_sampleid_setup();
480 case nir_intrinsic_load_sample_mask_in
:
481 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
482 assert(v
->brw
->gen
>= 7);
483 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
484 if (reg
->file
== BAD_FILE
)
485 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
486 BRW_REGISTER_TYPE_D
));
498 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
500 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
501 nir_foreach_overload(shader
, overload
) {
502 assert(strcmp(overload
->function
->name
, "main") == 0);
503 assert(overload
->impl
);
504 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
509 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
511 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
512 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
513 unsigned array_elems
=
514 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
515 unsigned size
= array_elems
* reg
->num_components
;
516 nir_locals
[reg
->index
] = vgrf(size
);
519 nir_emit_cf_list(&impl
->body
);
523 fs_visitor::nir_emit_cf_list(exec_list
*list
)
525 exec_list_validate(list
);
526 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
527 switch (node
->type
) {
529 nir_emit_if(nir_cf_node_as_if(node
));
532 case nir_cf_node_loop
:
533 nir_emit_loop(nir_cf_node_as_loop(node
));
536 case nir_cf_node_block
:
537 nir_emit_block(nir_cf_node_as_block(node
));
541 unreachable("Invalid CFG node block");
547 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
549 /* first, put the condition into f0 */
550 fs_inst
*inst
= emit(MOV(reg_null_d
,
551 retype(get_nir_src(if_stmt
->condition
),
552 BRW_REGISTER_TYPE_D
)));
553 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
555 emit(IF(BRW_PREDICATE_NORMAL
));
557 nir_emit_cf_list(&if_stmt
->then_list
);
559 /* note: if the else is empty, dead CF elimination will remove it */
560 emit(BRW_OPCODE_ELSE
);
562 nir_emit_cf_list(&if_stmt
->else_list
);
564 emit(BRW_OPCODE_ENDIF
);
566 if (!try_replace_with_sel() && brw
->gen
< 6) {
567 no16("Can't support (non-uniform) control flow on SIMD16\n");
572 fs_visitor::nir_emit_loop(nir_loop
*loop
)
575 no16("Can't support (non-uniform) control flow on SIMD16\n");
580 nir_emit_cf_list(&loop
->body
);
582 emit(BRW_OPCODE_WHILE
);
586 fs_visitor::nir_emit_block(nir_block
*block
)
588 nir_foreach_instr(block
, instr
) {
589 nir_emit_instr(instr
);
594 fs_visitor::nir_emit_instr(nir_instr
*instr
)
596 switch (instr
->type
) {
597 case nir_instr_type_alu
:
598 nir_emit_alu(nir_instr_as_alu(instr
));
601 case nir_instr_type_intrinsic
:
602 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
605 case nir_instr_type_tex
:
606 nir_emit_texture(nir_instr_as_tex(instr
));
609 case nir_instr_type_load_const
:
610 /* We can hit these, but we do nothing now and use them as
615 case nir_instr_type_jump
:
616 nir_emit_jump(nir_instr_as_jump(instr
));
620 unreachable("unknown instruction type");
625 brw_type_for_nir_type(nir_alu_type type
)
628 case nir_type_unsigned
:
629 return BRW_REGISTER_TYPE_UD
;
632 return BRW_REGISTER_TYPE_D
;
634 return BRW_REGISTER_TYPE_F
;
636 unreachable("unknown type");
639 return BRW_REGISTER_TYPE_F
;
643 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
644 const fs_reg
&result
)
646 if (instr
->src
[0].src
.is_ssa
||
647 !instr
->src
[0].src
.reg
.reg
||
648 !instr
->src
[0].src
.reg
.reg
->parent_instr
)
651 if (instr
->src
[0].src
.reg
.reg
->parent_instr
->type
!=
652 nir_instr_type_intrinsic
)
655 nir_intrinsic_instr
*src0
=
656 nir_instr_as_intrinsic(instr
->src
[0].src
.reg
.reg
->parent_instr
);
658 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
661 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
662 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
665 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
666 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
669 fs_reg tmp
= vgrf(glsl_type::int_type
);
672 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
673 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
675 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
677 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
678 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
680 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
682 * This negation looks like it's safe in practice, because bits 0:4 will
683 * surely be TRIANGLES
686 if (value1
->f
[0] == -1.0f
) {
690 tmp
.type
= BRW_REGISTER_TYPE_W
;
691 tmp
.subreg_offset
= 2;
694 fs_inst
*or_inst
= emit(OR(tmp
, g0
, fs_reg(0x3f80)));
695 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
697 tmp
.type
= BRW_REGISTER_TYPE_D
;
698 tmp
.subreg_offset
= 0;
701 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
702 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
704 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
706 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
707 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
709 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
711 * This negation looks like it's safe in practice, because bits 0:4 will
712 * surely be TRIANGLES
715 if (value1
->f
[0] == -1.0f
) {
719 emit(OR(tmp
, g1_6
, fs_reg(0x3f800000)));
721 emit(AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000)));
727 fs_visitor::nir_emit_alu(nir_alu_instr
*instr
)
729 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
732 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
733 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
736 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
737 op
[i
] = get_nir_src(instr
->src
[i
].src
);
738 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
739 op
[i
].abs
= instr
->src
[i
].abs
;
740 op
[i
].negate
= instr
->src
[i
].negate
;
743 /* We get a bunch of mov's out of the from_ssa pass and they may still
744 * be vectorized. We'll handle them as a special-case. We'll also
745 * handle vecN here because it's basically the same thing.
753 fs_reg temp
= result
;
754 bool need_extra_copy
= false;
755 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
756 if (!instr
->src
[i
].src
.is_ssa
&&
757 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
758 need_extra_copy
= true;
759 temp
= retype(vgrf(4), result
.type
);
764 for (unsigned i
= 0; i
< 4; i
++) {
765 if (!(instr
->dest
.write_mask
& (1 << i
)))
768 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
769 inst
= emit(MOV(offset(temp
, i
),
770 offset(op
[0], instr
->src
[0].swizzle
[i
])));
772 inst
= emit(MOV(offset(temp
, i
),
773 offset(op
[i
], instr
->src
[i
].swizzle
[0])));
775 inst
->saturate
= instr
->dest
.saturate
;
778 /* In this case the source and destination registers were the same,
779 * so we need to insert an extra set of moves in order to deal with
782 if (need_extra_copy
) {
783 for (unsigned i
= 0; i
< 4; i
++) {
784 if (!(instr
->dest
.write_mask
& (1 << i
)))
787 emit(MOV(offset(result
, i
), offset(temp
, i
)));
796 /* At this point, we have dealt with any instruction that operates on
797 * more than a single channel. Therefore, we can just adjust the source
798 * and destination registers for that channel and emit the instruction.
800 unsigned channel
= 0;
801 if (nir_op_infos
[instr
->op
].output_size
== 0) {
802 /* Since NIR is doing the scalarizing for us, we should only ever see
803 * vectorized operations with a single channel.
805 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
806 channel
= ffs(instr
->dest
.write_mask
) - 1;
808 result
= offset(result
, channel
);
811 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
812 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
813 op
[i
] = offset(op
[i
], instr
->src
[i
].swizzle
[channel
]);
819 inst
= emit(MOV(result
, op
[0]));
820 inst
->saturate
= instr
->dest
.saturate
;
825 emit(MOV(result
, op
[0]));
829 /* AND(val, 0x80000000) gives the sign bit.
831 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
834 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
836 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
837 op
[0].type
= BRW_REGISTER_TYPE_UD
;
838 result
.type
= BRW_REGISTER_TYPE_UD
;
839 emit(AND(result_int
, op
[0], fs_reg(0x80000000u
)));
841 inst
= emit(OR(result_int
, result_int
, fs_reg(0x3f800000u
)));
842 inst
->predicate
= BRW_PREDICATE_NORMAL
;
843 if (instr
->dest
.saturate
) {
844 inst
= emit(MOV(result
, result
));
845 inst
->saturate
= true;
851 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
852 * -> non-negative val generates 0x00000000.
853 * Predicated OR sets 1 if val is positive.
855 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
));
856 emit(ASR(result
, op
[0], fs_reg(31)));
857 inst
= emit(OR(result
, result
, fs_reg(1)));
858 inst
->predicate
= BRW_PREDICATE_NORMAL
;
862 inst
= emit_math(SHADER_OPCODE_RCP
, result
, op
[0]);
863 inst
->saturate
= instr
->dest
.saturate
;
867 inst
= emit_math(SHADER_OPCODE_EXP2
, result
, op
[0]);
868 inst
->saturate
= instr
->dest
.saturate
;
872 inst
= emit_math(SHADER_OPCODE_LOG2
, result
, op
[0]);
873 inst
->saturate
= instr
->dest
.saturate
;
878 unreachable("not reached: should be handled by ir_explog_to_explog2");
881 case nir_op_fsin_reduced
:
882 inst
= emit_math(SHADER_OPCODE_SIN
, result
, op
[0]);
883 inst
->saturate
= instr
->dest
.saturate
;
887 case nir_op_fcos_reduced
:
888 inst
= emit_math(SHADER_OPCODE_COS
, result
, op
[0]);
889 inst
->saturate
= instr
->dest
.saturate
;
893 if (fs_key
->high_quality_derivatives
) {
894 inst
= emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
896 inst
= emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
898 inst
->saturate
= instr
->dest
.saturate
;
900 case nir_op_fddx_fine
:
901 inst
= emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
902 inst
->saturate
= instr
->dest
.saturate
;
904 case nir_op_fddx_coarse
:
905 inst
= emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
906 inst
->saturate
= instr
->dest
.saturate
;
909 if (fs_key
->high_quality_derivatives
) {
910 inst
= emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
911 fs_reg(fs_key
->render_to_fbo
));
913 inst
= emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
914 fs_reg(fs_key
->render_to_fbo
));
916 inst
->saturate
= instr
->dest
.saturate
;
918 case nir_op_fddy_fine
:
919 inst
= emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
920 fs_reg(fs_key
->render_to_fbo
));
921 inst
->saturate
= instr
->dest
.saturate
;
923 case nir_op_fddy_coarse
:
924 inst
= emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
925 fs_reg(fs_key
->render_to_fbo
));
926 inst
->saturate
= instr
->dest
.saturate
;
931 inst
= emit(ADD(result
, op
[0], op
[1]));
932 inst
->saturate
= instr
->dest
.saturate
;
936 inst
= emit(MUL(result
, op
[0], op
[1]));
937 inst
->saturate
= instr
->dest
.saturate
;
942 emit(MUL(result
, op
[0], op
[1]));
945 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
946 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
948 if (value0
&& value0
->u
[0] < (1 << 16)) {
950 emit(MUL(result
, op
[0], op
[1]));
952 emit(MUL(result
, op
[1], op
[0]));
955 } else if (value1
&& value1
->u
[0] < (1 << 16)) {
957 emit(MUL(result
, op
[1], op
[0]));
959 emit(MUL(result
, op
[0], op
[1]));
966 no16("SIMD16 explicit accumulator operands unsupported\n");
968 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
970 emit(MUL(acc
, op
[0], op
[1]));
971 emit(MACH(reg_null_d
, op
[0], op
[1]));
972 emit(MOV(result
, fs_reg(acc
)));
976 case nir_op_imul_high
:
977 case nir_op_umul_high
: {
979 no16("SIMD16 explicit accumulator operands unsupported\n");
981 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
983 emit(MUL(acc
, op
[0], op
[1]));
984 emit(MACH(result
, op
[0], op
[1]));
990 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
993 case nir_op_uadd_carry
: {
995 no16("SIMD16 explicit accumulator operands unsupported\n");
997 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
998 BRW_REGISTER_TYPE_UD
);
1000 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
1001 emit(MOV(result
, fs_reg(acc
)));
1005 case nir_op_usub_borrow
: {
1007 no16("SIMD16 explicit accumulator operands unsupported\n");
1009 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
1010 BRW_REGISTER_TYPE_UD
);
1012 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
1013 emit(MOV(result
, fs_reg(acc
)));
1018 emit_math(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1024 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
));
1030 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
));
1035 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1040 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1044 if (brw
->gen
>= 8) {
1045 resolve_source_modifiers(&op
[0]);
1047 emit(NOT(result
, op
[0]));
1050 if (brw
->gen
>= 8) {
1051 resolve_source_modifiers(&op
[0]);
1052 resolve_source_modifiers(&op
[1]);
1054 emit(XOR(result
, op
[0], op
[1]));
1057 if (brw
->gen
>= 8) {
1058 resolve_source_modifiers(&op
[0]);
1059 resolve_source_modifiers(&op
[1]);
1061 emit(OR(result
, op
[0], op
[1]));
1064 if (brw
->gen
>= 8) {
1065 resolve_source_modifiers(&op
[0]);
1066 resolve_source_modifiers(&op
[1]);
1068 emit(AND(result
, op
[0], op
[1]));
1080 case nir_op_ball_fequal2
:
1081 case nir_op_ball_iequal2
:
1082 case nir_op_ball_fequal3
:
1083 case nir_op_ball_iequal3
:
1084 case nir_op_ball_fequal4
:
1085 case nir_op_ball_iequal4
:
1086 case nir_op_bany_fnequal2
:
1087 case nir_op_bany_inequal2
:
1088 case nir_op_bany_fnequal3
:
1089 case nir_op_bany_inequal3
:
1090 case nir_op_bany_fnequal4
:
1091 case nir_op_bany_inequal4
:
1092 unreachable("Lowered by nir_lower_alu_reductions");
1094 case nir_op_fnoise1_1
:
1095 case nir_op_fnoise1_2
:
1096 case nir_op_fnoise1_3
:
1097 case nir_op_fnoise1_4
:
1098 case nir_op_fnoise2_1
:
1099 case nir_op_fnoise2_2
:
1100 case nir_op_fnoise2_3
:
1101 case nir_op_fnoise2_4
:
1102 case nir_op_fnoise3_1
:
1103 case nir_op_fnoise3_2
:
1104 case nir_op_fnoise3_3
:
1105 case nir_op_fnoise3_4
:
1106 case nir_op_fnoise4_1
:
1107 case nir_op_fnoise4_2
:
1108 case nir_op_fnoise4_3
:
1109 case nir_op_fnoise4_4
:
1110 unreachable("not reached: should be handled by lower_noise");
1113 unreachable("not reached: should be handled by ldexp_to_arith()");
1116 inst
= emit_math(SHADER_OPCODE_SQRT
, result
, op
[0]);
1117 inst
->saturate
= instr
->dest
.saturate
;
1121 inst
= emit_math(SHADER_OPCODE_RSQ
, result
, op
[0]);
1122 inst
->saturate
= instr
->dest
.saturate
;
1126 emit(AND(result
, op
[0], fs_reg(1)));
1129 emit(AND(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0], fs_reg(0x3f800000u
)));
1133 emit(CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1136 emit(CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1140 inst
= emit(RNDZ(result
, op
[0]));
1141 inst
->saturate
= instr
->dest
.saturate
;
1144 case nir_op_fceil
: {
1145 op
[0].negate
= !op
[0].negate
;
1146 fs_reg temp
= vgrf(glsl_type::float_type
);
1147 emit(RNDD(temp
, op
[0]));
1149 inst
= emit(MOV(result
, temp
));
1150 inst
->saturate
= instr
->dest
.saturate
;
1154 inst
= emit(RNDD(result
, op
[0]));
1155 inst
->saturate
= instr
->dest
.saturate
;
1158 inst
= emit(FRC(result
, op
[0]));
1159 inst
->saturate
= instr
->dest
.saturate
;
1161 case nir_op_fround_even
:
1162 inst
= emit(RNDE(result
, op
[0]));
1163 inst
->saturate
= instr
->dest
.saturate
;
1169 if (brw
->gen
>= 6) {
1170 inst
= emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1171 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1173 emit(CMP(reg_null_d
, op
[0], op
[1], BRW_CONDITIONAL_L
));
1174 inst
= emit(SEL(result
, op
[0], op
[1]));
1175 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1177 inst
->saturate
= instr
->dest
.saturate
;
1183 if (brw
->gen
>= 6) {
1184 inst
= emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1185 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1187 emit(CMP(reg_null_d
, op
[0], op
[1], BRW_CONDITIONAL_GE
));
1188 inst
= emit(SEL(result
, op
[0], op
[1]));
1189 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1191 inst
->saturate
= instr
->dest
.saturate
;
1194 case nir_op_pack_snorm_2x16
:
1195 case nir_op_pack_snorm_4x8
:
1196 case nir_op_pack_unorm_2x16
:
1197 case nir_op_pack_unorm_4x8
:
1198 case nir_op_unpack_snorm_2x16
:
1199 case nir_op_unpack_snorm_4x8
:
1200 case nir_op_unpack_unorm_2x16
:
1201 case nir_op_unpack_unorm_4x8
:
1202 case nir_op_unpack_half_2x16
:
1203 case nir_op_pack_half_2x16
:
1204 unreachable("not reached: should be handled by lower_packing_builtins");
1206 case nir_op_unpack_half_2x16_split_x
:
1207 inst
= emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1208 inst
->saturate
= instr
->dest
.saturate
;
1210 case nir_op_unpack_half_2x16_split_y
:
1211 inst
= emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1212 inst
->saturate
= instr
->dest
.saturate
;
1216 inst
= emit_math(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1217 inst
->saturate
= instr
->dest
.saturate
;
1220 case nir_op_bitfield_reverse
:
1221 emit(BFREV(result
, op
[0]));
1224 case nir_op_bit_count
:
1225 emit(CBIT(result
, op
[0]));
1228 case nir_op_ufind_msb
:
1229 case nir_op_ifind_msb
: {
1230 emit(FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]));
1232 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1233 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1234 * subtract the result from 31 to convert the MSB count into an LSB count.
1237 emit(CMP(reg_null_d
, result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
1238 fs_reg
neg_result(result
);
1239 neg_result
.negate
= true;
1240 inst
= emit(ADD(result
, neg_result
, fs_reg(31)));
1241 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1245 case nir_op_find_lsb
:
1246 emit(FBL(result
, op
[0]));
1249 case nir_op_ubitfield_extract
:
1250 case nir_op_ibitfield_extract
:
1251 emit(BFE(result
, op
[2], op
[1], op
[0]));
1254 emit(BFI1(result
, op
[0], op
[1]));
1257 emit(BFI2(result
, op
[0], op
[1], op
[2]));
1260 case nir_op_bitfield_insert
:
1261 unreachable("not reached: should be handled by "
1262 "lower_instructions::bitfield_insert_to_bfm_bfi");
1265 emit(SHL(result
, op
[0], op
[1]));
1268 emit(ASR(result
, op
[0], op
[1]));
1271 emit(SHR(result
, op
[0], op
[1]));
1274 case nir_op_pack_half_2x16_split
:
1275 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1279 inst
= emit(MAD(result
, op
[2], op
[1], op
[0]));
1280 inst
->saturate
= instr
->dest
.saturate
;
1284 inst
= emit_lrp(result
, op
[0], op
[1], op
[2]);
1285 inst
->saturate
= instr
->dest
.saturate
;
1289 if (optimize_frontfacing_ternary(instr
, result
))
1292 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1293 inst
= emit(SEL(result
, op
[1], op
[2]));
1294 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1298 unreachable("unhandled instruction");
1301 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1302 * to sign extend the low bit to 0/~0
1304 if (brw
->gen
<= 5 &&
1305 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1306 fs_reg masked
= vgrf(glsl_type::int_type
);
1307 emit(AND(masked
, result
, fs_reg(1)));
1308 masked
.negate
= true;
1309 emit(MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
));
1314 fs_visitor::get_nir_src(nir_src src
)
1317 assert(src
.ssa
->parent_instr
->type
== nir_instr_type_load_const
);
1318 nir_load_const_instr
*load
= nir_instr_as_load_const(src
.ssa
->parent_instr
);
1319 fs_reg reg
= vgrf(src
.ssa
->num_components
);
1320 reg
.type
= BRW_REGISTER_TYPE_D
;
1322 for (unsigned i
= 0; i
< src
.ssa
->num_components
; ++i
)
1323 emit(MOV(offset(reg
, i
), fs_reg(load
->value
.i
[i
])));
1328 if (src
.reg
.reg
->is_global
)
1329 reg
= nir_globals
[src
.reg
.reg
->index
];
1331 reg
= nir_locals
[src
.reg
.reg
->index
];
1333 /* to avoid floating-point denorm flushing problems, set the type by
1334 * default to D - instructions that need floating point semantics will set
1335 * this to F if they need to
1337 reg
= retype(offset(reg
, src
.reg
.base_offset
), BRW_REGISTER_TYPE_D
);
1338 if (src
.reg
.indirect
) {
1339 reg
.reladdr
= new(mem_ctx
) fs_reg();
1340 *reg
.reladdr
= retype(get_nir_src(*src
.reg
.indirect
),
1341 BRW_REGISTER_TYPE_D
);
1349 fs_visitor::get_nir_dest(nir_dest dest
)
1352 if (dest
.reg
.reg
->is_global
)
1353 reg
= nir_globals
[dest
.reg
.reg
->index
];
1355 reg
= nir_locals
[dest
.reg
.reg
->index
];
1357 reg
= offset(reg
, dest
.reg
.base_offset
);
1358 if (dest
.reg
.indirect
) {
1359 reg
.reladdr
= new(mem_ctx
) fs_reg();
1360 *reg
.reladdr
= retype(get_nir_src(*dest
.reg
.indirect
),
1361 BRW_REGISTER_TYPE_D
);
1368 fs_visitor::emit_percomp(fs_inst
*inst
, unsigned wr_mask
)
1370 for (unsigned i
= 0; i
< 4; i
++) {
1371 if (!((wr_mask
>> i
) & 1))
1374 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(*inst
);
1375 new_inst
->dst
= offset(new_inst
->dst
, i
);
1376 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1377 if (inst
->src
[j
].file
== GRF
)
1378 new_inst
->src
[j
] = offset(new_inst
->src
[j
], i
);
1385 fs_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
1388 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1389 dest
= get_nir_dest(instr
->dest
);
1391 bool has_indirect
= false;
1393 switch (instr
->intrinsic
) {
1394 case nir_intrinsic_discard
:
1395 case nir_intrinsic_discard_if
: {
1396 /* We track our discarded pixels in f0.1. By predicating on it, we can
1397 * update just the flag bits that aren't yet discarded. If there's no
1398 * condition, we emit a CMP of g0 != g0, so all currently executing
1399 * channels will get turned off.
1402 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1403 cmp
= emit(CMP(reg_null_f
, get_nir_src(instr
->src
[0]),
1404 fs_reg(0), BRW_CONDITIONAL_Z
));
1406 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1407 BRW_REGISTER_TYPE_UW
));
1408 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
, BRW_CONDITIONAL_NZ
));
1410 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1411 cmp
->flag_subreg
= 1;
1413 if (brw
->gen
>= 6) {
1414 emit_discard_jump();
1419 case nir_intrinsic_atomic_counter_inc
:
1420 case nir_intrinsic_atomic_counter_dec
:
1421 case nir_intrinsic_atomic_counter_read
: {
1422 unsigned surf_index
= prog_data
->binding_table
.abo_start
+
1423 (unsigned) instr
->const_index
[0];
1424 fs_reg offset
= fs_reg(get_nir_src(instr
->src
[0]));
1426 switch (instr
->intrinsic
) {
1427 case nir_intrinsic_atomic_counter_inc
:
1428 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
1429 fs_reg(), fs_reg());
1431 case nir_intrinsic_atomic_counter_dec
:
1432 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
1433 fs_reg(), fs_reg());
1435 case nir_intrinsic_atomic_counter_read
:
1436 emit_untyped_surface_read(surf_index
, dest
, offset
);
1439 unreachable("Unreachable");
1444 case nir_intrinsic_load_front_face
:
1445 emit(MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1446 *emit_frontfacing_interpolation()));
1449 case nir_intrinsic_load_vertex_id
:
1450 unreachable("should be lowered by lower_vertex_id()");
1452 case nir_intrinsic_load_vertex_id_zero_base
: {
1453 fs_reg vertex_id
= nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
1454 assert(vertex_id
.file
!= BAD_FILE
);
1455 dest
.type
= vertex_id
.type
;
1456 emit(MOV(dest
, vertex_id
));
1460 case nir_intrinsic_load_base_vertex
: {
1461 fs_reg base_vertex
= nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
1462 assert(base_vertex
.file
!= BAD_FILE
);
1463 dest
.type
= base_vertex
.type
;
1464 emit(MOV(dest
, base_vertex
));
1468 case nir_intrinsic_load_instance_id
: {
1469 fs_reg instance_id
= nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
1470 assert(instance_id
.file
!= BAD_FILE
);
1471 dest
.type
= instance_id
.type
;
1472 emit(MOV(dest
, instance_id
));
1476 case nir_intrinsic_load_sample_mask_in
: {
1477 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1478 assert(sample_mask_in
.file
!= BAD_FILE
);
1479 dest
.type
= sample_mask_in
.type
;
1480 emit(MOV(dest
, sample_mask_in
));
1484 case nir_intrinsic_load_sample_pos
: {
1485 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1486 assert(sample_pos
.file
!= BAD_FILE
);
1487 dest
.type
= sample_pos
.type
;
1488 emit(MOV(dest
, sample_pos
));
1489 emit(MOV(offset(dest
, 1), offset(sample_pos
, 1)));
1493 case nir_intrinsic_load_sample_id
: {
1494 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1495 assert(sample_id
.file
!= BAD_FILE
);
1496 dest
.type
= sample_id
.type
;
1497 emit(MOV(dest
, sample_id
));
1501 case nir_intrinsic_load_uniform_indirect
:
1502 has_indirect
= true;
1503 case nir_intrinsic_load_uniform
: {
1504 unsigned index
= instr
->const_index
[0];
1507 if (index
< num_direct_uniforms
) {
1508 uniform_reg
= fs_reg(UNIFORM
, 0);
1510 uniform_reg
= fs_reg(UNIFORM
, num_direct_uniforms
);
1511 index
-= num_direct_uniforms
;
1514 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1515 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1516 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), index
);
1518 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1521 emit(MOV(dest
, src
));
1522 dest
= offset(dest
, 1);
1528 case nir_intrinsic_load_ubo_indirect
:
1529 has_indirect
= true;
1531 case nir_intrinsic_load_ubo
: {
1532 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1536 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1539 /* The block index is not a constant. Evaluate the index expression
1540 * per-channel and add the base UBO index; the generator will select
1541 * a value from any live channel.
1543 surf_index
= vgrf(glsl_type::uint_type
);
1544 emit(ADD(surf_index
, get_nir_src(instr
->src
[0]),
1545 fs_reg(stage_prog_data
->binding_table
.ubo_start
)))
1546 ->force_writemask_all
= true;
1548 /* Assume this may touch any UBO. It would be nice to provide
1549 * a tighter bound, but the array information is already lowered away.
1551 brw_mark_surface_used(prog_data
,
1552 stage_prog_data
->binding_table
.ubo_start
+
1553 shader_prog
->NumUniformBlocks
- 1);
1557 /* Turn the byte offset into a dword offset. */
1558 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1559 emit(SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1560 BRW_REGISTER_TYPE_D
),
1563 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1564 for (int i
= 0; i
< instr
->num_components
; i
++)
1565 emit(VARYING_PULL_CONSTANT_LOAD(offset(dest
, i
), surf_index
,
1566 base_offset
, vec4_offset
+ i
));
1568 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1569 packed_consts
.type
= dest
.type
;
1571 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1572 emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1573 surf_index
, const_offset_reg
);
1575 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1576 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1578 /* The std140 packing rules don't allow vectors to cross 16-byte
1579 * boundaries, and a reg is 32 bytes.
1581 assert(packed_consts
.subreg_offset
< 32);
1583 emit(MOV(dest
, packed_consts
));
1584 dest
= offset(dest
, 1);
1590 case nir_intrinsic_load_input_indirect
:
1591 has_indirect
= true;
1593 case nir_intrinsic_load_input
: {
1595 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1596 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1597 fs_reg src
= offset(retype(nir_inputs
, dest
.type
),
1598 instr
->const_index
[0] + index
);
1600 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1603 emit(MOV(dest
, src
));
1604 dest
= offset(dest
, 1);
1610 /* Handle ARB_gpu_shader5 interpolation intrinsics
1612 * It's worth a quick word of explanation as to why we handle the full
1613 * variable-based interpolation intrinsic rather than a lowered version
1614 * with like we do for other inputs. We have to do that because the way
1615 * we set up inputs doesn't allow us to use the already setup inputs for
1616 * interpolation. At the beginning of the shader, we go through all of
1617 * the input variables and do the initial interpolation and put it in
1618 * the nir_inputs array based on its location as determined in
1619 * nir_lower_io. If the input isn't used, dead code cleans up and
1620 * everything works fine. However, when we get to the ARB_gpu_shader5
1621 * interpolation intrinsics, we need to reinterpolate the input
1622 * differently. If we used an intrinsic that just had an index it would
1623 * only give us the offset into the nir_inputs array. However, this is
1624 * useless because that value is post-interpolation and we need
1625 * pre-interpolation. In order to get the actual location of the bits
1626 * we get from the vertex fetching hardware, we need the variable.
1628 case nir_intrinsic_interp_var_at_centroid
:
1629 case nir_intrinsic_interp_var_at_sample
:
1630 case nir_intrinsic_interp_var_at_offset
: {
1631 /* in SIMD16 mode, the pixel interpolator returns coords interleaved
1632 * 8 channels at a time, same as the barycentric coords presented in
1633 * the FS payload. this requires a bit of extra work to support.
1635 no16("interpolate_at_* not yet supported in SIMD16 mode.");
1637 fs_reg dst_x
= vgrf(2);
1638 fs_reg dst_y
= offset(dst_x
, 1);
1640 /* For most messages, we need one reg of ignored data; the hardware
1641 * requires mlen==1 even when there is no payload. in the per-slot
1642 * offset case, we'll replace this with the proper source data.
1644 fs_reg src
= vgrf(glsl_type::float_type
);
1645 int mlen
= 1; /* one reg unless overriden */
1648 switch (instr
->intrinsic
) {
1649 case nir_intrinsic_interp_var_at_centroid
:
1650 inst
= emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
, dst_x
, src
, fs_reg(0u));
1653 case nir_intrinsic_interp_var_at_sample
: {
1654 /* XXX: We should probably handle non-constant sample id's */
1655 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1656 assert(const_sample
);
1657 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1658 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_x
, src
,
1663 case nir_intrinsic_interp_var_at_offset
: {
1664 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1667 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1668 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1670 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_x
, src
,
1671 fs_reg(off_x
| (off_y
<< 4)));
1673 src
= vgrf(glsl_type::ivec2_type
);
1674 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1675 BRW_REGISTER_TYPE_F
);
1676 for (int i
= 0; i
< 2; i
++) {
1677 fs_reg temp
= vgrf(glsl_type::float_type
);
1678 emit(MUL(temp
, offset(offset_src
, i
), fs_reg(16.0f
)));
1679 fs_reg itemp
= vgrf(glsl_type::int_type
);
1680 emit(MOV(itemp
, temp
)); /* float to int */
1682 /* Clamp the upper end of the range to +7/16.
1683 * ARB_gpu_shader5 requires that we support a maximum offset
1684 * of +0.5, which isn't representable in a S0.4 value -- if
1685 * we didn't clamp it, we'd end up with -8/16, which is the
1686 * opposite of what the shader author wanted.
1688 * This is legal due to ARB_gpu_shader5's quantization
1691 * "Not all values of <offset> may be supported; x and y
1692 * offsets may be rounded to fixed-point values with the
1693 * number of fraction bits given by the
1694 * implementation-dependent constant
1695 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1698 emit(BRW_OPCODE_SEL
, offset(src
, i
), itemp
, fs_reg(7))
1699 ->conditional_mod
= BRW_CONDITIONAL_L
; /* min(src2, 7) */
1703 inst
= emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_x
, src
,
1710 unreachable("Invalid intrinsic");
1714 inst
->regs_written
= 2; /* 2 floats per slot returned */
1715 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1716 INTERP_QUALIFIER_NOPERSPECTIVE
;
1718 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1719 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1720 src
.type
= dest
.type
;
1722 emit(FS_OPCODE_LINTERP
, dest
, dst_x
, dst_y
, src
);
1723 dest
= offset(dest
, 1);
1728 case nir_intrinsic_store_output_indirect
:
1729 has_indirect
= true;
1730 case nir_intrinsic_store_output
: {
1731 fs_reg src
= get_nir_src(instr
->src
[0]);
1733 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1734 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1735 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
),
1736 instr
->const_index
[0] + index
);
1738 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1740 emit(MOV(new_dest
, src
));
1741 src
= offset(src
, 1);
1748 unreachable("unknown intrinsic");
1753 fs_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1755 unsigned sampler
= instr
->sampler_index
;
1756 fs_reg
sampler_reg(sampler
);
1758 /* FINISHME: We're failing to recompile our programs when the sampler is
1759 * updated. This only matters for the texture rectangle scale parameters
1760 * (pre-gen6, or gen6+ with GL_CLAMP).
1762 int texunit
= prog
->SamplerUnits
[sampler
];
1764 int gather_component
= instr
->component
;
1766 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1768 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1771 int lod_components
= 0, offset_components
= 0;
1773 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1776 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1777 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1778 switch (instr
->src
[i
].src_type
) {
1779 case nir_tex_src_bias
:
1780 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1782 case nir_tex_src_comparitor
:
1783 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1785 case nir_tex_src_coord
:
1786 switch (instr
->op
) {
1788 case nir_texop_txf_ms
:
1789 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1792 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1796 case nir_tex_src_ddx
:
1797 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1798 lod_components
= nir_tex_instr_src_size(instr
, i
);
1800 case nir_tex_src_ddy
:
1801 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1803 case nir_tex_src_lod
:
1804 switch (instr
->op
) {
1806 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1809 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1812 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1816 case nir_tex_src_ms_index
:
1817 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1819 case nir_tex_src_offset
:
1820 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1821 if (instr
->is_array
)
1822 offset_components
= instr
->coord_components
- 1;
1824 offset_components
= instr
->coord_components
;
1826 case nir_tex_src_projector
:
1827 projector
= retype(src
, BRW_REGISTER_TYPE_F
);
1830 case nir_tex_src_sampler_offset
: {
1831 /* Figure out the highest possible sampler index and mark it as used */
1832 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1833 if (instr
->op
== nir_texop_tg4
&& brw
->gen
< 8) {
1834 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1836 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1838 brw_mark_surface_used(prog_data
, max_used
);
1840 /* Emit code to evaluate the actual indexing expression */
1841 sampler_reg
= vgrf(glsl_type::uint_type
);
1842 emit(ADD(sampler_reg
, src
, fs_reg(sampler
)))
1843 ->force_writemask_all
= true;
1848 unreachable("unknown texture source");
1852 if (projector
.file
!= BAD_FILE
) {
1853 fs_reg invproj
= vgrf(glsl_type::float_type
);
1854 emit_math(SHADER_OPCODE_RCP
, invproj
, projector
);
1855 for (int i
= 0; i
< 3; i
++)
1856 emit(MUL(offset(coordinate
, i
), offset(coordinate
, i
), invproj
));
1859 if (instr
->op
== nir_texop_txf_ms
) {
1860 if (brw
->gen
>= 7 &&
1861 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1862 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1868 for (unsigned i
= 0; i
< 3; i
++) {
1869 if (instr
->const_offset
[i
] != 0) {
1870 assert(offset_components
== 0);
1871 tex_offset
= fs_reg(brw_texture_offset(ctx
, instr
->const_offset
, 3));
1876 enum glsl_base_type dest_base_type
;
1877 switch (instr
->dest_type
) {
1878 case nir_type_float
:
1879 dest_base_type
= GLSL_TYPE_FLOAT
;
1882 dest_base_type
= GLSL_TYPE_INT
;
1884 case nir_type_unsigned
:
1885 dest_base_type
= GLSL_TYPE_UINT
;
1888 unreachable("bad type");
1891 const glsl_type
*dest_type
=
1892 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1895 ir_texture_opcode op
;
1896 switch (instr
->op
) {
1897 case nir_texop_lod
: op
= ir_lod
; break;
1898 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1899 case nir_texop_tex
: op
= ir_tex
; break;
1900 case nir_texop_tg4
: op
= ir_tg4
; break;
1901 case nir_texop_txb
: op
= ir_txb
; break;
1902 case nir_texop_txd
: op
= ir_txd
; break;
1903 case nir_texop_txf
: op
= ir_txf
; break;
1904 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1905 case nir_texop_txl
: op
= ir_txl
; break;
1906 case nir_texop_txs
: op
= ir_txs
; break;
1908 unreachable("unknown texture opcode");
1911 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1912 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1913 tex_offset
, mcs
, gather_component
,
1914 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1916 fs_reg dest
= get_nir_dest(instr
->dest
);
1917 dest
.type
= this->result
.type
;
1918 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1919 emit_percomp(MOV(dest
, this->result
), (1 << num_components
) - 1);
1923 fs_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1925 switch (instr
->type
) {
1926 case nir_jump_break
:
1927 emit(BRW_OPCODE_BREAK
);
1929 case nir_jump_continue
:
1930 emit(BRW_OPCODE_CONTINUE
);
1932 case nir_jump_return
:
1934 unreachable("unknown jump");