2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 /* get the main function and emit it */
45 nir_foreach_function(function
, nir
) {
46 assert(strcmp(function
->name
, "main") == 0);
47 assert(function
->impl
);
48 nir_emit_impl(function
->impl
);
53 fs_visitor::nir_setup_inputs()
55 if (stage
!= MESA_SHADER_FRAGMENT
)
58 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
60 nir_foreach_variable(var
, &nir
->inputs
) {
61 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
64 if (var
->data
.location
== VARYING_SLOT_POS
) {
65 reg
= *emit_fragcoord_interpolation();
66 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
68 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
69 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
70 reg
.type
= BRW_REGISTER_TYPE_D
;
71 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
72 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
73 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
74 reg
.type
= BRW_REGISTER_TYPE_D
;
75 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
77 int location
= var
->data
.location
;
78 emit_general_interpolation(&input
, var
->name
, var
->type
,
79 (glsl_interp_qualifier
) var
->data
.interpolation
,
80 &location
, var
->data
.centroid
,
87 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
88 const glsl_type
*type
,
91 if (type
->is_array() || type
->is_matrix()) {
92 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
93 const unsigned length
= glsl_get_length(type
);
95 for (unsigned i
= 0; i
< length
; i
++) {
96 nir_setup_single_output_varying(reg
, elem_type
, location
);
98 } else if (type
->is_record()) {
99 for (unsigned i
= 0; i
< type
->length
; i
++) {
100 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
101 nir_setup_single_output_varying(reg
, field_type
, location
);
104 assert(type
->is_scalar() || type
->is_vector());
105 unsigned num_elements
= type
->vector_elements
;
106 if (type
->is_double())
108 for (unsigned count
= 0; count
< num_elements
; count
+= 4) {
109 this->outputs
[*location
] = *reg
;
110 this->output_components
[*location
] = MIN2(4, num_elements
- count
);
111 *reg
= offset(*reg
, bld
, 4);
118 fs_visitor::nir_setup_outputs()
120 if (stage
== MESA_SHADER_TESS_CTRL
)
123 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
125 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
127 nir_foreach_variable(var
, &nir
->outputs
) {
128 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
131 case MESA_SHADER_VERTEX
:
132 case MESA_SHADER_TESS_EVAL
:
133 case MESA_SHADER_GEOMETRY
: {
134 unsigned location
= var
->data
.location
;
135 nir_setup_single_output_varying(®
, var
->type
, &location
);
138 case MESA_SHADER_FRAGMENT
:
139 if (key
->force_dual_color_blend
&&
140 var
->data
.location
== FRAG_RESULT_DATA1
) {
141 this->dual_src_output
= reg
;
142 this->do_dual_src
= true;
143 } else if (var
->data
.index
> 0) {
144 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
145 assert(var
->data
.index
== 1);
146 this->dual_src_output
= reg
;
147 this->do_dual_src
= true;
148 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
149 /* Writing gl_FragColor outputs to all color regions. */
150 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
151 this->outputs
[i
] = reg
;
152 this->output_components
[i
] = 4;
154 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
155 this->frag_depth
= reg
;
156 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
157 this->frag_stencil
= reg
;
158 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
159 this->sample_mask
= reg
;
161 int vector_elements
= var
->type
->without_array()->vector_elements
;
163 /* gl_FragData or a user-defined FS output */
164 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
165 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
167 /* General color output. */
168 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
169 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
170 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
171 this->output_components
[output
] = vector_elements
;
176 unreachable("unhandled shader stage");
182 fs_visitor::nir_setup_uniforms()
184 if (dispatch_width
!= 8)
187 uniforms
= nir
->num_uniforms
/ 4;
191 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
195 nir_foreach_instr(instr
, block
) {
196 if (instr
->type
!= nir_instr_type_intrinsic
)
199 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
200 switch (intrin
->intrinsic
) {
201 case nir_intrinsic_load_vertex_id
:
202 unreachable("should be lowered by lower_vertex_id().");
204 case nir_intrinsic_load_vertex_id_zero_base
:
205 assert(v
->stage
== MESA_SHADER_VERTEX
);
206 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
207 if (reg
->file
== BAD_FILE
)
208 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
211 case nir_intrinsic_load_base_vertex
:
212 assert(v
->stage
== MESA_SHADER_VERTEX
);
213 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
214 if (reg
->file
== BAD_FILE
)
215 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
218 case nir_intrinsic_load_instance_id
:
219 assert(v
->stage
== MESA_SHADER_VERTEX
);
220 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
221 if (reg
->file
== BAD_FILE
)
222 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
225 case nir_intrinsic_load_base_instance
:
226 assert(v
->stage
== MESA_SHADER_VERTEX
);
227 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
228 if (reg
->file
== BAD_FILE
)
229 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
232 case nir_intrinsic_load_draw_id
:
233 assert(v
->stage
== MESA_SHADER_VERTEX
);
234 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
235 if (reg
->file
== BAD_FILE
)
236 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
239 case nir_intrinsic_load_invocation_id
:
240 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
242 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
243 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
244 if (reg
->file
== BAD_FILE
) {
245 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
246 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
247 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
248 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
253 case nir_intrinsic_load_sample_pos
:
254 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
255 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
256 if (reg
->file
== BAD_FILE
)
257 *reg
= *v
->emit_samplepos_setup();
260 case nir_intrinsic_load_sample_id
:
261 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
262 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
263 if (reg
->file
== BAD_FILE
)
264 *reg
= *v
->emit_sampleid_setup();
267 case nir_intrinsic_load_sample_mask_in
:
268 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
269 assert(v
->devinfo
->gen
>= 7);
270 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
271 if (reg
->file
== BAD_FILE
)
272 *reg
= *v
->emit_samplemaskin_setup();
275 case nir_intrinsic_load_local_invocation_id
:
276 assert(v
->stage
== MESA_SHADER_COMPUTE
);
277 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
278 if (reg
->file
== BAD_FILE
)
279 *reg
= *v
->emit_cs_local_invocation_id_setup();
282 case nir_intrinsic_load_work_group_id
:
283 assert(v
->stage
== MESA_SHADER_COMPUTE
);
284 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
285 if (reg
->file
== BAD_FILE
)
286 *reg
= *v
->emit_cs_work_group_id_setup();
289 case nir_intrinsic_load_helper_invocation
:
290 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
291 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
292 if (reg
->file
== BAD_FILE
) {
293 const fs_builder abld
=
294 v
->bld
.annotate("gl_HelperInvocation", NULL
);
296 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
297 * pixel mask is in g1.7 of the thread payload.
299 * We move the per-channel pixel enable bit to the low bit of each
300 * channel by shifting the byte containing the pixel mask by the
301 * vector immediate 0x76543210UV.
303 * The region of <1,8,0> reads only 1 byte (the pixel masks for
304 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
305 * masks for 2 and 3) in SIMD16.
307 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
309 stride(byte_offset(retype(brw_vec1_grf(1, 0),
310 BRW_REGISTER_TYPE_UB
), 28),
312 brw_imm_uv(0x76543210));
314 /* A set bit in the pixel mask means the channel is enabled, but
315 * that is the opposite of gl_HelperInvocation so we need to invert
318 * The negate source-modifier bit of logical instructions on Gen8+
319 * performs 1's complement negation, so we can use that instead of
322 fs_reg inverted
= negate(shifted
);
323 if (v
->devinfo
->gen
< 8) {
324 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
325 abld
.NOT(inverted
, shifted
);
328 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
329 * with 1 and negating.
331 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
332 abld
.AND(anded
, inverted
, brw_imm_uw(1));
334 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
335 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
349 fs_visitor::nir_emit_system_values()
351 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
352 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
353 nir_system_values
[i
] = fs_reg();
356 nir_foreach_function(function
, nir
) {
357 assert(strcmp(function
->name
, "main") == 0);
358 assert(function
->impl
);
359 nir_foreach_block(block
, function
->impl
) {
360 emit_system_values_block(block
, this);
366 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
368 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
369 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
370 nir_locals
[i
] = fs_reg();
373 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
374 unsigned array_elems
=
375 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
376 unsigned size
= array_elems
* reg
->num_components
;
377 const brw_reg_type reg_type
=
378 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
379 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
382 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
385 nir_emit_cf_list(&impl
->body
);
389 fs_visitor::nir_emit_cf_list(exec_list
*list
)
391 exec_list_validate(list
);
392 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
393 switch (node
->type
) {
395 nir_emit_if(nir_cf_node_as_if(node
));
398 case nir_cf_node_loop
:
399 nir_emit_loop(nir_cf_node_as_loop(node
));
402 case nir_cf_node_block
:
403 nir_emit_block(nir_cf_node_as_block(node
));
407 unreachable("Invalid CFG node block");
413 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
415 /* first, put the condition into f0 */
416 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
417 retype(get_nir_src(if_stmt
->condition
),
418 BRW_REGISTER_TYPE_D
));
419 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
421 bld
.IF(BRW_PREDICATE_NORMAL
);
423 nir_emit_cf_list(&if_stmt
->then_list
);
425 /* note: if the else is empty, dead CF elimination will remove it */
426 bld
.emit(BRW_OPCODE_ELSE
);
428 nir_emit_cf_list(&if_stmt
->else_list
);
430 bld
.emit(BRW_OPCODE_ENDIF
);
434 fs_visitor::nir_emit_loop(nir_loop
*loop
)
436 bld
.emit(BRW_OPCODE_DO
);
438 nir_emit_cf_list(&loop
->body
);
440 bld
.emit(BRW_OPCODE_WHILE
);
444 fs_visitor::nir_emit_block(nir_block
*block
)
446 nir_foreach_instr(instr
, block
) {
447 nir_emit_instr(instr
);
452 fs_visitor::nir_emit_instr(nir_instr
*instr
)
454 const fs_builder abld
= bld
.annotate(NULL
, instr
);
456 switch (instr
->type
) {
457 case nir_instr_type_alu
:
458 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
461 case nir_instr_type_intrinsic
:
463 case MESA_SHADER_VERTEX
:
464 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
466 case MESA_SHADER_TESS_CTRL
:
467 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
469 case MESA_SHADER_TESS_EVAL
:
470 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
472 case MESA_SHADER_GEOMETRY
:
473 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
475 case MESA_SHADER_FRAGMENT
:
476 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
478 case MESA_SHADER_COMPUTE
:
479 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
482 unreachable("unsupported shader stage");
486 case nir_instr_type_tex
:
487 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
490 case nir_instr_type_load_const
:
491 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
494 case nir_instr_type_ssa_undef
:
495 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
498 case nir_instr_type_jump
:
499 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
503 unreachable("unknown instruction type");
508 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
512 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
513 const fs_reg
&result
)
515 if (!instr
->src
[0].src
.is_ssa
||
516 !instr
->src
[0].src
.ssa
->parent_instr
)
519 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
522 nir_alu_instr
*src0
=
523 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
525 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
526 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
529 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
530 assert(element
!= NULL
);
532 enum opcode extract_op
;
533 if (src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
) {
534 assert(element
->u32
[0] <= 1);
535 extract_op
= SHADER_OPCODE_EXTRACT_WORD
;
537 assert(element
->u32
[0] <= 3);
538 extract_op
= SHADER_OPCODE_EXTRACT_BYTE
;
541 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
542 op0
.type
= brw_type_for_nir_type(
543 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
544 nir_src_bit_size(src0
->src
[0].src
)));
545 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
547 set_saturate(instr
->dest
.saturate
,
548 bld
.emit(extract_op
, result
, op0
, brw_imm_ud(element
->u32
[0])));
553 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
554 const fs_reg
&result
)
556 if (!instr
->src
[0].src
.is_ssa
||
557 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
560 nir_intrinsic_instr
*src0
=
561 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
563 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
566 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
567 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
570 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
571 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
574 fs_reg tmp
= vgrf(glsl_type::int_type
);
576 if (devinfo
->gen
>= 6) {
577 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
578 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
580 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
582 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
583 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
585 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
587 * This negation looks like it's safe in practice, because bits 0:4 will
588 * surely be TRIANGLES
591 if (value1
->f32
[0] == -1.0f
) {
595 tmp
.type
= BRW_REGISTER_TYPE_W
;
596 tmp
.subreg_offset
= 2;
599 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
601 tmp
.type
= BRW_REGISTER_TYPE_D
;
602 tmp
.subreg_offset
= 0;
605 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
606 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
608 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
610 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
611 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
613 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
615 * This negation looks like it's safe in practice, because bits 0:4 will
616 * surely be TRIANGLES
619 if (value1
->f32
[0] == -1.0f
) {
623 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
625 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
631 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
633 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
636 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
637 result
.type
= brw_type_for_nir_type(
638 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
639 nir_dest_bit_size(instr
->dest
.dest
)));
642 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
643 op
[i
] = get_nir_src(instr
->src
[i
].src
);
644 op
[i
].type
= brw_type_for_nir_type(
645 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
646 nir_src_bit_size(instr
->src
[i
].src
)));
647 op
[i
].abs
= instr
->src
[i
].abs
;
648 op
[i
].negate
= instr
->src
[i
].negate
;
651 /* We get a bunch of mov's out of the from_ssa pass and they may still
652 * be vectorized. We'll handle them as a special-case. We'll also
653 * handle vecN here because it's basically the same thing.
661 fs_reg temp
= result
;
662 bool need_extra_copy
= false;
663 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
664 if (!instr
->src
[i
].src
.is_ssa
&&
665 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
666 need_extra_copy
= true;
667 temp
= bld
.vgrf(result
.type
, 4);
672 for (unsigned i
= 0; i
< 4; i
++) {
673 if (!(instr
->dest
.write_mask
& (1 << i
)))
676 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
677 inst
= bld
.MOV(offset(temp
, bld
, i
),
678 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
680 inst
= bld
.MOV(offset(temp
, bld
, i
),
681 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
683 inst
->saturate
= instr
->dest
.saturate
;
686 /* In this case the source and destination registers were the same,
687 * so we need to insert an extra set of moves in order to deal with
690 if (need_extra_copy
) {
691 for (unsigned i
= 0; i
< 4; i
++) {
692 if (!(instr
->dest
.write_mask
& (1 << i
)))
695 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
704 /* At this point, we have dealt with any instruction that operates on
705 * more than a single channel. Therefore, we can just adjust the source
706 * and destination registers for that channel and emit the instruction.
708 unsigned channel
= 0;
709 if (nir_op_infos
[instr
->op
].output_size
== 0) {
710 /* Since NIR is doing the scalarizing for us, we should only ever see
711 * vectorized operations with a single channel.
713 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
714 channel
= ffs(instr
->dest
.write_mask
) - 1;
716 result
= offset(result
, bld
, channel
);
719 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
720 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
721 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
727 if (optimize_extract_to_float(instr
, result
))
736 inst
= bld
.MOV(result
, op
[0]);
737 inst
->saturate
= instr
->dest
.saturate
;
742 bld
.MOV(result
, op
[0]);
746 if (type_sz(op
[0].type
) < 8) {
747 /* AND(val, 0x80000000) gives the sign bit.
749 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
752 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
754 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
755 op
[0].type
= BRW_REGISTER_TYPE_UD
;
756 result
.type
= BRW_REGISTER_TYPE_UD
;
757 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
759 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
760 inst
->predicate
= BRW_PREDICATE_NORMAL
;
761 if (instr
->dest
.saturate
) {
762 inst
= bld
.MOV(result
, result
);
763 inst
->saturate
= true;
766 /* For doubles we do the same but we need to consider:
768 * - 2-src instructions can't operate with 64-bit immediates
769 * - The sign is encoded in the high 32-bit of each DF
770 * - CMP with DF requires special handling in SIMD16
771 * - We need to produce a DF result.
774 /* 2-src instructions can't have 64-bit immediates, so put 0.0 in
775 * a register and compare with that.
777 fs_reg tmp
= vgrf(glsl_type::double_type
);
778 bld
.MOV(tmp
, brw_imm_df(0.0));
780 /* A direct DF CMP using the flag register (null dst) won't work in
781 * SIMD16 because the CMP will be split in two by lower_simd_width,
782 * resulting in two CMP instructions with the same dst (NULL),
783 * leading to dead code elimination of the first one. In SIMD8,
784 * however, there is no need to split the CMP and we can save some
787 fs_reg dst_tmp
= vgrf(glsl_type::double_type
);
788 bld
.CMP(dst_tmp
, op
[0], tmp
, BRW_CONDITIONAL_NZ
);
790 /* In SIMD16 we want to avoid using a NULL dst register with DF CMP,
791 * so we store the result of the comparison in a vgrf instead and
792 * then we generate a UD comparison from that that won't have to
793 * be split by lower_simd_width. This is what NIR does to handle
794 * double comparisons in the general case.
796 if (bld
.dispatch_width() == 16 ) {
797 fs_reg dst_tmp_ud
= retype(dst_tmp
, BRW_REGISTER_TYPE_UD
);
798 bld
.MOV(dst_tmp_ud
, subscript(dst_tmp
, BRW_REGISTER_TYPE_UD
, 0));
799 bld
.CMP(bld
.null_reg_ud(),
800 dst_tmp_ud
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
803 /* Get the high 32-bit of each double component where the sign is */
804 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
805 bld
.MOV(result_int
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
807 /* Get the sign bit */
808 bld
.AND(result_int
, result_int
, brw_imm_ud(0x80000000u
));
810 /* Add 1.0 to the sign, predicated to skip the case of op[0] == 0.0 */
811 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
812 inst
->predicate
= BRW_PREDICATE_NORMAL
;
814 /* Convert from 32-bit float to 64-bit double */
815 result
.type
= BRW_REGISTER_TYPE_DF
;
816 inst
= bld
.MOV(result
, retype(result_int
, BRW_REGISTER_TYPE_F
));
818 if (instr
->dest
.saturate
) {
819 inst
= bld
.MOV(result
, result
);
820 inst
->saturate
= true;
827 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
828 * -> non-negative val generates 0x00000000.
829 * Predicated OR sets 1 if val is positive.
831 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
832 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
833 bld
.ASR(result
, op
[0], brw_imm_d(31));
834 inst
= bld
.OR(result
, result
, brw_imm_d(1));
835 inst
->predicate
= BRW_PREDICATE_NORMAL
;
839 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
840 inst
->saturate
= instr
->dest
.saturate
;
844 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
845 inst
->saturate
= instr
->dest
.saturate
;
849 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
850 inst
->saturate
= instr
->dest
.saturate
;
854 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
855 inst
->saturate
= instr
->dest
.saturate
;
859 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
860 inst
->saturate
= instr
->dest
.saturate
;
864 if (fs_key
->high_quality_derivatives
) {
865 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
867 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
869 inst
->saturate
= instr
->dest
.saturate
;
871 case nir_op_fddx_fine
:
872 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
873 inst
->saturate
= instr
->dest
.saturate
;
875 case nir_op_fddx_coarse
:
876 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
877 inst
->saturate
= instr
->dest
.saturate
;
880 if (fs_key
->high_quality_derivatives
) {
881 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
883 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
885 inst
->saturate
= instr
->dest
.saturate
;
887 case nir_op_fddy_fine
:
888 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
889 inst
->saturate
= instr
->dest
.saturate
;
891 case nir_op_fddy_coarse
:
892 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
893 inst
->saturate
= instr
->dest
.saturate
;
897 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
899 inst
= bld
.ADD(result
, op
[0], op
[1]);
900 inst
->saturate
= instr
->dest
.saturate
;
904 inst
= bld
.MUL(result
, op
[0], op
[1]);
905 inst
->saturate
= instr
->dest
.saturate
;
909 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
910 bld
.MUL(result
, op
[0], op
[1]);
913 case nir_op_imul_high
:
914 case nir_op_umul_high
:
915 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
916 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
921 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
922 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
925 case nir_op_uadd_carry
:
926 unreachable("Should have been lowered by carry_to_arith().");
928 case nir_op_usub_borrow
:
929 unreachable("Should have been lowered by borrow_to_arith().");
933 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
934 * appears that our hardware just does the right thing for signed
937 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
938 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
942 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
943 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
945 /* Math instructions don't support conditional mod */
946 inst
= bld
.MOV(bld
.null_reg_d(), result
);
947 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
949 /* Now, we need to determine if signs of the sources are different.
950 * When we XOR the sources, the top bit is 0 if they are the same and 1
951 * if they are different. We can then use a conditional modifier to
952 * turn that into a predicate. This leads us to an XOR.l instruction.
954 * Technically, according to the PRM, you're not allowed to use .l on a
955 * XOR instruction. However, emperical experiments and Curro's reading
956 * of the simulator source both indicate that it's safe.
958 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
959 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
960 inst
->predicate
= BRW_PREDICATE_NORMAL
;
961 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
963 /* If the result of the initial remainder operation is non-zero and the
964 * two sources have different signs, add in a copy of op[1] to get the
965 * final integer modulus value.
967 inst
= bld
.ADD(result
, result
, op
[1]);
968 inst
->predicate
= BRW_PREDICATE_NORMAL
;
976 fs_reg dest
= result
;
977 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
978 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
980 brw_conditional_mod cond
;
983 cond
= BRW_CONDITIONAL_L
;
986 cond
= BRW_CONDITIONAL_GE
;
989 cond
= BRW_CONDITIONAL_Z
;
992 cond
= BRW_CONDITIONAL_NZ
;
995 unreachable("bad opcode");
997 bld
.CMP(dest
, op
[0], op
[1], cond
);
998 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
999 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1006 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1007 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1012 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1013 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1017 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1018 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
1022 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1023 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
1027 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1028 if (devinfo
->gen
>= 8) {
1029 op
[0] = resolve_source_modifiers(op
[0]);
1031 bld
.NOT(result
, op
[0]);
1034 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1035 if (devinfo
->gen
>= 8) {
1036 op
[0] = resolve_source_modifiers(op
[0]);
1037 op
[1] = resolve_source_modifiers(op
[1]);
1039 bld
.XOR(result
, op
[0], op
[1]);
1042 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1043 if (devinfo
->gen
>= 8) {
1044 op
[0] = resolve_source_modifiers(op
[0]);
1045 op
[1] = resolve_source_modifiers(op
[1]);
1047 bld
.OR(result
, op
[0], op
[1]);
1050 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1051 if (devinfo
->gen
>= 8) {
1052 op
[0] = resolve_source_modifiers(op
[0]);
1053 op
[1] = resolve_source_modifiers(op
[1]);
1055 bld
.AND(result
, op
[0], op
[1]);
1061 case nir_op_ball_fequal2
:
1062 case nir_op_ball_iequal2
:
1063 case nir_op_ball_fequal3
:
1064 case nir_op_ball_iequal3
:
1065 case nir_op_ball_fequal4
:
1066 case nir_op_ball_iequal4
:
1067 case nir_op_bany_fnequal2
:
1068 case nir_op_bany_inequal2
:
1069 case nir_op_bany_fnequal3
:
1070 case nir_op_bany_inequal3
:
1071 case nir_op_bany_fnequal4
:
1072 case nir_op_bany_inequal4
:
1073 unreachable("Lowered by nir_lower_alu_reductions");
1075 case nir_op_fnoise1_1
:
1076 case nir_op_fnoise1_2
:
1077 case nir_op_fnoise1_3
:
1078 case nir_op_fnoise1_4
:
1079 case nir_op_fnoise2_1
:
1080 case nir_op_fnoise2_2
:
1081 case nir_op_fnoise2_3
:
1082 case nir_op_fnoise2_4
:
1083 case nir_op_fnoise3_1
:
1084 case nir_op_fnoise3_2
:
1085 case nir_op_fnoise3_3
:
1086 case nir_op_fnoise3_4
:
1087 case nir_op_fnoise4_1
:
1088 case nir_op_fnoise4_2
:
1089 case nir_op_fnoise4_3
:
1090 case nir_op_fnoise4_4
:
1091 unreachable("not reached: should be handled by lower_noise");
1094 unreachable("not reached: should be handled by ldexp_to_arith()");
1097 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1098 inst
->saturate
= instr
->dest
.saturate
;
1102 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1103 inst
->saturate
= instr
->dest
.saturate
;
1108 bld
.MOV(result
, negate(op
[0]));
1112 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1115 /* two-argument instructions can't take 64-bit immediates */
1116 fs_reg zero
= vgrf(glsl_type::double_type
);
1117 bld
.MOV(zero
, brw_imm_df(0.0));
1118 /* A SIMD16 execution needs to be split in two instructions, so use
1119 * a vgrf instead of the flag register as dst so instruction splitting
1122 fs_reg tmp
= vgrf(glsl_type::double_type
);
1123 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1124 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1128 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1132 inst
= bld
.RNDZ(result
, op
[0]);
1133 inst
->saturate
= instr
->dest
.saturate
;
1136 case nir_op_fceil
: {
1137 op
[0].negate
= !op
[0].negate
;
1138 fs_reg temp
= vgrf(glsl_type::float_type
);
1139 bld
.RNDD(temp
, op
[0]);
1141 inst
= bld
.MOV(result
, temp
);
1142 inst
->saturate
= instr
->dest
.saturate
;
1146 inst
= bld
.RNDD(result
, op
[0]);
1147 inst
->saturate
= instr
->dest
.saturate
;
1150 inst
= bld
.FRC(result
, op
[0]);
1151 inst
->saturate
= instr
->dest
.saturate
;
1153 case nir_op_fround_even
:
1154 inst
= bld
.RNDE(result
, op
[0]);
1155 inst
->saturate
= instr
->dest
.saturate
;
1158 case nir_op_fquantize2f16
: {
1159 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1160 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1161 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1163 /* The destination stride must be at least as big as the source stride. */
1164 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1167 /* Check for denormal */
1168 fs_reg abs_src0
= op
[0];
1169 abs_src0
.abs
= true;
1170 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1172 /* Get the appropriately signed zero */
1173 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1174 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1175 brw_imm_ud(0x80000000));
1176 /* Do the actual F32 -> F16 -> F32 conversion */
1177 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1178 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1179 /* Select that or zero based on normal status */
1180 inst
= bld
.SEL(result
, zero
, tmp32
);
1181 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1182 inst
->saturate
= instr
->dest
.saturate
;
1188 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1190 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1191 inst
->saturate
= instr
->dest
.saturate
;
1196 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1198 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1199 inst
->saturate
= instr
->dest
.saturate
;
1202 case nir_op_pack_snorm_2x16
:
1203 case nir_op_pack_snorm_4x8
:
1204 case nir_op_pack_unorm_2x16
:
1205 case nir_op_pack_unorm_4x8
:
1206 case nir_op_unpack_snorm_2x16
:
1207 case nir_op_unpack_snorm_4x8
:
1208 case nir_op_unpack_unorm_2x16
:
1209 case nir_op_unpack_unorm_4x8
:
1210 case nir_op_unpack_half_2x16
:
1211 case nir_op_pack_half_2x16
:
1212 unreachable("not reached: should be handled by lower_packing_builtins");
1214 case nir_op_unpack_half_2x16_split_x
:
1215 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1216 inst
->saturate
= instr
->dest
.saturate
;
1218 case nir_op_unpack_half_2x16_split_y
:
1219 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1220 inst
->saturate
= instr
->dest
.saturate
;
1223 case nir_op_pack_double_2x32_split
:
1224 /* Optimize the common case where we are re-packing a double with
1225 * the result of a previous double unpack. In this case we can take the
1226 * 32-bit value to use in the re-pack from the original double and bypass
1227 * the unpack operation.
1229 for (int i
= 0; i
< 2; i
++) {
1230 if (instr
->src
[i
].src
.is_ssa
)
1233 const nir_instr
*parent_instr
= instr
->src
[i
].src
.ssa
->parent_instr
;
1234 if (parent_instr
->type
== nir_instr_type_alu
)
1237 const nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1238 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_x
||
1239 alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1242 if (!alu_parent
->src
[0].src
.is_ssa
)
1245 op
[i
] = get_nir_src(alu_parent
->src
[0].src
);
1246 op
[i
] = offset(retype(op
[i
], BRW_REGISTER_TYPE_DF
), bld
,
1247 alu_parent
->src
[0].swizzle
[channel
]);
1248 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1249 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 1);
1251 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 0);
1253 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1256 case nir_op_unpack_double_2x32_split_x
:
1257 case nir_op_unpack_double_2x32_split_y
: {
1258 /* Optimize the common case where we are unpacking from a double we have
1259 * previously packed. In this case we can just bypass the pack operation
1260 * and source directly from its arguments.
1262 unsigned index
= (instr
->op
== nir_op_unpack_double_2x32_split_x
) ? 0 : 1;
1263 if (instr
->src
[0].src
.is_ssa
) {
1264 nir_instr
*parent_instr
= instr
->src
[0].src
.ssa
->parent_instr
;
1265 if (parent_instr
->type
== nir_instr_type_alu
) {
1266 nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1267 if (alu_parent
->op
== nir_op_pack_double_2x32_split
&&
1268 alu_parent
->src
[index
].src
.is_ssa
) {
1269 op
[0] = retype(get_nir_src(alu_parent
->src
[index
].src
),
1270 BRW_REGISTER_TYPE_UD
);
1272 offset(op
[0], bld
, alu_parent
->src
[index
].swizzle
[channel
]);
1273 bld
.MOV(result
, op
[0]);
1279 if (instr
->op
== nir_op_unpack_double_2x32_split_x
)
1280 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1282 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1287 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1288 inst
->saturate
= instr
->dest
.saturate
;
1291 case nir_op_bitfield_reverse
:
1292 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1293 bld
.BFREV(result
, op
[0]);
1296 case nir_op_bit_count
:
1297 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1298 bld
.CBIT(result
, op
[0]);
1301 case nir_op_ufind_msb
:
1302 case nir_op_ifind_msb
: {
1303 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1304 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1306 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1307 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1308 * subtract the result from 31 to convert the MSB count into an LSB count.
1310 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1312 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1313 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1314 inst
->src
[0].negate
= true;
1318 case nir_op_find_lsb
:
1319 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1320 bld
.FBL(result
, op
[0]);
1323 case nir_op_ubitfield_extract
:
1324 case nir_op_ibitfield_extract
:
1325 unreachable("should have been lowered");
1328 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1329 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1332 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1333 bld
.BFI1(result
, op
[0], op
[1]);
1336 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1337 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1340 case nir_op_bitfield_insert
:
1341 unreachable("not reached: should have been lowered");
1344 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1345 bld
.SHL(result
, op
[0], op
[1]);
1348 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1349 bld
.ASR(result
, op
[0], op
[1]);
1352 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1353 bld
.SHR(result
, op
[0], op
[1]);
1356 case nir_op_pack_half_2x16_split
:
1357 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1361 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1362 inst
->saturate
= instr
->dest
.saturate
;
1366 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1367 inst
->saturate
= instr
->dest
.saturate
;
1371 if (optimize_frontfacing_ternary(instr
, result
))
1374 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1375 inst
= bld
.SEL(result
, op
[1], op
[2]);
1376 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1379 case nir_op_extract_u8
:
1380 case nir_op_extract_i8
: {
1381 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1382 assert(byte
!= NULL
);
1383 bld
.emit(SHADER_OPCODE_EXTRACT_BYTE
,
1384 result
, op
[0], brw_imm_ud(byte
->u32
[0]));
1388 case nir_op_extract_u16
:
1389 case nir_op_extract_i16
: {
1390 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1391 assert(word
!= NULL
);
1392 bld
.emit(SHADER_OPCODE_EXTRACT_WORD
,
1393 result
, op
[0], brw_imm_ud(word
->u32
[0]));
1398 unreachable("unhandled instruction");
1401 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1402 * to sign extend the low bit to 0/~0
1404 if (devinfo
->gen
<= 5 &&
1405 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1406 fs_reg masked
= vgrf(glsl_type::int_type
);
1407 bld
.AND(masked
, result
, brw_imm_d(1));
1408 masked
.negate
= true;
1409 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1414 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1415 nir_load_const_instr
*instr
)
1417 const brw_reg_type reg_type
=
1418 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1419 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1421 switch (instr
->def
.bit_size
) {
1423 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1424 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1428 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1429 bld
.MOV(offset(reg
, bld
, i
), brw_imm_df(instr
->value
.f64
[i
]));
1433 unreachable("Invalid bit size");
1436 nir_ssa_values
[instr
->def
.index
] = reg
;
1440 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1442 const brw_reg_type reg_type
=
1443 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1444 nir_ssa_values
[instr
->def
.index
] =
1445 bld
.vgrf(reg_type
, instr
->def
.num_components
);
1449 fs_visitor::get_nir_src(const nir_src
&src
)
1453 reg
= nir_ssa_values
[src
.ssa
->index
];
1455 /* We don't handle indirects on locals */
1456 assert(src
.reg
.indirect
== NULL
);
1457 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1458 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1461 /* to avoid floating-point denorm flushing problems, set the type by
1462 * default to D - instructions that need floating point semantics will set
1463 * this to F if they need to
1465 return retype(reg
, BRW_REGISTER_TYPE_D
);
1469 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1472 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1474 nir_const_value
*val
= nir_src_as_const_value(src
);
1475 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1479 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1482 const brw_reg_type reg_type
=
1483 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1484 nir_ssa_values
[dest
.ssa
.index
] =
1485 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1486 return nir_ssa_values
[dest
.ssa
.index
];
1488 /* We don't handle indirects on locals */
1489 assert(dest
.reg
.indirect
== NULL
);
1490 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1491 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1496 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1498 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1499 BRW_REGISTER_TYPE_UD
);
1501 unsigned indirect_max
= 0;
1503 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1504 tail
= tail
->child
) {
1505 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1506 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1507 const unsigned size
= glsl_get_length(tail
->type
);
1508 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1509 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1510 image
= offset(image
, bld
, base
* element_size
);
1512 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1513 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1515 /* Accessing an invalid surface index with the dataport can result
1516 * in a hang. According to the spec "if the index used to
1517 * select an individual element is negative or greater than or
1518 * equal to the size of the array, the results of the operation
1519 * are undefined but may not lead to termination" -- which is one
1520 * of the possible outcomes of the hang. Clamp the index to
1521 * prevent access outside of the array bounds.
1523 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1524 BRW_REGISTER_TYPE_UD
),
1525 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1527 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1529 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1530 if (indirect
.file
== BAD_FILE
) {
1533 bld
.ADD(indirect
, indirect
, tmp
);
1538 if (indirect
.file
== BAD_FILE
) {
1541 /* Emit a pile of MOVs to load the uniform into a temporary. The
1542 * dead-code elimination pass will get rid of what we don't use.
1544 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1545 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1546 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1547 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1548 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1555 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1558 for (unsigned i
= 0; i
< 4; i
++) {
1559 if (!((wr_mask
>> i
) & 1))
1562 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1563 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1564 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1565 if (new_inst
->src
[j
].file
== VGRF
)
1566 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1573 * Get the matching channel register datatype for an image intrinsic of the
1574 * specified GLSL image type.
1577 get_image_base_type(const glsl_type
*type
)
1579 switch ((glsl_base_type
)type
->sampled_type
) {
1580 case GLSL_TYPE_UINT
:
1581 return BRW_REGISTER_TYPE_UD
;
1583 return BRW_REGISTER_TYPE_D
;
1584 case GLSL_TYPE_FLOAT
:
1585 return BRW_REGISTER_TYPE_F
;
1587 unreachable("Not reached.");
1592 * Get the appropriate atomic op for an image atomic intrinsic.
1595 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1598 case nir_intrinsic_image_atomic_add
:
1600 case nir_intrinsic_image_atomic_min
:
1601 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1602 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1603 case nir_intrinsic_image_atomic_max
:
1604 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1605 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1606 case nir_intrinsic_image_atomic_and
:
1608 case nir_intrinsic_image_atomic_or
:
1610 case nir_intrinsic_image_atomic_xor
:
1612 case nir_intrinsic_image_atomic_exchange
:
1614 case nir_intrinsic_image_atomic_comp_swap
:
1615 return BRW_AOP_CMPWR
;
1617 unreachable("Not reachable.");
1622 emit_pixel_interpolater_send(const fs_builder
&bld
,
1627 glsl_interp_qualifier interpolation
)
1633 if (src
.file
== BAD_FILE
) {
1635 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1639 mlen
= 2 * bld
.dispatch_width() / 8;
1642 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1644 /* 2 floats per slot returned */
1645 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1646 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1652 * Computes 1 << x, given a D/UD register containing some value x.
1655 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1657 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1659 fs_reg result
= bld
.vgrf(x
.type
, 1);
1660 fs_reg one
= bld
.vgrf(x
.type
, 1);
1662 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1663 bld
.SHL(result
, one
, x
);
1668 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1670 assert(stage
== MESA_SHADER_GEOMETRY
);
1672 struct brw_gs_prog_data
*gs_prog_data
=
1673 (struct brw_gs_prog_data
*) prog_data
;
1675 /* We can only do EndPrimitive() functionality when the control data
1676 * consists of cut bits. Fortunately, the only time it isn't is when the
1677 * output type is points, in which case EndPrimitive() is a no-op.
1679 if (gs_prog_data
->control_data_format
!=
1680 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1684 /* Cut bits use one bit per vertex. */
1685 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1687 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1688 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1690 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1691 * vertex n, 0 otherwise. So all we need to do here is mark bit
1692 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1693 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1694 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1696 * Note that if EndPrimitive() is called before emitting any vertices, this
1697 * will cause us to set bit 31 of the control_data_bits register to 1.
1698 * That's fine because:
1700 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1701 * output, so the hardware will ignore cut bit 31.
1703 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1704 * last vertex, so setting cut bit 31 has no effect (since the primitive
1705 * is automatically ended when the GS terminates).
1707 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1708 * control_data_bits register to 0 when the first vertex is emitted.
1711 const fs_builder abld
= bld
.annotate("end primitive");
1713 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1714 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1715 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1716 fs_reg mask
= intexp2(abld
, prev_count
);
1717 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1718 * attention to the lower 5 bits of its second source argument, so on this
1719 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1720 * ((vertex_count - 1) % 32).
1722 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1726 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1728 assert(stage
== MESA_SHADER_GEOMETRY
);
1729 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1731 struct brw_gs_prog_data
*gs_prog_data
=
1732 (struct brw_gs_prog_data
*) prog_data
;
1734 const fs_builder abld
= bld
.annotate("emit control data bits");
1735 const fs_builder fwa_bld
= bld
.exec_all();
1737 /* We use a single UD register to accumulate control data bits (32 bits
1738 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1741 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1742 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1743 * use the Channel Mask phase to enable/disable which DWord within that
1744 * group to write. (Remember, different SIMD8 channels may have emitted
1745 * different numbers of vertices, so we may need per-slot offsets.)
1747 * Channel masking presents an annoying problem: we may have to replicate
1748 * the data up to 4 times:
1750 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1752 * To avoid penalizing shaders that emit a small number of vertices, we
1753 * can avoid these sometimes: if the size of the control data header is
1754 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1755 * land in the same 128-bit group, so we can skip per-slot offsets.
1757 * Similarly, if the control data header is <= 32 bits, there is only one
1758 * DWord, so we can skip channel masks.
1760 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1762 fs_reg channel_mask
, per_slot_offset
;
1764 if (gs_compile
->control_data_header_size_bits
> 32) {
1765 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1766 channel_mask
= vgrf(glsl_type::uint_type
);
1769 if (gs_compile
->control_data_header_size_bits
> 128) {
1770 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1771 per_slot_offset
= vgrf(glsl_type::uint_type
);
1774 /* Figure out which DWord we're trying to write to using the formula:
1776 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1778 * Since bits_per_vertex is a power of two, and is known at compile
1779 * time, this can be optimized to:
1781 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1783 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1784 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1785 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1786 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1787 unsigned log2_bits_per_vertex
=
1788 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1789 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1791 if (per_slot_offset
.file
!= BAD_FILE
) {
1792 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1793 * the appropriate OWord within the control data header.
1795 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1798 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1799 * write to the appropriate DWORD within the OWORD.
1801 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1802 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1803 channel_mask
= intexp2(fwa_bld
, channel
);
1804 /* Then the channel masks need to be in bits 23:16. */
1805 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1808 /* Store the control data bits in the message payload and send it. */
1810 if (channel_mask
.file
!= BAD_FILE
)
1811 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1812 if (per_slot_offset
.file
!= BAD_FILE
)
1815 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1816 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1818 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1819 if (per_slot_offset
.file
!= BAD_FILE
)
1820 sources
[i
++] = per_slot_offset
;
1821 if (channel_mask
.file
!= BAD_FILE
)
1822 sources
[i
++] = channel_mask
;
1824 sources
[i
++] = this->control_data_bits
;
1827 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1828 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1830 /* We need to increment Global Offset by 256-bits to make room for
1831 * Broadwell's extra "Vertex Count" payload at the beginning of the
1832 * URB entry. Since this is an OWord message, Global Offset is counted
1833 * in 128-bit units, so we must set it to 2.
1835 if (gs_prog_data
->static_vertex_count
== -1)
1840 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1843 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1845 /* Note: we are calling this *before* increasing vertex_count, so
1846 * this->vertex_count == vertex_count - 1 in the formula above.
1849 /* Stream mode uses 2 bits per vertex */
1850 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1852 /* Must be a valid stream */
1853 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1855 /* Control data bits are initialized to 0 so we don't have to set any
1856 * bits when sending vertices to stream 0.
1861 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1863 /* reg::sid = stream_id */
1864 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1865 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1867 /* reg:shift_count = 2 * (vertex_count - 1) */
1868 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1869 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1871 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1872 * attention to the lower 5 bits of its second source argument, so on this
1873 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1874 * stream_id << ((2 * (vertex_count - 1)) % 32).
1876 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1877 abld
.SHL(mask
, sid
, shift_count
);
1878 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1882 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1885 assert(stage
== MESA_SHADER_GEOMETRY
);
1887 struct brw_gs_prog_data
*gs_prog_data
=
1888 (struct brw_gs_prog_data
*) prog_data
;
1890 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1891 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1893 /* Haswell and later hardware ignores the "Render Stream Select" bits
1894 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1895 * and instead sends all primitives down the pipeline for rasterization.
1896 * If the SOL stage is enabled, "Render Stream Select" is honored and
1897 * primitives bound to non-zero streams are discarded after stream output.
1899 * Since the only purpose of primives sent to non-zero streams is to
1900 * be recorded by transform feedback, we can simply discard all geometry
1901 * bound to these streams when transform feedback is disabled.
1903 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1906 /* If we're outputting 32 control data bits or less, then we can wait
1907 * until the shader is over to output them all. Otherwise we need to
1908 * output them as we go. Now is the time to do it, since we're about to
1909 * output the vertex_count'th vertex, so it's guaranteed that the
1910 * control data bits associated with the (vertex_count - 1)th vertex are
1913 if (gs_compile
->control_data_header_size_bits
> 32) {
1914 const fs_builder abld
=
1915 bld
.annotate("emit vertex: emit control data bits");
1917 /* Only emit control data bits if we've finished accumulating a batch
1918 * of 32 bits. This is the case when:
1920 * (vertex_count * bits_per_vertex) % 32 == 0
1922 * (in other words, when the last 5 bits of vertex_count *
1923 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1924 * integer n (which is always the case, since bits_per_vertex is
1925 * always 1 or 2), this is equivalent to requiring that the last 5-n
1926 * bits of vertex_count are 0:
1928 * vertex_count & (2^(5-n) - 1) == 0
1930 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1933 * vertex_count & (32 / bits_per_vertex - 1) == 0
1935 * TODO: If vertex_count is an immediate, we could do some of this math
1936 * at compile time...
1939 abld
.AND(bld
.null_reg_d(), vertex_count
,
1940 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1941 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1943 abld
.IF(BRW_PREDICATE_NORMAL
);
1944 /* If vertex_count is 0, then no control data bits have been
1945 * accumulated yet, so we can skip emitting them.
1947 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1948 BRW_CONDITIONAL_NEQ
);
1949 abld
.IF(BRW_PREDICATE_NORMAL
);
1950 emit_gs_control_data_bits(vertex_count
);
1951 abld
.emit(BRW_OPCODE_ENDIF
);
1953 /* Reset control_data_bits to 0 so we can start accumulating a new
1956 * Note: in the case where vertex_count == 0, this neutralizes the
1957 * effect of any call to EndPrimitive() that the shader may have
1958 * made before outputting its first vertex.
1960 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1961 inst
->force_writemask_all
= true;
1962 abld
.emit(BRW_OPCODE_ENDIF
);
1965 emit_urb_writes(vertex_count
);
1967 /* In stream mode we have to set control data bits for all vertices
1968 * unless we have disabled control data bits completely (which we do
1969 * do for GL_POINTS outputs that don't use streams).
1971 if (gs_compile
->control_data_header_size_bits
> 0 &&
1972 gs_prog_data
->control_data_format
==
1973 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1974 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1979 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1980 const nir_src
&vertex_src
,
1981 unsigned base_offset
,
1982 const nir_src
&offset_src
,
1983 unsigned num_components
)
1985 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1987 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1988 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1989 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1991 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1992 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1993 * gl_PointSize is available as a GS input, however, so it must be that.
1995 const bool is_point_size
= (base_offset
== 0);
1997 /* TODO: figure out push input layout for invocations == 1 */
1998 if (gs_prog_data
->invocations
== 1 &&
1999 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2000 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2001 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2002 vertex_const
->u32
[0] * push_reg_count
;
2003 /* This input was pushed into registers. */
2004 if (is_point_size
) {
2005 /* gl_PointSize comes in .w */
2006 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
2008 for (unsigned i
= 0; i
< num_components
; i
++) {
2009 bld
.MOV(offset(dst
, bld
, i
),
2010 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
2016 /* Resort to the pull model. Ensure the VUE handles are provided. */
2017 gs_prog_data
->base
.include_vue_handles
= true;
2019 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2020 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2022 if (gs_prog_data
->invocations
== 1) {
2024 /* The vertex index is constant; just select the proper URB handle. */
2026 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2027 BRW_REGISTER_TYPE_UD
);
2029 /* The vertex index is non-constant. We need to use indirect
2030 * addressing to fetch the proper URB handle.
2032 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2033 * indicating that channel <n> should read the handle from
2034 * DWord <n>. We convert that to bytes by multiplying by 4.
2036 * Next, we convert the vertex index to bytes by multiplying
2037 * by 32 (shifting by 5), and add the two together. This is
2038 * the final indirect byte offset.
2040 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
2041 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2042 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2043 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2045 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2046 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2047 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2048 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2049 /* Convert vertex_index to bytes (multiply by 32) */
2050 bld
.SHL(vertex_offset_bytes
,
2051 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2053 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2055 /* Use first_icp_handle as the base offset. There is one register
2056 * of URB handles per vertex, so inform the register allocator that
2057 * we might read up to nir->info.gs.vertices_in registers.
2059 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2060 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2061 fs_reg(icp_offset_bytes
),
2062 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2065 assert(gs_prog_data
->invocations
> 1);
2068 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2070 retype(brw_vec1_grf(first_icp_handle
+
2071 vertex_const
->i32
[0] / 8,
2072 vertex_const
->i32
[0] % 8),
2073 BRW_REGISTER_TYPE_UD
));
2075 /* The vertex index is non-constant. We need to use indirect
2076 * addressing to fetch the proper URB handle.
2079 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2081 /* Convert vertex_index to bytes (multiply by 4) */
2082 bld
.SHL(icp_offset_bytes
,
2083 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2086 /* Use first_icp_handle as the base offset. There is one DWord
2087 * of URB handles per vertex, so inform the register allocator that
2088 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2090 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2091 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2092 fs_reg(icp_offset_bytes
),
2093 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2100 /* Constant indexing - use global offset. */
2101 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2102 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2103 inst
->base_mrf
= -1;
2105 inst
->regs_written
= num_components
;
2107 /* Indirect indexing - use per-slot offsets as well. */
2108 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
2109 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2110 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2112 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2113 inst
->offset
= base_offset
;
2114 inst
->base_mrf
= -1;
2116 inst
->regs_written
= num_components
;
2119 if (is_point_size
) {
2120 /* Read the whole VUE header (because of alignment) and read .w. */
2121 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
2123 inst
->regs_written
= 4;
2124 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2129 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2131 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2132 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2135 /* The only constant offset we should find is 0. brw_nir.c's
2136 * add_const_offset_to_base() will fold other constant offsets
2137 * into instr->const_index[0].
2139 assert(const_value
->u32
[0] == 0);
2143 return get_nir_src(*offset_src
);
2147 do_untyped_vector_read(const fs_builder
&bld
,
2149 const fs_reg surf_index
,
2150 const fs_reg offset_reg
,
2151 unsigned num_components
)
2153 if (type_sz(dest
.type
) == 4) {
2154 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2157 BRW_PREDICATE_NONE
);
2158 read_result
.type
= dest
.type
;
2159 for (unsigned i
= 0; i
< num_components
; i
++)
2160 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2161 } else if (type_sz(dest
.type
) == 8) {
2162 /* Reading a dvec, so we need to:
2164 * 1. Multiply num_components by 2, to account for the fact that we
2165 * need to read 64-bit components.
2166 * 2. Shuffle the result of the load to form valid 64-bit elements
2167 * 3. Emit a second load (for components z/w) if needed.
2169 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2170 bld
.MOV(read_offset
, offset_reg
);
2172 int iters
= num_components
<= 2 ? 1 : 2;
2174 /* Load the dvec, the first iteration loads components x/y, the second
2175 * iteration, if needed, loads components z/w
2177 for (int it
= 0; it
< iters
; it
++) {
2178 /* Compute number of components to read in this iteration */
2179 int iter_components
= MIN2(2, num_components
);
2180 num_components
-= iter_components
;
2182 /* Read. Since this message reads 32-bit components, we need to
2183 * read twice as many components.
2185 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2187 iter_components
* 2,
2188 BRW_PREDICATE_NONE
);
2190 /* Shuffle the 32-bit load result into valid 64-bit data */
2191 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2192 shuffle_32bit_load_result_to_64bit_data(
2193 bld
, packed_result
, read_result
, iter_components
);
2195 /* Move each component to its destination */
2196 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2197 for (int c
= 0; c
< iter_components
; c
++) {
2198 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2199 offset(packed_result
, bld
, c
));
2202 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2205 unreachable("Unsupported type");
2210 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2211 nir_intrinsic_instr
*instr
)
2213 assert(stage
== MESA_SHADER_VERTEX
);
2216 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2217 dest
= get_nir_dest(instr
->dest
);
2219 switch (instr
->intrinsic
) {
2220 case nir_intrinsic_load_vertex_id
:
2221 unreachable("should be lowered by lower_vertex_id()");
2223 case nir_intrinsic_load_vertex_id_zero_base
:
2224 case nir_intrinsic_load_base_vertex
:
2225 case nir_intrinsic_load_instance_id
:
2226 case nir_intrinsic_load_base_instance
:
2227 case nir_intrinsic_load_draw_id
: {
2228 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2229 fs_reg val
= nir_system_values
[sv
];
2230 assert(val
.file
!= BAD_FILE
);
2231 dest
.type
= val
.type
;
2237 nir_emit_intrinsic(bld
, instr
);
2243 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2244 nir_intrinsic_instr
*instr
)
2246 assert(stage
== MESA_SHADER_TESS_CTRL
);
2247 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2248 struct brw_tcs_prog_data
*tcs_prog_data
=
2249 (struct brw_tcs_prog_data
*) prog_data
;
2252 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2253 dst
= get_nir_dest(instr
->dest
);
2255 switch (instr
->intrinsic
) {
2256 case nir_intrinsic_load_primitive_id
:
2257 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2259 case nir_intrinsic_load_invocation_id
:
2260 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2262 case nir_intrinsic_load_patch_vertices_in
:
2263 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2264 brw_imm_d(tcs_key
->input_vertices
));
2267 case nir_intrinsic_barrier
: {
2268 if (tcs_prog_data
->instances
== 1)
2271 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2272 fs_reg m0_2
= byte_offset(m0
, 2 * sizeof(uint32_t));
2274 const fs_builder fwa_bld
= bld
.exec_all();
2276 /* Zero the message header */
2277 fwa_bld
.MOV(m0
, brw_imm_ud(0u));
2279 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2280 fwa_bld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2281 brw_imm_ud(INTEL_MASK(16, 13)));
2283 /* Shift it up to bits 27:24. */
2284 fwa_bld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2286 /* Set the Barrier Count and the enable bit */
2287 fwa_bld
.OR(m0_2
, m0_2
,
2288 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2290 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2294 case nir_intrinsic_load_input
:
2295 unreachable("nir_lower_io should never give us these.");
2298 case nir_intrinsic_load_per_vertex_input
: {
2299 fs_reg indirect_offset
= get_indirect_offset(instr
);
2300 unsigned imm_offset
= instr
->const_index
[0];
2302 const nir_src
&vertex_src
= instr
->src
[0];
2303 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2310 /* Emit a MOV to resolve <0,1,0> regioning. */
2311 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2313 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2314 vertex_const
->i32
[0] & 7),
2315 BRW_REGISTER_TYPE_UD
));
2316 } else if (tcs_prog_data
->instances
== 1 &&
2317 vertex_src
.is_ssa
&&
2318 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2319 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2320 /* For the common case of only 1 instance, an array index of
2321 * gl_InvocationID means reading g1. Skip all the indirect work.
2323 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2325 /* The vertex index is non-constant. We need to use indirect
2326 * addressing to fetch the proper URB handle.
2328 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2330 /* Each ICP handle is a single DWord (4 bytes) */
2331 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2332 bld
.SHL(vertex_offset_bytes
,
2333 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2336 /* Start at g1. We might read up to 4 registers. */
2337 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2338 fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes
,
2339 brw_imm_ud(4 * REG_SIZE
));
2342 /* We can only read two double components with each URB read, so
2343 * we send two read messages in that case, each one loading up to
2344 * two double components.
2346 unsigned num_iterations
= 1;
2347 unsigned num_components
= instr
->num_components
;
2348 fs_reg orig_dst
= dst
;
2349 if (type_sz(dst
.type
) == 8) {
2350 if (instr
->num_components
> 2) {
2355 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2359 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2360 if (indirect_offset
.file
== BAD_FILE
) {
2361 /* Constant indexing - use global offset. */
2362 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2363 inst
->offset
= imm_offset
;
2365 inst
->base_mrf
= -1;
2367 /* Indirect indexing - use per-slot offsets as well. */
2368 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2369 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2370 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2372 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2373 inst
->offset
= imm_offset
;
2374 inst
->base_mrf
= -1;
2377 inst
->regs_written
= num_components
* type_sz(dst
.type
) / 4;
2379 /* If we are reading 64-bit data using 32-bit read messages we need
2380 * build proper 64-bit data elements by shuffling the low and high
2381 * 32-bit components around like we do for other things like UBOs
2384 if (type_sz(dst
.type
) == 8) {
2385 shuffle_32bit_load_result_to_64bit_data(
2386 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2388 for (unsigned c
= 0; c
< num_components
; c
++) {
2389 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2390 offset(dst
, bld
, c
));
2394 /* Copy the temporary to the destination to deal with writemasking.
2396 * Also attempt to deal with gl_PointSize being in the .w component.
2398 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2399 assert(type_sz(dst
.type
) < 8);
2400 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2401 inst
->regs_written
= 4;
2402 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2405 /* If we are loading double data and we need a second read message
2406 * adjust the write offset
2408 if (num_iterations
> 1) {
2409 num_components
= instr
->num_components
- 2;
2410 if (indirect_offset
.file
== BAD_FILE
) {
2413 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2414 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2415 indirect_offset
= new_indirect
;
2422 case nir_intrinsic_load_output
:
2423 case nir_intrinsic_load_per_vertex_output
: {
2424 fs_reg indirect_offset
= get_indirect_offset(instr
);
2425 unsigned imm_offset
= instr
->const_index
[0];
2428 if (indirect_offset
.file
== BAD_FILE
) {
2429 /* Replicate the patch handle to all enabled channels */
2430 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2431 bld
.MOV(patch_handle
,
2432 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2434 if (imm_offset
== 0) {
2435 /* This is a read of gl_TessLevelInner[], which lives in the
2436 * Patch URB header. The layout depends on the domain.
2438 dst
.type
= BRW_REGISTER_TYPE_F
;
2439 switch (tcs_key
->tes_primitive_mode
) {
2441 /* DWords 3-2 (reversed) */
2442 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2444 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2447 inst
->base_mrf
= -1;
2448 inst
->regs_written
= 4;
2450 /* dst.xy = tmp.wz */
2451 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2452 bld
.MOV(offset(dst
, bld
, 1), offset(tmp
, bld
, 2));
2456 /* DWord 4; hardcode offset = 1 and regs_written = 1 */
2457 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2460 inst
->base_mrf
= -1;
2461 inst
->regs_written
= 1;
2464 /* All channels are undefined. */
2467 unreachable("Bogus tessellation domain");
2469 } else if (imm_offset
== 1) {
2470 /* This is a read of gl_TessLevelOuter[], which lives in the
2471 * Patch URB header. The layout depends on the domain.
2473 dst
.type
= BRW_REGISTER_TYPE_F
;
2475 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2476 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2479 inst
->base_mrf
= -1;
2480 inst
->regs_written
= 4;
2482 /* Reswizzle: WZYX */
2484 offset(tmp
, bld
, 3),
2485 offset(tmp
, bld
, 2),
2486 offset(tmp
, bld
, 1),
2487 offset(tmp
, bld
, 0),
2490 unsigned num_components
;
2491 switch (tcs_key
->tes_primitive_mode
) {
2499 /* Isolines are not reversed; swizzle .zw -> .xy */
2500 srcs
[0] = offset(tmp
, bld
, 2);
2501 srcs
[1] = offset(tmp
, bld
, 3);
2505 unreachable("Bogus tessellation domain");
2507 bld
.LOAD_PAYLOAD(dst
, srcs
, num_components
, 0);
2509 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2510 inst
->offset
= imm_offset
;
2512 inst
->base_mrf
= -1;
2513 inst
->regs_written
= instr
->num_components
;
2516 /* Indirect indexing - use per-slot offsets as well. */
2517 const fs_reg srcs
[] = {
2518 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2521 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2522 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2524 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2525 inst
->offset
= imm_offset
;
2527 inst
->base_mrf
= -1;
2528 inst
->regs_written
= instr
->num_components
;
2533 case nir_intrinsic_store_output
:
2534 case nir_intrinsic_store_per_vertex_output
: {
2535 fs_reg value
= get_nir_src(instr
->src
[0]);
2536 bool is_64bit
= (instr
->src
[0].is_ssa
?
2537 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2538 fs_reg indirect_offset
= get_indirect_offset(instr
);
2539 unsigned imm_offset
= instr
->const_index
[0];
2540 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2541 unsigned mask
= instr
->const_index
[1];
2542 unsigned header_regs
= 0;
2544 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2546 if (indirect_offset
.file
!= BAD_FILE
) {
2547 srcs
[header_regs
++] = indirect_offset
;
2548 } else if (!is_passthrough_shader
) {
2549 if (imm_offset
== 0) {
2550 value
.type
= BRW_REGISTER_TYPE_F
;
2552 mask
&= (1 << tesslevel_inner_components(tcs_key
->tes_primitive_mode
)) - 1;
2554 /* This is a write to gl_TessLevelInner[], which lives in the
2555 * Patch URB header. The layout depends on the domain.
2557 switch (tcs_key
->tes_primitive_mode
) {
2559 /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
2560 * We use an XXYX swizzle to reverse put .xy in the .wz
2561 * channels, and use a .zw writemask.
2563 mask
= writemask_for_backwards_vector(mask
);
2564 swiz
= BRW_SWIZZLE4(0, 0, 1, 0);
2567 /* gl_TessLevelInner[].x lives at DWord 4, so we set the
2568 * writemask to X and bump the URB offset by 1.
2573 /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
2576 unreachable("Bogus tessellation domain");
2578 } else if (imm_offset
== 1) {
2579 /* This is a write to gl_TessLevelOuter[] which lives in the
2580 * Patch URB Header at DWords 4-7. However, it's reversed, so
2581 * instead of .xyzw we have .wzyx.
2583 value
.type
= BRW_REGISTER_TYPE_F
;
2585 mask
&= (1 << tesslevel_outer_components(tcs_key
->tes_primitive_mode
)) - 1;
2587 if (tcs_key
->tes_primitive_mode
== GL_ISOLINES
) {
2588 /* Isolines .xy should be stored in .zw, in order. */
2589 swiz
= BRW_SWIZZLE4(0, 0, 0, 1);
2592 /* Other domains are reversed; store .wzyx instead of .xyzw */
2593 swiz
= BRW_SWIZZLE_WZYX
;
2594 mask
= writemask_for_backwards_vector(mask
);
2602 unsigned num_components
= _mesa_fls(mask
);
2605 /* We can only pack two 64-bit components in a single message, so send
2606 * 2 messages if we have more components
2608 unsigned num_iterations
= 1;
2609 unsigned iter_components
= num_components
;
2610 if (is_64bit
&& instr
->num_components
> 2) {
2612 iter_components
= 2;
2615 /* 64-bit data needs to me shuffled before we can write it to the URB.
2616 * We will use this temporary to shuffle the components in each
2620 fs_reg(VGRF
, alloc
.allocate(2 * iter_components
), value
.type
);
2622 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2623 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2624 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2625 opcode
= indirect_offset
.file
!= BAD_FILE
?
2626 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2627 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2628 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2629 /* Expand the 64-bit mask to 32-bit channels. We only handle
2630 * two channels in each iteration, so we only care about X/Y.
2632 unsigned mask32
= 0;
2633 if (mask
& WRITEMASK_X
)
2634 mask32
|= WRITEMASK_XY
;
2635 if (mask
& WRITEMASK_Y
)
2636 mask32
|= WRITEMASK_ZW
;
2638 /* If the mask does not include any of the channels X or Y there
2639 * is nothing to do in this iteration. Move on to the next couple
2640 * of 64-bit channels.
2648 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2649 opcode
= indirect_offset
.file
!= BAD_FILE
?
2650 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2651 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2653 opcode
= indirect_offset
.file
!= BAD_FILE
?
2654 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2655 SHADER_OPCODE_URB_WRITE_SIMD8
;
2658 for (unsigned i
= 0; i
< iter_components
; i
++) {
2659 if (!(mask
& (1 << i
)))
2663 srcs
[header_regs
+ i
] = offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2665 /* We need to shuffle the 64-bit data to match the layout
2666 * expected by our 32-bit URB write messages. We use a temporary
2669 unsigned channel
= BRW_GET_SWZ(swiz
, iter
* 2 + i
);
2670 shuffle_64bit_data_for_32bit_write(bld
,
2671 retype(offset(tmp
, bld
, 2 * i
), BRW_REGISTER_TYPE_F
),
2672 retype(offset(value
, bld
, 2 * channel
), BRW_REGISTER_TYPE_DF
),
2675 /* Now copy the data to the destination */
2676 fs_reg dest
= fs_reg(VGRF
, alloc
.allocate(2), value
.type
);
2677 unsigned idx
= 2 * i
;
2678 bld
.MOV(dest
, offset(tmp
, bld
, idx
));
2679 bld
.MOV(offset(dest
, bld
, 1), offset(tmp
, bld
, idx
+ 1));
2680 srcs
[header_regs
+ idx
] = dest
;
2681 srcs
[header_regs
+ idx
+ 1] = offset(dest
, bld
, 1);
2686 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
);
2688 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2689 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2691 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2692 inst
->offset
= imm_offset
;
2694 inst
->base_mrf
= -1;
2696 /* If this is a 64-bit attribute, select the next two 64-bit channels
2697 * to be handled in the next iteration.
2708 nir_emit_intrinsic(bld
, instr
);
2714 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2715 nir_intrinsic_instr
*instr
)
2717 assert(stage
== MESA_SHADER_TESS_EVAL
);
2718 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
2721 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2722 dest
= get_nir_dest(instr
->dest
);
2724 switch (instr
->intrinsic
) {
2725 case nir_intrinsic_load_primitive_id
:
2726 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2728 case nir_intrinsic_load_tess_coord
:
2729 /* gl_TessCoord is part of the payload in g1-3 */
2730 for (unsigned i
= 0; i
< 3; i
++) {
2731 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2735 case nir_intrinsic_load_tess_level_outer
:
2736 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
2737 * appears as a push-model input. So, we can simply use the ATTR file
2738 * rather than issuing URB read messages. The data is stored in the
2739 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
2742 switch (tes_prog_data
->domain
) {
2743 case BRW_TESS_DOMAIN_QUAD
:
2744 for (unsigned i
= 0; i
< 4; i
++)
2745 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2747 case BRW_TESS_DOMAIN_TRI
:
2748 for (unsigned i
= 0; i
< 3; i
++)
2749 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2751 case BRW_TESS_DOMAIN_ISOLINE
:
2752 for (unsigned i
= 0; i
< 2; i
++)
2753 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2758 case nir_intrinsic_load_tess_level_inner
:
2759 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
2760 * appears as a push-model input. So, we can simply use the ATTR file
2761 * rather than issuing URB read messages.
2763 switch (tes_prog_data
->domain
) {
2764 case BRW_TESS_DOMAIN_QUAD
:
2765 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
2766 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
2768 case BRW_TESS_DOMAIN_TRI
:
2769 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
2771 case BRW_TESS_DOMAIN_ISOLINE
:
2772 /* ignore - value is undefined */
2777 case nir_intrinsic_load_input
:
2778 case nir_intrinsic_load_per_vertex_input
: {
2779 fs_reg indirect_offset
= get_indirect_offset(instr
);
2780 unsigned imm_offset
= instr
->const_index
[0];
2783 if (indirect_offset
.file
== BAD_FILE
) {
2784 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2785 * which is 16 registers (since each holds 2 vec4 slots).
2787 const unsigned max_push_slots
= 32;
2788 if (imm_offset
< max_push_slots
) {
2789 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2790 for (int i
= 0; i
< instr
->num_components
; i
++) {
2791 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) + i
;
2792 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2794 tes_prog_data
->base
.urb_read_length
=
2795 MAX2(tes_prog_data
->base
.urb_read_length
,
2796 DIV_ROUND_UP(imm_offset
+ 1, 2));
2798 /* Replicate the patch handle to all enabled channels */
2799 const fs_reg srcs
[] = {
2800 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2802 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2803 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2805 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
2807 inst
->offset
= imm_offset
;
2808 inst
->base_mrf
= -1;
2809 inst
->regs_written
= instr
->num_components
;
2812 /* Indirect indexing - use per-slot offsets as well. */
2813 const fs_reg srcs
[] = {
2814 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2817 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2818 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2820 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
2822 inst
->offset
= imm_offset
;
2823 inst
->base_mrf
= -1;
2824 inst
->regs_written
= instr
->num_components
;
2829 nir_emit_intrinsic(bld
, instr
);
2835 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2836 nir_intrinsic_instr
*instr
)
2838 assert(stage
== MESA_SHADER_GEOMETRY
);
2839 fs_reg indirect_offset
;
2842 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2843 dest
= get_nir_dest(instr
->dest
);
2845 switch (instr
->intrinsic
) {
2846 case nir_intrinsic_load_primitive_id
:
2847 assert(stage
== MESA_SHADER_GEOMETRY
);
2848 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
2849 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2850 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2853 case nir_intrinsic_load_input
:
2854 unreachable("load_input intrinsics are invalid for the GS stage");
2856 case nir_intrinsic_load_per_vertex_input
:
2857 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2858 instr
->src
[1], instr
->num_components
);
2861 case nir_intrinsic_emit_vertex_with_counter
:
2862 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2865 case nir_intrinsic_end_primitive_with_counter
:
2866 emit_gs_end_primitive(instr
->src
[0]);
2869 case nir_intrinsic_set_vertex_count
:
2870 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2873 case nir_intrinsic_load_invocation_id
: {
2874 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2875 assert(val
.file
!= BAD_FILE
);
2876 dest
.type
= val
.type
;
2882 nir_emit_intrinsic(bld
, instr
);
2888 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
2889 nir_intrinsic_instr
*instr
)
2891 assert(stage
== MESA_SHADER_FRAGMENT
);
2892 struct brw_wm_prog_data
*wm_prog_data
=
2893 (struct brw_wm_prog_data
*) prog_data
;
2894 const struct brw_wm_prog_key
*wm_key
= (const struct brw_wm_prog_key
*) key
;
2897 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2898 dest
= get_nir_dest(instr
->dest
);
2900 switch (instr
->intrinsic
) {
2901 case nir_intrinsic_load_front_face
:
2902 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
2903 *emit_frontfacing_interpolation());
2906 case nir_intrinsic_load_sample_pos
: {
2907 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
2908 assert(sample_pos
.file
!= BAD_FILE
);
2909 dest
.type
= sample_pos
.type
;
2910 bld
.MOV(dest
, sample_pos
);
2911 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
2915 case nir_intrinsic_load_helper_invocation
:
2916 case nir_intrinsic_load_sample_mask_in
:
2917 case nir_intrinsic_load_sample_id
: {
2918 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2919 fs_reg val
= nir_system_values
[sv
];
2920 assert(val
.file
!= BAD_FILE
);
2921 dest
.type
= val
.type
;
2926 case nir_intrinsic_discard
:
2927 case nir_intrinsic_discard_if
: {
2928 /* We track our discarded pixels in f0.1. By predicating on it, we can
2929 * update just the flag bits that aren't yet discarded. If there's no
2930 * condition, we emit a CMP of g0 != g0, so all currently executing
2931 * channels will get turned off.
2934 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
2935 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
2936 brw_imm_d(0), BRW_CONDITIONAL_Z
);
2938 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2939 BRW_REGISTER_TYPE_UW
));
2940 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
2942 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2943 cmp
->flag_subreg
= 1;
2945 if (devinfo
->gen
>= 6) {
2946 emit_discard_jump();
2951 case nir_intrinsic_interp_var_at_centroid
:
2952 case nir_intrinsic_interp_var_at_sample
:
2953 case nir_intrinsic_interp_var_at_offset
: {
2954 /* Handle ARB_gpu_shader5 interpolation intrinsics
2956 * It's worth a quick word of explanation as to why we handle the full
2957 * variable-based interpolation intrinsic rather than a lowered version
2958 * with like we do for other inputs. We have to do that because the way
2959 * we set up inputs doesn't allow us to use the already setup inputs for
2960 * interpolation. At the beginning of the shader, we go through all of
2961 * the input variables and do the initial interpolation and put it in
2962 * the nir_inputs array based on its location as determined in
2963 * nir_lower_io. If the input isn't used, dead code cleans up and
2964 * everything works fine. However, when we get to the ARB_gpu_shader5
2965 * interpolation intrinsics, we need to reinterpolate the input
2966 * differently. If we used an intrinsic that just had an index it would
2967 * only give us the offset into the nir_inputs array. However, this is
2968 * useless because that value is post-interpolation and we need
2969 * pre-interpolation. In order to get the actual location of the bits
2970 * we get from the vertex fetching hardware, we need the variable.
2972 wm_prog_data
->pulls_bary
= true;
2974 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2975 const glsl_interp_qualifier interpolation
=
2976 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2978 switch (instr
->intrinsic
) {
2979 case nir_intrinsic_interp_var_at_centroid
:
2980 emit_pixel_interpolater_send(bld
,
2981 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2988 case nir_intrinsic_interp_var_at_sample
: {
2989 if (!wm_key
->multisample_fbo
) {
2990 /* From the ARB_gpu_shader5 specification:
2991 * "If multisample buffers are not available, the input varying
2992 * will be evaluated at the center of the pixel."
2994 emit_pixel_interpolater_send(bld
,
2995 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
3003 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3006 unsigned msg_data
= const_sample
->i32
[0] << 4;
3008 emit_pixel_interpolater_send(bld
,
3009 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3012 brw_imm_ud(msg_data
),
3015 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3016 BRW_REGISTER_TYPE_UD
);
3018 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3019 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3020 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3021 bld
.exec_all().group(1, 0)
3022 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3023 emit_pixel_interpolater_send(bld
,
3024 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3030 /* Make a loop that sends a message to the pixel interpolater
3031 * for the sample number in each live channel. If there are
3032 * multiple channels with the same sample number then these
3033 * will be handled simultaneously with a single interation of
3036 bld
.emit(BRW_OPCODE_DO
);
3038 /* Get the next live sample number into sample_id_reg */
3039 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3041 /* Set the flag register so that we can perform the send
3042 * message on all channels that have the same sample number
3044 bld
.CMP(bld
.null_reg_ud(),
3045 sample_src
, sample_id
,
3046 BRW_CONDITIONAL_EQ
);
3047 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3048 bld
.exec_all().group(1, 0)
3049 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3051 emit_pixel_interpolater_send(bld
,
3052 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3057 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3059 /* Continue the loop if there are any live channels left */
3060 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3062 bld
.emit(BRW_OPCODE_WHILE
));
3069 case nir_intrinsic_interp_var_at_offset
: {
3070 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3073 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3074 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3076 emit_pixel_interpolater_send(bld
,
3077 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3080 brw_imm_ud(off_x
| (off_y
<< 4)),
3083 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3084 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3085 BRW_REGISTER_TYPE_F
);
3086 for (int i
= 0; i
< 2; i
++) {
3087 fs_reg temp
= vgrf(glsl_type::float_type
);
3088 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3089 fs_reg itemp
= vgrf(glsl_type::int_type
);
3091 bld
.MOV(itemp
, temp
);
3093 /* Clamp the upper end of the range to +7/16.
3094 * ARB_gpu_shader5 requires that we support a maximum offset
3095 * of +0.5, which isn't representable in a S0.4 value -- if
3096 * we didn't clamp it, we'd end up with -8/16, which is the
3097 * opposite of what the shader author wanted.
3099 * This is legal due to ARB_gpu_shader5's quantization
3102 * "Not all values of <offset> may be supported; x and y
3103 * offsets may be rounded to fixed-point values with the
3104 * number of fraction bits given by the
3105 * implementation-dependent constant
3106 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3108 set_condmod(BRW_CONDITIONAL_L
,
3109 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3112 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3113 emit_pixel_interpolater_send(bld
,
3124 unreachable("Invalid intrinsic");
3127 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3128 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
3129 src
.type
= dest
.type
;
3131 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
3132 dest
= offset(dest
, bld
, 1);
3137 nir_emit_intrinsic(bld
, instr
);
3143 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3144 nir_intrinsic_instr
*instr
)
3146 assert(stage
== MESA_SHADER_COMPUTE
);
3147 struct brw_cs_prog_data
*cs_prog_data
=
3148 (struct brw_cs_prog_data
*) prog_data
;
3151 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3152 dest
= get_nir_dest(instr
->dest
);
3154 switch (instr
->intrinsic
) {
3155 case nir_intrinsic_barrier
:
3157 cs_prog_data
->uses_barrier
= true;
3160 case nir_intrinsic_load_local_invocation_id
:
3161 case nir_intrinsic_load_work_group_id
: {
3162 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3163 fs_reg val
= nir_system_values
[sv
];
3164 assert(val
.file
!= BAD_FILE
);
3165 dest
.type
= val
.type
;
3166 for (unsigned i
= 0; i
< 3; i
++)
3167 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3171 case nir_intrinsic_load_num_work_groups
: {
3172 const unsigned surface
=
3173 cs_prog_data
->binding_table
.work_groups_start
;
3175 cs_prog_data
->uses_num_work_groups
= true;
3177 fs_reg surf_index
= brw_imm_ud(surface
);
3178 brw_mark_surface_used(prog_data
, surface
);
3180 /* Read the 3 GLuint components of gl_NumWorkGroups */
3181 for (unsigned i
= 0; i
< 3; i
++) {
3182 fs_reg read_result
=
3183 emit_untyped_read(bld
, surf_index
,
3185 1 /* dims */, 1 /* size */,
3186 BRW_PREDICATE_NONE
);
3187 read_result
.type
= dest
.type
;
3188 bld
.MOV(dest
, read_result
);
3189 dest
= offset(dest
, bld
, 1);
3194 case nir_intrinsic_shared_atomic_add
:
3195 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3197 case nir_intrinsic_shared_atomic_imin
:
3198 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3200 case nir_intrinsic_shared_atomic_umin
:
3201 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3203 case nir_intrinsic_shared_atomic_imax
:
3204 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3206 case nir_intrinsic_shared_atomic_umax
:
3207 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3209 case nir_intrinsic_shared_atomic_and
:
3210 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3212 case nir_intrinsic_shared_atomic_or
:
3213 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3215 case nir_intrinsic_shared_atomic_xor
:
3216 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3218 case nir_intrinsic_shared_atomic_exchange
:
3219 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3221 case nir_intrinsic_shared_atomic_comp_swap
:
3222 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3225 case nir_intrinsic_load_shared
: {
3226 assert(devinfo
->gen
>= 7);
3228 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3230 /* Get the offset to read from */
3232 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3234 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3236 offset_reg
= vgrf(glsl_type::uint_type
);
3238 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3239 brw_imm_ud(instr
->const_index
[0]));
3242 /* Read the vector */
3243 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3244 instr
->num_components
);
3248 case nir_intrinsic_store_shared
: {
3249 assert(devinfo
->gen
>= 7);
3252 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3255 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3258 unsigned writemask
= instr
->const_index
[1];
3260 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3261 * since the untyped writes below operate in units of 32-bits, which
3262 * means that we need to write twice as many components each time.
3263 * Also, we have to suffle 64-bit data to be in the appropriate layout
3264 * expected by our 32-bit write messages.
3266 unsigned type_size
= 4;
3267 unsigned bit_size
= instr
->src
[0].is_ssa
?
3268 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3269 if (bit_size
== 64) {
3272 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3273 shuffle_64bit_data_for_32bit_write(
3275 retype(tmp
, BRW_REGISTER_TYPE_F
),
3276 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3277 instr
->num_components
);
3281 unsigned type_slots
= type_size
/ 4;
3283 /* Combine groups of consecutive enabled channels in one write
3284 * message. We use ffs to find the first enabled channel and then ffs on
3285 * the bit-inverse, down-shifted writemask to determine the length of
3286 * the block of enabled bits.
3289 unsigned first_component
= ffs(writemask
) - 1;
3290 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3292 /* We can't write more than 2 64-bit components at once. Limit the
3293 * length of the write to what we can do and let the next iteration
3297 length
= MIN2(2, length
);
3300 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3302 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3303 type_size
* first_component
);
3305 offset_reg
= vgrf(glsl_type::uint_type
);
3307 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3308 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3311 emit_untyped_write(bld
, surf_index
, offset_reg
,
3312 offset(val_reg
, bld
, first_component
* type_slots
),
3313 1 /* dims */, length
* type_slots
,
3314 BRW_PREDICATE_NONE
);
3316 /* Clear the bits in the writemask that we just wrote, then try
3317 * again to see if more channels are left.
3319 writemask
&= (15 << (first_component
+ length
));
3326 nir_emit_intrinsic(bld
, instr
);
3332 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3335 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3336 dest
= get_nir_dest(instr
->dest
);
3338 switch (instr
->intrinsic
) {
3339 case nir_intrinsic_atomic_counter_inc
:
3340 case nir_intrinsic_atomic_counter_dec
:
3341 case nir_intrinsic_atomic_counter_read
: {
3342 /* Get the arguments of the atomic intrinsic. */
3343 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3344 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3345 instr
->const_index
[0]);
3348 /* Emit a surface read or atomic op. */
3349 switch (instr
->intrinsic
) {
3350 case nir_intrinsic_atomic_counter_read
:
3351 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3354 case nir_intrinsic_atomic_counter_inc
:
3355 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
3356 fs_reg(), 1, 1, BRW_AOP_INC
);
3359 case nir_intrinsic_atomic_counter_dec
:
3360 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
3361 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
3365 unreachable("Unreachable");
3368 /* Assign the result. */
3369 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3371 /* Mark the surface as used. */
3372 brw_mark_surface_used(stage_prog_data
, surface
);
3376 case nir_intrinsic_image_load
:
3377 case nir_intrinsic_image_store
:
3378 case nir_intrinsic_image_atomic_add
:
3379 case nir_intrinsic_image_atomic_min
:
3380 case nir_intrinsic_image_atomic_max
:
3381 case nir_intrinsic_image_atomic_and
:
3382 case nir_intrinsic_image_atomic_or
:
3383 case nir_intrinsic_image_atomic_xor
:
3384 case nir_intrinsic_image_atomic_exchange
:
3385 case nir_intrinsic_image_atomic_comp_swap
: {
3386 using namespace image_access
;
3388 /* Get the referenced image variable and type. */
3389 const nir_variable
*var
= instr
->variables
[0]->var
;
3390 const glsl_type
*type
= var
->type
->without_array();
3391 const brw_reg_type base_type
= get_image_base_type(type
);
3393 /* Get some metadata from the image intrinsic. */
3394 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3395 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3396 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3397 const unsigned format
= var
->data
.image
.format
;
3399 /* Get the arguments of the image intrinsic. */
3400 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3401 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3402 BRW_REGISTER_TYPE_UD
);
3403 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3404 retype(get_nir_src(instr
->src
[2]), base_type
) :
3406 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3407 retype(get_nir_src(instr
->src
[3]), base_type
) :
3411 /* Emit an image load, store or atomic op. */
3412 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3413 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3415 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3416 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3417 var
->data
.image
.write_only
? GL_NONE
: format
);
3420 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3421 surf_dims
, arr_dims
, info
->dest_components
,
3422 get_image_atomic_op(instr
->intrinsic
, type
));
3424 /* Assign the result. */
3425 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3426 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3427 offset(tmp
, bld
, c
));
3431 case nir_intrinsic_memory_barrier_atomic_counter
:
3432 case nir_intrinsic_memory_barrier_buffer
:
3433 case nir_intrinsic_memory_barrier_image
:
3434 case nir_intrinsic_memory_barrier
: {
3435 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
3436 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3441 case nir_intrinsic_group_memory_barrier
:
3442 case nir_intrinsic_memory_barrier_shared
:
3443 /* We treat these workgroup-level barriers as no-ops. This should be
3444 * safe at present and as long as:
3446 * - Memory access instructions are not subsequently reordered by the
3447 * compiler back-end.
3449 * - All threads from a given compute shader workgroup fit within a
3450 * single subslice and therefore talk to the same HDC shared unit
3451 * what supposedly guarantees ordering and coherency between threads
3452 * from the same workgroup. This may change in the future when we
3453 * start splitting workgroups across multiple subslices.
3455 * - The context is not in fault-and-stream mode, which could cause
3456 * memory transactions (including to SLM) prior to the barrier to be
3457 * replayed after the barrier if a pagefault occurs. This shouldn't
3458 * be a problem up to and including SKL because fault-and-stream is
3459 * not usable due to hardware issues, but that's likely to change in
3464 case nir_intrinsic_shader_clock
: {
3465 /* We cannot do anything if there is an event, so ignore it for now */
3466 fs_reg shader_clock
= get_timestamp(bld
);
3467 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
3469 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3473 case nir_intrinsic_image_size
: {
3474 /* Get the referenced image variable and type. */
3475 const nir_variable
*var
= instr
->variables
[0]->var
;
3476 const glsl_type
*type
= var
->type
->without_array();
3478 /* Get the size of the image. */
3479 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3480 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3482 /* For 1DArray image types, the array index is stored in the Z component.
3483 * Fix this by swizzling the Z component to the Y component.
3485 const bool is_1d_array_image
=
3486 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3487 type
->sampler_array
;
3489 /* For CubeArray images, we should count the number of cubes instead
3490 * of the number of faces. Fix it by dividing the (Z component) by 6.
3492 const bool is_cube_array_image
=
3493 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3494 type
->sampler_array
;
3496 /* Copy all the components. */
3497 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3498 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
3499 if ((int)c
>= type
->coordinate_components()) {
3500 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3502 } else if (c
== 1 && is_1d_array_image
) {
3503 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3504 offset(size
, bld
, 2));
3505 } else if (c
== 2 && is_cube_array_image
) {
3506 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3507 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3508 offset(size
, bld
, c
), brw_imm_d(6));
3510 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3511 offset(size
, bld
, c
));
3518 case nir_intrinsic_image_samples
:
3519 /* The driver does not support multi-sampled images. */
3520 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3523 case nir_intrinsic_load_uniform
: {
3524 /* Offsets are in bytes but they should always be multiples of 4 */
3525 assert(instr
->const_index
[0] % 4 == 0);
3527 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3529 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3531 /* Offsets are in bytes but they should always be multiples of 4 */
3532 assert(const_offset
->u32
[0] % 4 == 0);
3533 src
.reg_offset
= const_offset
->u32
[0] / 4;
3535 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3536 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3539 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3540 BRW_REGISTER_TYPE_UD
);
3542 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3543 * go past the end of the uniform. In order to keep the n'th
3544 * component from running past, we subtract off the size of all but
3545 * one component of the vector.
3547 assert(instr
->const_index
[1] >=
3548 instr
->num_components
* (int) type_sz(dest
.type
));
3549 unsigned read_size
= instr
->const_index
[1] -
3550 (instr
->num_components
- 1) * type_sz(dest
.type
);
3552 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3553 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3554 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3555 indirect
, brw_imm_ud(read_size
));
3561 case nir_intrinsic_load_ubo
: {
3562 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3566 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3567 const_index
->u32
[0];
3568 surf_index
= brw_imm_ud(index
);
3569 brw_mark_surface_used(prog_data
, index
);
3571 /* The block index is not a constant. Evaluate the index expression
3572 * per-channel and add the base UBO index; we have to select a value
3573 * from any live channel.
3575 surf_index
= vgrf(glsl_type::uint_type
);
3576 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3577 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3578 surf_index
= bld
.emit_uniformize(surf_index
);
3580 /* Assume this may touch any UBO. It would be nice to provide
3581 * a tighter bound, but the array information is already lowered away.
3583 brw_mark_surface_used(prog_data
,
3584 stage_prog_data
->binding_table
.ubo_start
+
3585 nir
->info
.num_ubos
- 1);
3588 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3589 if (const_offset
== NULL
) {
3590 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3591 BRW_REGISTER_TYPE_UD
);
3593 for (int i
= 0; i
< instr
->num_components
; i
++)
3594 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3595 base_offset
, i
* type_sz(dest
.type
));
3597 /* Even if we are loading doubles, a pull constant load will load
3598 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3599 * need to load a full dvec4 we will have to emit 2 loads. This is
3600 * similar to demote_pull_constants(), except that in that case we
3601 * see individual accesses to each component of the vector and then
3602 * we let CSE deal with duplicate loads. Here we see a vector access
3603 * and we have to split it if necessary.
3605 const unsigned type_size
= type_sz(dest
.type
);
3606 const fs_reg packed_consts
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
3607 for (unsigned c
= 0; c
< instr
->num_components
;) {
3608 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
3610 /* Number of usable components in the next 16B-aligned load */
3611 const unsigned count
= MIN2(instr
->num_components
- c
,
3612 (16 - base
% 16) / type_size
);
3615 .emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3616 packed_consts
, surf_index
, brw_imm_ud(base
& ~15));
3618 const fs_reg consts
=
3619 retype(byte_offset(packed_consts
, base
& 15), dest
.type
);
3621 for (unsigned d
= 0; d
< count
; d
++)
3622 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3630 case nir_intrinsic_load_ssbo
: {
3631 assert(devinfo
->gen
>= 7);
3633 nir_const_value
*const_uniform_block
=
3634 nir_src_as_const_value(instr
->src
[0]);
3637 if (const_uniform_block
) {
3638 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3639 const_uniform_block
->u32
[0];
3640 surf_index
= brw_imm_ud(index
);
3641 brw_mark_surface_used(prog_data
, index
);
3643 surf_index
= vgrf(glsl_type::uint_type
);
3644 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3645 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3647 /* Assume this may touch any UBO. It would be nice to provide
3648 * a tighter bound, but the array information is already lowered away.
3650 brw_mark_surface_used(prog_data
,
3651 stage_prog_data
->binding_table
.ssbo_start
+
3652 nir
->info
.num_ssbos
- 1);
3656 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3658 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3660 offset_reg
= get_nir_src(instr
->src
[1]);
3663 /* Read the vector */
3664 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3665 instr
->num_components
);
3670 case nir_intrinsic_load_input
: {
3672 if (stage
== MESA_SHADER_VERTEX
) {
3673 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
3675 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
3676 instr
->const_index
[0]);
3679 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3680 assert(const_offset
&& "Indirect input loads not allowed");
3681 src
= offset(src
, bld
, const_offset
->u32
[0]);
3683 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3684 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3687 if (type_sz(src
.type
) == 8) {
3688 shuffle_32bit_load_result_to_64bit_data(bld
,
3690 retype(dest
, BRW_REGISTER_TYPE_F
),
3691 instr
->num_components
);
3697 case nir_intrinsic_store_ssbo
: {
3698 assert(devinfo
->gen
>= 7);
3702 nir_const_value
*const_uniform_block
=
3703 nir_src_as_const_value(instr
->src
[1]);
3704 if (const_uniform_block
) {
3705 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3706 const_uniform_block
->u32
[0];
3707 surf_index
= brw_imm_ud(index
);
3708 brw_mark_surface_used(prog_data
, index
);
3710 surf_index
= vgrf(glsl_type::uint_type
);
3711 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
3712 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3714 brw_mark_surface_used(prog_data
,
3715 stage_prog_data
->binding_table
.ssbo_start
+
3716 nir
->info
.num_ssbos
- 1);
3720 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3723 unsigned writemask
= instr
->const_index
[0];
3725 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3726 * since the untyped writes below operate in units of 32-bits, which
3727 * means that we need to write twice as many components each time.
3728 * Also, we have to suffle 64-bit data to be in the appropriate layout
3729 * expected by our 32-bit write messages.
3731 unsigned type_size
= 4;
3732 unsigned bit_size
= instr
->src
[0].is_ssa
?
3733 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3734 if (bit_size
== 64) {
3737 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3738 shuffle_64bit_data_for_32bit_write(bld
,
3739 retype(tmp
, BRW_REGISTER_TYPE_F
),
3740 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3741 instr
->num_components
);
3745 unsigned type_slots
= type_size
/ 4;
3747 /* Combine groups of consecutive enabled channels in one write
3748 * message. We use ffs to find the first enabled channel and then ffs on
3749 * the bit-inverse, down-shifted writemask to determine the length of
3750 * the block of enabled bits.
3753 unsigned first_component
= ffs(writemask
) - 1;
3754 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3756 /* We can't write more than 2 64-bit components at once. Limit the
3757 * length of the write to what we can do and let the next iteration
3761 length
= MIN2(2, length
);
3764 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
3766 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
3767 type_size
* first_component
);
3769 offset_reg
= vgrf(glsl_type::uint_type
);
3771 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
3772 brw_imm_ud(type_size
* first_component
));
3776 emit_untyped_write(bld
, surf_index
, offset_reg
,
3777 offset(val_reg
, bld
, first_component
* type_slots
),
3778 1 /* dims */, length
* type_slots
,
3779 BRW_PREDICATE_NONE
);
3781 /* Clear the bits in the writemask that we just wrote, then try
3782 * again to see if more channels are left.
3784 writemask
&= (15 << (first_component
+ length
));
3789 case nir_intrinsic_store_output
: {
3790 fs_reg src
= get_nir_src(instr
->src
[0]);
3791 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
3792 instr
->const_index
[0]);
3794 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3795 assert(const_offset
&& "Indirect output stores not allowed");
3796 new_dest
= offset(new_dest
, bld
, const_offset
->u32
[0]);
3798 unsigned num_components
= instr
->num_components
;
3799 unsigned bit_size
= instr
->src
[0].is_ssa
?
3800 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3801 if (bit_size
== 64) {
3803 fs_reg(VGRF
, alloc
.allocate(2 * num_components
),
3804 BRW_REGISTER_TYPE_F
);
3805 shuffle_64bit_data_for_32bit_write(
3806 bld
, tmp
, retype(src
, BRW_REGISTER_TYPE_DF
), num_components
);
3807 src
= retype(tmp
, src
.type
);
3808 num_components
*= 2;
3811 for (unsigned j
= 0; j
< num_components
; j
++) {
3812 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
3817 case nir_intrinsic_ssbo_atomic_add
:
3818 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
3820 case nir_intrinsic_ssbo_atomic_imin
:
3821 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
3823 case nir_intrinsic_ssbo_atomic_umin
:
3824 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
3826 case nir_intrinsic_ssbo_atomic_imax
:
3827 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
3829 case nir_intrinsic_ssbo_atomic_umax
:
3830 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
3832 case nir_intrinsic_ssbo_atomic_and
:
3833 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
3835 case nir_intrinsic_ssbo_atomic_or
:
3836 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
3838 case nir_intrinsic_ssbo_atomic_xor
:
3839 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
3841 case nir_intrinsic_ssbo_atomic_exchange
:
3842 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
3844 case nir_intrinsic_ssbo_atomic_comp_swap
:
3845 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3848 case nir_intrinsic_get_buffer_size
: {
3849 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
3850 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
3851 int reg_width
= dispatch_width
/ 8;
3854 fs_reg source
= brw_imm_d(0);
3856 int mlen
= 1 * reg_width
;
3858 /* A resinfo's sampler message is used to get the buffer size.
3859 * The SIMD8's writeback message consists of four registers and
3860 * SIMD16's writeback message consists of 8 destination registers
3861 * (two per each component), although we are only interested on the
3862 * first component, where resinfo returns the buffer size for
3865 int regs_written
= 4 * mlen
;
3866 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
3867 BRW_REGISTER_TYPE_UD
);
3868 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
3869 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
3870 BRW_REGISTER_TYPE_UD
);
3871 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
3872 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
3873 src_payload
, brw_imm_ud(index
));
3874 inst
->header_size
= 0;
3876 inst
->regs_written
= regs_written
;
3878 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
3880 brw_mark_surface_used(prog_data
, index
);
3885 unreachable("unknown intrinsic");
3890 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
3891 int op
, nir_intrinsic_instr
*instr
)
3894 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3895 dest
= get_nir_dest(instr
->dest
);
3898 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
3899 if (const_surface
) {
3900 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
3901 const_surface
->u32
[0];
3902 surface
= brw_imm_ud(surf_index
);
3903 brw_mark_surface_used(prog_data
, surf_index
);
3905 surface
= vgrf(glsl_type::uint_type
);
3906 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
3907 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3909 /* Assume this may touch any SSBO. This is the same we do for other
3910 * UBO/SSBO accesses with non-constant surface.
3912 brw_mark_surface_used(prog_data
,
3913 stage_prog_data
->binding_table
.ssbo_start
+
3914 nir
->info
.num_ssbos
- 1);
3917 fs_reg offset
= get_nir_src(instr
->src
[1]);
3918 fs_reg data1
= get_nir_src(instr
->src
[2]);
3920 if (op
== BRW_AOP_CMPWR
)
3921 data2
= get_nir_src(instr
->src
[3]);
3923 /* Emit the actual atomic operation operation */
3925 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3927 1 /* dims */, 1 /* rsize */,
3929 BRW_PREDICATE_NONE
);
3930 dest
.type
= atomic_result
.type
;
3931 bld
.MOV(dest
, atomic_result
);
3935 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
3936 int op
, nir_intrinsic_instr
*instr
)
3939 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3940 dest
= get_nir_dest(instr
->dest
);
3942 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
3943 fs_reg offset
= get_nir_src(instr
->src
[0]);
3944 fs_reg data1
= get_nir_src(instr
->src
[1]);
3946 if (op
== BRW_AOP_CMPWR
)
3947 data2
= get_nir_src(instr
->src
[2]);
3949 /* Emit the actual atomic operation operation */
3951 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3953 1 /* dims */, 1 /* rsize */,
3955 BRW_PREDICATE_NONE
);
3956 dest
.type
= atomic_result
.type
;
3957 bld
.MOV(dest
, atomic_result
);
3961 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
3963 unsigned texture
= instr
->texture_index
;
3964 unsigned sampler
= instr
->sampler_index
;
3966 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3968 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
3969 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
3971 int lod_components
= 0;
3973 /* The hardware requires a LOD for buffer textures */
3974 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
3975 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
3977 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
3978 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
3979 switch (instr
->src
[i
].src_type
) {
3980 case nir_tex_src_bias
:
3981 srcs
[TEX_LOGICAL_SRC_LOD
] =
3982 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
3984 case nir_tex_src_comparitor
:
3985 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
3987 case nir_tex_src_coord
:
3988 switch (instr
->op
) {
3990 case nir_texop_txf_ms
:
3991 case nir_texop_txf_ms_mcs
:
3992 case nir_texop_samples_identical
:
3993 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
3996 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4000 case nir_tex_src_ddx
:
4001 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4002 lod_components
= nir_tex_instr_src_size(instr
, i
);
4004 case nir_tex_src_ddy
:
4005 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4007 case nir_tex_src_lod
:
4008 switch (instr
->op
) {
4010 srcs
[TEX_LOGICAL_SRC_LOD
] =
4011 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4014 srcs
[TEX_LOGICAL_SRC_LOD
] =
4015 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4018 srcs
[TEX_LOGICAL_SRC_LOD
] =
4019 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4023 case nir_tex_src_ms_index
:
4024 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4027 case nir_tex_src_offset
: {
4028 nir_const_value
*const_offset
=
4029 nir_src_as_const_value(instr
->src
[i
].src
);
4031 unsigned header_bits
= brw_texture_offset(const_offset
->i32
, 3);
4032 if (header_bits
!= 0)
4033 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] = brw_imm_ud(header_bits
);
4035 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] =
4036 retype(src
, BRW_REGISTER_TYPE_D
);
4041 case nir_tex_src_projector
:
4042 unreachable("should be lowered");
4044 case nir_tex_src_texture_offset
: {
4045 /* Figure out the highest possible texture index and mark it as used */
4046 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4047 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4048 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4050 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4052 brw_mark_surface_used(prog_data
, max_used
);
4054 /* Emit code to evaluate the actual indexing expression */
4055 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4056 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4057 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4061 case nir_tex_src_sampler_offset
: {
4062 /* Emit code to evaluate the actual indexing expression */
4063 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4064 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4065 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4069 case nir_tex_src_ms_mcs
:
4070 assert(instr
->op
== nir_texop_txf_ms
);
4071 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4074 case nir_tex_src_plane
: {
4075 nir_const_value
*const_plane
=
4076 nir_src_as_const_value(instr
->src
[i
].src
);
4077 const uint32_t plane
= const_plane
->u32
[0];
4078 const uint32_t texture_index
=
4079 instr
->texture_index
+
4080 stage_prog_data
->binding_table
.plane_start
[plane
] -
4081 stage_prog_data
->binding_table
.texture_start
;
4083 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4088 unreachable("unknown texture source");
4092 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4093 (instr
->op
== nir_texop_txf_ms
||
4094 instr
->op
== nir_texop_samples_identical
)) {
4095 if (devinfo
->gen
>= 7 &&
4096 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4097 srcs
[TEX_LOGICAL_SRC_MCS
] =
4098 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4099 instr
->coord_components
,
4100 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4102 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4106 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4107 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4109 if (instr
->op
== nir_texop_query_levels
) {
4110 /* textureQueryLevels() is implemented in terms of TXS so we need to
4111 * pass a valid LOD argument.
4113 assert(srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
);
4114 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
4118 switch (instr
->op
) {
4120 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
4123 opcode
= FS_OPCODE_TXB_LOGICAL
;
4126 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4129 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4132 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4134 case nir_texop_txf_ms
:
4135 if ((key_tex
->msaa_16
& (1 << sampler
)))
4136 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4138 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4140 case nir_texop_txf_ms_mcs
:
4141 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4143 case nir_texop_query_levels
:
4145 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4148 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4151 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= BAD_FILE
&&
4152 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= IMM
)
4153 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4155 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4157 case nir_texop_texture_samples
: {
4158 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4160 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
, 4);
4161 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, tmp
,
4162 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
4163 srcs
[TEX_LOGICAL_SRC_SURFACE
],
4164 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4166 inst
->header_size
= 1;
4167 inst
->base_mrf
= -1;
4168 inst
->regs_written
= 4 * (dispatch_width
/ 8);
4170 /* Pick off the one component we care about */
4174 case nir_texop_samples_identical
: {
4175 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4177 /* If mcs is an immediate value, it means there is no MCS. In that case
4178 * just return false.
4180 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4181 bld
.MOV(dst
, brw_imm_ud(0u));
4182 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4183 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4184 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4185 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4186 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4188 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4189 BRW_CONDITIONAL_EQ
);
4194 unreachable("unknown texture opcode");
4197 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(instr
->dest_type
), 4);
4198 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4200 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4201 if (devinfo
->gen
>= 9 &&
4202 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4203 unsigned write_mask
= instr
->dest
.is_ssa
?
4204 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4205 (1 << dest_size
) - 1;
4206 assert(write_mask
!= 0); /* dead code should have been eliminated */
4207 inst
->regs_written
= _mesa_fls(write_mask
) * dispatch_width
/ 8;
4209 inst
->regs_written
= 4 * dispatch_width
/ 8;
4212 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4213 inst
->shadow_compare
= true;
4215 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
== IMM
)
4216 inst
->offset
= srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].ud
;
4218 if (instr
->op
== nir_texop_tg4
) {
4219 if (instr
->component
== 1 &&
4220 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4221 /* gather4 sampler is broken for green channel on RG32F --
4222 * we must ask for blue instead.
4224 inst
->offset
|= 2 << 16;
4226 inst
->offset
|= instr
->component
<< 16;
4229 if (devinfo
->gen
== 6)
4230 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4234 for (unsigned i
= 0; i
< dest_size
; i
++)
4235 nir_dest
[i
] = offset(dst
, bld
, i
);
4237 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
4240 if (instr
->op
== nir_texop_query_levels
) {
4241 /* # levels is in .w */
4242 nir_dest
[0] = offset(dst
, bld
, 3);
4243 } else if (instr
->op
== nir_texop_txs
&& dest_size
>= 3 &&
4244 (devinfo
->gen
< 7 || is_cube_array
)) {
4245 fs_reg depth
= offset(dst
, bld
, 2);
4246 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
4248 if (is_cube_array
) {
4249 /* fixup #layers for cube map arrays */
4250 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, brw_imm_d(6));
4251 } else if (devinfo
->gen
< 7) {
4252 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4253 bld
.emit_minmax(fixed_depth
, depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4256 nir_dest
[2] = fixed_depth
;
4259 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4263 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4265 switch (instr
->type
) {
4266 case nir_jump_break
:
4267 bld
.emit(BRW_OPCODE_BREAK
);
4269 case nir_jump_continue
:
4270 bld
.emit(BRW_OPCODE_CONTINUE
);
4272 case nir_jump_return
:
4274 unreachable("unknown jump");
4279 * This helper takes the result of a load operation that reads 32-bit elements
4287 * and shuffles the data to get this:
4294 * Which is exactly what we want if the load is reading 64-bit components
4295 * like doubles, where x represents the low 32-bit of the x double component
4296 * and y represents the high 32-bit of the x double component (likewise with
4297 * z and w for double component y). The parameter @components represents
4298 * the number of 64-bit components present in @src. This would typically be
4299 * 2 at most, since we can only fit 2 double elements in the result of a
4302 * Notice that @dst and @src can be the same register.
4305 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4308 uint32_t components
)
4310 assert(type_sz(src
.type
) == 4);
4311 assert(type_sz(dst
.type
) == 8);
4313 /* A temporary that we will use to shuffle the 32-bit data of each
4314 * component in the vector into valid 64-bit data. We can't write directly
4315 * to dst because dst can be (and would usually be) the same as src
4316 * and in that case the first MOV in the loop below would overwrite the
4317 * data read in the second MOV.
4319 fs_reg tmp
= bld
.vgrf(dst
.type
);
4321 for (unsigned i
= 0; i
< components
; i
++) {
4322 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4324 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4325 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4327 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4332 * This helper does the inverse operation of
4333 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4335 * We need to do this when we are going to use untyped write messsages that
4336 * operate with 32-bit components in order to arrange our 64-bit data to be
4337 * in the expected layout.
4339 * Notice that callers of this function, unlike in the case of the inverse
4340 * operation, would typically need to call this with dst and src being
4341 * different registers, since they would otherwise corrupt the original
4342 * 64-bit data they are about to write. Because of this the function checks
4343 * that the src and dst regions involved in the operation do not overlap.
4346 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4349 uint32_t components
)
4351 assert(type_sz(src
.type
) == 8);
4352 assert(type_sz(dst
.type
) == 4);
4354 assert(!src
.in_range(dst
, 2 * components
* bld
.dispatch_width() / 8));
4356 for (unsigned i
= 0; i
< components
; i
++) {
4357 const fs_reg component_i
= offset(src
, bld
, i
);
4358 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4359 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));