2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "program/prog_to_nir.h"
29 #include "brw_fs_surface_builder.h"
35 fs_visitor::emit_nir_code()
37 nir_shader
*nir
= prog
->nir
;
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
42 nir_setup_inputs(nir
);
43 nir_setup_outputs(nir
);
44 nir_setup_uniforms(nir
);
45 nir_emit_system_values(nir
);
47 /* get the main function and emit it */
48 nir_foreach_overload(nir
, overload
) {
49 assert(strcmp(overload
->function
->name
, "main") == 0);
50 assert(overload
->impl
);
51 nir_emit_impl(overload
->impl
);
56 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
58 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, shader
->num_inputs
);
60 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
61 enum brw_reg_type type
= brw_type_for_base_type(var
->type
);
62 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
66 case MESA_SHADER_VERTEX
: {
67 /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
68 * stored in nir_variable::location.
70 * However, NIR's load_input intrinsics use a different index - an
71 * offset into a single contiguous array containing all inputs.
72 * This index corresponds to the nir_variable::driver_location field.
74 * So, we need to copy from fs_reg(ATTR, var->location) to
75 * offset(nir_inputs, var->data.driver_location).
77 const glsl_type
*const t
= var
->type
->without_array();
78 const unsigned components
= t
->components();
79 const unsigned cols
= t
->matrix_columns
;
80 const unsigned elts
= t
->vector_elements
;
81 unsigned array_length
= var
->type
->is_array() ? var
->type
->length
: 1;
82 for (unsigned i
= 0; i
< array_length
; i
++) {
83 for (unsigned j
= 0; j
< cols
; j
++) {
84 for (unsigned k
= 0; k
< elts
; k
++) {
85 bld
.MOV(offset(retype(input
, type
), bld
,
86 components
* i
+ elts
* j
+ k
),
87 offset(fs_reg(ATTR
, var
->data
.location
+ i
, type
),
94 case MESA_SHADER_GEOMETRY
:
95 case MESA_SHADER_COMPUTE
:
96 case MESA_SHADER_TESS_CTRL
:
97 case MESA_SHADER_TESS_EVAL
:
98 unreachable("fs_visitor not used for these stages yet.");
100 case MESA_SHADER_FRAGMENT
:
101 if (var
->data
.location
== VARYING_SLOT_POS
) {
102 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
103 var
->data
.origin_upper_left
);
104 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
107 emit_general_interpolation(input
, var
->name
, var
->type
,
108 (glsl_interp_qualifier
) var
->data
.interpolation
,
109 var
->data
.location
, var
->data
.centroid
,
118 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
120 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
122 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, shader
->num_outputs
);
124 foreach_list_typed(nir_variable
, var
, node
, &shader
->outputs
) {
125 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
127 int vector_elements
=
128 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
129 : var
->type
->vector_elements
;
132 case MESA_SHADER_VERTEX
:
133 for (int i
= 0; i
< ALIGN(type_size(var
->type
), 4) / 4; i
++) {
134 int output
= var
->data
.location
+ i
;
135 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
136 this->output_components
[output
] = vector_elements
;
139 case MESA_SHADER_FRAGMENT
:
140 if (var
->data
.index
> 0) {
141 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
142 assert(var
->data
.index
== 1);
143 this->dual_src_output
= reg
;
144 this->do_dual_src
= true;
145 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
146 /* Writing gl_FragColor outputs to all color regions. */
147 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
148 this->outputs
[i
] = reg
;
149 this->output_components
[i
] = 4;
151 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
152 this->frag_depth
= reg
;
153 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
154 this->sample_mask
= reg
;
156 /* gl_FragData or a user-defined FS output */
157 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
158 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
160 /* General color output. */
161 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
162 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
163 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
164 this->output_components
[output
] = vector_elements
;
169 unreachable("unhandled shader stage");
175 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
177 num_direct_uniforms
= shader
->num_direct_uniforms
;
179 if (dispatch_width
!= 8)
182 /* We split the uniform register file in half. The first half is
183 * entirely direct uniforms. The second half is indirect.
185 param_size
[0] = num_direct_uniforms
;
186 if (shader
->num_uniforms
> num_direct_uniforms
)
187 param_size
[num_direct_uniforms
] = shader
->num_uniforms
- num_direct_uniforms
;
189 uniforms
= shader
->num_uniforms
;
192 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
193 /* UBO's and atomics don't take up space in the uniform file */
194 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
197 if (strncmp(var
->name
, "gl_", 3) == 0)
198 nir_setup_builtin_uniform(var
);
200 nir_setup_uniform(var
);
203 /* prog_to_nir doesn't create uniform variables; set param up directly. */
204 for (unsigned p
= 0; p
< prog
->Parameters
->NumParameters
; p
++) {
205 for (unsigned int i
= 0; i
< 4; i
++) {
206 stage_prog_data
->param
[4 * p
+ i
] =
207 &prog
->Parameters
->ParameterValues
[p
][i
];
214 fs_visitor::nir_setup_uniform(nir_variable
*var
)
216 int namelen
= strlen(var
->name
);
218 /* The data for our (non-builtin) uniforms is stored in a series of
219 * gl_uniform_driver_storage structs for each subcomponent that
220 * glGetUniformLocation() could name. We know it's been set up in the
221 * same order we'd walk the type, so walk the list of storage and find
222 * anything with our name, or the prefix of a component that starts with
225 unsigned index
= var
->data
.driver_location
;
226 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
227 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
229 if (storage
->builtin
)
232 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
233 (storage
->name
[namelen
] != 0 &&
234 storage
->name
[namelen
] != '.' &&
235 storage
->name
[namelen
] != '[')) {
239 unsigned slots
= storage
->type
->component_slots();
240 if (storage
->array_elements
)
241 slots
*= storage
->array_elements
;
243 for (unsigned i
= 0; i
< slots
; i
++) {
244 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
248 /* Make sure we actually initialized the right amount of stuff here. */
249 assert(var
->data
.driver_location
+ var
->type
->component_slots() == index
);
253 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
255 const nir_state_slot
*const slots
= var
->state_slots
;
256 assert(var
->state_slots
!= NULL
);
258 unsigned uniform_index
= var
->data
.driver_location
;
259 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
260 /* This state reference has already been setup by ir_to_mesa, but we'll
261 * get the same index back here.
263 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
264 (gl_state_index
*)slots
[i
].tokens
);
266 /* Add each of the unique swizzles of the element as a parameter.
267 * This'll end up matching the expected layout of the
268 * array/matrix/structure we're trying to fill in.
271 for (unsigned int j
= 0; j
< 4; j
++) {
272 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
273 if (swiz
== last_swiz
)
277 stage_prog_data
->param
[uniform_index
++] =
278 &prog
->Parameters
->ParameterValues
[index
][swiz
];
284 emit_system_values_block(nir_block
*block
, void *void_visitor
)
286 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
289 nir_foreach_instr(block
, instr
) {
290 if (instr
->type
!= nir_instr_type_intrinsic
)
293 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
294 switch (intrin
->intrinsic
) {
295 case nir_intrinsic_load_vertex_id
:
296 unreachable("should be lowered by lower_vertex_id().");
298 case nir_intrinsic_load_vertex_id_zero_base
:
299 assert(v
->stage
== MESA_SHADER_VERTEX
);
300 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
301 if (reg
->file
== BAD_FILE
)
302 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
305 case nir_intrinsic_load_base_vertex
:
306 assert(v
->stage
== MESA_SHADER_VERTEX
);
307 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
308 if (reg
->file
== BAD_FILE
)
309 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
312 case nir_intrinsic_load_instance_id
:
313 assert(v
->stage
== MESA_SHADER_VERTEX
);
314 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
315 if (reg
->file
== BAD_FILE
)
316 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
319 case nir_intrinsic_load_sample_pos
:
320 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
321 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
322 if (reg
->file
== BAD_FILE
)
323 *reg
= *v
->emit_samplepos_setup();
326 case nir_intrinsic_load_sample_id
:
327 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
328 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
329 if (reg
->file
== BAD_FILE
)
330 *reg
= *v
->emit_sampleid_setup();
333 case nir_intrinsic_load_sample_mask_in
:
334 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
335 assert(v
->devinfo
->gen
>= 7);
336 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
337 if (reg
->file
== BAD_FILE
)
338 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
339 BRW_REGISTER_TYPE_D
));
351 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
353 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
354 nir_foreach_overload(shader
, overload
) {
355 assert(strcmp(overload
->function
->name
, "main") == 0);
356 assert(overload
->impl
);
357 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
362 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
364 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
365 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
366 unsigned array_elems
=
367 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
368 unsigned size
= array_elems
* reg
->num_components
;
369 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
372 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
375 nir_emit_cf_list(&impl
->body
);
379 fs_visitor::nir_emit_cf_list(exec_list
*list
)
381 exec_list_validate(list
);
382 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
383 switch (node
->type
) {
385 nir_emit_if(nir_cf_node_as_if(node
));
388 case nir_cf_node_loop
:
389 nir_emit_loop(nir_cf_node_as_loop(node
));
392 case nir_cf_node_block
:
393 nir_emit_block(nir_cf_node_as_block(node
));
397 unreachable("Invalid CFG node block");
403 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
405 /* first, put the condition into f0 */
406 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
407 retype(get_nir_src(if_stmt
->condition
),
408 BRW_REGISTER_TYPE_D
));
409 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
411 bld
.IF(BRW_PREDICATE_NORMAL
);
413 nir_emit_cf_list(&if_stmt
->then_list
);
415 /* note: if the else is empty, dead CF elimination will remove it */
416 bld
.emit(BRW_OPCODE_ELSE
);
418 nir_emit_cf_list(&if_stmt
->else_list
);
420 bld
.emit(BRW_OPCODE_ENDIF
);
422 try_replace_with_sel();
426 fs_visitor::nir_emit_loop(nir_loop
*loop
)
428 bld
.emit(BRW_OPCODE_DO
);
430 nir_emit_cf_list(&loop
->body
);
432 bld
.emit(BRW_OPCODE_WHILE
);
436 fs_visitor::nir_emit_block(nir_block
*block
)
438 nir_foreach_instr(block
, instr
) {
439 nir_emit_instr(instr
);
444 fs_visitor::nir_emit_instr(nir_instr
*instr
)
446 const fs_builder abld
= bld
.annotate(NULL
, instr
);
448 switch (instr
->type
) {
449 case nir_instr_type_alu
:
450 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
453 case nir_instr_type_intrinsic
:
454 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
457 case nir_instr_type_tex
:
458 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
461 case nir_instr_type_load_const
:
462 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
465 case nir_instr_type_ssa_undef
:
466 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
469 case nir_instr_type_jump
:
470 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
474 unreachable("unknown instruction type");
479 brw_type_for_nir_type(nir_alu_type type
)
482 case nir_type_unsigned
:
483 return BRW_REGISTER_TYPE_UD
;
486 return BRW_REGISTER_TYPE_D
;
488 return BRW_REGISTER_TYPE_F
;
490 unreachable("unknown type");
493 return BRW_REGISTER_TYPE_F
;
497 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
498 const fs_reg
&result
)
500 if (!instr
->src
[0].src
.is_ssa
||
501 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
504 nir_intrinsic_instr
*src0
=
505 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
507 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
510 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
511 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
514 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
515 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
518 fs_reg tmp
= vgrf(glsl_type::int_type
);
520 if (devinfo
->gen
>= 6) {
521 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
522 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
524 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
526 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
527 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
529 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
531 * This negation looks like it's safe in practice, because bits 0:4 will
532 * surely be TRIANGLES
535 if (value1
->f
[0] == -1.0f
) {
539 tmp
.type
= BRW_REGISTER_TYPE_W
;
540 tmp
.subreg_offset
= 2;
543 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
544 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
546 tmp
.type
= BRW_REGISTER_TYPE_D
;
547 tmp
.subreg_offset
= 0;
550 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
551 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
553 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
555 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
556 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
558 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
560 * This negation looks like it's safe in practice, because bits 0:4 will
561 * surely be TRIANGLES
564 if (value1
->f
[0] == -1.0f
) {
568 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
570 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
576 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
578 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
581 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
582 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
585 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
586 op
[i
] = get_nir_src(instr
->src
[i
].src
);
587 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
588 op
[i
].abs
= instr
->src
[i
].abs
;
589 op
[i
].negate
= instr
->src
[i
].negate
;
592 /* We get a bunch of mov's out of the from_ssa pass and they may still
593 * be vectorized. We'll handle them as a special-case. We'll also
594 * handle vecN here because it's basically the same thing.
602 fs_reg temp
= result
;
603 bool need_extra_copy
= false;
604 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
605 if (!instr
->src
[i
].src
.is_ssa
&&
606 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
607 need_extra_copy
= true;
608 temp
= bld
.vgrf(result
.type
, 4);
613 for (unsigned i
= 0; i
< 4; i
++) {
614 if (!(instr
->dest
.write_mask
& (1 << i
)))
617 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
618 inst
= bld
.MOV(offset(temp
, bld
, i
),
619 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
621 inst
= bld
.MOV(offset(temp
, bld
, i
),
622 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
624 inst
->saturate
= instr
->dest
.saturate
;
627 /* In this case the source and destination registers were the same,
628 * so we need to insert an extra set of moves in order to deal with
631 if (need_extra_copy
) {
632 for (unsigned i
= 0; i
< 4; i
++) {
633 if (!(instr
->dest
.write_mask
& (1 << i
)))
636 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
645 /* At this point, we have dealt with any instruction that operates on
646 * more than a single channel. Therefore, we can just adjust the source
647 * and destination registers for that channel and emit the instruction.
649 unsigned channel
= 0;
650 if (nir_op_infos
[instr
->op
].output_size
== 0) {
651 /* Since NIR is doing the scalarizing for us, we should only ever see
652 * vectorized operations with a single channel.
654 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
655 channel
= ffs(instr
->dest
.write_mask
) - 1;
657 result
= offset(result
, bld
, channel
);
660 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
661 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
662 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
668 inst
= bld
.MOV(result
, op
[0]);
669 inst
->saturate
= instr
->dest
.saturate
;
674 bld
.MOV(result
, op
[0]);
678 /* AND(val, 0x80000000) gives the sign bit.
680 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
683 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
685 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
686 op
[0].type
= BRW_REGISTER_TYPE_UD
;
687 result
.type
= BRW_REGISTER_TYPE_UD
;
688 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
690 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
691 inst
->predicate
= BRW_PREDICATE_NORMAL
;
692 if (instr
->dest
.saturate
) {
693 inst
= bld
.MOV(result
, result
);
694 inst
->saturate
= true;
700 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
701 * -> non-negative val generates 0x00000000.
702 * Predicated OR sets 1 if val is positive.
704 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
705 bld
.ASR(result
, op
[0], fs_reg(31));
706 inst
= bld
.OR(result
, result
, fs_reg(1));
707 inst
->predicate
= BRW_PREDICATE_NORMAL
;
711 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
712 inst
->saturate
= instr
->dest
.saturate
;
716 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
717 inst
->saturate
= instr
->dest
.saturate
;
721 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
722 inst
->saturate
= instr
->dest
.saturate
;
726 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
727 inst
->saturate
= instr
->dest
.saturate
;
731 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
732 inst
->saturate
= instr
->dest
.saturate
;
736 if (fs_key
->high_quality_derivatives
) {
737 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
739 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
741 inst
->saturate
= instr
->dest
.saturate
;
743 case nir_op_fddx_fine
:
744 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
745 inst
->saturate
= instr
->dest
.saturate
;
747 case nir_op_fddx_coarse
:
748 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
749 inst
->saturate
= instr
->dest
.saturate
;
752 if (fs_key
->high_quality_derivatives
) {
753 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
754 fs_reg(fs_key
->render_to_fbo
));
756 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
757 fs_reg(fs_key
->render_to_fbo
));
759 inst
->saturate
= instr
->dest
.saturate
;
761 case nir_op_fddy_fine
:
762 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
763 fs_reg(fs_key
->render_to_fbo
));
764 inst
->saturate
= instr
->dest
.saturate
;
766 case nir_op_fddy_coarse
:
767 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
768 fs_reg(fs_key
->render_to_fbo
));
769 inst
->saturate
= instr
->dest
.saturate
;
774 inst
= bld
.ADD(result
, op
[0], op
[1]);
775 inst
->saturate
= instr
->dest
.saturate
;
779 inst
= bld
.MUL(result
, op
[0], op
[1]);
780 inst
->saturate
= instr
->dest
.saturate
;
784 bld
.MUL(result
, op
[0], op
[1]);
787 case nir_op_imul_high
:
788 case nir_op_umul_high
: {
789 if (devinfo
->gen
>= 7)
790 no16("SIMD16 explicit accumulator operands unsupported\n");
792 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
794 fs_inst
*mul
= bld
.MUL(acc
, op
[0], op
[1]);
795 bld
.MACH(result
, op
[0], op
[1]);
797 /* Until Gen8, integer multiplies read 32-bits from one source, and
798 * 16-bits from the other, and relying on the MACH instruction to
799 * generate the high bits of the result.
801 * On Gen8, the multiply instruction does a full 32x32-bit multiply,
802 * but in order to do a 64x64-bit multiply we have to simulate the
803 * previous behavior and then use a MACH instruction.
805 * FINISHME: Don't use source modifiers on src1.
807 if (devinfo
->gen
>= 8) {
808 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
809 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
810 if (mul
->src
[1].type
== BRW_REGISTER_TYPE_D
) {
811 mul
->src
[1].type
= BRW_REGISTER_TYPE_W
;
812 mul
->src
[1].stride
= 2;
814 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
815 mul
->src
[1].stride
= 2;
823 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
826 case nir_op_uadd_carry
:
827 unreachable("Should have been lowered by carry_to_arith().");
829 case nir_op_usub_borrow
:
830 unreachable("Should have been lowered by borrow_to_arith().");
833 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
839 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
845 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
850 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
855 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
859 if (devinfo
->gen
>= 8) {
860 resolve_source_modifiers(&op
[0]);
862 bld
.NOT(result
, op
[0]);
865 if (devinfo
->gen
>= 8) {
866 resolve_source_modifiers(&op
[0]);
867 resolve_source_modifiers(&op
[1]);
869 bld
.XOR(result
, op
[0], op
[1]);
872 if (devinfo
->gen
>= 8) {
873 resolve_source_modifiers(&op
[0]);
874 resolve_source_modifiers(&op
[1]);
876 bld
.OR(result
, op
[0], op
[1]);
879 if (devinfo
->gen
>= 8) {
880 resolve_source_modifiers(&op
[0]);
881 resolve_source_modifiers(&op
[1]);
883 bld
.AND(result
, op
[0], op
[1]);
895 case nir_op_ball_fequal2
:
896 case nir_op_ball_iequal2
:
897 case nir_op_ball_fequal3
:
898 case nir_op_ball_iequal3
:
899 case nir_op_ball_fequal4
:
900 case nir_op_ball_iequal4
:
901 case nir_op_bany_fnequal2
:
902 case nir_op_bany_inequal2
:
903 case nir_op_bany_fnequal3
:
904 case nir_op_bany_inequal3
:
905 case nir_op_bany_fnequal4
:
906 case nir_op_bany_inequal4
:
907 unreachable("Lowered by nir_lower_alu_reductions");
909 case nir_op_fnoise1_1
:
910 case nir_op_fnoise1_2
:
911 case nir_op_fnoise1_3
:
912 case nir_op_fnoise1_4
:
913 case nir_op_fnoise2_1
:
914 case nir_op_fnoise2_2
:
915 case nir_op_fnoise2_3
:
916 case nir_op_fnoise2_4
:
917 case nir_op_fnoise3_1
:
918 case nir_op_fnoise3_2
:
919 case nir_op_fnoise3_3
:
920 case nir_op_fnoise3_4
:
921 case nir_op_fnoise4_1
:
922 case nir_op_fnoise4_2
:
923 case nir_op_fnoise4_3
:
924 case nir_op_fnoise4_4
:
925 unreachable("not reached: should be handled by lower_noise");
928 unreachable("not reached: should be handled by ldexp_to_arith()");
931 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
932 inst
->saturate
= instr
->dest
.saturate
;
936 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
937 inst
->saturate
= instr
->dest
.saturate
;
942 bld
.MOV(result
, negate(op
[0]));
946 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
949 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
953 inst
= bld
.RNDZ(result
, op
[0]);
954 inst
->saturate
= instr
->dest
.saturate
;
958 op
[0].negate
= !op
[0].negate
;
959 fs_reg temp
= vgrf(glsl_type::float_type
);
960 bld
.RNDD(temp
, op
[0]);
962 inst
= bld
.MOV(result
, temp
);
963 inst
->saturate
= instr
->dest
.saturate
;
967 inst
= bld
.RNDD(result
, op
[0]);
968 inst
->saturate
= instr
->dest
.saturate
;
971 inst
= bld
.FRC(result
, op
[0]);
972 inst
->saturate
= instr
->dest
.saturate
;
974 case nir_op_fround_even
:
975 inst
= bld
.RNDE(result
, op
[0]);
976 inst
->saturate
= instr
->dest
.saturate
;
982 if (devinfo
->gen
>= 6) {
983 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
984 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
986 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
987 inst
= bld
.SEL(result
, op
[0], op
[1]);
988 inst
->predicate
= BRW_PREDICATE_NORMAL
;
990 inst
->saturate
= instr
->dest
.saturate
;
996 if (devinfo
->gen
>= 6) {
997 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
998 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1000 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
1001 inst
= bld
.SEL(result
, op
[0], op
[1]);
1002 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1004 inst
->saturate
= instr
->dest
.saturate
;
1007 case nir_op_pack_snorm_2x16
:
1008 case nir_op_pack_snorm_4x8
:
1009 case nir_op_pack_unorm_2x16
:
1010 case nir_op_pack_unorm_4x8
:
1011 case nir_op_unpack_snorm_2x16
:
1012 case nir_op_unpack_snorm_4x8
:
1013 case nir_op_unpack_unorm_2x16
:
1014 case nir_op_unpack_unorm_4x8
:
1015 case nir_op_unpack_half_2x16
:
1016 case nir_op_pack_half_2x16
:
1017 unreachable("not reached: should be handled by lower_packing_builtins");
1019 case nir_op_unpack_half_2x16_split_x
:
1020 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1021 inst
->saturate
= instr
->dest
.saturate
;
1023 case nir_op_unpack_half_2x16_split_y
:
1024 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1025 inst
->saturate
= instr
->dest
.saturate
;
1029 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1030 inst
->saturate
= instr
->dest
.saturate
;
1033 case nir_op_bitfield_reverse
:
1034 bld
.BFREV(result
, op
[0]);
1037 case nir_op_bit_count
:
1038 bld
.CBIT(result
, op
[0]);
1041 case nir_op_ufind_msb
:
1042 case nir_op_ifind_msb
: {
1043 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1045 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1046 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1047 * subtract the result from 31 to convert the MSB count into an LSB count.
1050 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
1051 fs_reg
neg_result(result
);
1052 neg_result
.negate
= true;
1053 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
1054 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1058 case nir_op_find_lsb
:
1059 bld
.FBL(result
, op
[0]);
1062 case nir_op_ubitfield_extract
:
1063 case nir_op_ibitfield_extract
:
1064 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1067 bld
.BFI1(result
, op
[0], op
[1]);
1070 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1073 case nir_op_bitfield_insert
:
1074 unreachable("not reached: should be handled by "
1075 "lower_instructions::bitfield_insert_to_bfm_bfi");
1078 bld
.SHL(result
, op
[0], op
[1]);
1081 bld
.ASR(result
, op
[0], op
[1]);
1084 bld
.SHR(result
, op
[0], op
[1]);
1087 case nir_op_pack_half_2x16_split
:
1088 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1092 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1093 inst
->saturate
= instr
->dest
.saturate
;
1097 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1098 inst
->saturate
= instr
->dest
.saturate
;
1102 if (optimize_frontfacing_ternary(instr
, result
))
1105 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
1106 inst
= bld
.SEL(result
, op
[1], op
[2]);
1107 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1111 unreachable("unhandled instruction");
1114 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1115 * to sign extend the low bit to 0/~0
1117 if (devinfo
->gen
<= 5 &&
1118 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1119 fs_reg masked
= vgrf(glsl_type::int_type
);
1120 bld
.AND(masked
, result
, fs_reg(1));
1121 masked
.negate
= true;
1122 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1127 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1128 nir_load_const_instr
*instr
)
1130 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1132 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1133 bld
.MOV(offset(reg
, bld
, i
), fs_reg(instr
->value
.i
[i
]));
1135 nir_ssa_values
[instr
->def
.index
] = reg
;
1139 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1141 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1142 instr
->def
.num_components
);
1146 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1147 unsigned base_offset
, nir_src
*indirect
)
1151 assert(!nir_reg
->is_global
);
1153 reg
= v
->nir_locals
[nir_reg
->index
];
1155 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1157 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1159 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1160 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1161 fs_reg(multiplier
));
1168 fs_visitor::get_nir_src(nir_src src
)
1172 reg
= nir_ssa_values
[src
.ssa
->index
];
1174 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1178 /* to avoid floating-point denorm flushing problems, set the type by
1179 * default to D - instructions that need floating point semantics will set
1180 * this to F if they need to
1182 return retype(reg
, BRW_REGISTER_TYPE_D
);
1186 fs_visitor::get_nir_dest(nir_dest dest
)
1189 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1190 dest
.ssa
.num_components
);
1191 return nir_ssa_values
[dest
.ssa
.index
];
1194 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1199 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1202 for (unsigned i
= 0; i
< 4; i
++) {
1203 if (!((wr_mask
>> i
) & 1))
1206 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1207 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1208 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1209 if (new_inst
->src
[j
].file
== GRF
)
1210 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1217 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1220 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1221 dest
= get_nir_dest(instr
->dest
);
1223 bool has_indirect
= false;
1225 switch (instr
->intrinsic
) {
1226 case nir_intrinsic_discard
:
1227 case nir_intrinsic_discard_if
: {
1228 /* We track our discarded pixels in f0.1. By predicating on it, we can
1229 * update just the flag bits that aren't yet discarded. If there's no
1230 * condition, we emit a CMP of g0 != g0, so all currently executing
1231 * channels will get turned off.
1234 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1235 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1236 fs_reg(0), BRW_CONDITIONAL_Z
);
1238 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1239 BRW_REGISTER_TYPE_UW
));
1240 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1242 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1243 cmp
->flag_subreg
= 1;
1245 if (devinfo
->gen
>= 6) {
1246 emit_discard_jump();
1251 case nir_intrinsic_atomic_counter_inc
:
1252 case nir_intrinsic_atomic_counter_dec
:
1253 case nir_intrinsic_atomic_counter_read
: {
1254 using namespace surface_access
;
1256 /* Get the arguments of the atomic intrinsic. */
1257 const fs_reg offset
= get_nir_src(instr
->src
[0]);
1258 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
1259 instr
->const_index
[0]);
1262 /* Emit a surface read or atomic op. */
1263 switch (instr
->intrinsic
) {
1264 case nir_intrinsic_atomic_counter_read
:
1265 tmp
= emit_untyped_read(bld
, fs_reg(surface
), offset
, 1, 1);
1268 case nir_intrinsic_atomic_counter_inc
:
1269 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1270 fs_reg(), 1, 1, BRW_AOP_INC
);
1273 case nir_intrinsic_atomic_counter_dec
:
1274 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1275 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
1279 unreachable("Unreachable");
1282 /* Assign the result. */
1283 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
1285 /* Mark the surface as used. */
1286 brw_mark_surface_used(stage_prog_data
, surface
);
1290 case nir_intrinsic_memory_barrier
: {
1291 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
1292 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
1297 case nir_intrinsic_load_front_face
:
1298 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1299 *emit_frontfacing_interpolation());
1302 case nir_intrinsic_load_vertex_id
:
1303 unreachable("should be lowered by lower_vertex_id()");
1305 case nir_intrinsic_load_vertex_id_zero_base
: {
1306 fs_reg vertex_id
= nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
1307 assert(vertex_id
.file
!= BAD_FILE
);
1308 dest
.type
= vertex_id
.type
;
1309 bld
.MOV(dest
, vertex_id
);
1313 case nir_intrinsic_load_base_vertex
: {
1314 fs_reg base_vertex
= nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
1315 assert(base_vertex
.file
!= BAD_FILE
);
1316 dest
.type
= base_vertex
.type
;
1317 bld
.MOV(dest
, base_vertex
);
1321 case nir_intrinsic_load_instance_id
: {
1322 fs_reg instance_id
= nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
1323 assert(instance_id
.file
!= BAD_FILE
);
1324 dest
.type
= instance_id
.type
;
1325 bld
.MOV(dest
, instance_id
);
1329 case nir_intrinsic_load_sample_mask_in
: {
1330 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1331 assert(sample_mask_in
.file
!= BAD_FILE
);
1332 dest
.type
= sample_mask_in
.type
;
1333 bld
.MOV(dest
, sample_mask_in
);
1337 case nir_intrinsic_load_sample_pos
: {
1338 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1339 assert(sample_pos
.file
!= BAD_FILE
);
1340 dest
.type
= sample_pos
.type
;
1341 bld
.MOV(dest
, sample_pos
);
1342 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1346 case nir_intrinsic_load_sample_id
: {
1347 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1348 assert(sample_id
.file
!= BAD_FILE
);
1349 dest
.type
= sample_id
.type
;
1350 bld
.MOV(dest
, sample_id
);
1354 case nir_intrinsic_load_uniform_indirect
:
1355 has_indirect
= true;
1357 case nir_intrinsic_load_uniform
: {
1358 unsigned index
= instr
->const_index
[0];
1361 if (index
< num_direct_uniforms
) {
1362 uniform_reg
= fs_reg(UNIFORM
, 0);
1364 uniform_reg
= fs_reg(UNIFORM
, num_direct_uniforms
);
1365 index
-= num_direct_uniforms
;
1368 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1369 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, index
);
1371 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1375 dest
= offset(dest
, bld
, 1);
1380 case nir_intrinsic_load_ubo_indirect
:
1381 has_indirect
= true;
1383 case nir_intrinsic_load_ubo
: {
1384 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1388 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1391 /* The block index is not a constant. Evaluate the index expression
1392 * per-channel and add the base UBO index; we have to select a value
1393 * from any live channel.
1395 surf_index
= vgrf(glsl_type::uint_type
);
1396 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1397 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1398 surf_index
= bld
.emit_uniformize(surf_index
);
1400 /* Assume this may touch any UBO. It would be nice to provide
1401 * a tighter bound, but the array information is already lowered away.
1403 brw_mark_surface_used(prog_data
,
1404 stage_prog_data
->binding_table
.ubo_start
+
1405 shader_prog
->NumUniformBlocks
- 1);
1409 /* Turn the byte offset into a dword offset. */
1410 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1411 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1412 BRW_REGISTER_TYPE_D
),
1415 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1416 for (int i
= 0; i
< instr
->num_components
; i
++)
1417 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
1418 base_offset
, vec4_offset
+ i
);
1420 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1421 packed_consts
.type
= dest
.type
;
1423 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1424 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1425 surf_index
, const_offset_reg
);
1427 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1428 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1430 /* The std140 packing rules don't allow vectors to cross 16-byte
1431 * boundaries, and a reg is 32 bytes.
1433 assert(packed_consts
.subreg_offset
< 32);
1435 bld
.MOV(dest
, packed_consts
);
1436 dest
= offset(dest
, bld
, 1);
1442 case nir_intrinsic_load_input_indirect
:
1443 has_indirect
= true;
1445 case nir_intrinsic_load_input
: {
1447 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1448 fs_reg src
= offset(retype(nir_inputs
, dest
.type
), bld
,
1449 instr
->const_index
[0] + index
);
1451 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1455 dest
= offset(dest
, bld
, 1);
1460 /* Handle ARB_gpu_shader5 interpolation intrinsics
1462 * It's worth a quick word of explanation as to why we handle the full
1463 * variable-based interpolation intrinsic rather than a lowered version
1464 * with like we do for other inputs. We have to do that because the way
1465 * we set up inputs doesn't allow us to use the already setup inputs for
1466 * interpolation. At the beginning of the shader, we go through all of
1467 * the input variables and do the initial interpolation and put it in
1468 * the nir_inputs array based on its location as determined in
1469 * nir_lower_io. If the input isn't used, dead code cleans up and
1470 * everything works fine. However, when we get to the ARB_gpu_shader5
1471 * interpolation intrinsics, we need to reinterpolate the input
1472 * differently. If we used an intrinsic that just had an index it would
1473 * only give us the offset into the nir_inputs array. However, this is
1474 * useless because that value is post-interpolation and we need
1475 * pre-interpolation. In order to get the actual location of the bits
1476 * we get from the vertex fetching hardware, we need the variable.
1478 case nir_intrinsic_interp_var_at_centroid
:
1479 case nir_intrinsic_interp_var_at_sample
:
1480 case nir_intrinsic_interp_var_at_offset
: {
1481 assert(stage
== MESA_SHADER_FRAGMENT
);
1483 ((struct brw_wm_prog_data
*) prog_data
)->pulls_bary
= true;
1485 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1487 /* For most messages, we need one reg of ignored data; the hardware
1488 * requires mlen==1 even when there is no payload. in the per-slot
1489 * offset case, we'll replace this with the proper source data.
1491 fs_reg src
= vgrf(glsl_type::float_type
);
1492 int mlen
= 1; /* one reg unless overriden */
1495 switch (instr
->intrinsic
) {
1496 case nir_intrinsic_interp_var_at_centroid
:
1497 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1498 dst_xy
, src
, fs_reg(0u));
1501 case nir_intrinsic_interp_var_at_sample
: {
1502 /* XXX: We should probably handle non-constant sample id's */
1503 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1504 assert(const_sample
);
1505 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1506 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_xy
, src
,
1511 case nir_intrinsic_interp_var_at_offset
: {
1512 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1515 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1516 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1518 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_xy
, src
,
1519 fs_reg(off_x
| (off_y
<< 4)));
1521 src
= vgrf(glsl_type::ivec2_type
);
1522 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1523 BRW_REGISTER_TYPE_F
);
1524 for (int i
= 0; i
< 2; i
++) {
1525 fs_reg temp
= vgrf(glsl_type::float_type
);
1526 bld
.MUL(temp
, offset(offset_src
, bld
, i
), fs_reg(16.0f
));
1527 fs_reg itemp
= vgrf(glsl_type::int_type
);
1528 bld
.MOV(itemp
, temp
); /* float to int */
1530 /* Clamp the upper end of the range to +7/16.
1531 * ARB_gpu_shader5 requires that we support a maximum offset
1532 * of +0.5, which isn't representable in a S0.4 value -- if
1533 * we didn't clamp it, we'd end up with -8/16, which is the
1534 * opposite of what the shader author wanted.
1536 * This is legal due to ARB_gpu_shader5's quantization
1539 * "Not all values of <offset> may be supported; x and y
1540 * offsets may be rounded to fixed-point values with the
1541 * number of fraction bits given by the
1542 * implementation-dependent constant
1543 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1545 set_condmod(BRW_CONDITIONAL_L
,
1546 bld
.SEL(offset(src
, bld
, i
), itemp
, fs_reg(7)));
1549 mlen
= 2 * dispatch_width
/ 8;
1550 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_xy
, src
,
1557 unreachable("Invalid intrinsic");
1561 /* 2 floats per slot returned */
1562 inst
->regs_written
= 2 * dispatch_width
/ 8;
1563 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1564 INTERP_QUALIFIER_NOPERSPECTIVE
;
1566 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1567 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1568 src
.type
= dest
.type
;
1570 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1571 dest
= offset(dest
, bld
, 1);
1576 case nir_intrinsic_store_output_indirect
:
1577 has_indirect
= true;
1579 case nir_intrinsic_store_output
: {
1580 fs_reg src
= get_nir_src(instr
->src
[0]);
1582 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1583 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
1584 instr
->const_index
[0] + index
);
1586 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1588 bld
.MOV(new_dest
, src
);
1589 src
= offset(src
, bld
, 1);
1594 case nir_intrinsic_barrier
:
1599 unreachable("unknown intrinsic");
1604 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1606 unsigned sampler
= instr
->sampler_index
;
1607 fs_reg
sampler_reg(sampler
);
1609 /* FINISHME: We're failing to recompile our programs when the sampler is
1610 * updated. This only matters for the texture rectangle scale parameters
1611 * (pre-gen6, or gen6+ with GL_CLAMP).
1613 int texunit
= prog
->SamplerUnits
[sampler
];
1615 int gather_component
= instr
->component
;
1617 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1619 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1622 int lod_components
= 0;
1623 int UNUSED offset_components
= 0;
1625 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1627 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1628 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1629 switch (instr
->src
[i
].src_type
) {
1630 case nir_tex_src_bias
:
1631 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1633 case nir_tex_src_comparitor
:
1634 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1636 case nir_tex_src_coord
:
1637 switch (instr
->op
) {
1639 case nir_texop_txf_ms
:
1640 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1643 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1647 case nir_tex_src_ddx
:
1648 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1649 lod_components
= nir_tex_instr_src_size(instr
, i
);
1651 case nir_tex_src_ddy
:
1652 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1654 case nir_tex_src_lod
:
1655 switch (instr
->op
) {
1657 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1660 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1663 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1667 case nir_tex_src_ms_index
:
1668 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1670 case nir_tex_src_offset
:
1671 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1672 if (instr
->is_array
)
1673 offset_components
= instr
->coord_components
- 1;
1675 offset_components
= instr
->coord_components
;
1677 case nir_tex_src_projector
:
1678 unreachable("should be lowered");
1680 case nir_tex_src_sampler_offset
: {
1681 /* Figure out the highest possible sampler index and mark it as used */
1682 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1683 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
1684 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1686 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1688 brw_mark_surface_used(prog_data
, max_used
);
1690 /* Emit code to evaluate the actual indexing expression */
1691 sampler_reg
= vgrf(glsl_type::uint_type
);
1692 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
1693 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
1698 unreachable("unknown texture source");
1702 if (instr
->op
== nir_texop_txf_ms
) {
1703 if (devinfo
->gen
>= 7 &&
1704 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1705 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1711 for (unsigned i
= 0; i
< 3; i
++) {
1712 if (instr
->const_offset
[i
] != 0) {
1713 assert(offset_components
== 0);
1714 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
1719 enum glsl_base_type dest_base_type
;
1720 switch (instr
->dest_type
) {
1721 case nir_type_float
:
1722 dest_base_type
= GLSL_TYPE_FLOAT
;
1725 dest_base_type
= GLSL_TYPE_INT
;
1727 case nir_type_unsigned
:
1728 dest_base_type
= GLSL_TYPE_UINT
;
1731 unreachable("bad type");
1734 const glsl_type
*dest_type
=
1735 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1738 ir_texture_opcode op
;
1739 switch (instr
->op
) {
1740 case nir_texop_lod
: op
= ir_lod
; break;
1741 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1742 case nir_texop_tex
: op
= ir_tex
; break;
1743 case nir_texop_tg4
: op
= ir_tg4
; break;
1744 case nir_texop_txb
: op
= ir_txb
; break;
1745 case nir_texop_txd
: op
= ir_txd
; break;
1746 case nir_texop_txf
: op
= ir_txf
; break;
1747 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1748 case nir_texop_txl
: op
= ir_txl
; break;
1749 case nir_texop_txs
: op
= ir_txs
; break;
1751 unreachable("unknown texture opcode");
1754 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1755 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1756 tex_offset
, mcs
, gather_component
,
1757 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1759 fs_reg dest
= get_nir_dest(instr
->dest
);
1760 dest
.type
= this->result
.type
;
1761 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1762 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
1763 dest
, this->result
),
1764 (1 << num_components
) - 1);
1768 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
1770 switch (instr
->type
) {
1771 case nir_jump_break
:
1772 bld
.emit(BRW_OPCODE_BREAK
);
1774 case nir_jump_continue
:
1775 bld
.emit(BRW_OPCODE_CONTINUE
);
1777 case nir_jump_return
:
1779 unreachable("unknown jump");