2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
41 nir_emit_system_values();
43 /* get the main function and emit it */
44 nir_foreach_function(function
, nir
) {
45 assert(strcmp(function
->name
, "main") == 0);
46 assert(function
->impl
);
47 nir_emit_impl(function
->impl
);
52 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
53 const glsl_type
*type
,
56 if (type
->is_array() || type
->is_matrix()) {
57 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
58 const unsigned length
= glsl_get_length(type
);
60 for (unsigned i
= 0; i
< length
; i
++) {
61 nir_setup_single_output_varying(reg
, elem_type
, location
);
63 } else if (type
->is_record()) {
64 for (unsigned i
= 0; i
< type
->length
; i
++) {
65 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
66 nir_setup_single_output_varying(reg
, field_type
, location
);
69 assert(type
->is_scalar() || type
->is_vector());
70 unsigned num_iter
= 1;
71 if (type
->is_dual_slot())
73 for (unsigned count
= 0; count
< num_iter
; count
++) {
74 this->outputs
[*location
] = *reg
;
75 *reg
= offset(*reg
, bld
, 4);
82 fs_visitor::nir_setup_outputs()
84 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
87 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
89 nir_foreach_variable(var
, &nir
->outputs
) {
91 case MESA_SHADER_VERTEX
:
92 case MESA_SHADER_TESS_EVAL
:
93 case MESA_SHADER_GEOMETRY
: {
94 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
95 unsigned location
= var
->data
.location
;
96 nir_setup_single_output_varying(®
, var
->type
, &location
);
100 unreachable("unhandled shader stage");
106 fs_visitor::nir_setup_uniforms()
108 if (dispatch_width
!= min_dispatch_width
)
111 uniforms
= nir
->num_uniforms
/ 4;
115 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
119 nir_foreach_instr(instr
, block
) {
120 if (instr
->type
!= nir_instr_type_intrinsic
)
123 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
124 switch (intrin
->intrinsic
) {
125 case nir_intrinsic_load_vertex_id
:
126 unreachable("should be lowered by lower_vertex_id().");
128 case nir_intrinsic_load_vertex_id_zero_base
:
129 assert(v
->stage
== MESA_SHADER_VERTEX
);
130 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
131 if (reg
->file
== BAD_FILE
)
132 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
135 case nir_intrinsic_load_base_vertex
:
136 assert(v
->stage
== MESA_SHADER_VERTEX
);
137 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
138 if (reg
->file
== BAD_FILE
)
139 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
142 case nir_intrinsic_load_instance_id
:
143 assert(v
->stage
== MESA_SHADER_VERTEX
);
144 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
145 if (reg
->file
== BAD_FILE
)
146 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
149 case nir_intrinsic_load_base_instance
:
150 assert(v
->stage
== MESA_SHADER_VERTEX
);
151 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
152 if (reg
->file
== BAD_FILE
)
153 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
156 case nir_intrinsic_load_draw_id
:
157 assert(v
->stage
== MESA_SHADER_VERTEX
);
158 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
159 if (reg
->file
== BAD_FILE
)
160 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
163 case nir_intrinsic_load_invocation_id
:
164 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
166 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
167 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
168 if (reg
->file
== BAD_FILE
) {
169 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
170 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
171 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
172 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
177 case nir_intrinsic_load_sample_pos
:
178 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
179 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
180 if (reg
->file
== BAD_FILE
)
181 *reg
= *v
->emit_samplepos_setup();
184 case nir_intrinsic_load_sample_id
:
185 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
186 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
187 if (reg
->file
== BAD_FILE
)
188 *reg
= *v
->emit_sampleid_setup();
191 case nir_intrinsic_load_sample_mask_in
:
192 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
193 assert(v
->devinfo
->gen
>= 7);
194 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
195 if (reg
->file
== BAD_FILE
)
196 *reg
= *v
->emit_samplemaskin_setup();
199 case nir_intrinsic_load_work_group_id
:
200 assert(v
->stage
== MESA_SHADER_COMPUTE
);
201 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
202 if (reg
->file
== BAD_FILE
)
203 *reg
= *v
->emit_cs_work_group_id_setup();
206 case nir_intrinsic_load_helper_invocation
:
207 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
208 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
209 if (reg
->file
== BAD_FILE
) {
210 const fs_builder abld
=
211 v
->bld
.annotate("gl_HelperInvocation", NULL
);
213 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
214 * pixel mask is in g1.7 of the thread payload.
216 * We move the per-channel pixel enable bit to the low bit of each
217 * channel by shifting the byte containing the pixel mask by the
218 * vector immediate 0x76543210UV.
220 * The region of <1,8,0> reads only 1 byte (the pixel masks for
221 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
222 * masks for 2 and 3) in SIMD16.
224 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
226 stride(byte_offset(retype(brw_vec1_grf(1, 0),
227 BRW_REGISTER_TYPE_UB
), 28),
229 brw_imm_v(0x76543210));
231 /* A set bit in the pixel mask means the channel is enabled, but
232 * that is the opposite of gl_HelperInvocation so we need to invert
235 * The negate source-modifier bit of logical instructions on Gen8+
236 * performs 1's complement negation, so we can use that instead of
239 fs_reg inverted
= negate(shifted
);
240 if (v
->devinfo
->gen
< 8) {
241 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
242 abld
.NOT(inverted
, shifted
);
245 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
246 * with 1 and negating.
248 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
249 abld
.AND(anded
, inverted
, brw_imm_uw(1));
251 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
252 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
266 fs_visitor::nir_emit_system_values()
268 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
269 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
270 nir_system_values
[i
] = fs_reg();
273 nir_foreach_function(function
, nir
) {
274 assert(strcmp(function
->name
, "main") == 0);
275 assert(function
->impl
);
276 nir_foreach_block(block
, function
->impl
) {
277 emit_system_values_block(block
, this);
283 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
285 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
286 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
287 nir_locals
[i
] = fs_reg();
290 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
291 unsigned array_elems
=
292 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
293 unsigned size
= array_elems
* reg
->num_components
;
294 const brw_reg_type reg_type
=
295 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
296 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
299 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
302 nir_emit_cf_list(&impl
->body
);
306 fs_visitor::nir_emit_cf_list(exec_list
*list
)
308 exec_list_validate(list
);
309 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
310 switch (node
->type
) {
312 nir_emit_if(nir_cf_node_as_if(node
));
315 case nir_cf_node_loop
:
316 nir_emit_loop(nir_cf_node_as_loop(node
));
319 case nir_cf_node_block
:
320 nir_emit_block(nir_cf_node_as_block(node
));
324 unreachable("Invalid CFG node block");
330 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
332 /* first, put the condition into f0 */
333 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
334 retype(get_nir_src(if_stmt
->condition
),
335 BRW_REGISTER_TYPE_D
));
336 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
338 bld
.IF(BRW_PREDICATE_NORMAL
);
340 nir_emit_cf_list(&if_stmt
->then_list
);
342 /* note: if the else is empty, dead CF elimination will remove it */
343 bld
.emit(BRW_OPCODE_ELSE
);
345 nir_emit_cf_list(&if_stmt
->else_list
);
347 bld
.emit(BRW_OPCODE_ENDIF
);
351 fs_visitor::nir_emit_loop(nir_loop
*loop
)
353 bld
.emit(BRW_OPCODE_DO
);
355 nir_emit_cf_list(&loop
->body
);
357 bld
.emit(BRW_OPCODE_WHILE
);
361 fs_visitor::nir_emit_block(nir_block
*block
)
363 nir_foreach_instr(instr
, block
) {
364 nir_emit_instr(instr
);
369 fs_visitor::nir_emit_instr(nir_instr
*instr
)
371 const fs_builder abld
= bld
.annotate(NULL
, instr
);
373 switch (instr
->type
) {
374 case nir_instr_type_alu
:
375 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
378 case nir_instr_type_intrinsic
:
380 case MESA_SHADER_VERTEX
:
381 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
383 case MESA_SHADER_TESS_CTRL
:
384 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
386 case MESA_SHADER_TESS_EVAL
:
387 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
389 case MESA_SHADER_GEOMETRY
:
390 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
392 case MESA_SHADER_FRAGMENT
:
393 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
395 case MESA_SHADER_COMPUTE
:
396 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
399 unreachable("unsupported shader stage");
403 case nir_instr_type_tex
:
404 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
407 case nir_instr_type_load_const
:
408 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
411 case nir_instr_type_ssa_undef
:
412 /* We create a new VGRF for undefs on every use (by handling
413 * them in get_nir_src()), rather than for each definition.
414 * This helps register coalescing eliminate MOVs from undef.
418 case nir_instr_type_jump
:
419 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
423 unreachable("unknown instruction type");
428 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
432 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
433 const fs_reg
&result
)
435 if (!instr
->src
[0].src
.is_ssa
||
436 !instr
->src
[0].src
.ssa
->parent_instr
)
439 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
442 nir_alu_instr
*src0
=
443 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
445 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
446 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
449 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
450 assert(element
!= NULL
);
452 /* Element type to extract.*/
453 const brw_reg_type type
= brw_int_type(
454 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
455 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
457 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
458 op0
.type
= brw_type_for_nir_type(
459 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
460 nir_src_bit_size(src0
->src
[0].src
)));
461 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
463 set_saturate(instr
->dest
.saturate
,
464 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
469 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
470 const fs_reg
&result
)
472 if (!instr
->src
[0].src
.is_ssa
||
473 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
476 nir_intrinsic_instr
*src0
=
477 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
479 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
482 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
483 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
486 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
487 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
490 fs_reg tmp
= vgrf(glsl_type::int_type
);
492 if (devinfo
->gen
>= 6) {
493 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
494 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
496 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
498 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
499 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
501 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
503 * This negation looks like it's safe in practice, because bits 0:4 will
504 * surely be TRIANGLES
507 if (value1
->f32
[0] == -1.0f
) {
511 tmp
.type
= BRW_REGISTER_TYPE_W
;
512 tmp
.subreg_offset
= 2;
515 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
517 tmp
.type
= BRW_REGISTER_TYPE_D
;
518 tmp
.subreg_offset
= 0;
521 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
522 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
524 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
526 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
527 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
529 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
531 * This negation looks like it's safe in practice, because bits 0:4 will
532 * surely be TRIANGLES
535 if (value1
->f32
[0] == -1.0f
) {
539 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
541 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
547 emit_find_msb_using_lzd(const fs_builder
&bld
,
548 const fs_reg
&result
,
556 /* LZD of an absolute value source almost always does the right
557 * thing. There are two problem values:
559 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
560 * 0. However, findMSB(int(0x80000000)) == 30.
562 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
563 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
565 * For a value of zero or negative one, -1 will be returned.
567 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
568 * findMSB(-(1<<x)) should return x-1.
570 * For all negative number cases, including 0x80000000 and
571 * 0xffffffff, the correct value is obtained from LZD if instead of
572 * negating the (already negative) value the logical-not is used. A
573 * conditonal logical-not can be achieved in two instructions.
575 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
577 bld
.ASR(temp
, src
, brw_imm_d(31));
578 bld
.XOR(temp
, temp
, src
);
581 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
582 retype(temp
, BRW_REGISTER_TYPE_UD
));
584 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
585 * from the LSB side. Subtract the result from 31 to convert the MSB
586 * count into an LSB count. If no bits are set, LZD will return 32.
587 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
589 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
590 inst
->src
[0].negate
= true;
594 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
596 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
599 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
600 result
.type
= brw_type_for_nir_type(
601 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
602 nir_dest_bit_size(instr
->dest
.dest
)));
605 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
606 op
[i
] = get_nir_src(instr
->src
[i
].src
);
607 op
[i
].type
= brw_type_for_nir_type(
608 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
609 nir_src_bit_size(instr
->src
[i
].src
)));
610 op
[i
].abs
= instr
->src
[i
].abs
;
611 op
[i
].negate
= instr
->src
[i
].negate
;
614 /* We get a bunch of mov's out of the from_ssa pass and they may still
615 * be vectorized. We'll handle them as a special-case. We'll also
616 * handle vecN here because it's basically the same thing.
624 fs_reg temp
= result
;
625 bool need_extra_copy
= false;
626 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
627 if (!instr
->src
[i
].src
.is_ssa
&&
628 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
629 need_extra_copy
= true;
630 temp
= bld
.vgrf(result
.type
, 4);
635 for (unsigned i
= 0; i
< 4; i
++) {
636 if (!(instr
->dest
.write_mask
& (1 << i
)))
639 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
640 inst
= bld
.MOV(offset(temp
, bld
, i
),
641 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
643 inst
= bld
.MOV(offset(temp
, bld
, i
),
644 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
646 inst
->saturate
= instr
->dest
.saturate
;
649 /* In this case the source and destination registers were the same,
650 * so we need to insert an extra set of moves in order to deal with
653 if (need_extra_copy
) {
654 for (unsigned i
= 0; i
< 4; i
++) {
655 if (!(instr
->dest
.write_mask
& (1 << i
)))
658 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
667 /* At this point, we have dealt with any instruction that operates on
668 * more than a single channel. Therefore, we can just adjust the source
669 * and destination registers for that channel and emit the instruction.
671 unsigned channel
= 0;
672 if (nir_op_infos
[instr
->op
].output_size
== 0) {
673 /* Since NIR is doing the scalarizing for us, we should only ever see
674 * vectorized operations with a single channel.
676 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
677 channel
= ffs(instr
->dest
.write_mask
) - 1;
679 result
= offset(result
, bld
, channel
);
682 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
683 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
684 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
690 if (optimize_extract_to_float(instr
, result
))
692 inst
= bld
.MOV(result
, op
[0]);
693 inst
->saturate
= instr
->dest
.saturate
;
699 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
701 * "When source or destination is 64b (...), regioning in Align1
702 * must follow these rules:
704 * 1. Source and destination horizontal stride must be aligned to
708 * This means that 32-bit to 64-bit conversions need to have the 32-bit
709 * data elements aligned to 64-bit. This restriction does not apply to
712 if (devinfo
->is_cherryview
|| devinfo
->is_broxton
) {
713 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
714 tmp
= subscript(tmp
, op
[0].type
, 0);
715 inst
= bld
.MOV(tmp
, op
[0]);
716 inst
= bld
.MOV(result
, tmp
);
717 inst
->saturate
= instr
->dest
.saturate
;
724 inst
= bld
.MOV(result
, op
[0]);
725 inst
->saturate
= instr
->dest
.saturate
;
730 bld
.MOV(result
, op
[0]);
734 if (type_sz(op
[0].type
) < 8) {
735 /* AND(val, 0x80000000) gives the sign bit.
737 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
740 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
742 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
743 op
[0].type
= BRW_REGISTER_TYPE_UD
;
744 result
.type
= BRW_REGISTER_TYPE_UD
;
745 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
747 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
748 inst
->predicate
= BRW_PREDICATE_NORMAL
;
749 if (instr
->dest
.saturate
) {
750 inst
= bld
.MOV(result
, result
);
751 inst
->saturate
= true;
754 /* For doubles we do the same but we need to consider:
756 * - 2-src instructions can't operate with 64-bit immediates
757 * - The sign is encoded in the high 32-bit of each DF
758 * - CMP with DF requires special handling in SIMD16
759 * - We need to produce a DF result.
762 /* 2-src instructions can't have 64-bit immediates, so put 0.0 in
763 * a register and compare with that.
765 fs_reg tmp
= vgrf(glsl_type::double_type
);
766 bld
.MOV(tmp
, setup_imm_df(bld
, 0.0));
768 /* A direct DF CMP using the flag register (null dst) won't work in
769 * SIMD16 because the CMP will be split in two by lower_simd_width,
770 * resulting in two CMP instructions with the same dst (NULL),
771 * leading to dead code elimination of the first one. In SIMD8,
772 * however, there is no need to split the CMP and we can save some
775 fs_reg dst_tmp
= vgrf(glsl_type::double_type
);
776 bld
.CMP(dst_tmp
, op
[0], tmp
, BRW_CONDITIONAL_NZ
);
778 /* In SIMD16 we want to avoid using a NULL dst register with DF CMP,
779 * so we store the result of the comparison in a vgrf instead and
780 * then we generate a UD comparison from that that won't have to
781 * be split by lower_simd_width. This is what NIR does to handle
782 * double comparisons in the general case.
784 if (bld
.dispatch_width() == 16 ) {
785 fs_reg dst_tmp_ud
= retype(dst_tmp
, BRW_REGISTER_TYPE_UD
);
786 bld
.MOV(dst_tmp_ud
, subscript(dst_tmp
, BRW_REGISTER_TYPE_UD
, 0));
787 bld
.CMP(bld
.null_reg_ud(),
788 dst_tmp_ud
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
791 /* Get the high 32-bit of each double component where the sign is */
792 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
793 bld
.MOV(result_int
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
795 /* Get the sign bit */
796 bld
.AND(result_int
, result_int
, brw_imm_ud(0x80000000u
));
798 /* Add 1.0 to the sign, predicated to skip the case of op[0] == 0.0 */
799 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
800 inst
->predicate
= BRW_PREDICATE_NORMAL
;
802 /* Convert from 32-bit float to 64-bit double */
803 result
.type
= BRW_REGISTER_TYPE_DF
;
804 inst
= bld
.MOV(result
, retype(result_int
, BRW_REGISTER_TYPE_F
));
806 if (instr
->dest
.saturate
) {
807 inst
= bld
.MOV(result
, result
);
808 inst
->saturate
= true;
815 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
816 * -> non-negative val generates 0x00000000.
817 * Predicated OR sets 1 if val is positive.
819 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
820 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
821 bld
.ASR(result
, op
[0], brw_imm_d(31));
822 inst
= bld
.OR(result
, result
, brw_imm_d(1));
823 inst
->predicate
= BRW_PREDICATE_NORMAL
;
827 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
828 inst
->saturate
= instr
->dest
.saturate
;
832 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
833 inst
->saturate
= instr
->dest
.saturate
;
837 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
838 inst
->saturate
= instr
->dest
.saturate
;
842 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
843 inst
->saturate
= instr
->dest
.saturate
;
847 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
848 inst
->saturate
= instr
->dest
.saturate
;
852 if (fs_key
->high_quality_derivatives
) {
853 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
855 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
857 inst
->saturate
= instr
->dest
.saturate
;
859 case nir_op_fddx_fine
:
860 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
861 inst
->saturate
= instr
->dest
.saturate
;
863 case nir_op_fddx_coarse
:
864 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
865 inst
->saturate
= instr
->dest
.saturate
;
868 if (fs_key
->high_quality_derivatives
) {
869 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
871 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
873 inst
->saturate
= instr
->dest
.saturate
;
875 case nir_op_fddy_fine
:
876 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
877 inst
->saturate
= instr
->dest
.saturate
;
879 case nir_op_fddy_coarse
:
880 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
881 inst
->saturate
= instr
->dest
.saturate
;
885 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
887 inst
= bld
.ADD(result
, op
[0], op
[1]);
888 inst
->saturate
= instr
->dest
.saturate
;
892 inst
= bld
.MUL(result
, op
[0], op
[1]);
893 inst
->saturate
= instr
->dest
.saturate
;
897 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
898 bld
.MUL(result
, op
[0], op
[1]);
901 case nir_op_imul_high
:
902 case nir_op_umul_high
:
903 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
904 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
909 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
910 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
913 case nir_op_uadd_carry
:
914 unreachable("Should have been lowered by carry_to_arith().");
916 case nir_op_usub_borrow
:
917 unreachable("Should have been lowered by borrow_to_arith().");
921 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
922 * appears that our hardware just does the right thing for signed
925 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
926 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
930 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
931 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
933 /* Math instructions don't support conditional mod */
934 inst
= bld
.MOV(bld
.null_reg_d(), result
);
935 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
937 /* Now, we need to determine if signs of the sources are different.
938 * When we XOR the sources, the top bit is 0 if they are the same and 1
939 * if they are different. We can then use a conditional modifier to
940 * turn that into a predicate. This leads us to an XOR.l instruction.
942 * Technically, according to the PRM, you're not allowed to use .l on a
943 * XOR instruction. However, emperical experiments and Curro's reading
944 * of the simulator source both indicate that it's safe.
946 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
947 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
948 inst
->predicate
= BRW_PREDICATE_NORMAL
;
949 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
951 /* If the result of the initial remainder operation is non-zero and the
952 * two sources have different signs, add in a copy of op[1] to get the
953 * final integer modulus value.
955 inst
= bld
.ADD(result
, result
, op
[1]);
956 inst
->predicate
= BRW_PREDICATE_NORMAL
;
964 fs_reg dest
= result
;
965 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
966 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
968 brw_conditional_mod cond
;
971 cond
= BRW_CONDITIONAL_L
;
974 cond
= BRW_CONDITIONAL_GE
;
977 cond
= BRW_CONDITIONAL_Z
;
980 cond
= BRW_CONDITIONAL_NZ
;
983 unreachable("bad opcode");
985 bld
.CMP(dest
, op
[0], op
[1], cond
);
986 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
987 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
994 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
995 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1000 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1001 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1005 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1006 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
1010 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1011 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
1015 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1016 if (devinfo
->gen
>= 8) {
1017 op
[0] = resolve_source_modifiers(op
[0]);
1019 bld
.NOT(result
, op
[0]);
1022 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1023 if (devinfo
->gen
>= 8) {
1024 op
[0] = resolve_source_modifiers(op
[0]);
1025 op
[1] = resolve_source_modifiers(op
[1]);
1027 bld
.XOR(result
, op
[0], op
[1]);
1030 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1031 if (devinfo
->gen
>= 8) {
1032 op
[0] = resolve_source_modifiers(op
[0]);
1033 op
[1] = resolve_source_modifiers(op
[1]);
1035 bld
.OR(result
, op
[0], op
[1]);
1038 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1039 if (devinfo
->gen
>= 8) {
1040 op
[0] = resolve_source_modifiers(op
[0]);
1041 op
[1] = resolve_source_modifiers(op
[1]);
1043 bld
.AND(result
, op
[0], op
[1]);
1049 case nir_op_ball_fequal2
:
1050 case nir_op_ball_iequal2
:
1051 case nir_op_ball_fequal3
:
1052 case nir_op_ball_iequal3
:
1053 case nir_op_ball_fequal4
:
1054 case nir_op_ball_iequal4
:
1055 case nir_op_bany_fnequal2
:
1056 case nir_op_bany_inequal2
:
1057 case nir_op_bany_fnequal3
:
1058 case nir_op_bany_inequal3
:
1059 case nir_op_bany_fnequal4
:
1060 case nir_op_bany_inequal4
:
1061 unreachable("Lowered by nir_lower_alu_reductions");
1063 case nir_op_fnoise1_1
:
1064 case nir_op_fnoise1_2
:
1065 case nir_op_fnoise1_3
:
1066 case nir_op_fnoise1_4
:
1067 case nir_op_fnoise2_1
:
1068 case nir_op_fnoise2_2
:
1069 case nir_op_fnoise2_3
:
1070 case nir_op_fnoise2_4
:
1071 case nir_op_fnoise3_1
:
1072 case nir_op_fnoise3_2
:
1073 case nir_op_fnoise3_3
:
1074 case nir_op_fnoise3_4
:
1075 case nir_op_fnoise4_1
:
1076 case nir_op_fnoise4_2
:
1077 case nir_op_fnoise4_3
:
1078 case nir_op_fnoise4_4
:
1079 unreachable("not reached: should be handled by lower_noise");
1082 unreachable("not reached: should be handled by ldexp_to_arith()");
1085 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1086 inst
->saturate
= instr
->dest
.saturate
;
1090 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1091 inst
->saturate
= instr
->dest
.saturate
;
1096 bld
.MOV(result
, negate(op
[0]));
1100 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1103 /* two-argument instructions can't take 64-bit immediates */
1104 fs_reg zero
= vgrf(glsl_type::double_type
);
1105 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1106 /* A SIMD16 execution needs to be split in two instructions, so use
1107 * a vgrf instead of the flag register as dst so instruction splitting
1110 fs_reg tmp
= vgrf(glsl_type::double_type
);
1111 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1112 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1116 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1120 inst
= bld
.RNDZ(result
, op
[0]);
1121 inst
->saturate
= instr
->dest
.saturate
;
1124 case nir_op_fceil
: {
1125 op
[0].negate
= !op
[0].negate
;
1126 fs_reg temp
= vgrf(glsl_type::float_type
);
1127 bld
.RNDD(temp
, op
[0]);
1129 inst
= bld
.MOV(result
, temp
);
1130 inst
->saturate
= instr
->dest
.saturate
;
1134 inst
= bld
.RNDD(result
, op
[0]);
1135 inst
->saturate
= instr
->dest
.saturate
;
1138 inst
= bld
.FRC(result
, op
[0]);
1139 inst
->saturate
= instr
->dest
.saturate
;
1141 case nir_op_fround_even
:
1142 inst
= bld
.RNDE(result
, op
[0]);
1143 inst
->saturate
= instr
->dest
.saturate
;
1146 case nir_op_fquantize2f16
: {
1147 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1148 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1149 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1151 /* The destination stride must be at least as big as the source stride. */
1152 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1155 /* Check for denormal */
1156 fs_reg abs_src0
= op
[0];
1157 abs_src0
.abs
= true;
1158 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1160 /* Get the appropriately signed zero */
1161 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1162 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1163 brw_imm_ud(0x80000000));
1164 /* Do the actual F32 -> F16 -> F32 conversion */
1165 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1166 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1167 /* Select that or zero based on normal status */
1168 inst
= bld
.SEL(result
, zero
, tmp32
);
1169 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1170 inst
->saturate
= instr
->dest
.saturate
;
1176 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1178 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1179 inst
->saturate
= instr
->dest
.saturate
;
1184 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1186 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1187 inst
->saturate
= instr
->dest
.saturate
;
1190 case nir_op_pack_snorm_2x16
:
1191 case nir_op_pack_snorm_4x8
:
1192 case nir_op_pack_unorm_2x16
:
1193 case nir_op_pack_unorm_4x8
:
1194 case nir_op_unpack_snorm_2x16
:
1195 case nir_op_unpack_snorm_4x8
:
1196 case nir_op_unpack_unorm_2x16
:
1197 case nir_op_unpack_unorm_4x8
:
1198 case nir_op_unpack_half_2x16
:
1199 case nir_op_pack_half_2x16
:
1200 unreachable("not reached: should be handled by lower_packing_builtins");
1202 case nir_op_unpack_half_2x16_split_x
:
1203 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1204 inst
->saturate
= instr
->dest
.saturate
;
1206 case nir_op_unpack_half_2x16_split_y
:
1207 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1208 inst
->saturate
= instr
->dest
.saturate
;
1211 case nir_op_pack_double_2x32_split
:
1212 /* Optimize the common case where we are re-packing a double with
1213 * the result of a previous double unpack. In this case we can take the
1214 * 32-bit value to use in the re-pack from the original double and bypass
1215 * the unpack operation.
1217 for (int i
= 0; i
< 2; i
++) {
1218 if (instr
->src
[i
].src
.is_ssa
)
1221 const nir_instr
*parent_instr
= instr
->src
[i
].src
.ssa
->parent_instr
;
1222 if (parent_instr
->type
== nir_instr_type_alu
)
1225 const nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1226 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_x
||
1227 alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1230 if (!alu_parent
->src
[0].src
.is_ssa
)
1233 op
[i
] = get_nir_src(alu_parent
->src
[0].src
);
1234 op
[i
] = offset(retype(op
[i
], BRW_REGISTER_TYPE_DF
), bld
,
1235 alu_parent
->src
[0].swizzle
[channel
]);
1236 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1237 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 1);
1239 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 0);
1241 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1244 case nir_op_unpack_double_2x32_split_x
:
1245 case nir_op_unpack_double_2x32_split_y
: {
1246 /* Optimize the common case where we are unpacking from a double we have
1247 * previously packed. In this case we can just bypass the pack operation
1248 * and source directly from its arguments.
1250 unsigned index
= (instr
->op
== nir_op_unpack_double_2x32_split_x
) ? 0 : 1;
1251 if (instr
->src
[0].src
.is_ssa
) {
1252 nir_instr
*parent_instr
= instr
->src
[0].src
.ssa
->parent_instr
;
1253 if (parent_instr
->type
== nir_instr_type_alu
) {
1254 nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1255 if (alu_parent
->op
== nir_op_pack_double_2x32_split
&&
1256 alu_parent
->src
[index
].src
.is_ssa
) {
1257 op
[0] = retype(get_nir_src(alu_parent
->src
[index
].src
),
1258 BRW_REGISTER_TYPE_UD
);
1260 offset(op
[0], bld
, alu_parent
->src
[index
].swizzle
[channel
]);
1261 bld
.MOV(result
, op
[0]);
1267 if (instr
->op
== nir_op_unpack_double_2x32_split_x
)
1268 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1270 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1275 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1276 inst
->saturate
= instr
->dest
.saturate
;
1279 case nir_op_bitfield_reverse
:
1280 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1281 bld
.BFREV(result
, op
[0]);
1284 case nir_op_bit_count
:
1285 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1286 bld
.CBIT(result
, op
[0]);
1289 case nir_op_ufind_msb
: {
1290 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1291 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1295 case nir_op_ifind_msb
: {
1296 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1298 if (devinfo
->gen
< 7) {
1299 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1301 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1303 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1304 * count from the LSB side. If FBH didn't return an error
1305 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1306 * count into an LSB count.
1308 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1310 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1311 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1312 inst
->src
[0].negate
= true;
1317 case nir_op_find_lsb
:
1318 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1320 if (devinfo
->gen
< 7) {
1321 fs_reg temp
= vgrf(glsl_type::int_type
);
1323 /* (x & -x) generates a value that consists of only the LSB of x.
1324 * For all powers of 2, findMSB(y) == findLSB(y).
1326 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1327 fs_reg negated_src
= src
;
1329 /* One must be negated, and the other must be non-negated. It
1330 * doesn't matter which is which.
1332 negated_src
.negate
= true;
1335 bld
.AND(temp
, src
, negated_src
);
1336 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1338 bld
.FBL(result
, op
[0]);
1342 case nir_op_ubitfield_extract
:
1343 case nir_op_ibitfield_extract
:
1344 unreachable("should have been lowered");
1347 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1348 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1351 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1352 bld
.BFI1(result
, op
[0], op
[1]);
1355 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1356 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1359 case nir_op_bitfield_insert
:
1360 unreachable("not reached: should have been lowered");
1363 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1364 bld
.SHL(result
, op
[0], op
[1]);
1367 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1368 bld
.ASR(result
, op
[0], op
[1]);
1371 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1372 bld
.SHR(result
, op
[0], op
[1]);
1375 case nir_op_pack_half_2x16_split
:
1376 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1380 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1381 inst
->saturate
= instr
->dest
.saturate
;
1385 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1386 inst
->saturate
= instr
->dest
.saturate
;
1390 if (optimize_frontfacing_ternary(instr
, result
))
1393 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1394 inst
= bld
.SEL(result
, op
[1], op
[2]);
1395 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1398 case nir_op_extract_u8
:
1399 case nir_op_extract_i8
: {
1400 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1401 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1402 assert(byte
!= NULL
);
1403 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1407 case nir_op_extract_u16
:
1408 case nir_op_extract_i16
: {
1409 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1410 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1411 assert(word
!= NULL
);
1412 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1417 unreachable("unhandled instruction");
1420 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1421 * to sign extend the low bit to 0/~0
1423 if (devinfo
->gen
<= 5 &&
1424 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1425 fs_reg masked
= vgrf(glsl_type::int_type
);
1426 bld
.AND(masked
, result
, brw_imm_d(1));
1427 masked
.negate
= true;
1428 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1433 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1434 nir_load_const_instr
*instr
)
1436 const brw_reg_type reg_type
=
1437 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1438 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1440 switch (instr
->def
.bit_size
) {
1442 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1443 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1447 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1448 bld
.MOV(offset(reg
, bld
, i
),
1449 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1453 unreachable("Invalid bit size");
1456 nir_ssa_values
[instr
->def
.index
] = reg
;
1460 fs_visitor::get_nir_src(const nir_src
&src
)
1464 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1465 const brw_reg_type reg_type
= src
.ssa
->bit_size
== 32 ?
1466 BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1467 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1469 reg
= nir_ssa_values
[src
.ssa
->index
];
1472 /* We don't handle indirects on locals */
1473 assert(src
.reg
.indirect
== NULL
);
1474 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1475 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1478 /* to avoid floating-point denorm flushing problems, set the type by
1479 * default to D - instructions that need floating point semantics will set
1480 * this to F if they need to
1482 return retype(reg
, BRW_REGISTER_TYPE_D
);
1486 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1489 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1491 nir_const_value
*val
= nir_src_as_const_value(src
);
1492 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1496 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1499 const brw_reg_type reg_type
=
1500 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1501 nir_ssa_values
[dest
.ssa
.index
] =
1502 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1503 return nir_ssa_values
[dest
.ssa
.index
];
1505 /* We don't handle indirects on locals */
1506 assert(dest
.reg
.indirect
== NULL
);
1507 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1508 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1513 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1515 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1516 BRW_REGISTER_TYPE_UD
);
1518 unsigned indirect_max
= 0;
1520 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1521 tail
= tail
->child
) {
1522 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1523 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1524 const unsigned size
= glsl_get_length(tail
->type
);
1525 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1526 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1527 image
= offset(image
, bld
, base
* element_size
);
1529 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1530 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1532 /* Accessing an invalid surface index with the dataport can result
1533 * in a hang. According to the spec "if the index used to
1534 * select an individual element is negative or greater than or
1535 * equal to the size of the array, the results of the operation
1536 * are undefined but may not lead to termination" -- which is one
1537 * of the possible outcomes of the hang. Clamp the index to
1538 * prevent access outside of the array bounds.
1540 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1541 BRW_REGISTER_TYPE_UD
),
1542 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1544 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1546 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1547 if (indirect
.file
== BAD_FILE
) {
1550 bld
.ADD(indirect
, indirect
, tmp
);
1555 if (indirect
.file
== BAD_FILE
) {
1558 /* Emit a pile of MOVs to load the uniform into a temporary. The
1559 * dead-code elimination pass will get rid of what we don't use.
1561 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1562 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1563 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1564 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1565 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1572 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1575 for (unsigned i
= 0; i
< 4; i
++) {
1576 if (!((wr_mask
>> i
) & 1))
1579 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1580 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1581 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1582 if (new_inst
->src
[j
].file
== VGRF
)
1583 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1590 * Get the matching channel register datatype for an image intrinsic of the
1591 * specified GLSL image type.
1594 get_image_base_type(const glsl_type
*type
)
1596 switch ((glsl_base_type
)type
->sampled_type
) {
1597 case GLSL_TYPE_UINT
:
1598 return BRW_REGISTER_TYPE_UD
;
1600 return BRW_REGISTER_TYPE_D
;
1601 case GLSL_TYPE_FLOAT
:
1602 return BRW_REGISTER_TYPE_F
;
1604 unreachable("Not reached.");
1609 * Get the appropriate atomic op for an image atomic intrinsic.
1612 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1615 case nir_intrinsic_image_atomic_add
:
1617 case nir_intrinsic_image_atomic_min
:
1618 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1619 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1620 case nir_intrinsic_image_atomic_max
:
1621 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1622 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1623 case nir_intrinsic_image_atomic_and
:
1625 case nir_intrinsic_image_atomic_or
:
1627 case nir_intrinsic_image_atomic_xor
:
1629 case nir_intrinsic_image_atomic_exchange
:
1631 case nir_intrinsic_image_atomic_comp_swap
:
1632 return BRW_AOP_CMPWR
;
1634 unreachable("Not reachable.");
1639 emit_pixel_interpolater_send(const fs_builder
&bld
,
1644 glsl_interp_mode interpolation
)
1646 struct brw_wm_prog_data
*wm_prog_data
=
1647 (struct brw_wm_prog_data
*) bld
.shader
->stage_prog_data
;
1652 if (src
.file
== BAD_FILE
) {
1654 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1658 mlen
= 2 * bld
.dispatch_width() / 8;
1661 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1663 /* 2 floats per slot returned */
1664 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1665 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1667 wm_prog_data
->pulls_bary
= true;
1673 * Computes 1 << x, given a D/UD register containing some value x.
1676 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1678 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1680 fs_reg result
= bld
.vgrf(x
.type
, 1);
1681 fs_reg one
= bld
.vgrf(x
.type
, 1);
1683 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1684 bld
.SHL(result
, one
, x
);
1689 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1691 assert(stage
== MESA_SHADER_GEOMETRY
);
1693 struct brw_gs_prog_data
*gs_prog_data
=
1694 (struct brw_gs_prog_data
*) prog_data
;
1696 if (gs_compile
->control_data_header_size_bits
== 0)
1699 /* We can only do EndPrimitive() functionality when the control data
1700 * consists of cut bits. Fortunately, the only time it isn't is when the
1701 * output type is points, in which case EndPrimitive() is a no-op.
1703 if (gs_prog_data
->control_data_format
!=
1704 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1708 /* Cut bits use one bit per vertex. */
1709 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1711 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1712 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1714 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1715 * vertex n, 0 otherwise. So all we need to do here is mark bit
1716 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1717 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1718 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1720 * Note that if EndPrimitive() is called before emitting any vertices, this
1721 * will cause us to set bit 31 of the control_data_bits register to 1.
1722 * That's fine because:
1724 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1725 * output, so the hardware will ignore cut bit 31.
1727 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1728 * last vertex, so setting cut bit 31 has no effect (since the primitive
1729 * is automatically ended when the GS terminates).
1731 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1732 * control_data_bits register to 0 when the first vertex is emitted.
1735 const fs_builder abld
= bld
.annotate("end primitive");
1737 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1738 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1739 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1740 fs_reg mask
= intexp2(abld
, prev_count
);
1741 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1742 * attention to the lower 5 bits of its second source argument, so on this
1743 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1744 * ((vertex_count - 1) % 32).
1746 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1750 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1752 assert(stage
== MESA_SHADER_GEOMETRY
);
1753 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1755 struct brw_gs_prog_data
*gs_prog_data
=
1756 (struct brw_gs_prog_data
*) prog_data
;
1758 const fs_builder abld
= bld
.annotate("emit control data bits");
1759 const fs_builder fwa_bld
= bld
.exec_all();
1761 /* We use a single UD register to accumulate control data bits (32 bits
1762 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1765 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1766 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1767 * use the Channel Mask phase to enable/disable which DWord within that
1768 * group to write. (Remember, different SIMD8 channels may have emitted
1769 * different numbers of vertices, so we may need per-slot offsets.)
1771 * Channel masking presents an annoying problem: we may have to replicate
1772 * the data up to 4 times:
1774 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1776 * To avoid penalizing shaders that emit a small number of vertices, we
1777 * can avoid these sometimes: if the size of the control data header is
1778 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1779 * land in the same 128-bit group, so we can skip per-slot offsets.
1781 * Similarly, if the control data header is <= 32 bits, there is only one
1782 * DWord, so we can skip channel masks.
1784 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1786 fs_reg channel_mask
, per_slot_offset
;
1788 if (gs_compile
->control_data_header_size_bits
> 32) {
1789 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1790 channel_mask
= vgrf(glsl_type::uint_type
);
1793 if (gs_compile
->control_data_header_size_bits
> 128) {
1794 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1795 per_slot_offset
= vgrf(glsl_type::uint_type
);
1798 /* Figure out which DWord we're trying to write to using the formula:
1800 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1802 * Since bits_per_vertex is a power of two, and is known at compile
1803 * time, this can be optimized to:
1805 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1807 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1808 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1809 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1810 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1811 unsigned log2_bits_per_vertex
=
1812 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1813 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1815 if (per_slot_offset
.file
!= BAD_FILE
) {
1816 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1817 * the appropriate OWord within the control data header.
1819 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1822 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1823 * write to the appropriate DWORD within the OWORD.
1825 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1826 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1827 channel_mask
= intexp2(fwa_bld
, channel
);
1828 /* Then the channel masks need to be in bits 23:16. */
1829 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1832 /* Store the control data bits in the message payload and send it. */
1834 if (channel_mask
.file
!= BAD_FILE
)
1835 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1836 if (per_slot_offset
.file
!= BAD_FILE
)
1839 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1840 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1842 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1843 if (per_slot_offset
.file
!= BAD_FILE
)
1844 sources
[i
++] = per_slot_offset
;
1845 if (channel_mask
.file
!= BAD_FILE
)
1846 sources
[i
++] = channel_mask
;
1848 sources
[i
++] = this->control_data_bits
;
1851 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1852 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1854 /* We need to increment Global Offset by 256-bits to make room for
1855 * Broadwell's extra "Vertex Count" payload at the beginning of the
1856 * URB entry. Since this is an OWord message, Global Offset is counted
1857 * in 128-bit units, so we must set it to 2.
1859 if (gs_prog_data
->static_vertex_count
== -1)
1864 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1867 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1869 /* Note: we are calling this *before* increasing vertex_count, so
1870 * this->vertex_count == vertex_count - 1 in the formula above.
1873 /* Stream mode uses 2 bits per vertex */
1874 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1876 /* Must be a valid stream */
1877 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1879 /* Control data bits are initialized to 0 so we don't have to set any
1880 * bits when sending vertices to stream 0.
1885 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1887 /* reg::sid = stream_id */
1888 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1889 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1891 /* reg:shift_count = 2 * (vertex_count - 1) */
1892 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1893 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1895 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1896 * attention to the lower 5 bits of its second source argument, so on this
1897 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1898 * stream_id << ((2 * (vertex_count - 1)) % 32).
1900 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1901 abld
.SHL(mask
, sid
, shift_count
);
1902 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1906 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1909 assert(stage
== MESA_SHADER_GEOMETRY
);
1911 struct brw_gs_prog_data
*gs_prog_data
=
1912 (struct brw_gs_prog_data
*) prog_data
;
1914 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1915 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1917 /* Haswell and later hardware ignores the "Render Stream Select" bits
1918 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1919 * and instead sends all primitives down the pipeline for rasterization.
1920 * If the SOL stage is enabled, "Render Stream Select" is honored and
1921 * primitives bound to non-zero streams are discarded after stream output.
1923 * Since the only purpose of primives sent to non-zero streams is to
1924 * be recorded by transform feedback, we can simply discard all geometry
1925 * bound to these streams when transform feedback is disabled.
1927 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1930 /* If we're outputting 32 control data bits or less, then we can wait
1931 * until the shader is over to output them all. Otherwise we need to
1932 * output them as we go. Now is the time to do it, since we're about to
1933 * output the vertex_count'th vertex, so it's guaranteed that the
1934 * control data bits associated with the (vertex_count - 1)th vertex are
1937 if (gs_compile
->control_data_header_size_bits
> 32) {
1938 const fs_builder abld
=
1939 bld
.annotate("emit vertex: emit control data bits");
1941 /* Only emit control data bits if we've finished accumulating a batch
1942 * of 32 bits. This is the case when:
1944 * (vertex_count * bits_per_vertex) % 32 == 0
1946 * (in other words, when the last 5 bits of vertex_count *
1947 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1948 * integer n (which is always the case, since bits_per_vertex is
1949 * always 1 or 2), this is equivalent to requiring that the last 5-n
1950 * bits of vertex_count are 0:
1952 * vertex_count & (2^(5-n) - 1) == 0
1954 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1957 * vertex_count & (32 / bits_per_vertex - 1) == 0
1959 * TODO: If vertex_count is an immediate, we could do some of this math
1960 * at compile time...
1963 abld
.AND(bld
.null_reg_d(), vertex_count
,
1964 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1965 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1967 abld
.IF(BRW_PREDICATE_NORMAL
);
1968 /* If vertex_count is 0, then no control data bits have been
1969 * accumulated yet, so we can skip emitting them.
1971 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1972 BRW_CONDITIONAL_NEQ
);
1973 abld
.IF(BRW_PREDICATE_NORMAL
);
1974 emit_gs_control_data_bits(vertex_count
);
1975 abld
.emit(BRW_OPCODE_ENDIF
);
1977 /* Reset control_data_bits to 0 so we can start accumulating a new
1980 * Note: in the case where vertex_count == 0, this neutralizes the
1981 * effect of any call to EndPrimitive() that the shader may have
1982 * made before outputting its first vertex.
1984 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1985 inst
->force_writemask_all
= true;
1986 abld
.emit(BRW_OPCODE_ENDIF
);
1989 emit_urb_writes(vertex_count
);
1991 /* In stream mode we have to set control data bits for all vertices
1992 * unless we have disabled control data bits completely (which we do
1993 * do for GL_POINTS outputs that don't use streams).
1995 if (gs_compile
->control_data_header_size_bits
> 0 &&
1996 gs_prog_data
->control_data_format
==
1997 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1998 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2003 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2004 const nir_src
&vertex_src
,
2005 unsigned base_offset
,
2006 const nir_src
&offset_src
,
2007 unsigned num_components
,
2008 unsigned first_component
)
2010 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
2012 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2013 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2014 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2016 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
2017 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
2018 * gl_PointSize is available as a GS input, however, so it must be that.
2020 const bool is_point_size
= (base_offset
== 0);
2022 /* TODO: figure out push input layout for invocations == 1 */
2023 if (gs_prog_data
->invocations
== 1 &&
2024 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2025 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2026 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2027 vertex_const
->u32
[0] * push_reg_count
;
2028 /* This input was pushed into registers. */
2029 if (is_point_size
) {
2030 /* gl_PointSize comes in .w */
2031 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
2033 for (unsigned i
= 0; i
< num_components
; i
++) {
2034 bld
.MOV(offset(dst
, bld
, i
),
2035 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
2041 /* Resort to the pull model. Ensure the VUE handles are provided. */
2042 gs_prog_data
->base
.include_vue_handles
= true;
2044 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2045 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2047 if (gs_prog_data
->invocations
== 1) {
2049 /* The vertex index is constant; just select the proper URB handle. */
2051 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2052 BRW_REGISTER_TYPE_UD
);
2054 /* The vertex index is non-constant. We need to use indirect
2055 * addressing to fetch the proper URB handle.
2057 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2058 * indicating that channel <n> should read the handle from
2059 * DWord <n>. We convert that to bytes by multiplying by 4.
2061 * Next, we convert the vertex index to bytes by multiplying
2062 * by 32 (shifting by 5), and add the two together. This is
2063 * the final indirect byte offset.
2065 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
2066 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2067 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2068 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2070 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2071 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2072 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2073 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2074 /* Convert vertex_index to bytes (multiply by 32) */
2075 bld
.SHL(vertex_offset_bytes
,
2076 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2078 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2080 /* Use first_icp_handle as the base offset. There is one register
2081 * of URB handles per vertex, so inform the register allocator that
2082 * we might read up to nir->info.gs.vertices_in registers.
2084 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2085 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2086 fs_reg(icp_offset_bytes
),
2087 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2090 assert(gs_prog_data
->invocations
> 1);
2093 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2095 retype(brw_vec1_grf(first_icp_handle
+
2096 vertex_const
->i32
[0] / 8,
2097 vertex_const
->i32
[0] % 8),
2098 BRW_REGISTER_TYPE_UD
));
2100 /* The vertex index is non-constant. We need to use indirect
2101 * addressing to fetch the proper URB handle.
2104 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2106 /* Convert vertex_index to bytes (multiply by 4) */
2107 bld
.SHL(icp_offset_bytes
,
2108 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2111 /* Use first_icp_handle as the base offset. There is one DWord
2112 * of URB handles per vertex, so inform the register allocator that
2113 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2115 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2116 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2117 fs_reg(icp_offset_bytes
),
2118 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2125 fs_reg tmp_dst
= dst
;
2126 fs_reg indirect_offset
= get_nir_src(offset_src
);
2127 unsigned num_iterations
= 1;
2128 unsigned orig_num_components
= num_components
;
2130 if (type_sz(dst
.type
) == 8) {
2131 if (num_components
> 2) {
2135 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2137 first_component
= first_component
/ 2;
2140 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2142 /* Constant indexing - use global offset. */
2143 if (first_component
!= 0) {
2144 unsigned read_components
= num_components
+ first_component
;
2145 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2146 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2147 inst
->regs_written
= read_components
* type_sz(tmp_dst
.type
) / 4;
2148 for (unsigned i
= 0; i
< num_components
; i
++) {
2149 bld
.MOV(offset(tmp_dst
, bld
, i
),
2150 offset(tmp
, bld
, i
+ first_component
));
2153 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2155 inst
->regs_written
= num_components
* type_sz(tmp_dst
.type
) / 4;
2157 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2160 /* Indirect indexing - use per-slot offsets as well. */
2161 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2162 unsigned read_components
= num_components
+ first_component
;
2163 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2164 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2165 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2166 if (first_component
!= 0) {
2167 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2169 inst
->regs_written
= read_components
* type_sz(tmp_dst
.type
) / 4;
2170 for (unsigned i
= 0; i
< num_components
; i
++) {
2171 bld
.MOV(offset(tmp_dst
, bld
, i
),
2172 offset(tmp
, bld
, i
+ first_component
));
2175 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2177 inst
->regs_written
= num_components
* type_sz(tmp_dst
.type
) / 4;
2179 inst
->offset
= base_offset
;
2183 if (type_sz(dst
.type
) == 8) {
2184 shuffle_32bit_load_result_to_64bit_data(
2185 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2187 for (unsigned c
= 0; c
< num_components
; c
++)
2188 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2191 if (num_iterations
> 1) {
2192 num_components
= orig_num_components
- 2;
2196 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2197 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2198 indirect_offset
= new_indirect
;
2203 if (is_point_size
) {
2204 /* Read the whole VUE header (because of alignment) and read .w. */
2205 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
2207 inst
->regs_written
= 4;
2208 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2213 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2215 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2216 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2219 /* The only constant offset we should find is 0. brw_nir.c's
2220 * add_const_offset_to_base() will fold other constant offsets
2221 * into instr->const_index[0].
2223 assert(const_value
->u32
[0] == 0);
2227 return get_nir_src(*offset_src
);
2231 do_untyped_vector_read(const fs_builder
&bld
,
2233 const fs_reg surf_index
,
2234 const fs_reg offset_reg
,
2235 unsigned num_components
)
2237 if (type_sz(dest
.type
) == 4) {
2238 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2241 BRW_PREDICATE_NONE
);
2242 read_result
.type
= dest
.type
;
2243 for (unsigned i
= 0; i
< num_components
; i
++)
2244 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2245 } else if (type_sz(dest
.type
) == 8) {
2246 /* Reading a dvec, so we need to:
2248 * 1. Multiply num_components by 2, to account for the fact that we
2249 * need to read 64-bit components.
2250 * 2. Shuffle the result of the load to form valid 64-bit elements
2251 * 3. Emit a second load (for components z/w) if needed.
2253 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2254 bld
.MOV(read_offset
, offset_reg
);
2256 int iters
= num_components
<= 2 ? 1 : 2;
2258 /* Load the dvec, the first iteration loads components x/y, the second
2259 * iteration, if needed, loads components z/w
2261 for (int it
= 0; it
< iters
; it
++) {
2262 /* Compute number of components to read in this iteration */
2263 int iter_components
= MIN2(2, num_components
);
2264 num_components
-= iter_components
;
2266 /* Read. Since this message reads 32-bit components, we need to
2267 * read twice as many components.
2269 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2271 iter_components
* 2,
2272 BRW_PREDICATE_NONE
);
2274 /* Shuffle the 32-bit load result into valid 64-bit data */
2275 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2276 shuffle_32bit_load_result_to_64bit_data(
2277 bld
, packed_result
, read_result
, iter_components
);
2279 /* Move each component to its destination */
2280 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2281 for (int c
= 0; c
< iter_components
; c
++) {
2282 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2283 offset(packed_result
, bld
, c
));
2286 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2289 unreachable("Unsupported type");
2294 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2295 nir_intrinsic_instr
*instr
)
2297 assert(stage
== MESA_SHADER_VERTEX
);
2300 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2301 dest
= get_nir_dest(instr
->dest
);
2303 switch (instr
->intrinsic
) {
2304 case nir_intrinsic_load_vertex_id
:
2305 unreachable("should be lowered by lower_vertex_id()");
2307 case nir_intrinsic_load_vertex_id_zero_base
:
2308 case nir_intrinsic_load_base_vertex
:
2309 case nir_intrinsic_load_instance_id
:
2310 case nir_intrinsic_load_base_instance
:
2311 case nir_intrinsic_load_draw_id
: {
2312 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2313 fs_reg val
= nir_system_values
[sv
];
2314 assert(val
.file
!= BAD_FILE
);
2315 dest
.type
= val
.type
;
2320 case nir_intrinsic_load_input
: {
2321 fs_reg src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2322 unsigned first_component
= nir_intrinsic_component(instr
);
2323 unsigned num_components
= instr
->num_components
;
2324 enum brw_reg_type type
= dest
.type
;
2326 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2327 assert(const_offset
&& "Indirect input loads not allowed");
2328 src
= offset(src
, bld
, const_offset
->u32
[0]);
2330 for (unsigned j
= 0; j
< num_components
; j
++) {
2331 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2334 if (type
== BRW_REGISTER_TYPE_DF
) {
2335 /* Once the double vector is read, set again its original register
2336 * type to continue with normal execution.
2338 src
= retype(src
, type
);
2339 dest
= retype(dest
, type
);
2342 if (type_sz(src
.type
) == 8) {
2343 shuffle_32bit_load_result_to_64bit_data(bld
,
2345 retype(dest
, BRW_REGISTER_TYPE_F
),
2346 instr
->num_components
);
2352 nir_emit_intrinsic(bld
, instr
);
2358 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2359 nir_intrinsic_instr
*instr
)
2361 assert(stage
== MESA_SHADER_TESS_CTRL
);
2362 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2363 struct brw_tcs_prog_data
*tcs_prog_data
=
2364 (struct brw_tcs_prog_data
*) prog_data
;
2367 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2368 dst
= get_nir_dest(instr
->dest
);
2370 switch (instr
->intrinsic
) {
2371 case nir_intrinsic_load_primitive_id
:
2372 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2374 case nir_intrinsic_load_invocation_id
:
2375 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2377 case nir_intrinsic_load_patch_vertices_in
:
2378 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2379 brw_imm_d(tcs_key
->input_vertices
));
2382 case nir_intrinsic_barrier
: {
2383 if (tcs_prog_data
->instances
== 1)
2386 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2387 fs_reg m0_2
= component(m0
, 2);
2389 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2391 /* Zero the message header */
2392 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2394 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2395 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2396 brw_imm_ud(INTEL_MASK(16, 13)));
2398 /* Shift it up to bits 27:24. */
2399 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2401 /* Set the Barrier Count and the enable bit */
2402 chanbld
.OR(m0_2
, m0_2
,
2403 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2405 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2409 case nir_intrinsic_load_input
:
2410 unreachable("nir_lower_io should never give us these.");
2413 case nir_intrinsic_load_per_vertex_input
: {
2414 fs_reg indirect_offset
= get_indirect_offset(instr
);
2415 unsigned imm_offset
= instr
->const_index
[0];
2417 const nir_src
&vertex_src
= instr
->src
[0];
2418 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2425 /* Emit a MOV to resolve <0,1,0> regioning. */
2426 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2428 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2429 vertex_const
->i32
[0] & 7),
2430 BRW_REGISTER_TYPE_UD
));
2431 } else if (tcs_prog_data
->instances
== 1 &&
2432 vertex_src
.is_ssa
&&
2433 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2434 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2435 /* For the common case of only 1 instance, an array index of
2436 * gl_InvocationID means reading g1. Skip all the indirect work.
2438 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2440 /* The vertex index is non-constant. We need to use indirect
2441 * addressing to fetch the proper URB handle.
2443 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2445 /* Each ICP handle is a single DWord (4 bytes) */
2446 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2447 bld
.SHL(vertex_offset_bytes
,
2448 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2451 /* Start at g1. We might read up to 4 registers. */
2452 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2453 fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes
,
2454 brw_imm_ud(4 * REG_SIZE
));
2457 /* We can only read two double components with each URB read, so
2458 * we send two read messages in that case, each one loading up to
2459 * two double components.
2461 unsigned num_iterations
= 1;
2462 unsigned num_components
= instr
->num_components
;
2463 unsigned first_component
= nir_intrinsic_component(instr
);
2464 fs_reg orig_dst
= dst
;
2465 if (type_sz(dst
.type
) == 8) {
2466 first_component
= first_component
/ 2;
2467 if (instr
->num_components
> 2) {
2472 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2476 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2477 if (indirect_offset
.file
== BAD_FILE
) {
2478 /* Constant indexing - use global offset. */
2479 if (first_component
!= 0) {
2480 unsigned read_components
= num_components
+ first_component
;
2481 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2482 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2483 for (unsigned i
= 0; i
< num_components
; i
++) {
2484 bld
.MOV(offset(dst
, bld
, i
),
2485 offset(tmp
, bld
, i
+ first_component
));
2488 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2490 inst
->offset
= imm_offset
;
2493 /* Indirect indexing - use per-slot offsets as well. */
2494 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2495 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2496 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2497 if (first_component
!= 0) {
2498 unsigned read_components
= num_components
+ first_component
;
2499 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2500 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2502 for (unsigned i
= 0; i
< num_components
; i
++) {
2503 bld
.MOV(offset(dst
, bld
, i
),
2504 offset(tmp
, bld
, i
+ first_component
));
2507 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2510 inst
->offset
= imm_offset
;
2513 inst
->regs_written
=
2514 ((num_components
+ first_component
) * type_sz(dst
.type
) / 4);
2516 /* If we are reading 64-bit data using 32-bit read messages we need
2517 * build proper 64-bit data elements by shuffling the low and high
2518 * 32-bit components around like we do for other things like UBOs
2521 if (type_sz(dst
.type
) == 8) {
2522 shuffle_32bit_load_result_to_64bit_data(
2523 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2525 for (unsigned c
= 0; c
< num_components
; c
++) {
2526 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2527 offset(dst
, bld
, c
));
2531 /* Copy the temporary to the destination to deal with writemasking.
2533 * Also attempt to deal with gl_PointSize being in the .w component.
2535 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2536 assert(type_sz(dst
.type
) < 8);
2537 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2538 inst
->regs_written
= 4;
2539 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2542 /* If we are loading double data and we need a second read message
2543 * adjust the write offset
2545 if (num_iterations
> 1) {
2546 num_components
= instr
->num_components
- 2;
2553 case nir_intrinsic_load_output
:
2554 case nir_intrinsic_load_per_vertex_output
: {
2555 fs_reg indirect_offset
= get_indirect_offset(instr
);
2556 unsigned imm_offset
= instr
->const_index
[0];
2557 unsigned first_component
= nir_intrinsic_component(instr
);
2560 if (indirect_offset
.file
== BAD_FILE
) {
2561 /* Replicate the patch handle to all enabled channels */
2562 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2563 bld
.MOV(patch_handle
,
2564 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2566 if (imm_offset
== 0) {
2567 /* This is a read of gl_TessLevelInner[], which lives in the
2568 * Patch URB header. The layout depends on the domain.
2570 dst
.type
= BRW_REGISTER_TYPE_F
;
2571 switch (tcs_key
->tes_primitive_mode
) {
2573 /* DWords 3-2 (reversed) */
2574 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2576 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2579 inst
->regs_written
= 4;
2581 /* dst.xy = tmp.wz */
2582 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2583 bld
.MOV(offset(dst
, bld
, 1), offset(tmp
, bld
, 2));
2587 /* DWord 4; hardcode offset = 1 and regs_written = 1 */
2588 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2591 inst
->regs_written
= 1;
2594 /* All channels are undefined. */
2597 unreachable("Bogus tessellation domain");
2599 } else if (imm_offset
== 1) {
2600 /* This is a read of gl_TessLevelOuter[], which lives in the
2601 * Patch URB header. The layout depends on the domain.
2603 dst
.type
= BRW_REGISTER_TYPE_F
;
2605 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2606 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2609 inst
->regs_written
= 4;
2611 /* Reswizzle: WZYX */
2613 offset(tmp
, bld
, 3),
2614 offset(tmp
, bld
, 2),
2615 offset(tmp
, bld
, 1),
2616 offset(tmp
, bld
, 0),
2619 unsigned num_components
;
2620 switch (tcs_key
->tes_primitive_mode
) {
2628 /* Isolines are not reversed; swizzle .zw -> .xy */
2629 srcs
[0] = offset(tmp
, bld
, 2);
2630 srcs
[1] = offset(tmp
, bld
, 3);
2634 unreachable("Bogus tessellation domain");
2636 bld
.LOAD_PAYLOAD(dst
, srcs
, num_components
, 0);
2638 if (first_component
!= 0) {
2639 unsigned read_components
=
2640 instr
->num_components
+ first_component
;
2641 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2642 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2644 inst
->regs_written
= read_components
;
2645 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2646 bld
.MOV(offset(dst
, bld
, i
),
2647 offset(tmp
, bld
, i
+ first_component
));
2650 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2652 inst
->regs_written
= instr
->num_components
;
2654 inst
->offset
= imm_offset
;
2658 /* Indirect indexing - use per-slot offsets as well. */
2659 const fs_reg srcs
[] = {
2660 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2663 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2664 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2665 if (first_component
!= 0) {
2666 unsigned read_components
=
2667 instr
->num_components
+ first_component
;
2668 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2669 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2671 inst
->regs_written
= read_components
;
2672 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2673 bld
.MOV(offset(dst
, bld
, i
),
2674 offset(tmp
, bld
, i
+ first_component
));
2677 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2679 inst
->regs_written
= instr
->num_components
;
2681 inst
->offset
= imm_offset
;
2687 case nir_intrinsic_store_output
:
2688 case nir_intrinsic_store_per_vertex_output
: {
2689 fs_reg value
= get_nir_src(instr
->src
[0]);
2690 bool is_64bit
= (instr
->src
[0].is_ssa
?
2691 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2692 fs_reg indirect_offset
= get_indirect_offset(instr
);
2693 unsigned imm_offset
= instr
->const_index
[0];
2694 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2695 unsigned mask
= instr
->const_index
[1];
2696 unsigned header_regs
= 0;
2698 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2700 if (indirect_offset
.file
!= BAD_FILE
) {
2701 srcs
[header_regs
++] = indirect_offset
;
2702 } else if (!is_passthrough_shader
) {
2703 if (imm_offset
== 0) {
2704 value
.type
= BRW_REGISTER_TYPE_F
;
2706 mask
&= (1 << tesslevel_inner_components(tcs_key
->tes_primitive_mode
)) - 1;
2708 /* This is a write to gl_TessLevelInner[], which lives in the
2709 * Patch URB header. The layout depends on the domain.
2711 switch (tcs_key
->tes_primitive_mode
) {
2713 /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
2714 * We use an XXYX swizzle to reverse put .xy in the .wz
2715 * channels, and use a .zw writemask.
2717 mask
= writemask_for_backwards_vector(mask
);
2718 swiz
= BRW_SWIZZLE4(0, 0, 1, 0);
2721 /* gl_TessLevelInner[].x lives at DWord 4, so we set the
2722 * writemask to X and bump the URB offset by 1.
2727 /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
2730 unreachable("Bogus tessellation domain");
2732 } else if (imm_offset
== 1) {
2733 /* This is a write to gl_TessLevelOuter[] which lives in the
2734 * Patch URB Header at DWords 4-7. However, it's reversed, so
2735 * instead of .xyzw we have .wzyx.
2737 value
.type
= BRW_REGISTER_TYPE_F
;
2739 mask
&= (1 << tesslevel_outer_components(tcs_key
->tes_primitive_mode
)) - 1;
2741 if (tcs_key
->tes_primitive_mode
== GL_ISOLINES
) {
2742 /* Isolines .xy should be stored in .zw, in order. */
2743 swiz
= BRW_SWIZZLE4(0, 0, 0, 1);
2746 /* Other domains are reversed; store .wzyx instead of .xyzw */
2747 swiz
= BRW_SWIZZLE_WZYX
;
2748 mask
= writemask_for_backwards_vector(mask
);
2756 unsigned num_components
= util_last_bit(mask
);
2759 /* We can only pack two 64-bit components in a single message, so send
2760 * 2 messages if we have more components
2762 unsigned num_iterations
= 1;
2763 unsigned iter_components
= num_components
;
2764 unsigned first_component
= nir_intrinsic_component(instr
);
2766 first_component
= first_component
/ 2;
2767 if (instr
->num_components
> 2) {
2769 iter_components
= 2;
2773 /* 64-bit data needs to me shuffled before we can write it to the URB.
2774 * We will use this temporary to shuffle the components in each
2778 fs_reg(VGRF
, alloc
.allocate(2 * iter_components
), value
.type
);
2780 mask
= mask
<< first_component
;
2782 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2783 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2784 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2785 opcode
= indirect_offset
.file
!= BAD_FILE
?
2786 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2787 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2788 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2789 /* Expand the 64-bit mask to 32-bit channels. We only handle
2790 * two channels in each iteration, so we only care about X/Y.
2792 unsigned mask32
= 0;
2793 if (mask
& WRITEMASK_X
)
2794 mask32
|= WRITEMASK_XY
;
2795 if (mask
& WRITEMASK_Y
)
2796 mask32
|= WRITEMASK_ZW
;
2798 /* If the mask does not include any of the channels X or Y there
2799 * is nothing to do in this iteration. Move on to the next couple
2800 * of 64-bit channels.
2808 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2809 opcode
= indirect_offset
.file
!= BAD_FILE
?
2810 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2811 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2813 opcode
= indirect_offset
.file
!= BAD_FILE
?
2814 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2815 SHADER_OPCODE_URB_WRITE_SIMD8
;
2818 for (unsigned i
= 0; i
< iter_components
; i
++) {
2819 if (!(mask
& (1 << (i
+ first_component
))))
2823 srcs
[header_regs
+ i
+ first_component
] =
2824 offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2826 /* We need to shuffle the 64-bit data to match the layout
2827 * expected by our 32-bit URB write messages. We use a temporary
2830 unsigned channel
= BRW_GET_SWZ(swiz
, iter
* 2 + i
);
2831 shuffle_64bit_data_for_32bit_write(bld
,
2832 retype(offset(tmp
, bld
, 2 * i
), BRW_REGISTER_TYPE_F
),
2833 retype(offset(value
, bld
, 2 * channel
), BRW_REGISTER_TYPE_DF
),
2836 /* Now copy the data to the destination */
2837 fs_reg dest
= fs_reg(VGRF
, alloc
.allocate(2), value
.type
);
2838 unsigned idx
= 2 * i
;
2839 bld
.MOV(dest
, offset(tmp
, bld
, idx
));
2840 bld
.MOV(offset(dest
, bld
, 1), offset(tmp
, bld
, idx
+ 1));
2841 srcs
[header_regs
+ idx
+ first_component
* 2] = dest
;
2842 srcs
[header_regs
+ idx
+ 1 + first_component
* 2] =
2843 offset(dest
, bld
, 1);
2848 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2849 (is_64bit
? 2 * first_component
: first_component
);
2851 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2852 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2854 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2855 inst
->offset
= imm_offset
;
2858 /* If this is a 64-bit attribute, select the next two 64-bit channels
2859 * to be handled in the next iteration.
2870 nir_emit_intrinsic(bld
, instr
);
2876 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2877 nir_intrinsic_instr
*instr
)
2879 assert(stage
== MESA_SHADER_TESS_EVAL
);
2880 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
2883 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2884 dest
= get_nir_dest(instr
->dest
);
2886 switch (instr
->intrinsic
) {
2887 case nir_intrinsic_load_primitive_id
:
2888 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2890 case nir_intrinsic_load_tess_coord
:
2891 /* gl_TessCoord is part of the payload in g1-3 */
2892 for (unsigned i
= 0; i
< 3; i
++) {
2893 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2897 case nir_intrinsic_load_tess_level_outer
:
2898 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
2899 * appears as a push-model input. So, we can simply use the ATTR file
2900 * rather than issuing URB read messages. The data is stored in the
2901 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
2904 switch (tes_prog_data
->domain
) {
2905 case BRW_TESS_DOMAIN_QUAD
:
2906 for (unsigned i
= 0; i
< 4; i
++)
2907 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2909 case BRW_TESS_DOMAIN_TRI
:
2910 for (unsigned i
= 0; i
< 3; i
++)
2911 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2913 case BRW_TESS_DOMAIN_ISOLINE
:
2914 for (unsigned i
= 0; i
< 2; i
++)
2915 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 6 + i
));
2920 case nir_intrinsic_load_tess_level_inner
:
2921 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
2922 * appears as a push-model input. So, we can simply use the ATTR file
2923 * rather than issuing URB read messages.
2925 switch (tes_prog_data
->domain
) {
2926 case BRW_TESS_DOMAIN_QUAD
:
2927 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
2928 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
2930 case BRW_TESS_DOMAIN_TRI
:
2931 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
2933 case BRW_TESS_DOMAIN_ISOLINE
:
2934 /* ignore - value is undefined */
2939 case nir_intrinsic_load_input
:
2940 case nir_intrinsic_load_per_vertex_input
: {
2941 fs_reg indirect_offset
= get_indirect_offset(instr
);
2942 unsigned imm_offset
= instr
->const_index
[0];
2943 unsigned first_component
= nir_intrinsic_component(instr
);
2945 if (type_sz(dest
.type
) == 8) {
2946 first_component
= first_component
/ 2;
2950 if (indirect_offset
.file
== BAD_FILE
) {
2951 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2952 * which is 16 registers (since each holds 2 vec4 slots).
2954 const unsigned max_push_slots
= 32;
2955 if (imm_offset
< max_push_slots
) {
2956 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2957 for (int i
= 0; i
< instr
->num_components
; i
++) {
2958 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2959 i
+ first_component
;
2960 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2962 tes_prog_data
->base
.urb_read_length
=
2963 MAX2(tes_prog_data
->base
.urb_read_length
,
2964 DIV_ROUND_UP(imm_offset
+ 1, 2));
2966 /* Replicate the patch handle to all enabled channels */
2967 const fs_reg srcs
[] = {
2968 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2970 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2971 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2973 if (first_component
!= 0) {
2974 unsigned read_components
=
2975 instr
->num_components
+ first_component
;
2976 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2977 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2979 inst
->regs_written
= read_components
;
2980 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2981 bld
.MOV(offset(dest
, bld
, i
),
2982 offset(tmp
, bld
, i
+ first_component
));
2985 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2987 inst
->regs_written
= instr
->num_components
;
2990 inst
->offset
= imm_offset
;
2993 /* Indirect indexing - use per-slot offsets as well. */
2995 /* We can only read two double components with each URB read, so
2996 * we send two read messages in that case, each one loading up to
2997 * two double components.
2999 unsigned num_iterations
= 1;
3000 unsigned num_components
= instr
->num_components
;
3001 fs_reg orig_dest
= dest
;
3002 if (type_sz(dest
.type
) == 8) {
3003 if (instr
->num_components
> 2) {
3007 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
3011 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
3012 const fs_reg srcs
[] = {
3013 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3016 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3017 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3019 if (first_component
!= 0) {
3020 unsigned read_components
=
3021 num_components
+ first_component
;
3022 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3023 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3025 for (unsigned i
= 0; i
< num_components
; i
++) {
3026 bld
.MOV(offset(dest
, bld
, i
),
3027 offset(tmp
, bld
, i
+ first_component
));
3030 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3034 inst
->offset
= imm_offset
;
3035 inst
->regs_written
=
3036 ((num_components
+ first_component
) * type_sz(dest
.type
) / 4);
3038 /* If we are reading 64-bit data using 32-bit read messages we need
3039 * build proper 64-bit data elements by shuffling the low and high
3040 * 32-bit components around like we do for other things like UBOs
3043 if (type_sz(dest
.type
) == 8) {
3044 shuffle_32bit_load_result_to_64bit_data(
3045 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
3047 for (unsigned c
= 0; c
< num_components
; c
++) {
3048 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
3049 offset(dest
, bld
, c
));
3053 /* If we are loading double data and we need a second read message
3056 if (num_iterations
> 1) {
3057 num_components
= instr
->num_components
- 2;
3065 nir_emit_intrinsic(bld
, instr
);
3071 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3072 nir_intrinsic_instr
*instr
)
3074 assert(stage
== MESA_SHADER_GEOMETRY
);
3075 fs_reg indirect_offset
;
3078 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3079 dest
= get_nir_dest(instr
->dest
);
3081 switch (instr
->intrinsic
) {
3082 case nir_intrinsic_load_primitive_id
:
3083 assert(stage
== MESA_SHADER_GEOMETRY
);
3084 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
3085 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3086 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3089 case nir_intrinsic_load_input
:
3090 unreachable("load_input intrinsics are invalid for the GS stage");
3092 case nir_intrinsic_load_per_vertex_input
:
3093 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3094 instr
->src
[1], instr
->num_components
,
3095 nir_intrinsic_component(instr
));
3098 case nir_intrinsic_emit_vertex_with_counter
:
3099 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3102 case nir_intrinsic_end_primitive_with_counter
:
3103 emit_gs_end_primitive(instr
->src
[0]);
3106 case nir_intrinsic_set_vertex_count
:
3107 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3110 case nir_intrinsic_load_invocation_id
: {
3111 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3112 assert(val
.file
!= BAD_FILE
);
3113 dest
.type
= val
.type
;
3119 nir_emit_intrinsic(bld
, instr
);
3125 * Fetch the current render target layer index.
3128 fetch_render_target_array_index(const fs_builder
&bld
)
3130 if (bld
.shader
->devinfo
->gen
>= 6) {
3131 /* The render target array index is provided in the thread payload as
3132 * bits 26:16 of r0.0.
3134 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3135 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3139 /* Pre-SNB we only ever render into the first layer of the framebuffer
3140 * since layered rendering is not implemented.
3142 return brw_imm_ud(0);
3147 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3148 * framebuffer at the current fragment coordinates and sample index.
3151 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3154 const struct brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3156 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3157 const brw_wm_prog_key
*wm_key
=
3158 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3159 assert(!wm_key
->coherent_fb_fetch
);
3160 const brw_wm_prog_data
*wm_prog_data
=
3161 reinterpret_cast<const brw_wm_prog_data
*>(stage_prog_data
);
3163 /* Calculate the surface index relative to the start of the texture binding
3164 * table block, since that's what the texturing messages expect.
3166 const unsigned surface
= target
+
3167 wm_prog_data
->binding_table
.render_target_read_start
-
3168 wm_prog_data
->base
.binding_table
.texture_start
;
3170 brw_mark_surface_used(
3171 bld
.shader
->stage_prog_data
,
3172 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
3174 /* Calculate the fragment coordinates. */
3175 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3176 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3177 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3178 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3180 /* Calculate the sample index and MCS payload when multisampling. Luckily
3181 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3182 * shouldn't be necessary to recompile based on whether the framebuffer is
3185 if (wm_key
->multisample_fbo
&&
3186 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3187 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3189 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3190 const fs_reg mcs
= wm_key
->multisample_fbo
?
3191 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3193 /* Use either a normal or a CMS texel fetch message depending on whether
3194 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3195 * message just in case the framebuffer uses 16x multisampling, it should
3196 * be equivalent to the normal CMS fetch for lower multisampling modes.
3198 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3199 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3200 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3202 /* Emit the instruction. */
3203 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3205 brw_imm_ud(surface
), brw_imm_ud(0),
3206 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3207 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3209 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3210 inst
->regs_written
= 4 * inst
->dst
.component_size(inst
->exec_size
) /
3217 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3219 if (n
&& regs
[0].file
!= BAD_FILE
) {
3223 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3225 for (unsigned i
= 0; i
< n
; i
++)
3233 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3235 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3236 const brw_wm_prog_key
*const key
=
3237 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3238 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3239 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3241 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3242 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3244 else if (l
== FRAG_RESULT_COLOR
)
3245 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3246 MAX2(key
->nr_color_regions
, 1));
3248 else if (l
== FRAG_RESULT_DEPTH
)
3249 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3251 else if (l
== FRAG_RESULT_STENCIL
)
3252 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3254 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3255 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3257 else if (l
>= FRAG_RESULT_DATA0
&&
3258 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3259 return alloc_temporary(v
->bld
, 4,
3260 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3263 unreachable("Invalid location");
3267 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3268 nir_intrinsic_instr
*instr
)
3270 assert(stage
== MESA_SHADER_FRAGMENT
);
3273 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3274 dest
= get_nir_dest(instr
->dest
);
3276 switch (instr
->intrinsic
) {
3277 case nir_intrinsic_load_front_face
:
3278 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3279 *emit_frontfacing_interpolation());
3282 case nir_intrinsic_load_sample_pos
: {
3283 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3284 assert(sample_pos
.file
!= BAD_FILE
);
3285 dest
.type
= sample_pos
.type
;
3286 bld
.MOV(dest
, sample_pos
);
3287 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3291 case nir_intrinsic_load_helper_invocation
:
3292 case nir_intrinsic_load_sample_mask_in
:
3293 case nir_intrinsic_load_sample_id
: {
3294 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3295 fs_reg val
= nir_system_values
[sv
];
3296 assert(val
.file
!= BAD_FILE
);
3297 dest
.type
= val
.type
;
3302 case nir_intrinsic_store_output
: {
3303 const fs_reg src
= get_nir_src(instr
->src
[0]);
3304 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3305 assert(const_offset
&& "Indirect output stores not allowed");
3306 const unsigned location
= nir_intrinsic_base(instr
) +
3307 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3308 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3311 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3312 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3313 offset(src
, bld
, j
));
3318 case nir_intrinsic_load_output
: {
3319 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3320 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3321 assert(l
>= FRAG_RESULT_DATA0
);
3322 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3323 assert(const_offset
&& "Indirect output loads not allowed");
3324 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3325 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3327 assert(!reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
);
3328 emit_non_coherent_fb_read(bld
, tmp
, target
);
3330 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3331 bld
.MOV(offset(dest
, bld
, j
),
3332 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3338 case nir_intrinsic_discard
:
3339 case nir_intrinsic_discard_if
: {
3340 /* We track our discarded pixels in f0.1. By predicating on it, we can
3341 * update just the flag bits that aren't yet discarded. If there's no
3342 * condition, we emit a CMP of g0 != g0, so all currently executing
3343 * channels will get turned off.
3346 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3347 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3348 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3350 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3351 BRW_REGISTER_TYPE_UW
));
3352 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3354 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3355 cmp
->flag_subreg
= 1;
3357 if (devinfo
->gen
>= 6) {
3358 emit_discard_jump();
3363 case nir_intrinsic_load_input
: {
3364 /* load_input is only used for flat inputs */
3365 unsigned base
= nir_intrinsic_base(instr
);
3366 unsigned component
= nir_intrinsic_component(instr
);
3367 unsigned num_components
= instr
->num_components
;
3368 enum brw_reg_type type
= dest
.type
;
3370 /* Special case fields in the VUE header */
3371 if (base
== VARYING_SLOT_LAYER
)
3373 else if (base
== VARYING_SLOT_VIEWPORT
)
3376 if (nir_dest_bit_size(instr
->dest
) == 64) {
3377 /* const_index is in 32-bit type size units that could not be aligned
3378 * with DF. We need to read the double vector as if it was a float
3379 * vector of twice the number of components to fetch the right data.
3381 type
= BRW_REGISTER_TYPE_F
;
3382 num_components
*= 2;
3385 for (unsigned int i
= 0; i
< num_components
; i
++) {
3386 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3387 interp
= suboffset(interp
, 3);
3388 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3389 retype(fs_reg(interp
), type
));
3392 if (nir_dest_bit_size(instr
->dest
) == 64) {
3393 shuffle_32bit_load_result_to_64bit_data(bld
,
3396 instr
->num_components
);
3401 case nir_intrinsic_load_barycentric_pixel
:
3402 case nir_intrinsic_load_barycentric_centroid
:
3403 case nir_intrinsic_load_barycentric_sample
:
3404 /* Do nothing - load_interpolated_input handling will handle it later. */
3407 case nir_intrinsic_load_barycentric_at_sample
: {
3408 const glsl_interp_mode interpolation
=
3409 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3411 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3414 unsigned msg_data
= const_sample
->i32
[0] << 4;
3416 emit_pixel_interpolater_send(bld
,
3417 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3420 brw_imm_ud(msg_data
),
3423 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3424 BRW_REGISTER_TYPE_UD
);
3426 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3427 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3428 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3429 bld
.exec_all().group(1, 0)
3430 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3431 emit_pixel_interpolater_send(bld
,
3432 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3438 /* Make a loop that sends a message to the pixel interpolater
3439 * for the sample number in each live channel. If there are
3440 * multiple channels with the same sample number then these
3441 * will be handled simultaneously with a single interation of
3444 bld
.emit(BRW_OPCODE_DO
);
3446 /* Get the next live sample number into sample_id_reg */
3447 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3449 /* Set the flag register so that we can perform the send
3450 * message on all channels that have the same sample number
3452 bld
.CMP(bld
.null_reg_ud(),
3453 sample_src
, sample_id
,
3454 BRW_CONDITIONAL_EQ
);
3455 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3456 bld
.exec_all().group(1, 0)
3457 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3459 emit_pixel_interpolater_send(bld
,
3460 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3465 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3467 /* Continue the loop if there are any live channels left */
3468 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3470 bld
.emit(BRW_OPCODE_WHILE
));
3476 case nir_intrinsic_load_barycentric_at_offset
: {
3477 const glsl_interp_mode interpolation
=
3478 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3480 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3483 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3484 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3486 emit_pixel_interpolater_send(bld
,
3487 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3490 brw_imm_ud(off_x
| (off_y
<< 4)),
3493 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3494 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3495 BRW_REGISTER_TYPE_F
);
3496 for (int i
= 0; i
< 2; i
++) {
3497 fs_reg temp
= vgrf(glsl_type::float_type
);
3498 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3499 fs_reg itemp
= vgrf(glsl_type::int_type
);
3501 bld
.MOV(itemp
, temp
);
3503 /* Clamp the upper end of the range to +7/16.
3504 * ARB_gpu_shader5 requires that we support a maximum offset
3505 * of +0.5, which isn't representable in a S0.4 value -- if
3506 * we didn't clamp it, we'd end up with -8/16, which is the
3507 * opposite of what the shader author wanted.
3509 * This is legal due to ARB_gpu_shader5's quantization
3512 * "Not all values of <offset> may be supported; x and y
3513 * offsets may be rounded to fixed-point values with the
3514 * number of fraction bits given by the
3515 * implementation-dependent constant
3516 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3518 set_condmod(BRW_CONDITIONAL_L
,
3519 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3522 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3523 emit_pixel_interpolater_send(bld
,
3533 case nir_intrinsic_load_interpolated_input
: {
3534 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3535 emit_fragcoord_interpolation(dest
);
3539 assert(instr
->src
[0].ssa
&&
3540 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3541 nir_intrinsic_instr
*bary_intrinsic
=
3542 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3543 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3544 enum glsl_interp_mode interp_mode
=
3545 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3548 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3549 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3550 /* Use the result of the PI message */
3551 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3553 /* Use the delta_xy values computed from the payload */
3554 enum brw_barycentric_mode bary
=
3555 brw_barycentric_mode(interp_mode
, bary_intrin
);
3557 dst_xy
= this->delta_xy
[bary
];
3560 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3562 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3563 nir_intrinsic_component(instr
) + i
));
3564 interp
.type
= BRW_REGISTER_TYPE_F
;
3565 dest
.type
= BRW_REGISTER_TYPE_F
;
3567 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3568 fs_reg tmp
= vgrf(glsl_type::float_type
);
3569 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3570 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3572 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3579 nir_emit_intrinsic(bld
, instr
);
3585 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3586 nir_intrinsic_instr
*instr
)
3588 assert(stage
== MESA_SHADER_COMPUTE
);
3589 struct brw_cs_prog_data
*cs_prog_data
=
3590 (struct brw_cs_prog_data
*) prog_data
;
3593 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3594 dest
= get_nir_dest(instr
->dest
);
3596 switch (instr
->intrinsic
) {
3597 case nir_intrinsic_barrier
:
3599 cs_prog_data
->uses_barrier
= true;
3602 case nir_intrinsic_load_local_invocation_id
:
3603 case nir_intrinsic_load_work_group_id
: {
3604 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3605 fs_reg val
= nir_system_values
[sv
];
3606 assert(val
.file
!= BAD_FILE
);
3607 dest
.type
= val
.type
;
3608 for (unsigned i
= 0; i
< 3; i
++)
3609 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3613 case nir_intrinsic_load_num_work_groups
: {
3614 const unsigned surface
=
3615 cs_prog_data
->binding_table
.work_groups_start
;
3617 cs_prog_data
->uses_num_work_groups
= true;
3619 fs_reg surf_index
= brw_imm_ud(surface
);
3620 brw_mark_surface_used(prog_data
, surface
);
3622 /* Read the 3 GLuint components of gl_NumWorkGroups */
3623 for (unsigned i
= 0; i
< 3; i
++) {
3624 fs_reg read_result
=
3625 emit_untyped_read(bld
, surf_index
,
3627 1 /* dims */, 1 /* size */,
3628 BRW_PREDICATE_NONE
);
3629 read_result
.type
= dest
.type
;
3630 bld
.MOV(dest
, read_result
);
3631 dest
= offset(dest
, bld
, 1);
3636 case nir_intrinsic_shared_atomic_add
:
3637 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3639 case nir_intrinsic_shared_atomic_imin
:
3640 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3642 case nir_intrinsic_shared_atomic_umin
:
3643 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3645 case nir_intrinsic_shared_atomic_imax
:
3646 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3648 case nir_intrinsic_shared_atomic_umax
:
3649 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3651 case nir_intrinsic_shared_atomic_and
:
3652 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3654 case nir_intrinsic_shared_atomic_or
:
3655 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3657 case nir_intrinsic_shared_atomic_xor
:
3658 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3660 case nir_intrinsic_shared_atomic_exchange
:
3661 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3663 case nir_intrinsic_shared_atomic_comp_swap
:
3664 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3667 case nir_intrinsic_load_shared
: {
3668 assert(devinfo
->gen
>= 7);
3670 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3672 /* Get the offset to read from */
3674 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3676 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3678 offset_reg
= vgrf(glsl_type::uint_type
);
3680 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3681 brw_imm_ud(instr
->const_index
[0]));
3684 /* Read the vector */
3685 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3686 instr
->num_components
);
3690 case nir_intrinsic_store_shared
: {
3691 assert(devinfo
->gen
>= 7);
3694 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3697 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3700 unsigned writemask
= instr
->const_index
[1];
3702 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3703 * since the untyped writes below operate in units of 32-bits, which
3704 * means that we need to write twice as many components each time.
3705 * Also, we have to suffle 64-bit data to be in the appropriate layout
3706 * expected by our 32-bit write messages.
3708 unsigned type_size
= 4;
3709 unsigned bit_size
= instr
->src
[0].is_ssa
?
3710 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3711 if (bit_size
== 64) {
3714 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3715 shuffle_64bit_data_for_32bit_write(
3717 retype(tmp
, BRW_REGISTER_TYPE_F
),
3718 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3719 instr
->num_components
);
3723 unsigned type_slots
= type_size
/ 4;
3725 /* Combine groups of consecutive enabled channels in one write
3726 * message. We use ffs to find the first enabled channel and then ffs on
3727 * the bit-inverse, down-shifted writemask to determine the length of
3728 * the block of enabled bits.
3731 unsigned first_component
= ffs(writemask
) - 1;
3732 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3734 /* We can't write more than 2 64-bit components at once. Limit the
3735 * length of the write to what we can do and let the next iteration
3739 length
= MIN2(2, length
);
3742 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3744 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3745 type_size
* first_component
);
3747 offset_reg
= vgrf(glsl_type::uint_type
);
3749 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3750 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3753 emit_untyped_write(bld
, surf_index
, offset_reg
,
3754 offset(val_reg
, bld
, first_component
* type_slots
),
3755 1 /* dims */, length
* type_slots
,
3756 BRW_PREDICATE_NONE
);
3758 /* Clear the bits in the writemask that we just wrote, then try
3759 * again to see if more channels are left.
3761 writemask
&= (15 << (first_component
+ length
));
3768 nir_emit_intrinsic(bld
, instr
);
3774 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3777 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3778 dest
= get_nir_dest(instr
->dest
);
3780 switch (instr
->intrinsic
) {
3781 case nir_intrinsic_atomic_counter_inc
:
3782 case nir_intrinsic_atomic_counter_dec
:
3783 case nir_intrinsic_atomic_counter_read
: {
3784 if (stage
== MESA_SHADER_FRAGMENT
&&
3785 instr
->intrinsic
!= nir_intrinsic_atomic_counter_read
)
3786 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
3788 /* Get the arguments of the atomic intrinsic. */
3789 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3790 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3791 instr
->const_index
[0]);
3794 /* Emit a surface read or atomic op. */
3795 switch (instr
->intrinsic
) {
3796 case nir_intrinsic_atomic_counter_read
:
3797 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3800 case nir_intrinsic_atomic_counter_inc
:
3801 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
3802 fs_reg(), 1, 1, BRW_AOP_INC
);
3805 case nir_intrinsic_atomic_counter_dec
:
3806 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
3807 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
3811 unreachable("Unreachable");
3814 /* Assign the result. */
3815 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3817 /* Mark the surface as used. */
3818 brw_mark_surface_used(stage_prog_data
, surface
);
3822 case nir_intrinsic_image_load
:
3823 case nir_intrinsic_image_store
:
3824 case nir_intrinsic_image_atomic_add
:
3825 case nir_intrinsic_image_atomic_min
:
3826 case nir_intrinsic_image_atomic_max
:
3827 case nir_intrinsic_image_atomic_and
:
3828 case nir_intrinsic_image_atomic_or
:
3829 case nir_intrinsic_image_atomic_xor
:
3830 case nir_intrinsic_image_atomic_exchange
:
3831 case nir_intrinsic_image_atomic_comp_swap
: {
3832 using namespace image_access
;
3834 if (stage
== MESA_SHADER_FRAGMENT
&&
3835 instr
->intrinsic
!= nir_intrinsic_image_load
)
3836 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
3838 /* Get the referenced image variable and type. */
3839 const nir_variable
*var
= instr
->variables
[0]->var
;
3840 const glsl_type
*type
= var
->type
->without_array();
3841 const brw_reg_type base_type
= get_image_base_type(type
);
3843 /* Get some metadata from the image intrinsic. */
3844 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3845 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3846 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3847 const unsigned format
= var
->data
.image
.format
;
3849 /* Get the arguments of the image intrinsic. */
3850 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3851 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3852 BRW_REGISTER_TYPE_UD
);
3853 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3854 retype(get_nir_src(instr
->src
[2]), base_type
) :
3856 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3857 retype(get_nir_src(instr
->src
[3]), base_type
) :
3861 /* Emit an image load, store or atomic op. */
3862 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3863 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3865 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3866 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3867 var
->data
.image
.write_only
? GL_NONE
: format
);
3870 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3871 surf_dims
, arr_dims
, info
->dest_components
,
3872 get_image_atomic_op(instr
->intrinsic
, type
));
3874 /* Assign the result. */
3875 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3876 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3877 offset(tmp
, bld
, c
));
3881 case nir_intrinsic_memory_barrier_atomic_counter
:
3882 case nir_intrinsic_memory_barrier_buffer
:
3883 case nir_intrinsic_memory_barrier_image
:
3884 case nir_intrinsic_memory_barrier
: {
3885 const fs_builder ubld
= bld
.group(8, 0);
3886 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3887 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3892 case nir_intrinsic_group_memory_barrier
:
3893 case nir_intrinsic_memory_barrier_shared
:
3894 /* We treat these workgroup-level barriers as no-ops. This should be
3895 * safe at present and as long as:
3897 * - Memory access instructions are not subsequently reordered by the
3898 * compiler back-end.
3900 * - All threads from a given compute shader workgroup fit within a
3901 * single subslice and therefore talk to the same HDC shared unit
3902 * what supposedly guarantees ordering and coherency between threads
3903 * from the same workgroup. This may change in the future when we
3904 * start splitting workgroups across multiple subslices.
3906 * - The context is not in fault-and-stream mode, which could cause
3907 * memory transactions (including to SLM) prior to the barrier to be
3908 * replayed after the barrier if a pagefault occurs. This shouldn't
3909 * be a problem up to and including SKL because fault-and-stream is
3910 * not usable due to hardware issues, but that's likely to change in
3915 case nir_intrinsic_shader_clock
: {
3916 /* We cannot do anything if there is an event, so ignore it for now */
3917 fs_reg shader_clock
= get_timestamp(bld
);
3918 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
3920 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3924 case nir_intrinsic_image_size
: {
3925 /* Get the referenced image variable and type. */
3926 const nir_variable
*var
= instr
->variables
[0]->var
;
3927 const glsl_type
*type
= var
->type
->without_array();
3929 /* Get the size of the image. */
3930 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3931 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3933 /* For 1DArray image types, the array index is stored in the Z component.
3934 * Fix this by swizzling the Z component to the Y component.
3936 const bool is_1d_array_image
=
3937 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3938 type
->sampler_array
;
3940 /* For CubeArray images, we should count the number of cubes instead
3941 * of the number of faces. Fix it by dividing the (Z component) by 6.
3943 const bool is_cube_array_image
=
3944 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3945 type
->sampler_array
;
3947 /* Copy all the components. */
3948 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3949 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
3950 if ((int)c
>= type
->coordinate_components()) {
3951 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3953 } else if (c
== 1 && is_1d_array_image
) {
3954 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3955 offset(size
, bld
, 2));
3956 } else if (c
== 2 && is_cube_array_image
) {
3957 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3958 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3959 offset(size
, bld
, c
), brw_imm_d(6));
3961 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3962 offset(size
, bld
, c
));
3969 case nir_intrinsic_image_samples
:
3970 /* The driver does not support multi-sampled images. */
3971 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3974 case nir_intrinsic_load_uniform
: {
3975 /* Offsets are in bytes but they should always be multiples of 4 */
3976 assert(instr
->const_index
[0] % 4 == 0);
3978 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3980 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3982 /* Offsets are in bytes but they should always be multiples of 4 */
3983 assert(const_offset
->u32
[0] % 4 == 0);
3984 src
.reg_offset
= const_offset
->u32
[0] / 4;
3986 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3987 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3990 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3991 BRW_REGISTER_TYPE_UD
);
3993 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3994 * go past the end of the uniform. In order to keep the n'th
3995 * component from running past, we subtract off the size of all but
3996 * one component of the vector.
3998 assert(instr
->const_index
[1] >=
3999 instr
->num_components
* (int) type_sz(dest
.type
));
4000 unsigned read_size
= instr
->const_index
[1] -
4001 (instr
->num_components
- 1) * type_sz(dest
.type
);
4003 fs_reg indirect_chv_high_32bit
;
4004 bool is_chv_bxt_64bit
=
4005 (devinfo
->is_cherryview
|| devinfo
->is_broxton
) &&
4006 type_sz(dest
.type
) == 8;
4007 if (is_chv_bxt_64bit
) {
4008 indirect_chv_high_32bit
= vgrf(glsl_type::uint_type
);
4009 /* Calculate indirect address to read high 32 bits */
4010 bld
.ADD(indirect_chv_high_32bit
, indirect
, brw_imm_ud(4));
4013 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4014 if (!is_chv_bxt_64bit
) {
4015 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4016 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4017 indirect
, brw_imm_ud(read_size
));
4019 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4020 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, 0),
4021 offset(src
, bld
, j
),
4022 indirect
, brw_imm_ud(read_size
));
4024 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4025 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, 1),
4026 offset(src
, bld
, j
),
4027 indirect_chv_high_32bit
, brw_imm_ud(read_size
));
4034 case nir_intrinsic_load_ubo
: {
4035 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
4039 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4040 const_index
->u32
[0];
4041 surf_index
= brw_imm_ud(index
);
4042 brw_mark_surface_used(prog_data
, index
);
4044 /* The block index is not a constant. Evaluate the index expression
4045 * per-channel and add the base UBO index; we have to select a value
4046 * from any live channel.
4048 surf_index
= vgrf(glsl_type::uint_type
);
4049 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4050 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4051 surf_index
= bld
.emit_uniformize(surf_index
);
4053 /* Assume this may touch any UBO. It would be nice to provide
4054 * a tighter bound, but the array information is already lowered away.
4056 brw_mark_surface_used(prog_data
,
4057 stage_prog_data
->binding_table
.ubo_start
+
4058 nir
->info
.num_ubos
- 1);
4061 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4062 if (const_offset
== NULL
) {
4063 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4064 BRW_REGISTER_TYPE_UD
);
4066 for (int i
= 0; i
< instr
->num_components
; i
++)
4067 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4068 base_offset
, i
* type_sz(dest
.type
));
4070 /* Even if we are loading doubles, a pull constant load will load
4071 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4072 * need to load a full dvec4 we will have to emit 2 loads. This is
4073 * similar to demote_pull_constants(), except that in that case we
4074 * see individual accesses to each component of the vector and then
4075 * we let CSE deal with duplicate loads. Here we see a vector access
4076 * and we have to split it if necessary.
4078 const unsigned type_size
= type_sz(dest
.type
);
4079 const fs_reg packed_consts
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
4080 for (unsigned c
= 0; c
< instr
->num_components
;) {
4081 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
4083 /* Number of usable components in the next 16B-aligned load */
4084 const unsigned count
= MIN2(instr
->num_components
- c
,
4085 (16 - base
% 16) / type_size
);
4088 .emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4089 packed_consts
, surf_index
, brw_imm_ud(base
& ~15));
4091 const fs_reg consts
=
4092 retype(byte_offset(packed_consts
, base
& 15), dest
.type
);
4094 for (unsigned d
= 0; d
< count
; d
++)
4095 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4103 case nir_intrinsic_load_ssbo
: {
4104 assert(devinfo
->gen
>= 7);
4106 nir_const_value
*const_uniform_block
=
4107 nir_src_as_const_value(instr
->src
[0]);
4110 if (const_uniform_block
) {
4111 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4112 const_uniform_block
->u32
[0];
4113 surf_index
= brw_imm_ud(index
);
4114 brw_mark_surface_used(prog_data
, index
);
4116 surf_index
= vgrf(glsl_type::uint_type
);
4117 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4118 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4120 /* Assume this may touch any UBO. It would be nice to provide
4121 * a tighter bound, but the array information is already lowered away.
4123 brw_mark_surface_used(prog_data
,
4124 stage_prog_data
->binding_table
.ssbo_start
+
4125 nir
->info
.num_ssbos
- 1);
4129 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4131 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
4133 offset_reg
= get_nir_src(instr
->src
[1]);
4136 /* Read the vector */
4137 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4138 instr
->num_components
);
4143 case nir_intrinsic_store_ssbo
: {
4144 assert(devinfo
->gen
>= 7);
4146 if (stage
== MESA_SHADER_FRAGMENT
)
4147 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
4151 nir_const_value
*const_uniform_block
=
4152 nir_src_as_const_value(instr
->src
[1]);
4153 if (const_uniform_block
) {
4154 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4155 const_uniform_block
->u32
[0];
4156 surf_index
= brw_imm_ud(index
);
4157 brw_mark_surface_used(prog_data
, index
);
4159 surf_index
= vgrf(glsl_type::uint_type
);
4160 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4161 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4163 brw_mark_surface_used(prog_data
,
4164 stage_prog_data
->binding_table
.ssbo_start
+
4165 nir
->info
.num_ssbos
- 1);
4169 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4172 unsigned writemask
= instr
->const_index
[0];
4174 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4175 * since the untyped writes below operate in units of 32-bits, which
4176 * means that we need to write twice as many components each time.
4177 * Also, we have to suffle 64-bit data to be in the appropriate layout
4178 * expected by our 32-bit write messages.
4180 unsigned type_size
= 4;
4181 unsigned bit_size
= instr
->src
[0].is_ssa
?
4182 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
4183 if (bit_size
== 64) {
4186 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
4187 shuffle_64bit_data_for_32bit_write(bld
,
4188 retype(tmp
, BRW_REGISTER_TYPE_F
),
4189 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
4190 instr
->num_components
);
4194 unsigned type_slots
= type_size
/ 4;
4196 /* Combine groups of consecutive enabled channels in one write
4197 * message. We use ffs to find the first enabled channel and then ffs on
4198 * the bit-inverse, down-shifted writemask to determine the length of
4199 * the block of enabled bits.
4202 unsigned first_component
= ffs(writemask
) - 1;
4203 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
4205 /* We can't write more than 2 64-bit components at once. Limit the
4206 * length of the write to what we can do and let the next iteration
4210 length
= MIN2(2, length
);
4213 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4215 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4216 type_size
* first_component
);
4218 offset_reg
= vgrf(glsl_type::uint_type
);
4220 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4221 brw_imm_ud(type_size
* first_component
));
4225 emit_untyped_write(bld
, surf_index
, offset_reg
,
4226 offset(val_reg
, bld
, first_component
* type_slots
),
4227 1 /* dims */, length
* type_slots
,
4228 BRW_PREDICATE_NONE
);
4230 /* Clear the bits in the writemask that we just wrote, then try
4231 * again to see if more channels are left.
4233 writemask
&= (15 << (first_component
+ length
));
4238 case nir_intrinsic_store_output
: {
4239 fs_reg src
= get_nir_src(instr
->src
[0]);
4240 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
4241 instr
->const_index
[0]);
4243 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4244 assert(const_offset
&& "Indirect output stores not allowed");
4245 new_dest
= offset(new_dest
, bld
, const_offset
->u32
[0]);
4247 unsigned num_components
= instr
->num_components
;
4248 unsigned first_component
= nir_intrinsic_component(instr
);
4249 unsigned bit_size
= instr
->src
[0].is_ssa
?
4250 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
4251 if (bit_size
== 64) {
4253 fs_reg(VGRF
, alloc
.allocate(2 * num_components
),
4254 BRW_REGISTER_TYPE_F
);
4255 shuffle_64bit_data_for_32bit_write(
4256 bld
, tmp
, retype(src
, BRW_REGISTER_TYPE_DF
), num_components
);
4257 src
= retype(tmp
, src
.type
);
4258 num_components
*= 2;
4261 for (unsigned j
= 0; j
< num_components
; j
++) {
4262 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4263 offset(src
, bld
, j
));
4268 case nir_intrinsic_ssbo_atomic_add
:
4269 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4271 case nir_intrinsic_ssbo_atomic_imin
:
4272 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4274 case nir_intrinsic_ssbo_atomic_umin
:
4275 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4277 case nir_intrinsic_ssbo_atomic_imax
:
4278 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4280 case nir_intrinsic_ssbo_atomic_umax
:
4281 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4283 case nir_intrinsic_ssbo_atomic_and
:
4284 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4286 case nir_intrinsic_ssbo_atomic_or
:
4287 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4289 case nir_intrinsic_ssbo_atomic_xor
:
4290 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4292 case nir_intrinsic_ssbo_atomic_exchange
:
4293 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4295 case nir_intrinsic_ssbo_atomic_comp_swap
:
4296 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4299 case nir_intrinsic_get_buffer_size
: {
4300 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4301 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4303 /* A resinfo's sampler message is used to get the buffer size. The
4304 * SIMD8's writeback message consists of four registers and SIMD16's
4305 * writeback message consists of 8 destination registers (two per each
4306 * component). Because we are only interested on the first channel of
4307 * the first returned component, where resinfo returns the buffer size
4308 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4309 * the dispatch width.
4311 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4312 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4313 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4316 ubld
.MOV(src_payload
, brw_imm_d(0));
4318 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4319 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4320 src_payload
, brw_imm_ud(index
));
4321 inst
->header_size
= 0;
4323 inst
->regs_written
= 4;
4325 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4326 brw_mark_surface_used(prog_data
, index
);
4330 case nir_intrinsic_load_channel_num
: {
4331 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
4332 dest
= retype(dest
, BRW_REGISTER_TYPE_UD
);
4333 const fs_builder allbld8
= bld
.group(8, 0).exec_all();
4334 allbld8
.MOV(tmp
, brw_imm_v(0x76543210));
4335 if (dispatch_width
> 8)
4336 allbld8
.ADD(byte_offset(tmp
, 16), tmp
, brw_imm_uw(8u));
4337 if (dispatch_width
> 16) {
4338 const fs_builder allbld16
= bld
.group(16, 0).exec_all();
4339 allbld16
.ADD(byte_offset(tmp
, 32), tmp
, brw_imm_uw(16u));
4346 unreachable("unknown intrinsic");
4351 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4352 int op
, nir_intrinsic_instr
*instr
)
4354 if (stage
== MESA_SHADER_FRAGMENT
)
4355 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
4358 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4359 dest
= get_nir_dest(instr
->dest
);
4362 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4363 if (const_surface
) {
4364 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4365 const_surface
->u32
[0];
4366 surface
= brw_imm_ud(surf_index
);
4367 brw_mark_surface_used(prog_data
, surf_index
);
4369 surface
= vgrf(glsl_type::uint_type
);
4370 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4371 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4373 /* Assume this may touch any SSBO. This is the same we do for other
4374 * UBO/SSBO accesses with non-constant surface.
4376 brw_mark_surface_used(prog_data
,
4377 stage_prog_data
->binding_table
.ssbo_start
+
4378 nir
->info
.num_ssbos
- 1);
4381 fs_reg offset
= get_nir_src(instr
->src
[1]);
4382 fs_reg data1
= get_nir_src(instr
->src
[2]);
4384 if (op
== BRW_AOP_CMPWR
)
4385 data2
= get_nir_src(instr
->src
[3]);
4387 /* Emit the actual atomic operation */
4389 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4391 1 /* dims */, 1 /* rsize */,
4393 BRW_PREDICATE_NONE
);
4394 dest
.type
= atomic_result
.type
;
4395 bld
.MOV(dest
, atomic_result
);
4399 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4400 int op
, nir_intrinsic_instr
*instr
)
4403 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4404 dest
= get_nir_dest(instr
->dest
);
4406 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4408 fs_reg data1
= get_nir_src(instr
->src
[1]);
4410 if (op
== BRW_AOP_CMPWR
)
4411 data2
= get_nir_src(instr
->src
[2]);
4413 /* Get the offset */
4414 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4416 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4418 offset
= vgrf(glsl_type::uint_type
);
4420 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4421 brw_imm_ud(instr
->const_index
[0]));
4424 /* Emit the actual atomic operation operation */
4426 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4428 1 /* dims */, 1 /* rsize */,
4430 BRW_PREDICATE_NONE
);
4431 dest
.type
= atomic_result
.type
;
4432 bld
.MOV(dest
, atomic_result
);
4436 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4438 unsigned texture
= instr
->texture_index
;
4439 unsigned sampler
= instr
->sampler_index
;
4441 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4443 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4444 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4446 int lod_components
= 0;
4448 /* The hardware requires a LOD for buffer textures */
4449 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4450 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4452 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4453 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4454 switch (instr
->src
[i
].src_type
) {
4455 case nir_tex_src_bias
:
4456 srcs
[TEX_LOGICAL_SRC_LOD
] =
4457 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4459 case nir_tex_src_comparitor
:
4460 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4462 case nir_tex_src_coord
:
4463 switch (instr
->op
) {
4465 case nir_texop_txf_ms
:
4466 case nir_texop_txf_ms_mcs
:
4467 case nir_texop_samples_identical
:
4468 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4471 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4475 case nir_tex_src_ddx
:
4476 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4477 lod_components
= nir_tex_instr_src_size(instr
, i
);
4479 case nir_tex_src_ddy
:
4480 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4482 case nir_tex_src_lod
:
4483 switch (instr
->op
) {
4485 srcs
[TEX_LOGICAL_SRC_LOD
] =
4486 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4489 srcs
[TEX_LOGICAL_SRC_LOD
] =
4490 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4493 srcs
[TEX_LOGICAL_SRC_LOD
] =
4494 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4498 case nir_tex_src_ms_index
:
4499 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4502 case nir_tex_src_offset
: {
4503 nir_const_value
*const_offset
=
4504 nir_src_as_const_value(instr
->src
[i
].src
);
4506 unsigned header_bits
= brw_texture_offset(const_offset
->i32
, 3);
4507 if (header_bits
!= 0)
4508 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] = brw_imm_ud(header_bits
);
4510 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] =
4511 retype(src
, BRW_REGISTER_TYPE_D
);
4516 case nir_tex_src_projector
:
4517 unreachable("should be lowered");
4519 case nir_tex_src_texture_offset
: {
4520 /* Figure out the highest possible texture index and mark it as used */
4521 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4522 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4523 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4525 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4527 brw_mark_surface_used(prog_data
, max_used
);
4529 /* Emit code to evaluate the actual indexing expression */
4530 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4531 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4532 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4536 case nir_tex_src_sampler_offset
: {
4537 /* Emit code to evaluate the actual indexing expression */
4538 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4539 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4540 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4544 case nir_tex_src_ms_mcs
:
4545 assert(instr
->op
== nir_texop_txf_ms
);
4546 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4549 case nir_tex_src_plane
: {
4550 nir_const_value
*const_plane
=
4551 nir_src_as_const_value(instr
->src
[i
].src
);
4552 const uint32_t plane
= const_plane
->u32
[0];
4553 const uint32_t texture_index
=
4554 instr
->texture_index
+
4555 stage_prog_data
->binding_table
.plane_start
[plane
] -
4556 stage_prog_data
->binding_table
.texture_start
;
4558 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4563 unreachable("unknown texture source");
4567 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4568 (instr
->op
== nir_texop_txf_ms
||
4569 instr
->op
== nir_texop_samples_identical
)) {
4570 if (devinfo
->gen
>= 7 &&
4571 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4572 srcs
[TEX_LOGICAL_SRC_MCS
] =
4573 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4574 instr
->coord_components
,
4575 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4577 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4581 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4582 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4584 if (instr
->op
== nir_texop_query_levels
||
4585 (instr
->op
== nir_texop_tex
&& stage
!= MESA_SHADER_FRAGMENT
)) {
4586 /* textureQueryLevels() and texture() are implemented in terms of TXS
4587 * and TXL respectively, so we need to pass a valid LOD argument.
4589 assert(srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
);
4590 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
4594 switch (instr
->op
) {
4596 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4597 SHADER_OPCODE_TXL_LOGICAL
);
4600 opcode
= FS_OPCODE_TXB_LOGICAL
;
4603 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4606 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4609 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4611 case nir_texop_txf_ms
:
4612 if ((key_tex
->msaa_16
& (1 << sampler
)))
4613 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4615 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4617 case nir_texop_txf_ms_mcs
:
4618 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4620 case nir_texop_query_levels
:
4622 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4625 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4628 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= BAD_FILE
&&
4629 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= IMM
)
4630 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4632 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4634 case nir_texop_texture_samples
:
4635 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4637 case nir_texop_samples_identical
: {
4638 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4640 /* If mcs is an immediate value, it means there is no MCS. In that case
4641 * just return false.
4643 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4644 bld
.MOV(dst
, brw_imm_ud(0u));
4645 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4646 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4647 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4648 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4649 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4651 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4652 BRW_CONDITIONAL_EQ
);
4657 unreachable("unknown texture opcode");
4660 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(instr
->dest_type
), 4);
4661 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4663 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4664 if (devinfo
->gen
>= 9 &&
4665 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4666 unsigned write_mask
= instr
->dest
.is_ssa
?
4667 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4668 (1 << dest_size
) - 1;
4669 assert(write_mask
!= 0); /* dead code should have been eliminated */
4670 inst
->regs_written
= util_last_bit(write_mask
) * dispatch_width
/ 8;
4672 inst
->regs_written
= 4 * dispatch_width
/ 8;
4675 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4676 inst
->shadow_compare
= true;
4678 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
== IMM
)
4679 inst
->offset
= srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].ud
;
4681 if (instr
->op
== nir_texop_tg4
) {
4682 if (instr
->component
== 1 &&
4683 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4684 /* gather4 sampler is broken for green channel on RG32F --
4685 * we must ask for blue instead.
4687 inst
->offset
|= 2 << 16;
4689 inst
->offset
|= instr
->component
<< 16;
4692 if (devinfo
->gen
== 6)
4693 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4697 for (unsigned i
= 0; i
< dest_size
; i
++)
4698 nir_dest
[i
] = offset(dst
, bld
, i
);
4700 if (instr
->op
== nir_texop_query_levels
) {
4701 /* # levels is in .w */
4702 nir_dest
[0] = offset(dst
, bld
, 3);
4703 } else if (instr
->op
== nir_texop_txs
&&
4704 dest_size
>= 3 && devinfo
->gen
< 7) {
4705 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4706 fs_reg depth
= offset(dst
, bld
, 2);
4707 nir_dest
[2] = vgrf(glsl_type::int_type
);
4708 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4711 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4715 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4717 switch (instr
->type
) {
4718 case nir_jump_break
:
4719 bld
.emit(BRW_OPCODE_BREAK
);
4721 case nir_jump_continue
:
4722 bld
.emit(BRW_OPCODE_CONTINUE
);
4724 case nir_jump_return
:
4726 unreachable("unknown jump");
4731 * This helper takes the result of a load operation that reads 32-bit elements
4739 * and shuffles the data to get this:
4746 * Which is exactly what we want if the load is reading 64-bit components
4747 * like doubles, where x represents the low 32-bit of the x double component
4748 * and y represents the high 32-bit of the x double component (likewise with
4749 * z and w for double component y). The parameter @components represents
4750 * the number of 64-bit components present in @src. This would typically be
4751 * 2 at most, since we can only fit 2 double elements in the result of a
4754 * Notice that @dst and @src can be the same register.
4757 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4760 uint32_t components
)
4762 assert(type_sz(src
.type
) == 4);
4763 assert(type_sz(dst
.type
) == 8);
4765 /* A temporary that we will use to shuffle the 32-bit data of each
4766 * component in the vector into valid 64-bit data. We can't write directly
4767 * to dst because dst can be (and would usually be) the same as src
4768 * and in that case the first MOV in the loop below would overwrite the
4769 * data read in the second MOV.
4771 fs_reg tmp
= bld
.vgrf(dst
.type
);
4773 for (unsigned i
= 0; i
< components
; i
++) {
4774 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4776 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4777 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4779 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4784 * This helper does the inverse operation of
4785 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4787 * We need to do this when we are going to use untyped write messsages that
4788 * operate with 32-bit components in order to arrange our 64-bit data to be
4789 * in the expected layout.
4791 * Notice that callers of this function, unlike in the case of the inverse
4792 * operation, would typically need to call this with dst and src being
4793 * different registers, since they would otherwise corrupt the original
4794 * 64-bit data they are about to write. Because of this the function checks
4795 * that the src and dst regions involved in the operation do not overlap.
4798 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4801 uint32_t components
)
4803 assert(type_sz(src
.type
) == 8);
4804 assert(type_sz(dst
.type
) == 4);
4806 assert(!src
.in_range(dst
, 2 * components
* bld
.dispatch_width() / 8));
4808 for (unsigned i
= 0; i
< components
; i
++) {
4809 const fs_reg component_i
= offset(src
, bld
, i
);
4810 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4811 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4816 setup_imm_df(const fs_builder
&bld
, double v
)
4818 const struct brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4819 assert(devinfo
->gen
>= 7);
4821 if (devinfo
->gen
>= 8)
4822 return brw_imm_df(v
);
4824 /* gen7.5 does not support DF immediates straighforward but the DIM
4825 * instruction allows to set the 64-bit immediate value.
4827 if (devinfo
->is_haswell
) {
4828 const fs_builder ubld
= bld
.exec_all();
4829 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4830 ubld
.DIM(dst
, brw_imm_df(v
));
4831 return component(dst
, 0);
4834 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4835 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4836 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4838 * Alternatively, we could also produce a normal VGRF (without stride 0)
4839 * by writing to all the channels in the VGRF, however, that would hit the
4840 * gen7 bug where we have to split writes that span more than 1 register
4841 * into instructions with a width of 4 (otherwise the write to the second
4842 * register written runs into an execmask hardware bug) which isn't very
4855 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4856 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4857 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4858 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4860 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);