2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
41 nir_emit_system_values();
43 /* get the main function and emit it */
44 nir_foreach_function(function
, nir
) {
45 assert(strcmp(function
->name
, "main") == 0);
46 assert(function
->impl
);
47 nir_emit_impl(function
->impl
);
52 fs_visitor::nir_setup_outputs()
54 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
57 nir_foreach_variable(var
, &nir
->outputs
) {
58 const unsigned vec4s
=
59 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
60 : type_size_vec4(var
->type
);
61 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * vec4s
);
62 for (unsigned i
= 0; i
< vec4s
; i
++) {
63 if (outputs
[var
->data
.driver_location
+ i
].file
== BAD_FILE
)
64 outputs
[var
->data
.driver_location
+ i
] = offset(reg
, bld
, 4 * i
);
70 fs_visitor::nir_setup_uniforms()
72 if (dispatch_width
!= min_dispatch_width
)
75 uniforms
= nir
->num_uniforms
/ 4;
79 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
83 nir_foreach_instr(instr
, block
) {
84 if (instr
->type
!= nir_instr_type_intrinsic
)
87 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
88 switch (intrin
->intrinsic
) {
89 case nir_intrinsic_load_vertex_id
:
90 unreachable("should be lowered by lower_vertex_id().");
92 case nir_intrinsic_load_vertex_id_zero_base
:
93 assert(v
->stage
== MESA_SHADER_VERTEX
);
94 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
95 if (reg
->file
== BAD_FILE
)
96 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
99 case nir_intrinsic_load_base_vertex
:
100 assert(v
->stage
== MESA_SHADER_VERTEX
);
101 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
102 if (reg
->file
== BAD_FILE
)
103 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
106 case nir_intrinsic_load_instance_id
:
107 assert(v
->stage
== MESA_SHADER_VERTEX
);
108 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
109 if (reg
->file
== BAD_FILE
)
110 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
113 case nir_intrinsic_load_base_instance
:
114 assert(v
->stage
== MESA_SHADER_VERTEX
);
115 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
116 if (reg
->file
== BAD_FILE
)
117 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
120 case nir_intrinsic_load_draw_id
:
121 assert(v
->stage
== MESA_SHADER_VERTEX
);
122 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
123 if (reg
->file
== BAD_FILE
)
124 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
127 case nir_intrinsic_load_invocation_id
:
128 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
130 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
131 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
132 if (reg
->file
== BAD_FILE
) {
133 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
134 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
135 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
136 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
141 case nir_intrinsic_load_sample_pos
:
142 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
143 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
144 if (reg
->file
== BAD_FILE
)
145 *reg
= *v
->emit_samplepos_setup();
148 case nir_intrinsic_load_sample_id
:
149 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
150 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
151 if (reg
->file
== BAD_FILE
)
152 *reg
= *v
->emit_sampleid_setup();
155 case nir_intrinsic_load_sample_mask_in
:
156 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
157 assert(v
->devinfo
->gen
>= 7);
158 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
159 if (reg
->file
== BAD_FILE
)
160 *reg
= *v
->emit_samplemaskin_setup();
163 case nir_intrinsic_load_work_group_id
:
164 assert(v
->stage
== MESA_SHADER_COMPUTE
);
165 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
166 if (reg
->file
== BAD_FILE
)
167 *reg
= *v
->emit_cs_work_group_id_setup();
170 case nir_intrinsic_load_helper_invocation
:
171 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
172 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
173 if (reg
->file
== BAD_FILE
) {
174 const fs_builder abld
=
175 v
->bld
.annotate("gl_HelperInvocation", NULL
);
177 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
178 * pixel mask is in g1.7 of the thread payload.
180 * We move the per-channel pixel enable bit to the low bit of each
181 * channel by shifting the byte containing the pixel mask by the
182 * vector immediate 0x76543210UV.
184 * The region of <1,8,0> reads only 1 byte (the pixel masks for
185 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
186 * masks for 2 and 3) in SIMD16.
188 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
190 stride(byte_offset(retype(brw_vec1_grf(1, 0),
191 BRW_REGISTER_TYPE_UB
), 28),
193 brw_imm_v(0x76543210));
195 /* A set bit in the pixel mask means the channel is enabled, but
196 * that is the opposite of gl_HelperInvocation so we need to invert
199 * The negate source-modifier bit of logical instructions on Gen8+
200 * performs 1's complement negation, so we can use that instead of
203 fs_reg inverted
= negate(shifted
);
204 if (v
->devinfo
->gen
< 8) {
205 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
206 abld
.NOT(inverted
, shifted
);
209 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
210 * with 1 and negating.
212 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
213 abld
.AND(anded
, inverted
, brw_imm_uw(1));
215 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
216 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
230 fs_visitor::nir_emit_system_values()
232 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
233 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
234 nir_system_values
[i
] = fs_reg();
237 nir_foreach_function(function
, nir
) {
238 assert(strcmp(function
->name
, "main") == 0);
239 assert(function
->impl
);
240 nir_foreach_block(block
, function
->impl
) {
241 emit_system_values_block(block
, this);
247 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
249 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
250 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
251 nir_locals
[i
] = fs_reg();
254 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
255 unsigned array_elems
=
256 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
257 unsigned size
= array_elems
* reg
->num_components
;
258 const brw_reg_type reg_type
=
259 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
260 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
263 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
266 nir_emit_cf_list(&impl
->body
);
270 fs_visitor::nir_emit_cf_list(exec_list
*list
)
272 exec_list_validate(list
);
273 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
274 switch (node
->type
) {
276 nir_emit_if(nir_cf_node_as_if(node
));
279 case nir_cf_node_loop
:
280 nir_emit_loop(nir_cf_node_as_loop(node
));
283 case nir_cf_node_block
:
284 nir_emit_block(nir_cf_node_as_block(node
));
288 unreachable("Invalid CFG node block");
294 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
296 /* first, put the condition into f0 */
297 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
298 retype(get_nir_src(if_stmt
->condition
),
299 BRW_REGISTER_TYPE_D
));
300 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
302 bld
.IF(BRW_PREDICATE_NORMAL
);
304 nir_emit_cf_list(&if_stmt
->then_list
);
306 /* note: if the else is empty, dead CF elimination will remove it */
307 bld
.emit(BRW_OPCODE_ELSE
);
309 nir_emit_cf_list(&if_stmt
->else_list
);
311 bld
.emit(BRW_OPCODE_ENDIF
);
315 fs_visitor::nir_emit_loop(nir_loop
*loop
)
317 bld
.emit(BRW_OPCODE_DO
);
319 nir_emit_cf_list(&loop
->body
);
321 bld
.emit(BRW_OPCODE_WHILE
);
325 fs_visitor::nir_emit_block(nir_block
*block
)
327 nir_foreach_instr(instr
, block
) {
328 nir_emit_instr(instr
);
333 fs_visitor::nir_emit_instr(nir_instr
*instr
)
335 const fs_builder abld
= bld
.annotate(NULL
, instr
);
337 switch (instr
->type
) {
338 case nir_instr_type_alu
:
339 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
342 case nir_instr_type_intrinsic
:
344 case MESA_SHADER_VERTEX
:
345 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
347 case MESA_SHADER_TESS_CTRL
:
348 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
350 case MESA_SHADER_TESS_EVAL
:
351 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
353 case MESA_SHADER_GEOMETRY
:
354 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
356 case MESA_SHADER_FRAGMENT
:
357 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
359 case MESA_SHADER_COMPUTE
:
360 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
363 unreachable("unsupported shader stage");
367 case nir_instr_type_tex
:
368 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
371 case nir_instr_type_load_const
:
372 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
375 case nir_instr_type_ssa_undef
:
376 /* We create a new VGRF for undefs on every use (by handling
377 * them in get_nir_src()), rather than for each definition.
378 * This helps register coalescing eliminate MOVs from undef.
382 case nir_instr_type_jump
:
383 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
387 unreachable("unknown instruction type");
392 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
396 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
397 const fs_reg
&result
)
399 if (!instr
->src
[0].src
.is_ssa
||
400 !instr
->src
[0].src
.ssa
->parent_instr
)
403 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
406 nir_alu_instr
*src0
=
407 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
409 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
410 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
413 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
414 assert(element
!= NULL
);
416 /* Element type to extract.*/
417 const brw_reg_type type
= brw_int_type(
418 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
419 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
421 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
422 op0
.type
= brw_type_for_nir_type(
423 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
424 nir_src_bit_size(src0
->src
[0].src
)));
425 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
427 set_saturate(instr
->dest
.saturate
,
428 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
433 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
434 const fs_reg
&result
)
436 if (!instr
->src
[0].src
.is_ssa
||
437 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
440 nir_intrinsic_instr
*src0
=
441 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
443 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
446 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
447 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
450 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
451 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
454 fs_reg tmp
= vgrf(glsl_type::int_type
);
456 if (devinfo
->gen
>= 6) {
457 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
458 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
460 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
462 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
463 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
465 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
467 * This negation looks like it's safe in practice, because bits 0:4 will
468 * surely be TRIANGLES
471 if (value1
->f32
[0] == -1.0f
) {
475 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
476 g0
, brw_imm_uw(0x3f80));
478 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
479 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
481 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
483 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
484 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
486 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
488 * This negation looks like it's safe in practice, because bits 0:4 will
489 * surely be TRIANGLES
492 if (value1
->f32
[0] == -1.0f
) {
496 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
498 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
504 emit_find_msb_using_lzd(const fs_builder
&bld
,
505 const fs_reg
&result
,
513 /* LZD of an absolute value source almost always does the right
514 * thing. There are two problem values:
516 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
517 * 0. However, findMSB(int(0x80000000)) == 30.
519 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
520 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
522 * For a value of zero or negative one, -1 will be returned.
524 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
525 * findMSB(-(1<<x)) should return x-1.
527 * For all negative number cases, including 0x80000000 and
528 * 0xffffffff, the correct value is obtained from LZD if instead of
529 * negating the (already negative) value the logical-not is used. A
530 * conditonal logical-not can be achieved in two instructions.
532 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
534 bld
.ASR(temp
, src
, brw_imm_d(31));
535 bld
.XOR(temp
, temp
, src
);
538 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
539 retype(temp
, BRW_REGISTER_TYPE_UD
));
541 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
542 * from the LSB side. Subtract the result from 31 to convert the MSB
543 * count into an LSB count. If no bits are set, LZD will return 32.
544 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
546 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
547 inst
->src
[0].negate
= true;
551 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
553 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
556 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
557 result
.type
= brw_type_for_nir_type(
558 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
559 nir_dest_bit_size(instr
->dest
.dest
)));
562 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
563 op
[i
] = get_nir_src(instr
->src
[i
].src
);
564 op
[i
].type
= brw_type_for_nir_type(
565 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
566 nir_src_bit_size(instr
->src
[i
].src
)));
567 op
[i
].abs
= instr
->src
[i
].abs
;
568 op
[i
].negate
= instr
->src
[i
].negate
;
571 /* We get a bunch of mov's out of the from_ssa pass and they may still
572 * be vectorized. We'll handle them as a special-case. We'll also
573 * handle vecN here because it's basically the same thing.
581 fs_reg temp
= result
;
582 bool need_extra_copy
= false;
583 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
584 if (!instr
->src
[i
].src
.is_ssa
&&
585 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
586 need_extra_copy
= true;
587 temp
= bld
.vgrf(result
.type
, 4);
592 for (unsigned i
= 0; i
< 4; i
++) {
593 if (!(instr
->dest
.write_mask
& (1 << i
)))
596 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
597 inst
= bld
.MOV(offset(temp
, bld
, i
),
598 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
600 inst
= bld
.MOV(offset(temp
, bld
, i
),
601 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
603 inst
->saturate
= instr
->dest
.saturate
;
606 /* In this case the source and destination registers were the same,
607 * so we need to insert an extra set of moves in order to deal with
610 if (need_extra_copy
) {
611 for (unsigned i
= 0; i
< 4; i
++) {
612 if (!(instr
->dest
.write_mask
& (1 << i
)))
615 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
624 /* At this point, we have dealt with any instruction that operates on
625 * more than a single channel. Therefore, we can just adjust the source
626 * and destination registers for that channel and emit the instruction.
628 unsigned channel
= 0;
629 if (nir_op_infos
[instr
->op
].output_size
== 0) {
630 /* Since NIR is doing the scalarizing for us, we should only ever see
631 * vectorized operations with a single channel.
633 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
634 channel
= ffs(instr
->dest
.write_mask
) - 1;
636 result
= offset(result
, bld
, channel
);
639 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
640 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
641 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
647 if (optimize_extract_to_float(instr
, result
))
649 inst
= bld
.MOV(result
, op
[0]);
650 inst
->saturate
= instr
->dest
.saturate
;
656 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
658 * "When source or destination is 64b (...), regioning in Align1
659 * must follow these rules:
661 * 1. Source and destination horizontal stride must be aligned to
665 * This means that 32-bit to 64-bit conversions need to have the 32-bit
666 * data elements aligned to 64-bit. This restriction does not apply to
669 if (devinfo
->is_cherryview
|| devinfo
->is_broxton
) {
670 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
671 tmp
= subscript(tmp
, op
[0].type
, 0);
672 inst
= bld
.MOV(tmp
, op
[0]);
673 inst
= bld
.MOV(result
, tmp
);
674 inst
->saturate
= instr
->dest
.saturate
;
681 inst
= bld
.MOV(result
, op
[0]);
682 inst
->saturate
= instr
->dest
.saturate
;
687 bld
.MOV(result
, op
[0]);
691 if (type_sz(op
[0].type
) < 8) {
692 /* AND(val, 0x80000000) gives the sign bit.
694 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
697 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
699 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
700 op
[0].type
= BRW_REGISTER_TYPE_UD
;
701 result
.type
= BRW_REGISTER_TYPE_UD
;
702 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
704 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
705 inst
->predicate
= BRW_PREDICATE_NORMAL
;
706 if (instr
->dest
.saturate
) {
707 inst
= bld
.MOV(result
, result
);
708 inst
->saturate
= true;
711 /* For doubles we do the same but we need to consider:
713 * - 2-src instructions can't operate with 64-bit immediates
714 * - The sign is encoded in the high 32-bit of each DF
715 * - CMP with DF requires special handling in SIMD16
716 * - We need to produce a DF result.
719 /* 2-src instructions can't have 64-bit immediates, so put 0.0 in
720 * a register and compare with that.
722 fs_reg tmp
= vgrf(glsl_type::double_type
);
723 bld
.MOV(tmp
, setup_imm_df(bld
, 0.0));
725 /* A direct DF CMP using the flag register (null dst) won't work in
726 * SIMD16 because the CMP will be split in two by lower_simd_width,
727 * resulting in two CMP instructions with the same dst (NULL),
728 * leading to dead code elimination of the first one. In SIMD8,
729 * however, there is no need to split the CMP and we can save some
732 fs_reg dst_tmp
= vgrf(glsl_type::double_type
);
733 bld
.CMP(dst_tmp
, op
[0], tmp
, BRW_CONDITIONAL_NZ
);
735 /* In SIMD16 we want to avoid using a NULL dst register with DF CMP,
736 * so we store the result of the comparison in a vgrf instead and
737 * then we generate a UD comparison from that that won't have to
738 * be split by lower_simd_width. This is what NIR does to handle
739 * double comparisons in the general case.
741 if (bld
.dispatch_width() == 16 ) {
742 fs_reg dst_tmp_ud
= retype(dst_tmp
, BRW_REGISTER_TYPE_UD
);
743 bld
.MOV(dst_tmp_ud
, subscript(dst_tmp
, BRW_REGISTER_TYPE_UD
, 0));
744 bld
.CMP(bld
.null_reg_ud(),
745 dst_tmp_ud
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
748 /* Get the high 32-bit of each double component where the sign is */
749 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
750 bld
.MOV(result_int
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
752 /* Get the sign bit */
753 bld
.AND(result_int
, result_int
, brw_imm_ud(0x80000000u
));
755 /* Add 1.0 to the sign, predicated to skip the case of op[0] == 0.0 */
756 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
757 inst
->predicate
= BRW_PREDICATE_NORMAL
;
759 /* Convert from 32-bit float to 64-bit double */
760 result
.type
= BRW_REGISTER_TYPE_DF
;
761 inst
= bld
.MOV(result
, retype(result_int
, BRW_REGISTER_TYPE_F
));
763 if (instr
->dest
.saturate
) {
764 inst
= bld
.MOV(result
, result
);
765 inst
->saturate
= true;
772 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
773 * -> non-negative val generates 0x00000000.
774 * Predicated OR sets 1 if val is positive.
776 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
777 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
778 bld
.ASR(result
, op
[0], brw_imm_d(31));
779 inst
= bld
.OR(result
, result
, brw_imm_d(1));
780 inst
->predicate
= BRW_PREDICATE_NORMAL
;
784 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
785 inst
->saturate
= instr
->dest
.saturate
;
789 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
790 inst
->saturate
= instr
->dest
.saturate
;
794 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
795 inst
->saturate
= instr
->dest
.saturate
;
799 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
800 inst
->saturate
= instr
->dest
.saturate
;
804 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
805 inst
->saturate
= instr
->dest
.saturate
;
809 if (fs_key
->high_quality_derivatives
) {
810 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
812 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
814 inst
->saturate
= instr
->dest
.saturate
;
816 case nir_op_fddx_fine
:
817 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
818 inst
->saturate
= instr
->dest
.saturate
;
820 case nir_op_fddx_coarse
:
821 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
822 inst
->saturate
= instr
->dest
.saturate
;
825 if (fs_key
->high_quality_derivatives
) {
826 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
828 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
830 inst
->saturate
= instr
->dest
.saturate
;
832 case nir_op_fddy_fine
:
833 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
834 inst
->saturate
= instr
->dest
.saturate
;
836 case nir_op_fddy_coarse
:
837 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
838 inst
->saturate
= instr
->dest
.saturate
;
842 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
844 inst
= bld
.ADD(result
, op
[0], op
[1]);
845 inst
->saturate
= instr
->dest
.saturate
;
849 inst
= bld
.MUL(result
, op
[0], op
[1]);
850 inst
->saturate
= instr
->dest
.saturate
;
854 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
855 bld
.MUL(result
, op
[0], op
[1]);
858 case nir_op_imul_high
:
859 case nir_op_umul_high
:
860 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
861 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
866 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
867 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
870 case nir_op_uadd_carry
:
871 unreachable("Should have been lowered by carry_to_arith().");
873 case nir_op_usub_borrow
:
874 unreachable("Should have been lowered by borrow_to_arith().");
878 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
879 * appears that our hardware just does the right thing for signed
882 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
883 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
887 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
888 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
890 /* Math instructions don't support conditional mod */
891 inst
= bld
.MOV(bld
.null_reg_d(), result
);
892 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
894 /* Now, we need to determine if signs of the sources are different.
895 * When we XOR the sources, the top bit is 0 if they are the same and 1
896 * if they are different. We can then use a conditional modifier to
897 * turn that into a predicate. This leads us to an XOR.l instruction.
899 * Technically, according to the PRM, you're not allowed to use .l on a
900 * XOR instruction. However, emperical experiments and Curro's reading
901 * of the simulator source both indicate that it's safe.
903 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
904 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
905 inst
->predicate
= BRW_PREDICATE_NORMAL
;
906 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
908 /* If the result of the initial remainder operation is non-zero and the
909 * two sources have different signs, add in a copy of op[1] to get the
910 * final integer modulus value.
912 inst
= bld
.ADD(result
, result
, op
[1]);
913 inst
->predicate
= BRW_PREDICATE_NORMAL
;
921 fs_reg dest
= result
;
922 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
923 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
925 brw_conditional_mod cond
;
928 cond
= BRW_CONDITIONAL_L
;
931 cond
= BRW_CONDITIONAL_GE
;
934 cond
= BRW_CONDITIONAL_Z
;
937 cond
= BRW_CONDITIONAL_NZ
;
940 unreachable("bad opcode");
942 bld
.CMP(dest
, op
[0], op
[1], cond
);
943 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
944 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
951 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
952 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
957 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
958 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
962 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
963 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
967 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
968 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
972 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
973 if (devinfo
->gen
>= 8) {
974 op
[0] = resolve_source_modifiers(op
[0]);
976 bld
.NOT(result
, op
[0]);
979 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
980 if (devinfo
->gen
>= 8) {
981 op
[0] = resolve_source_modifiers(op
[0]);
982 op
[1] = resolve_source_modifiers(op
[1]);
984 bld
.XOR(result
, op
[0], op
[1]);
987 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
988 if (devinfo
->gen
>= 8) {
989 op
[0] = resolve_source_modifiers(op
[0]);
990 op
[1] = resolve_source_modifiers(op
[1]);
992 bld
.OR(result
, op
[0], op
[1]);
995 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
996 if (devinfo
->gen
>= 8) {
997 op
[0] = resolve_source_modifiers(op
[0]);
998 op
[1] = resolve_source_modifiers(op
[1]);
1000 bld
.AND(result
, op
[0], op
[1]);
1006 case nir_op_ball_fequal2
:
1007 case nir_op_ball_iequal2
:
1008 case nir_op_ball_fequal3
:
1009 case nir_op_ball_iequal3
:
1010 case nir_op_ball_fequal4
:
1011 case nir_op_ball_iequal4
:
1012 case nir_op_bany_fnequal2
:
1013 case nir_op_bany_inequal2
:
1014 case nir_op_bany_fnequal3
:
1015 case nir_op_bany_inequal3
:
1016 case nir_op_bany_fnequal4
:
1017 case nir_op_bany_inequal4
:
1018 unreachable("Lowered by nir_lower_alu_reductions");
1020 case nir_op_fnoise1_1
:
1021 case nir_op_fnoise1_2
:
1022 case nir_op_fnoise1_3
:
1023 case nir_op_fnoise1_4
:
1024 case nir_op_fnoise2_1
:
1025 case nir_op_fnoise2_2
:
1026 case nir_op_fnoise2_3
:
1027 case nir_op_fnoise2_4
:
1028 case nir_op_fnoise3_1
:
1029 case nir_op_fnoise3_2
:
1030 case nir_op_fnoise3_3
:
1031 case nir_op_fnoise3_4
:
1032 case nir_op_fnoise4_1
:
1033 case nir_op_fnoise4_2
:
1034 case nir_op_fnoise4_3
:
1035 case nir_op_fnoise4_4
:
1036 unreachable("not reached: should be handled by lower_noise");
1039 unreachable("not reached: should be handled by ldexp_to_arith()");
1042 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1043 inst
->saturate
= instr
->dest
.saturate
;
1047 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1048 inst
->saturate
= instr
->dest
.saturate
;
1053 bld
.MOV(result
, negate(op
[0]));
1057 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1060 /* two-argument instructions can't take 64-bit immediates */
1061 fs_reg zero
= vgrf(glsl_type::double_type
);
1062 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1063 /* A SIMD16 execution needs to be split in two instructions, so use
1064 * a vgrf instead of the flag register as dst so instruction splitting
1067 fs_reg tmp
= vgrf(glsl_type::double_type
);
1068 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1069 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1073 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1077 inst
= bld
.RNDZ(result
, op
[0]);
1078 inst
->saturate
= instr
->dest
.saturate
;
1081 case nir_op_fceil
: {
1082 op
[0].negate
= !op
[0].negate
;
1083 fs_reg temp
= vgrf(glsl_type::float_type
);
1084 bld
.RNDD(temp
, op
[0]);
1086 inst
= bld
.MOV(result
, temp
);
1087 inst
->saturate
= instr
->dest
.saturate
;
1091 inst
= bld
.RNDD(result
, op
[0]);
1092 inst
->saturate
= instr
->dest
.saturate
;
1095 inst
= bld
.FRC(result
, op
[0]);
1096 inst
->saturate
= instr
->dest
.saturate
;
1098 case nir_op_fround_even
:
1099 inst
= bld
.RNDE(result
, op
[0]);
1100 inst
->saturate
= instr
->dest
.saturate
;
1103 case nir_op_fquantize2f16
: {
1104 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1105 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1106 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1108 /* The destination stride must be at least as big as the source stride. */
1109 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1112 /* Check for denormal */
1113 fs_reg abs_src0
= op
[0];
1114 abs_src0
.abs
= true;
1115 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1117 /* Get the appropriately signed zero */
1118 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1119 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1120 brw_imm_ud(0x80000000));
1121 /* Do the actual F32 -> F16 -> F32 conversion */
1122 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1123 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1124 /* Select that or zero based on normal status */
1125 inst
= bld
.SEL(result
, zero
, tmp32
);
1126 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1127 inst
->saturate
= instr
->dest
.saturate
;
1133 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1135 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1136 inst
->saturate
= instr
->dest
.saturate
;
1141 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1143 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1144 inst
->saturate
= instr
->dest
.saturate
;
1147 case nir_op_pack_snorm_2x16
:
1148 case nir_op_pack_snorm_4x8
:
1149 case nir_op_pack_unorm_2x16
:
1150 case nir_op_pack_unorm_4x8
:
1151 case nir_op_unpack_snorm_2x16
:
1152 case nir_op_unpack_snorm_4x8
:
1153 case nir_op_unpack_unorm_2x16
:
1154 case nir_op_unpack_unorm_4x8
:
1155 case nir_op_unpack_half_2x16
:
1156 case nir_op_pack_half_2x16
:
1157 unreachable("not reached: should be handled by lower_packing_builtins");
1159 case nir_op_unpack_half_2x16_split_x
:
1160 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1161 inst
->saturate
= instr
->dest
.saturate
;
1163 case nir_op_unpack_half_2x16_split_y
:
1164 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1165 inst
->saturate
= instr
->dest
.saturate
;
1168 case nir_op_pack_double_2x32_split
:
1169 /* Optimize the common case where we are re-packing a double with
1170 * the result of a previous double unpack. In this case we can take the
1171 * 32-bit value to use in the re-pack from the original double and bypass
1172 * the unpack operation.
1174 for (int i
= 0; i
< 2; i
++) {
1175 if (instr
->src
[i
].src
.is_ssa
)
1178 const nir_instr
*parent_instr
= instr
->src
[i
].src
.ssa
->parent_instr
;
1179 if (parent_instr
->type
== nir_instr_type_alu
)
1182 const nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1183 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_x
||
1184 alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1187 if (!alu_parent
->src
[0].src
.is_ssa
)
1190 op
[i
] = get_nir_src(alu_parent
->src
[0].src
);
1191 op
[i
] = offset(retype(op
[i
], BRW_REGISTER_TYPE_DF
), bld
,
1192 alu_parent
->src
[0].swizzle
[channel
]);
1193 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1194 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 1);
1196 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 0);
1198 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1201 case nir_op_unpack_double_2x32_split_x
:
1202 case nir_op_unpack_double_2x32_split_y
: {
1203 /* Optimize the common case where we are unpacking from a double we have
1204 * previously packed. In this case we can just bypass the pack operation
1205 * and source directly from its arguments.
1207 unsigned index
= (instr
->op
== nir_op_unpack_double_2x32_split_x
) ? 0 : 1;
1208 if (instr
->src
[0].src
.is_ssa
) {
1209 nir_instr
*parent_instr
= instr
->src
[0].src
.ssa
->parent_instr
;
1210 if (parent_instr
->type
== nir_instr_type_alu
) {
1211 nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1212 if (alu_parent
->op
== nir_op_pack_double_2x32_split
&&
1213 alu_parent
->src
[index
].src
.is_ssa
) {
1214 op
[0] = retype(get_nir_src(alu_parent
->src
[index
].src
),
1215 BRW_REGISTER_TYPE_UD
);
1217 offset(op
[0], bld
, alu_parent
->src
[index
].swizzle
[channel
]);
1218 bld
.MOV(result
, op
[0]);
1224 if (instr
->op
== nir_op_unpack_double_2x32_split_x
)
1225 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1227 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1232 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1233 inst
->saturate
= instr
->dest
.saturate
;
1236 case nir_op_bitfield_reverse
:
1237 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1238 bld
.BFREV(result
, op
[0]);
1241 case nir_op_bit_count
:
1242 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1243 bld
.CBIT(result
, op
[0]);
1246 case nir_op_ufind_msb
: {
1247 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1248 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1252 case nir_op_ifind_msb
: {
1253 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1255 if (devinfo
->gen
< 7) {
1256 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1258 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1260 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1261 * count from the LSB side. If FBH didn't return an error
1262 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1263 * count into an LSB count.
1265 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1267 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1268 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1269 inst
->src
[0].negate
= true;
1274 case nir_op_find_lsb
:
1275 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1277 if (devinfo
->gen
< 7) {
1278 fs_reg temp
= vgrf(glsl_type::int_type
);
1280 /* (x & -x) generates a value that consists of only the LSB of x.
1281 * For all powers of 2, findMSB(y) == findLSB(y).
1283 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1284 fs_reg negated_src
= src
;
1286 /* One must be negated, and the other must be non-negated. It
1287 * doesn't matter which is which.
1289 negated_src
.negate
= true;
1292 bld
.AND(temp
, src
, negated_src
);
1293 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1295 bld
.FBL(result
, op
[0]);
1299 case nir_op_ubitfield_extract
:
1300 case nir_op_ibitfield_extract
:
1301 unreachable("should have been lowered");
1304 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1305 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1308 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1309 bld
.BFI1(result
, op
[0], op
[1]);
1312 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1313 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1316 case nir_op_bitfield_insert
:
1317 unreachable("not reached: should have been lowered");
1320 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1321 bld
.SHL(result
, op
[0], op
[1]);
1324 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1325 bld
.ASR(result
, op
[0], op
[1]);
1328 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1329 bld
.SHR(result
, op
[0], op
[1]);
1332 case nir_op_pack_half_2x16_split
:
1333 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1337 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1338 inst
->saturate
= instr
->dest
.saturate
;
1342 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1343 inst
->saturate
= instr
->dest
.saturate
;
1347 if (optimize_frontfacing_ternary(instr
, result
))
1350 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1351 inst
= bld
.SEL(result
, op
[1], op
[2]);
1352 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1355 case nir_op_extract_u8
:
1356 case nir_op_extract_i8
: {
1357 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1358 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1359 assert(byte
!= NULL
);
1360 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1364 case nir_op_extract_u16
:
1365 case nir_op_extract_i16
: {
1366 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1367 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1368 assert(word
!= NULL
);
1369 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1374 unreachable("unhandled instruction");
1377 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1378 * to sign extend the low bit to 0/~0
1380 if (devinfo
->gen
<= 5 &&
1381 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1382 fs_reg masked
= vgrf(glsl_type::int_type
);
1383 bld
.AND(masked
, result
, brw_imm_d(1));
1384 masked
.negate
= true;
1385 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1390 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1391 nir_load_const_instr
*instr
)
1393 const brw_reg_type reg_type
=
1394 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1395 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1397 switch (instr
->def
.bit_size
) {
1399 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1400 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1404 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1405 bld
.MOV(offset(reg
, bld
, i
),
1406 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1410 unreachable("Invalid bit size");
1413 nir_ssa_values
[instr
->def
.index
] = reg
;
1417 fs_visitor::get_nir_src(const nir_src
&src
)
1421 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1422 const brw_reg_type reg_type
= src
.ssa
->bit_size
== 32 ?
1423 BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1424 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1426 reg
= nir_ssa_values
[src
.ssa
->index
];
1429 /* We don't handle indirects on locals */
1430 assert(src
.reg
.indirect
== NULL
);
1431 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1432 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1435 /* to avoid floating-point denorm flushing problems, set the type by
1436 * default to D - instructions that need floating point semantics will set
1437 * this to F if they need to
1439 return retype(reg
, BRW_REGISTER_TYPE_D
);
1443 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1446 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1448 nir_const_value
*val
= nir_src_as_const_value(src
);
1449 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1453 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1456 const brw_reg_type reg_type
=
1457 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1458 nir_ssa_values
[dest
.ssa
.index
] =
1459 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1460 return nir_ssa_values
[dest
.ssa
.index
];
1462 /* We don't handle indirects on locals */
1463 assert(dest
.reg
.indirect
== NULL
);
1464 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1465 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1470 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1472 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1473 BRW_REGISTER_TYPE_UD
);
1475 unsigned indirect_max
= 0;
1477 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1478 tail
= tail
->child
) {
1479 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1480 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1481 const unsigned size
= glsl_get_length(tail
->type
);
1482 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1483 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1484 image
= offset(image
, bld
, base
* element_size
);
1486 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1487 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1489 /* Accessing an invalid surface index with the dataport can result
1490 * in a hang. According to the spec "if the index used to
1491 * select an individual element is negative or greater than or
1492 * equal to the size of the array, the results of the operation
1493 * are undefined but may not lead to termination" -- which is one
1494 * of the possible outcomes of the hang. Clamp the index to
1495 * prevent access outside of the array bounds.
1497 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1498 BRW_REGISTER_TYPE_UD
),
1499 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1501 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1503 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1504 if (indirect
.file
== BAD_FILE
) {
1507 bld
.ADD(indirect
, indirect
, tmp
);
1512 if (indirect
.file
== BAD_FILE
) {
1515 /* Emit a pile of MOVs to load the uniform into a temporary. The
1516 * dead-code elimination pass will get rid of what we don't use.
1518 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1519 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1520 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1521 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1522 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1529 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1532 for (unsigned i
= 0; i
< 4; i
++) {
1533 if (!((wr_mask
>> i
) & 1))
1536 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1537 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1538 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1539 if (new_inst
->src
[j
].file
== VGRF
)
1540 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1547 * Get the matching channel register datatype for an image intrinsic of the
1548 * specified GLSL image type.
1551 get_image_base_type(const glsl_type
*type
)
1553 switch ((glsl_base_type
)type
->sampled_type
) {
1554 case GLSL_TYPE_UINT
:
1555 return BRW_REGISTER_TYPE_UD
;
1557 return BRW_REGISTER_TYPE_D
;
1558 case GLSL_TYPE_FLOAT
:
1559 return BRW_REGISTER_TYPE_F
;
1561 unreachable("Not reached.");
1566 * Get the appropriate atomic op for an image atomic intrinsic.
1569 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1572 case nir_intrinsic_image_atomic_add
:
1574 case nir_intrinsic_image_atomic_min
:
1575 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1576 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1577 case nir_intrinsic_image_atomic_max
:
1578 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1579 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1580 case nir_intrinsic_image_atomic_and
:
1582 case nir_intrinsic_image_atomic_or
:
1584 case nir_intrinsic_image_atomic_xor
:
1586 case nir_intrinsic_image_atomic_exchange
:
1588 case nir_intrinsic_image_atomic_comp_swap
:
1589 return BRW_AOP_CMPWR
;
1591 unreachable("Not reachable.");
1596 emit_pixel_interpolater_send(const fs_builder
&bld
,
1601 glsl_interp_mode interpolation
)
1603 struct brw_wm_prog_data
*wm_prog_data
=
1604 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1609 if (src
.file
== BAD_FILE
) {
1611 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1615 mlen
= 2 * bld
.dispatch_width() / 8;
1618 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1620 /* 2 floats per slot returned */
1621 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1622 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1624 wm_prog_data
->pulls_bary
= true;
1630 * Computes 1 << x, given a D/UD register containing some value x.
1633 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1635 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1637 fs_reg result
= bld
.vgrf(x
.type
, 1);
1638 fs_reg one
= bld
.vgrf(x
.type
, 1);
1640 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1641 bld
.SHL(result
, one
, x
);
1646 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1648 assert(stage
== MESA_SHADER_GEOMETRY
);
1650 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1652 if (gs_compile
->control_data_header_size_bits
== 0)
1655 /* We can only do EndPrimitive() functionality when the control data
1656 * consists of cut bits. Fortunately, the only time it isn't is when the
1657 * output type is points, in which case EndPrimitive() is a no-op.
1659 if (gs_prog_data
->control_data_format
!=
1660 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1664 /* Cut bits use one bit per vertex. */
1665 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1667 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1668 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1670 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1671 * vertex n, 0 otherwise. So all we need to do here is mark bit
1672 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1673 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1674 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1676 * Note that if EndPrimitive() is called before emitting any vertices, this
1677 * will cause us to set bit 31 of the control_data_bits register to 1.
1678 * That's fine because:
1680 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1681 * output, so the hardware will ignore cut bit 31.
1683 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1684 * last vertex, so setting cut bit 31 has no effect (since the primitive
1685 * is automatically ended when the GS terminates).
1687 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1688 * control_data_bits register to 0 when the first vertex is emitted.
1691 const fs_builder abld
= bld
.annotate("end primitive");
1693 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1694 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1695 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1696 fs_reg mask
= intexp2(abld
, prev_count
);
1697 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1698 * attention to the lower 5 bits of its second source argument, so on this
1699 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1700 * ((vertex_count - 1) % 32).
1702 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1706 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1708 assert(stage
== MESA_SHADER_GEOMETRY
);
1709 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1711 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1713 const fs_builder abld
= bld
.annotate("emit control data bits");
1714 const fs_builder fwa_bld
= bld
.exec_all();
1716 /* We use a single UD register to accumulate control data bits (32 bits
1717 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1720 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1721 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1722 * use the Channel Mask phase to enable/disable which DWord within that
1723 * group to write. (Remember, different SIMD8 channels may have emitted
1724 * different numbers of vertices, so we may need per-slot offsets.)
1726 * Channel masking presents an annoying problem: we may have to replicate
1727 * the data up to 4 times:
1729 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1731 * To avoid penalizing shaders that emit a small number of vertices, we
1732 * can avoid these sometimes: if the size of the control data header is
1733 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1734 * land in the same 128-bit group, so we can skip per-slot offsets.
1736 * Similarly, if the control data header is <= 32 bits, there is only one
1737 * DWord, so we can skip channel masks.
1739 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1741 fs_reg channel_mask
, per_slot_offset
;
1743 if (gs_compile
->control_data_header_size_bits
> 32) {
1744 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1745 channel_mask
= vgrf(glsl_type::uint_type
);
1748 if (gs_compile
->control_data_header_size_bits
> 128) {
1749 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1750 per_slot_offset
= vgrf(glsl_type::uint_type
);
1753 /* Figure out which DWord we're trying to write to using the formula:
1755 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1757 * Since bits_per_vertex is a power of two, and is known at compile
1758 * time, this can be optimized to:
1760 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1762 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1763 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1764 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1765 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1766 unsigned log2_bits_per_vertex
=
1767 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1768 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1770 if (per_slot_offset
.file
!= BAD_FILE
) {
1771 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1772 * the appropriate OWord within the control data header.
1774 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1777 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1778 * write to the appropriate DWORD within the OWORD.
1780 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1781 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1782 channel_mask
= intexp2(fwa_bld
, channel
);
1783 /* Then the channel masks need to be in bits 23:16. */
1784 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1787 /* Store the control data bits in the message payload and send it. */
1789 if (channel_mask
.file
!= BAD_FILE
)
1790 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1791 if (per_slot_offset
.file
!= BAD_FILE
)
1794 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1795 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1797 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1798 if (per_slot_offset
.file
!= BAD_FILE
)
1799 sources
[i
++] = per_slot_offset
;
1800 if (channel_mask
.file
!= BAD_FILE
)
1801 sources
[i
++] = channel_mask
;
1803 sources
[i
++] = this->control_data_bits
;
1806 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1807 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1809 /* We need to increment Global Offset by 256-bits to make room for
1810 * Broadwell's extra "Vertex Count" payload at the beginning of the
1811 * URB entry. Since this is an OWord message, Global Offset is counted
1812 * in 128-bit units, so we must set it to 2.
1814 if (gs_prog_data
->static_vertex_count
== -1)
1819 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1822 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1824 /* Note: we are calling this *before* increasing vertex_count, so
1825 * this->vertex_count == vertex_count - 1 in the formula above.
1828 /* Stream mode uses 2 bits per vertex */
1829 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1831 /* Must be a valid stream */
1832 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1834 /* Control data bits are initialized to 0 so we don't have to set any
1835 * bits when sending vertices to stream 0.
1840 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1842 /* reg::sid = stream_id */
1843 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1844 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1846 /* reg:shift_count = 2 * (vertex_count - 1) */
1847 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1848 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1850 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1851 * attention to the lower 5 bits of its second source argument, so on this
1852 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1853 * stream_id << ((2 * (vertex_count - 1)) % 32).
1855 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1856 abld
.SHL(mask
, sid
, shift_count
);
1857 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1861 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1864 assert(stage
== MESA_SHADER_GEOMETRY
);
1866 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1868 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1869 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1871 /* Haswell and later hardware ignores the "Render Stream Select" bits
1872 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1873 * and instead sends all primitives down the pipeline for rasterization.
1874 * If the SOL stage is enabled, "Render Stream Select" is honored and
1875 * primitives bound to non-zero streams are discarded after stream output.
1877 * Since the only purpose of primives sent to non-zero streams is to
1878 * be recorded by transform feedback, we can simply discard all geometry
1879 * bound to these streams when transform feedback is disabled.
1881 if (stream_id
> 0 && !nir
->info
->has_transform_feedback_varyings
)
1884 /* If we're outputting 32 control data bits or less, then we can wait
1885 * until the shader is over to output them all. Otherwise we need to
1886 * output them as we go. Now is the time to do it, since we're about to
1887 * output the vertex_count'th vertex, so it's guaranteed that the
1888 * control data bits associated with the (vertex_count - 1)th vertex are
1891 if (gs_compile
->control_data_header_size_bits
> 32) {
1892 const fs_builder abld
=
1893 bld
.annotate("emit vertex: emit control data bits");
1895 /* Only emit control data bits if we've finished accumulating a batch
1896 * of 32 bits. This is the case when:
1898 * (vertex_count * bits_per_vertex) % 32 == 0
1900 * (in other words, when the last 5 bits of vertex_count *
1901 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1902 * integer n (which is always the case, since bits_per_vertex is
1903 * always 1 or 2), this is equivalent to requiring that the last 5-n
1904 * bits of vertex_count are 0:
1906 * vertex_count & (2^(5-n) - 1) == 0
1908 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1911 * vertex_count & (32 / bits_per_vertex - 1) == 0
1913 * TODO: If vertex_count is an immediate, we could do some of this math
1914 * at compile time...
1917 abld
.AND(bld
.null_reg_d(), vertex_count
,
1918 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1919 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1921 abld
.IF(BRW_PREDICATE_NORMAL
);
1922 /* If vertex_count is 0, then no control data bits have been
1923 * accumulated yet, so we can skip emitting them.
1925 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1926 BRW_CONDITIONAL_NEQ
);
1927 abld
.IF(BRW_PREDICATE_NORMAL
);
1928 emit_gs_control_data_bits(vertex_count
);
1929 abld
.emit(BRW_OPCODE_ENDIF
);
1931 /* Reset control_data_bits to 0 so we can start accumulating a new
1934 * Note: in the case where vertex_count == 0, this neutralizes the
1935 * effect of any call to EndPrimitive() that the shader may have
1936 * made before outputting its first vertex.
1938 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1939 inst
->force_writemask_all
= true;
1940 abld
.emit(BRW_OPCODE_ENDIF
);
1943 emit_urb_writes(vertex_count
);
1945 /* In stream mode we have to set control data bits for all vertices
1946 * unless we have disabled control data bits completely (which we do
1947 * do for GL_POINTS outputs that don't use streams).
1949 if (gs_compile
->control_data_header_size_bits
> 0 &&
1950 gs_prog_data
->control_data_format
==
1951 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1952 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1957 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1958 const nir_src
&vertex_src
,
1959 unsigned base_offset
,
1960 const nir_src
&offset_src
,
1961 unsigned num_components
,
1962 unsigned first_component
)
1964 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1966 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1967 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1968 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1970 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1971 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1972 * gl_PointSize is available as a GS input, however, so it must be that.
1974 const bool is_point_size
= (base_offset
== 0);
1976 /* TODO: figure out push input layout for invocations == 1 */
1977 if (gs_prog_data
->invocations
== 1 &&
1978 offset_const
!= NULL
&& vertex_const
!= NULL
&&
1979 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
1980 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
1981 vertex_const
->u32
[0] * push_reg_count
;
1982 /* This input was pushed into registers. */
1983 if (is_point_size
) {
1984 /* gl_PointSize comes in .w */
1985 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1987 for (unsigned i
= 0; i
< num_components
; i
++) {
1988 bld
.MOV(offset(dst
, bld
, i
),
1989 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
1995 /* Resort to the pull model. Ensure the VUE handles are provided. */
1996 gs_prog_data
->base
.include_vue_handles
= true;
1998 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1999 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2001 if (gs_prog_data
->invocations
== 1) {
2003 /* The vertex index is constant; just select the proper URB handle. */
2005 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2006 BRW_REGISTER_TYPE_UD
);
2008 /* The vertex index is non-constant. We need to use indirect
2009 * addressing to fetch the proper URB handle.
2011 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2012 * indicating that channel <n> should read the handle from
2013 * DWord <n>. We convert that to bytes by multiplying by 4.
2015 * Next, we convert the vertex index to bytes by multiplying
2016 * by 32 (shifting by 5), and add the two together. This is
2017 * the final indirect byte offset.
2019 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
2020 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2021 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2022 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2024 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2025 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2026 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2027 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2028 /* Convert vertex_index to bytes (multiply by 32) */
2029 bld
.SHL(vertex_offset_bytes
,
2030 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2032 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2034 /* Use first_icp_handle as the base offset. There is one register
2035 * of URB handles per vertex, so inform the register allocator that
2036 * we might read up to nir->info->gs.vertices_in registers.
2038 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2039 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2040 fs_reg(icp_offset_bytes
),
2041 brw_imm_ud(nir
->info
->gs
.vertices_in
* REG_SIZE
));
2044 assert(gs_prog_data
->invocations
> 1);
2047 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2049 retype(brw_vec1_grf(first_icp_handle
+
2050 vertex_const
->i32
[0] / 8,
2051 vertex_const
->i32
[0] % 8),
2052 BRW_REGISTER_TYPE_UD
));
2054 /* The vertex index is non-constant. We need to use indirect
2055 * addressing to fetch the proper URB handle.
2058 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2060 /* Convert vertex_index to bytes (multiply by 4) */
2061 bld
.SHL(icp_offset_bytes
,
2062 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2065 /* Use first_icp_handle as the base offset. There is one DWord
2066 * of URB handles per vertex, so inform the register allocator that
2067 * we might read up to ceil(nir->info->gs.vertices_in / 8) registers.
2069 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2070 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2071 fs_reg(icp_offset_bytes
),
2072 brw_imm_ud(DIV_ROUND_UP(nir
->info
->gs
.vertices_in
, 8) *
2079 fs_reg tmp_dst
= dst
;
2080 fs_reg indirect_offset
= get_nir_src(offset_src
);
2081 unsigned num_iterations
= 1;
2082 unsigned orig_num_components
= num_components
;
2084 if (type_sz(dst
.type
) == 8) {
2085 if (num_components
> 2) {
2089 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2091 first_component
= first_component
/ 2;
2094 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2096 /* Constant indexing - use global offset. */
2097 if (first_component
!= 0) {
2098 unsigned read_components
= num_components
+ first_component
;
2099 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2100 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2101 inst
->size_written
= read_components
*
2102 tmp
.component_size(inst
->exec_size
);
2103 for (unsigned i
= 0; i
< num_components
; i
++) {
2104 bld
.MOV(offset(tmp_dst
, bld
, i
),
2105 offset(tmp
, bld
, i
+ first_component
));
2108 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2110 inst
->size_written
= num_components
*
2111 tmp_dst
.component_size(inst
->exec_size
);
2113 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2116 /* Indirect indexing - use per-slot offsets as well. */
2117 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2118 unsigned read_components
= num_components
+ first_component
;
2119 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2120 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2121 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2122 if (first_component
!= 0) {
2123 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2125 inst
->size_written
= read_components
*
2126 tmp
.component_size(inst
->exec_size
);
2127 for (unsigned i
= 0; i
< num_components
; i
++) {
2128 bld
.MOV(offset(tmp_dst
, bld
, i
),
2129 offset(tmp
, bld
, i
+ first_component
));
2132 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2134 inst
->size_written
= num_components
*
2135 tmp_dst
.component_size(inst
->exec_size
);
2137 inst
->offset
= base_offset
;
2141 if (type_sz(dst
.type
) == 8) {
2142 shuffle_32bit_load_result_to_64bit_data(
2143 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2145 for (unsigned c
= 0; c
< num_components
; c
++)
2146 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2149 if (num_iterations
> 1) {
2150 num_components
= orig_num_components
- 2;
2154 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2155 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2156 indirect_offset
= new_indirect
;
2161 if (is_point_size
) {
2162 /* Read the whole VUE header (because of alignment) and read .w. */
2163 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
2165 inst
->size_written
= 4 * REG_SIZE
;
2166 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2171 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2173 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2174 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2177 /* The only constant offset we should find is 0. brw_nir.c's
2178 * add_const_offset_to_base() will fold other constant offsets
2179 * into instr->const_index[0].
2181 assert(const_value
->u32
[0] == 0);
2185 return get_nir_src(*offset_src
);
2189 do_untyped_vector_read(const fs_builder
&bld
,
2191 const fs_reg surf_index
,
2192 const fs_reg offset_reg
,
2193 unsigned num_components
)
2195 if (type_sz(dest
.type
) == 4) {
2196 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2199 BRW_PREDICATE_NONE
);
2200 read_result
.type
= dest
.type
;
2201 for (unsigned i
= 0; i
< num_components
; i
++)
2202 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2203 } else if (type_sz(dest
.type
) == 8) {
2204 /* Reading a dvec, so we need to:
2206 * 1. Multiply num_components by 2, to account for the fact that we
2207 * need to read 64-bit components.
2208 * 2. Shuffle the result of the load to form valid 64-bit elements
2209 * 3. Emit a second load (for components z/w) if needed.
2211 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2212 bld
.MOV(read_offset
, offset_reg
);
2214 int iters
= num_components
<= 2 ? 1 : 2;
2216 /* Load the dvec, the first iteration loads components x/y, the second
2217 * iteration, if needed, loads components z/w
2219 for (int it
= 0; it
< iters
; it
++) {
2220 /* Compute number of components to read in this iteration */
2221 int iter_components
= MIN2(2, num_components
);
2222 num_components
-= iter_components
;
2224 /* Read. Since this message reads 32-bit components, we need to
2225 * read twice as many components.
2227 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2229 iter_components
* 2,
2230 BRW_PREDICATE_NONE
);
2232 /* Shuffle the 32-bit load result into valid 64-bit data */
2233 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2234 shuffle_32bit_load_result_to_64bit_data(
2235 bld
, packed_result
, read_result
, iter_components
);
2237 /* Move each component to its destination */
2238 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2239 for (int c
= 0; c
< iter_components
; c
++) {
2240 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2241 offset(packed_result
, bld
, c
));
2244 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2247 unreachable("Unsupported type");
2252 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2253 nir_intrinsic_instr
*instr
)
2255 assert(stage
== MESA_SHADER_VERTEX
);
2258 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2259 dest
= get_nir_dest(instr
->dest
);
2261 switch (instr
->intrinsic
) {
2262 case nir_intrinsic_load_vertex_id
:
2263 unreachable("should be lowered by lower_vertex_id()");
2265 case nir_intrinsic_load_vertex_id_zero_base
:
2266 case nir_intrinsic_load_base_vertex
:
2267 case nir_intrinsic_load_instance_id
:
2268 case nir_intrinsic_load_base_instance
:
2269 case nir_intrinsic_load_draw_id
: {
2270 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2271 fs_reg val
= nir_system_values
[sv
];
2272 assert(val
.file
!= BAD_FILE
);
2273 dest
.type
= val
.type
;
2278 case nir_intrinsic_load_input
: {
2279 fs_reg src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2280 unsigned first_component
= nir_intrinsic_component(instr
);
2281 unsigned num_components
= instr
->num_components
;
2282 enum brw_reg_type type
= dest
.type
;
2284 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2285 assert(const_offset
&& "Indirect input loads not allowed");
2286 src
= offset(src
, bld
, const_offset
->u32
[0]);
2288 for (unsigned j
= 0; j
< num_components
; j
++) {
2289 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2292 if (type
== BRW_REGISTER_TYPE_DF
) {
2293 /* Once the double vector is read, set again its original register
2294 * type to continue with normal execution.
2296 src
= retype(src
, type
);
2297 dest
= retype(dest
, type
);
2300 if (type_sz(src
.type
) == 8) {
2301 shuffle_32bit_load_result_to_64bit_data(bld
,
2303 retype(dest
, BRW_REGISTER_TYPE_F
),
2304 instr
->num_components
);
2310 nir_emit_intrinsic(bld
, instr
);
2316 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2317 nir_intrinsic_instr
*instr
)
2319 assert(stage
== MESA_SHADER_TESS_CTRL
);
2320 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2321 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2324 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2325 dst
= get_nir_dest(instr
->dest
);
2327 switch (instr
->intrinsic
) {
2328 case nir_intrinsic_load_primitive_id
:
2329 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2331 case nir_intrinsic_load_invocation_id
:
2332 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2334 case nir_intrinsic_load_patch_vertices_in
:
2335 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2336 brw_imm_d(tcs_key
->input_vertices
));
2339 case nir_intrinsic_barrier
: {
2340 if (tcs_prog_data
->instances
== 1)
2343 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2344 fs_reg m0_2
= component(m0
, 2);
2346 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2348 /* Zero the message header */
2349 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2351 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2352 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2353 brw_imm_ud(INTEL_MASK(16, 13)));
2355 /* Shift it up to bits 27:24. */
2356 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2358 /* Set the Barrier Count and the enable bit */
2359 chanbld
.OR(m0_2
, m0_2
,
2360 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2362 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2366 case nir_intrinsic_load_input
:
2367 unreachable("nir_lower_io should never give us these.");
2370 case nir_intrinsic_load_per_vertex_input
: {
2371 fs_reg indirect_offset
= get_indirect_offset(instr
);
2372 unsigned imm_offset
= instr
->const_index
[0];
2374 const nir_src
&vertex_src
= instr
->src
[0];
2375 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2382 /* Emit a MOV to resolve <0,1,0> regioning. */
2383 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2385 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2386 vertex_const
->i32
[0] & 7),
2387 BRW_REGISTER_TYPE_UD
));
2388 } else if (tcs_prog_data
->instances
== 1 &&
2389 vertex_src
.is_ssa
&&
2390 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2391 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2392 /* For the common case of only 1 instance, an array index of
2393 * gl_InvocationID means reading g1. Skip all the indirect work.
2395 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2397 /* The vertex index is non-constant. We need to use indirect
2398 * addressing to fetch the proper URB handle.
2400 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2402 /* Each ICP handle is a single DWord (4 bytes) */
2403 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2404 bld
.SHL(vertex_offset_bytes
,
2405 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2408 /* Start at g1. We might read up to 4 registers. */
2409 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2410 fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes
,
2411 brw_imm_ud(4 * REG_SIZE
));
2414 /* We can only read two double components with each URB read, so
2415 * we send two read messages in that case, each one loading up to
2416 * two double components.
2418 unsigned num_iterations
= 1;
2419 unsigned num_components
= instr
->num_components
;
2420 unsigned first_component
= nir_intrinsic_component(instr
);
2421 fs_reg orig_dst
= dst
;
2422 if (type_sz(dst
.type
) == 8) {
2423 first_component
= first_component
/ 2;
2424 if (instr
->num_components
> 2) {
2429 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2433 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2434 if (indirect_offset
.file
== BAD_FILE
) {
2435 /* Constant indexing - use global offset. */
2436 if (first_component
!= 0) {
2437 unsigned read_components
= num_components
+ first_component
;
2438 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2439 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2440 for (unsigned i
= 0; i
< num_components
; i
++) {
2441 bld
.MOV(offset(dst
, bld
, i
),
2442 offset(tmp
, bld
, i
+ first_component
));
2445 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2447 inst
->offset
= imm_offset
;
2450 /* Indirect indexing - use per-slot offsets as well. */
2451 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2452 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2453 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2454 if (first_component
!= 0) {
2455 unsigned read_components
= num_components
+ first_component
;
2456 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2457 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2459 for (unsigned i
= 0; i
< num_components
; i
++) {
2460 bld
.MOV(offset(dst
, bld
, i
),
2461 offset(tmp
, bld
, i
+ first_component
));
2464 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2467 inst
->offset
= imm_offset
;
2470 inst
->size_written
= (num_components
+ first_component
) *
2471 inst
->dst
.component_size(inst
->exec_size
);
2473 /* If we are reading 64-bit data using 32-bit read messages we need
2474 * build proper 64-bit data elements by shuffling the low and high
2475 * 32-bit components around like we do for other things like UBOs
2478 if (type_sz(dst
.type
) == 8) {
2479 shuffle_32bit_load_result_to_64bit_data(
2480 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2482 for (unsigned c
= 0; c
< num_components
; c
++) {
2483 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2484 offset(dst
, bld
, c
));
2488 /* Copy the temporary to the destination to deal with writemasking.
2490 * Also attempt to deal with gl_PointSize being in the .w component.
2492 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2493 assert(type_sz(dst
.type
) < 8);
2494 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2495 inst
->size_written
= 4 * REG_SIZE
;
2496 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2499 /* If we are loading double data and we need a second read message
2500 * adjust the write offset
2502 if (num_iterations
> 1) {
2503 num_components
= instr
->num_components
- 2;
2510 case nir_intrinsic_load_output
:
2511 case nir_intrinsic_load_per_vertex_output
: {
2512 fs_reg indirect_offset
= get_indirect_offset(instr
);
2513 unsigned imm_offset
= instr
->const_index
[0];
2514 unsigned first_component
= nir_intrinsic_component(instr
);
2517 if (indirect_offset
.file
== BAD_FILE
) {
2518 /* Replicate the patch handle to all enabled channels */
2519 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2520 bld
.MOV(patch_handle
,
2521 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2523 if (imm_offset
== 0) {
2524 /* This is a read of gl_TessLevelInner[], which lives in the
2525 * Patch URB header. The layout depends on the domain.
2527 dst
.type
= BRW_REGISTER_TYPE_F
;
2528 switch (tcs_key
->tes_primitive_mode
) {
2530 /* DWords 3-2 (reversed) */
2531 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2533 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2536 inst
->size_written
= 4 * REG_SIZE
;
2538 /* dst.xy = tmp.wz */
2539 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2540 bld
.MOV(offset(dst
, bld
, 1), offset(tmp
, bld
, 2));
2544 /* DWord 4; hardcode offset = 1 and size_written = REG_SIZE */
2545 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2548 inst
->size_written
= REG_SIZE
;
2551 /* All channels are undefined. */
2554 unreachable("Bogus tessellation domain");
2556 } else if (imm_offset
== 1) {
2557 /* This is a read of gl_TessLevelOuter[], which lives in the
2558 * Patch URB header. The layout depends on the domain.
2560 dst
.type
= BRW_REGISTER_TYPE_F
;
2562 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2563 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2566 inst
->size_written
= 4 * REG_SIZE
;
2568 /* Reswizzle: WZYX */
2570 offset(tmp
, bld
, 3),
2571 offset(tmp
, bld
, 2),
2572 offset(tmp
, bld
, 1),
2573 offset(tmp
, bld
, 0),
2576 unsigned num_components
;
2577 switch (tcs_key
->tes_primitive_mode
) {
2585 /* Isolines are not reversed; swizzle .zw -> .xy */
2586 srcs
[0] = offset(tmp
, bld
, 2);
2587 srcs
[1] = offset(tmp
, bld
, 3);
2591 unreachable("Bogus tessellation domain");
2593 bld
.LOAD_PAYLOAD(dst
, srcs
, num_components
, 0);
2595 if (first_component
!= 0) {
2596 unsigned read_components
=
2597 instr
->num_components
+ first_component
;
2598 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2599 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2601 inst
->size_written
= read_components
* REG_SIZE
;
2602 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2603 bld
.MOV(offset(dst
, bld
, i
),
2604 offset(tmp
, bld
, i
+ first_component
));
2607 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2609 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2611 inst
->offset
= imm_offset
;
2615 /* Indirect indexing - use per-slot offsets as well. */
2616 const fs_reg srcs
[] = {
2617 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2620 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2621 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2622 if (first_component
!= 0) {
2623 unsigned read_components
=
2624 instr
->num_components
+ first_component
;
2625 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2626 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2628 inst
->size_written
= read_components
* REG_SIZE
;
2629 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2630 bld
.MOV(offset(dst
, bld
, i
),
2631 offset(tmp
, bld
, i
+ first_component
));
2634 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2636 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2638 inst
->offset
= imm_offset
;
2644 case nir_intrinsic_store_output
:
2645 case nir_intrinsic_store_per_vertex_output
: {
2646 fs_reg value
= get_nir_src(instr
->src
[0]);
2647 bool is_64bit
= (instr
->src
[0].is_ssa
?
2648 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2649 fs_reg indirect_offset
= get_indirect_offset(instr
);
2650 unsigned imm_offset
= instr
->const_index
[0];
2651 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2652 unsigned mask
= instr
->const_index
[1];
2653 unsigned header_regs
= 0;
2655 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2657 if (indirect_offset
.file
!= BAD_FILE
) {
2658 srcs
[header_regs
++] = indirect_offset
;
2659 } else if (!is_passthrough_shader
) {
2660 if (imm_offset
== 0) {
2661 value
.type
= BRW_REGISTER_TYPE_F
;
2663 mask
&= (1 << tesslevel_inner_components(tcs_key
->tes_primitive_mode
)) - 1;
2665 /* This is a write to gl_TessLevelInner[], which lives in the
2666 * Patch URB header. The layout depends on the domain.
2668 switch (tcs_key
->tes_primitive_mode
) {
2670 /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
2671 * We use an XXYX swizzle to reverse put .xy in the .wz
2672 * channels, and use a .zw writemask.
2674 mask
= writemask_for_backwards_vector(mask
);
2675 swiz
= BRW_SWIZZLE4(0, 0, 1, 0);
2678 /* gl_TessLevelInner[].x lives at DWord 4, so we set the
2679 * writemask to X and bump the URB offset by 1.
2684 /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
2687 unreachable("Bogus tessellation domain");
2689 } else if (imm_offset
== 1) {
2690 /* This is a write to gl_TessLevelOuter[] which lives in the
2691 * Patch URB Header at DWords 4-7. However, it's reversed, so
2692 * instead of .xyzw we have .wzyx.
2694 value
.type
= BRW_REGISTER_TYPE_F
;
2696 mask
&= (1 << tesslevel_outer_components(tcs_key
->tes_primitive_mode
)) - 1;
2698 if (tcs_key
->tes_primitive_mode
== GL_ISOLINES
) {
2699 /* Isolines .xy should be stored in .zw, in order. */
2700 swiz
= BRW_SWIZZLE4(0, 0, 0, 1);
2703 /* Other domains are reversed; store .wzyx instead of .xyzw */
2704 swiz
= BRW_SWIZZLE_WZYX
;
2705 mask
= writemask_for_backwards_vector(mask
);
2713 unsigned num_components
= util_last_bit(mask
);
2716 /* We can only pack two 64-bit components in a single message, so send
2717 * 2 messages if we have more components
2719 unsigned num_iterations
= 1;
2720 unsigned iter_components
= num_components
;
2721 unsigned first_component
= nir_intrinsic_component(instr
);
2723 first_component
= first_component
/ 2;
2724 if (instr
->num_components
> 2) {
2726 iter_components
= 2;
2730 /* 64-bit data needs to me shuffled before we can write it to the URB.
2731 * We will use this temporary to shuffle the components in each
2735 fs_reg(VGRF
, alloc
.allocate(2 * iter_components
), value
.type
);
2737 mask
= mask
<< first_component
;
2739 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2740 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2741 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2742 opcode
= indirect_offset
.file
!= BAD_FILE
?
2743 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2744 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2745 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2746 /* Expand the 64-bit mask to 32-bit channels. We only handle
2747 * two channels in each iteration, so we only care about X/Y.
2749 unsigned mask32
= 0;
2750 if (mask
& WRITEMASK_X
)
2751 mask32
|= WRITEMASK_XY
;
2752 if (mask
& WRITEMASK_Y
)
2753 mask32
|= WRITEMASK_ZW
;
2755 /* If the mask does not include any of the channels X or Y there
2756 * is nothing to do in this iteration. Move on to the next couple
2757 * of 64-bit channels.
2765 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2766 opcode
= indirect_offset
.file
!= BAD_FILE
?
2767 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2768 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2770 opcode
= indirect_offset
.file
!= BAD_FILE
?
2771 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2772 SHADER_OPCODE_URB_WRITE_SIMD8
;
2775 for (unsigned i
= 0; i
< iter_components
; i
++) {
2776 if (!(mask
& (1 << (i
+ first_component
))))
2780 srcs
[header_regs
+ i
+ first_component
] =
2781 offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2783 /* We need to shuffle the 64-bit data to match the layout
2784 * expected by our 32-bit URB write messages. We use a temporary
2787 unsigned channel
= BRW_GET_SWZ(swiz
, iter
* 2 + i
);
2788 shuffle_64bit_data_for_32bit_write(bld
,
2789 retype(offset(tmp
, bld
, 2 * i
), BRW_REGISTER_TYPE_F
),
2790 retype(offset(value
, bld
, 2 * channel
), BRW_REGISTER_TYPE_DF
),
2793 /* Now copy the data to the destination */
2794 fs_reg dest
= fs_reg(VGRF
, alloc
.allocate(2), value
.type
);
2795 unsigned idx
= 2 * i
;
2796 bld
.MOV(dest
, offset(tmp
, bld
, idx
));
2797 bld
.MOV(offset(dest
, bld
, 1), offset(tmp
, bld
, idx
+ 1));
2798 srcs
[header_regs
+ idx
+ first_component
* 2] = dest
;
2799 srcs
[header_regs
+ idx
+ 1 + first_component
* 2] =
2800 offset(dest
, bld
, 1);
2805 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2806 (is_64bit
? 2 * first_component
: first_component
);
2808 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2809 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2811 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2812 inst
->offset
= imm_offset
;
2815 /* If this is a 64-bit attribute, select the next two 64-bit channels
2816 * to be handled in the next iteration.
2827 nir_emit_intrinsic(bld
, instr
);
2833 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2834 nir_intrinsic_instr
*instr
)
2836 assert(stage
== MESA_SHADER_TESS_EVAL
);
2837 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2840 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2841 dest
= get_nir_dest(instr
->dest
);
2843 switch (instr
->intrinsic
) {
2844 case nir_intrinsic_load_primitive_id
:
2845 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2847 case nir_intrinsic_load_tess_coord
:
2848 /* gl_TessCoord is part of the payload in g1-3 */
2849 for (unsigned i
= 0; i
< 3; i
++) {
2850 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2854 case nir_intrinsic_load_tess_level_outer
:
2855 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
2856 * appears as a push-model input. So, we can simply use the ATTR file
2857 * rather than issuing URB read messages. The data is stored in the
2858 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
2861 switch (tes_prog_data
->domain
) {
2862 case BRW_TESS_DOMAIN_QUAD
:
2863 for (unsigned i
= 0; i
< 4; i
++)
2864 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2866 case BRW_TESS_DOMAIN_TRI
:
2867 for (unsigned i
= 0; i
< 3; i
++)
2868 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2870 case BRW_TESS_DOMAIN_ISOLINE
:
2871 for (unsigned i
= 0; i
< 2; i
++)
2872 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 6 + i
));
2877 case nir_intrinsic_load_tess_level_inner
:
2878 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
2879 * appears as a push-model input. So, we can simply use the ATTR file
2880 * rather than issuing URB read messages.
2882 switch (tes_prog_data
->domain
) {
2883 case BRW_TESS_DOMAIN_QUAD
:
2884 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
2885 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
2887 case BRW_TESS_DOMAIN_TRI
:
2888 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
2890 case BRW_TESS_DOMAIN_ISOLINE
:
2891 /* ignore - value is undefined */
2896 case nir_intrinsic_load_input
:
2897 case nir_intrinsic_load_per_vertex_input
: {
2898 fs_reg indirect_offset
= get_indirect_offset(instr
);
2899 unsigned imm_offset
= instr
->const_index
[0];
2900 unsigned first_component
= nir_intrinsic_component(instr
);
2902 if (type_sz(dest
.type
) == 8) {
2903 first_component
= first_component
/ 2;
2907 if (indirect_offset
.file
== BAD_FILE
) {
2908 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2909 * which is 16 registers (since each holds 2 vec4 slots).
2911 const unsigned max_push_slots
= 32;
2912 if (imm_offset
< max_push_slots
) {
2913 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2914 for (int i
= 0; i
< instr
->num_components
; i
++) {
2915 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2916 i
+ first_component
;
2917 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2919 tes_prog_data
->base
.urb_read_length
=
2920 MAX2(tes_prog_data
->base
.urb_read_length
,
2921 DIV_ROUND_UP(imm_offset
+ 1, 2));
2923 /* Replicate the patch handle to all enabled channels */
2924 const fs_reg srcs
[] = {
2925 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2927 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2928 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2930 if (first_component
!= 0) {
2931 unsigned read_components
=
2932 instr
->num_components
+ first_component
;
2933 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2934 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2936 inst
->size_written
= read_components
* REG_SIZE
;
2937 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2938 bld
.MOV(offset(dest
, bld
, i
),
2939 offset(tmp
, bld
, i
+ first_component
));
2942 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2944 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2947 inst
->offset
= imm_offset
;
2950 /* Indirect indexing - use per-slot offsets as well. */
2952 /* We can only read two double components with each URB read, so
2953 * we send two read messages in that case, each one loading up to
2954 * two double components.
2956 unsigned num_iterations
= 1;
2957 unsigned num_components
= instr
->num_components
;
2958 fs_reg orig_dest
= dest
;
2959 if (type_sz(dest
.type
) == 8) {
2960 if (instr
->num_components
> 2) {
2964 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2968 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2969 const fs_reg srcs
[] = {
2970 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2973 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2974 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2976 if (first_component
!= 0) {
2977 unsigned read_components
=
2978 num_components
+ first_component
;
2979 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2980 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2982 for (unsigned i
= 0; i
< num_components
; i
++) {
2983 bld
.MOV(offset(dest
, bld
, i
),
2984 offset(tmp
, bld
, i
+ first_component
));
2987 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2991 inst
->offset
= imm_offset
;
2992 inst
->size_written
= (num_components
+ first_component
) *
2993 inst
->dst
.component_size(inst
->exec_size
);
2995 /* If we are reading 64-bit data using 32-bit read messages we need
2996 * build proper 64-bit data elements by shuffling the low and high
2997 * 32-bit components around like we do for other things like UBOs
3000 if (type_sz(dest
.type
) == 8) {
3001 shuffle_32bit_load_result_to_64bit_data(
3002 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
3004 for (unsigned c
= 0; c
< num_components
; c
++) {
3005 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
3006 offset(dest
, bld
, c
));
3010 /* If we are loading double data and we need a second read message
3013 if (num_iterations
> 1) {
3014 num_components
= instr
->num_components
- 2;
3022 nir_emit_intrinsic(bld
, instr
);
3028 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3029 nir_intrinsic_instr
*instr
)
3031 assert(stage
== MESA_SHADER_GEOMETRY
);
3032 fs_reg indirect_offset
;
3035 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3036 dest
= get_nir_dest(instr
->dest
);
3038 switch (instr
->intrinsic
) {
3039 case nir_intrinsic_load_primitive_id
:
3040 assert(stage
== MESA_SHADER_GEOMETRY
);
3041 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3042 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3043 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3046 case nir_intrinsic_load_input
:
3047 unreachable("load_input intrinsics are invalid for the GS stage");
3049 case nir_intrinsic_load_per_vertex_input
:
3050 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3051 instr
->src
[1], instr
->num_components
,
3052 nir_intrinsic_component(instr
));
3055 case nir_intrinsic_emit_vertex_with_counter
:
3056 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3059 case nir_intrinsic_end_primitive_with_counter
:
3060 emit_gs_end_primitive(instr
->src
[0]);
3063 case nir_intrinsic_set_vertex_count
:
3064 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3067 case nir_intrinsic_load_invocation_id
: {
3068 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3069 assert(val
.file
!= BAD_FILE
);
3070 dest
.type
= val
.type
;
3076 nir_emit_intrinsic(bld
, instr
);
3082 * Fetch the current render target layer index.
3085 fetch_render_target_array_index(const fs_builder
&bld
)
3087 if (bld
.shader
->devinfo
->gen
>= 6) {
3088 /* The render target array index is provided in the thread payload as
3089 * bits 26:16 of r0.0.
3091 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3092 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3096 /* Pre-SNB we only ever render into the first layer of the framebuffer
3097 * since layered rendering is not implemented.
3099 return brw_imm_ud(0);
3104 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3105 * framebuffer at the current fragment coordinates and sample index.
3108 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3111 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3113 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3114 const brw_wm_prog_key
*wm_key
=
3115 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3116 assert(!wm_key
->coherent_fb_fetch
);
3117 const struct brw_wm_prog_data
*wm_prog_data
=
3118 brw_wm_prog_data(stage_prog_data
);
3120 /* Calculate the surface index relative to the start of the texture binding
3121 * table block, since that's what the texturing messages expect.
3123 const unsigned surface
= target
+
3124 wm_prog_data
->binding_table
.render_target_read_start
-
3125 wm_prog_data
->base
.binding_table
.texture_start
;
3127 brw_mark_surface_used(
3128 bld
.shader
->stage_prog_data
,
3129 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
3131 /* Calculate the fragment coordinates. */
3132 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3133 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3134 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3135 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3137 /* Calculate the sample index and MCS payload when multisampling. Luckily
3138 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3139 * shouldn't be necessary to recompile based on whether the framebuffer is
3142 if (wm_key
->multisample_fbo
&&
3143 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3144 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3146 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3147 const fs_reg mcs
= wm_key
->multisample_fbo
?
3148 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3150 /* Use either a normal or a CMS texel fetch message depending on whether
3151 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3152 * message just in case the framebuffer uses 16x multisampling, it should
3153 * be equivalent to the normal CMS fetch for lower multisampling modes.
3155 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3156 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3157 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3159 /* Emit the instruction. */
3160 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3162 brw_imm_ud(surface
), brw_imm_ud(0),
3163 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3164 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3166 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3167 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3173 * Actual coherent framebuffer read implemented using the native render target
3174 * read message. Requires SKL+.
3177 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3179 assert(bld
.shader
->devinfo
->gen
>= 9);
3180 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3181 inst
->target
= target
;
3182 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3188 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3190 if (n
&& regs
[0].file
!= BAD_FILE
) {
3194 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3196 for (unsigned i
= 0; i
< n
; i
++)
3204 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3206 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3207 const brw_wm_prog_key
*const key
=
3208 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3209 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3210 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3212 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3213 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3215 else if (l
== FRAG_RESULT_COLOR
)
3216 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3217 MAX2(key
->nr_color_regions
, 1));
3219 else if (l
== FRAG_RESULT_DEPTH
)
3220 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3222 else if (l
== FRAG_RESULT_STENCIL
)
3223 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3225 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3226 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3228 else if (l
>= FRAG_RESULT_DATA0
&&
3229 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3230 return alloc_temporary(v
->bld
, 4,
3231 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3234 unreachable("Invalid location");
3238 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3239 nir_intrinsic_instr
*instr
)
3241 assert(stage
== MESA_SHADER_FRAGMENT
);
3244 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3245 dest
= get_nir_dest(instr
->dest
);
3247 switch (instr
->intrinsic
) {
3248 case nir_intrinsic_load_front_face
:
3249 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3250 *emit_frontfacing_interpolation());
3253 case nir_intrinsic_load_sample_pos
: {
3254 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3255 assert(sample_pos
.file
!= BAD_FILE
);
3256 dest
.type
= sample_pos
.type
;
3257 bld
.MOV(dest
, sample_pos
);
3258 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3262 case nir_intrinsic_load_layer_id
:
3263 dest
.type
= BRW_REGISTER_TYPE_UD
;
3264 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3267 case nir_intrinsic_load_helper_invocation
:
3268 case nir_intrinsic_load_sample_mask_in
:
3269 case nir_intrinsic_load_sample_id
: {
3270 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3271 fs_reg val
= nir_system_values
[sv
];
3272 assert(val
.file
!= BAD_FILE
);
3273 dest
.type
= val
.type
;
3278 case nir_intrinsic_store_output
: {
3279 const fs_reg src
= get_nir_src(instr
->src
[0]);
3280 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3281 assert(const_offset
&& "Indirect output stores not allowed");
3282 const unsigned location
= nir_intrinsic_base(instr
) +
3283 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3284 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3287 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3288 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3289 offset(src
, bld
, j
));
3294 case nir_intrinsic_load_output
: {
3295 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3296 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3297 assert(l
>= FRAG_RESULT_DATA0
);
3298 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3299 assert(const_offset
&& "Indirect output loads not allowed");
3300 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3301 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3303 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3304 emit_coherent_fb_read(bld
, tmp
, target
);
3306 emit_non_coherent_fb_read(bld
, tmp
, target
);
3308 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3309 bld
.MOV(offset(dest
, bld
, j
),
3310 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3316 case nir_intrinsic_discard
:
3317 case nir_intrinsic_discard_if
: {
3318 /* We track our discarded pixels in f0.1. By predicating on it, we can
3319 * update just the flag bits that aren't yet discarded. If there's no
3320 * condition, we emit a CMP of g0 != g0, so all currently executing
3321 * channels will get turned off.
3324 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3325 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3326 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3328 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3329 BRW_REGISTER_TYPE_UW
));
3330 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3332 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3333 cmp
->flag_subreg
= 1;
3335 if (devinfo
->gen
>= 6) {
3336 emit_discard_jump();
3341 case nir_intrinsic_load_input
: {
3342 /* load_input is only used for flat inputs */
3343 unsigned base
= nir_intrinsic_base(instr
);
3344 unsigned component
= nir_intrinsic_component(instr
);
3345 unsigned num_components
= instr
->num_components
;
3346 enum brw_reg_type type
= dest
.type
;
3348 /* Special case fields in the VUE header */
3349 if (base
== VARYING_SLOT_LAYER
)
3351 else if (base
== VARYING_SLOT_VIEWPORT
)
3354 if (nir_dest_bit_size(instr
->dest
) == 64) {
3355 /* const_index is in 32-bit type size units that could not be aligned
3356 * with DF. We need to read the double vector as if it was a float
3357 * vector of twice the number of components to fetch the right data.
3359 type
= BRW_REGISTER_TYPE_F
;
3360 num_components
*= 2;
3363 for (unsigned int i
= 0; i
< num_components
; i
++) {
3364 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3365 interp
= suboffset(interp
, 3);
3366 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3367 retype(fs_reg(interp
), type
));
3370 if (nir_dest_bit_size(instr
->dest
) == 64) {
3371 shuffle_32bit_load_result_to_64bit_data(bld
,
3374 instr
->num_components
);
3379 case nir_intrinsic_load_barycentric_pixel
:
3380 case nir_intrinsic_load_barycentric_centroid
:
3381 case nir_intrinsic_load_barycentric_sample
:
3382 /* Do nothing - load_interpolated_input handling will handle it later. */
3385 case nir_intrinsic_load_barycentric_at_sample
: {
3386 const glsl_interp_mode interpolation
=
3387 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3389 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3392 unsigned msg_data
= const_sample
->i32
[0] << 4;
3394 emit_pixel_interpolater_send(bld
,
3395 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3398 brw_imm_ud(msg_data
),
3401 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3402 BRW_REGISTER_TYPE_UD
);
3404 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3405 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3406 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3407 bld
.exec_all().group(1, 0)
3408 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3409 emit_pixel_interpolater_send(bld
,
3410 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3416 /* Make a loop that sends a message to the pixel interpolater
3417 * for the sample number in each live channel. If there are
3418 * multiple channels with the same sample number then these
3419 * will be handled simultaneously with a single interation of
3422 bld
.emit(BRW_OPCODE_DO
);
3424 /* Get the next live sample number into sample_id_reg */
3425 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3427 /* Set the flag register so that we can perform the send
3428 * message on all channels that have the same sample number
3430 bld
.CMP(bld
.null_reg_ud(),
3431 sample_src
, sample_id
,
3432 BRW_CONDITIONAL_EQ
);
3433 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3434 bld
.exec_all().group(1, 0)
3435 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3437 emit_pixel_interpolater_send(bld
,
3438 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3443 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3445 /* Continue the loop if there are any live channels left */
3446 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3448 bld
.emit(BRW_OPCODE_WHILE
));
3454 case nir_intrinsic_load_barycentric_at_offset
: {
3455 const glsl_interp_mode interpolation
=
3456 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3458 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3461 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3462 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3464 emit_pixel_interpolater_send(bld
,
3465 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3468 brw_imm_ud(off_x
| (off_y
<< 4)),
3471 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3472 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3473 BRW_REGISTER_TYPE_F
);
3474 for (int i
= 0; i
< 2; i
++) {
3475 fs_reg temp
= vgrf(glsl_type::float_type
);
3476 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3477 fs_reg itemp
= vgrf(glsl_type::int_type
);
3479 bld
.MOV(itemp
, temp
);
3481 /* Clamp the upper end of the range to +7/16.
3482 * ARB_gpu_shader5 requires that we support a maximum offset
3483 * of +0.5, which isn't representable in a S0.4 value -- if
3484 * we didn't clamp it, we'd end up with -8/16, which is the
3485 * opposite of what the shader author wanted.
3487 * This is legal due to ARB_gpu_shader5's quantization
3490 * "Not all values of <offset> may be supported; x and y
3491 * offsets may be rounded to fixed-point values with the
3492 * number of fraction bits given by the
3493 * implementation-dependent constant
3494 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3496 set_condmod(BRW_CONDITIONAL_L
,
3497 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3500 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3501 emit_pixel_interpolater_send(bld
,
3511 case nir_intrinsic_load_interpolated_input
: {
3512 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3513 emit_fragcoord_interpolation(dest
);
3517 assert(instr
->src
[0].ssa
&&
3518 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3519 nir_intrinsic_instr
*bary_intrinsic
=
3520 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3521 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3522 enum glsl_interp_mode interp_mode
=
3523 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3526 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3527 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3528 /* Use the result of the PI message */
3529 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3531 /* Use the delta_xy values computed from the payload */
3532 enum brw_barycentric_mode bary
=
3533 brw_barycentric_mode(interp_mode
, bary_intrin
);
3535 dst_xy
= this->delta_xy
[bary
];
3538 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3540 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3541 nir_intrinsic_component(instr
) + i
));
3542 interp
.type
= BRW_REGISTER_TYPE_F
;
3543 dest
.type
= BRW_REGISTER_TYPE_F
;
3545 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3546 fs_reg tmp
= vgrf(glsl_type::float_type
);
3547 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3548 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3550 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3557 nir_emit_intrinsic(bld
, instr
);
3563 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3564 nir_intrinsic_instr
*instr
)
3566 assert(stage
== MESA_SHADER_COMPUTE
);
3567 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3570 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3571 dest
= get_nir_dest(instr
->dest
);
3573 switch (instr
->intrinsic
) {
3574 case nir_intrinsic_barrier
:
3576 cs_prog_data
->uses_barrier
= true;
3579 case nir_intrinsic_load_local_invocation_id
:
3580 case nir_intrinsic_load_work_group_id
: {
3581 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3582 fs_reg val
= nir_system_values
[sv
];
3583 assert(val
.file
!= BAD_FILE
);
3584 dest
.type
= val
.type
;
3585 for (unsigned i
= 0; i
< 3; i
++)
3586 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3590 case nir_intrinsic_load_num_work_groups
: {
3591 const unsigned surface
=
3592 cs_prog_data
->binding_table
.work_groups_start
;
3594 cs_prog_data
->uses_num_work_groups
= true;
3596 fs_reg surf_index
= brw_imm_ud(surface
);
3597 brw_mark_surface_used(prog_data
, surface
);
3599 /* Read the 3 GLuint components of gl_NumWorkGroups */
3600 for (unsigned i
= 0; i
< 3; i
++) {
3601 fs_reg read_result
=
3602 emit_untyped_read(bld
, surf_index
,
3604 1 /* dims */, 1 /* size */,
3605 BRW_PREDICATE_NONE
);
3606 read_result
.type
= dest
.type
;
3607 bld
.MOV(dest
, read_result
);
3608 dest
= offset(dest
, bld
, 1);
3613 case nir_intrinsic_shared_atomic_add
:
3614 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3616 case nir_intrinsic_shared_atomic_imin
:
3617 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3619 case nir_intrinsic_shared_atomic_umin
:
3620 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3622 case nir_intrinsic_shared_atomic_imax
:
3623 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3625 case nir_intrinsic_shared_atomic_umax
:
3626 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3628 case nir_intrinsic_shared_atomic_and
:
3629 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3631 case nir_intrinsic_shared_atomic_or
:
3632 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3634 case nir_intrinsic_shared_atomic_xor
:
3635 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3637 case nir_intrinsic_shared_atomic_exchange
:
3638 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3640 case nir_intrinsic_shared_atomic_comp_swap
:
3641 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3644 case nir_intrinsic_load_shared
: {
3645 assert(devinfo
->gen
>= 7);
3647 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3649 /* Get the offset to read from */
3651 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3653 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3655 offset_reg
= vgrf(glsl_type::uint_type
);
3657 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3658 brw_imm_ud(instr
->const_index
[0]));
3661 /* Read the vector */
3662 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3663 instr
->num_components
);
3667 case nir_intrinsic_store_shared
: {
3668 assert(devinfo
->gen
>= 7);
3671 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3674 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3677 unsigned writemask
= instr
->const_index
[1];
3679 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3680 * since the untyped writes below operate in units of 32-bits, which
3681 * means that we need to write twice as many components each time.
3682 * Also, we have to suffle 64-bit data to be in the appropriate layout
3683 * expected by our 32-bit write messages.
3685 unsigned type_size
= 4;
3686 unsigned bit_size
= instr
->src
[0].is_ssa
?
3687 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3688 if (bit_size
== 64) {
3691 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3692 shuffle_64bit_data_for_32bit_write(
3694 retype(tmp
, BRW_REGISTER_TYPE_F
),
3695 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3696 instr
->num_components
);
3700 unsigned type_slots
= type_size
/ 4;
3702 /* Combine groups of consecutive enabled channels in one write
3703 * message. We use ffs to find the first enabled channel and then ffs on
3704 * the bit-inverse, down-shifted writemask to determine the length of
3705 * the block of enabled bits.
3708 unsigned first_component
= ffs(writemask
) - 1;
3709 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3711 /* We can't write more than 2 64-bit components at once. Limit the
3712 * length of the write to what we can do and let the next iteration
3716 length
= MIN2(2, length
);
3719 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3721 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3722 type_size
* first_component
);
3724 offset_reg
= vgrf(glsl_type::uint_type
);
3726 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3727 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3730 emit_untyped_write(bld
, surf_index
, offset_reg
,
3731 offset(val_reg
, bld
, first_component
* type_slots
),
3732 1 /* dims */, length
* type_slots
,
3733 BRW_PREDICATE_NONE
);
3735 /* Clear the bits in the writemask that we just wrote, then try
3736 * again to see if more channels are left.
3738 writemask
&= (15 << (first_component
+ length
));
3745 nir_emit_intrinsic(bld
, instr
);
3751 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3754 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3755 dest
= get_nir_dest(instr
->dest
);
3757 switch (instr
->intrinsic
) {
3758 case nir_intrinsic_atomic_counter_inc
:
3759 case nir_intrinsic_atomic_counter_dec
:
3760 case nir_intrinsic_atomic_counter_read
:
3761 case nir_intrinsic_atomic_counter_add
:
3762 case nir_intrinsic_atomic_counter_min
:
3763 case nir_intrinsic_atomic_counter_max
:
3764 case nir_intrinsic_atomic_counter_and
:
3765 case nir_intrinsic_atomic_counter_or
:
3766 case nir_intrinsic_atomic_counter_xor
:
3767 case nir_intrinsic_atomic_counter_exchange
:
3768 case nir_intrinsic_atomic_counter_comp_swap
: {
3769 if (stage
== MESA_SHADER_FRAGMENT
&&
3770 instr
->intrinsic
!= nir_intrinsic_atomic_counter_read
)
3771 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3773 /* Get some metadata from the image intrinsic. */
3774 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3776 /* Get the arguments of the atomic intrinsic. */
3777 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3778 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3779 instr
->const_index
[0]);
3780 const fs_reg src0
= (info
->num_srcs
>= 2
3781 ? get_nir_src(instr
->src
[1]) : fs_reg());
3782 const fs_reg src1
= (info
->num_srcs
>= 3
3783 ? get_nir_src(instr
->src
[2]) : fs_reg());
3786 assert(info
->num_srcs
<= 3);
3788 /* Emit a surface read or atomic op. */
3789 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
3790 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3792 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, src0
,
3794 get_atomic_counter_op(instr
->intrinsic
));
3797 /* Assign the result. */
3798 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3800 /* Mark the surface as used. */
3801 brw_mark_surface_used(stage_prog_data
, surface
);
3805 case nir_intrinsic_image_load
:
3806 case nir_intrinsic_image_store
:
3807 case nir_intrinsic_image_atomic_add
:
3808 case nir_intrinsic_image_atomic_min
:
3809 case nir_intrinsic_image_atomic_max
:
3810 case nir_intrinsic_image_atomic_and
:
3811 case nir_intrinsic_image_atomic_or
:
3812 case nir_intrinsic_image_atomic_xor
:
3813 case nir_intrinsic_image_atomic_exchange
:
3814 case nir_intrinsic_image_atomic_comp_swap
: {
3815 using namespace image_access
;
3817 if (stage
== MESA_SHADER_FRAGMENT
&&
3818 instr
->intrinsic
!= nir_intrinsic_image_load
)
3819 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3821 /* Get the referenced image variable and type. */
3822 const nir_variable
*var
= instr
->variables
[0]->var
;
3823 const glsl_type
*type
= var
->type
->without_array();
3824 const brw_reg_type base_type
= get_image_base_type(type
);
3826 /* Get some metadata from the image intrinsic. */
3827 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3828 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3829 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3830 const unsigned format
= var
->data
.image
.format
;
3832 /* Get the arguments of the image intrinsic. */
3833 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3834 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3835 BRW_REGISTER_TYPE_UD
);
3836 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3837 retype(get_nir_src(instr
->src
[2]), base_type
) :
3839 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3840 retype(get_nir_src(instr
->src
[3]), base_type
) :
3844 /* Emit an image load, store or atomic op. */
3845 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3846 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3848 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3849 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3850 var
->data
.image
.write_only
? GL_NONE
: format
);
3853 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3854 surf_dims
, arr_dims
, info
->dest_components
,
3855 get_image_atomic_op(instr
->intrinsic
, type
));
3857 /* Assign the result. */
3858 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3859 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3860 offset(tmp
, bld
, c
));
3864 case nir_intrinsic_memory_barrier_atomic_counter
:
3865 case nir_intrinsic_memory_barrier_buffer
:
3866 case nir_intrinsic_memory_barrier_image
:
3867 case nir_intrinsic_memory_barrier
: {
3868 const fs_builder ubld
= bld
.group(8, 0);
3869 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3870 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3871 ->size_written
= 2 * REG_SIZE
;
3875 case nir_intrinsic_group_memory_barrier
:
3876 case nir_intrinsic_memory_barrier_shared
:
3877 /* We treat these workgroup-level barriers as no-ops. This should be
3878 * safe at present and as long as:
3880 * - Memory access instructions are not subsequently reordered by the
3881 * compiler back-end.
3883 * - All threads from a given compute shader workgroup fit within a
3884 * single subslice and therefore talk to the same HDC shared unit
3885 * what supposedly guarantees ordering and coherency between threads
3886 * from the same workgroup. This may change in the future when we
3887 * start splitting workgroups across multiple subslices.
3889 * - The context is not in fault-and-stream mode, which could cause
3890 * memory transactions (including to SLM) prior to the barrier to be
3891 * replayed after the barrier if a pagefault occurs. This shouldn't
3892 * be a problem up to and including SKL because fault-and-stream is
3893 * not usable due to hardware issues, but that's likely to change in
3898 case nir_intrinsic_shader_clock
: {
3899 /* We cannot do anything if there is an event, so ignore it for now */
3900 const fs_reg shader_clock
= get_timestamp(bld
);
3901 const fs_reg srcs
[] = { component(shader_clock
, 0),
3902 component(shader_clock
, 1) };
3903 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3907 case nir_intrinsic_image_size
: {
3908 /* Get the referenced image variable and type. */
3909 const nir_variable
*var
= instr
->variables
[0]->var
;
3910 const glsl_type
*type
= var
->type
->without_array();
3912 /* Get the size of the image. */
3913 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3914 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3916 /* For 1DArray image types, the array index is stored in the Z component.
3917 * Fix this by swizzling the Z component to the Y component.
3919 const bool is_1d_array_image
=
3920 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3921 type
->sampler_array
;
3923 /* For CubeArray images, we should count the number of cubes instead
3924 * of the number of faces. Fix it by dividing the (Z component) by 6.
3926 const bool is_cube_array_image
=
3927 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3928 type
->sampler_array
;
3930 /* Copy all the components. */
3931 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3932 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
3933 if ((int)c
>= type
->coordinate_components()) {
3934 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3936 } else if (c
== 1 && is_1d_array_image
) {
3937 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3938 offset(size
, bld
, 2));
3939 } else if (c
== 2 && is_cube_array_image
) {
3940 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3941 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3942 offset(size
, bld
, c
), brw_imm_d(6));
3944 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3945 offset(size
, bld
, c
));
3952 case nir_intrinsic_image_samples
:
3953 /* The driver does not support multi-sampled images. */
3954 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3957 case nir_intrinsic_load_uniform
: {
3958 /* Offsets are in bytes but they should always be multiples of 4 */
3959 assert(instr
->const_index
[0] % 4 == 0);
3961 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3963 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3965 /* Offsets are in bytes but they should always be multiples of 4 */
3966 assert(const_offset
->u32
[0] % 4 == 0);
3967 src
.offset
= const_offset
->u32
[0];
3969 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3970 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3973 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3974 BRW_REGISTER_TYPE_UD
);
3976 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3977 * go past the end of the uniform. In order to keep the n'th
3978 * component from running past, we subtract off the size of all but
3979 * one component of the vector.
3981 assert(instr
->const_index
[1] >=
3982 instr
->num_components
* (int) type_sz(dest
.type
));
3983 unsigned read_size
= instr
->const_index
[1] -
3984 (instr
->num_components
- 1) * type_sz(dest
.type
);
3986 fs_reg indirect_chv_high_32bit
;
3987 bool is_chv_bxt_64bit
=
3988 (devinfo
->is_cherryview
|| devinfo
->is_broxton
) &&
3989 type_sz(dest
.type
) == 8;
3990 if (is_chv_bxt_64bit
) {
3991 indirect_chv_high_32bit
= vgrf(glsl_type::uint_type
);
3992 /* Calculate indirect address to read high 32 bits */
3993 bld
.ADD(indirect_chv_high_32bit
, indirect
, brw_imm_ud(4));
3996 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3997 if (!is_chv_bxt_64bit
) {
3998 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3999 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4000 indirect
, brw_imm_ud(read_size
));
4002 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4003 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, 0),
4004 offset(src
, bld
, j
),
4005 indirect
, brw_imm_ud(read_size
));
4007 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4008 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, 1),
4009 offset(src
, bld
, j
),
4010 indirect_chv_high_32bit
, brw_imm_ud(read_size
));
4017 case nir_intrinsic_load_ubo
: {
4018 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
4022 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4023 const_index
->u32
[0];
4024 surf_index
= brw_imm_ud(index
);
4025 brw_mark_surface_used(prog_data
, index
);
4027 /* The block index is not a constant. Evaluate the index expression
4028 * per-channel and add the base UBO index; we have to select a value
4029 * from any live channel.
4031 surf_index
= vgrf(glsl_type::uint_type
);
4032 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4033 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4034 surf_index
= bld
.emit_uniformize(surf_index
);
4036 /* Assume this may touch any UBO. It would be nice to provide
4037 * a tighter bound, but the array information is already lowered away.
4039 brw_mark_surface_used(prog_data
,
4040 stage_prog_data
->binding_table
.ubo_start
+
4041 nir
->info
->num_ubos
- 1);
4044 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4045 if (const_offset
== NULL
) {
4046 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4047 BRW_REGISTER_TYPE_UD
);
4049 for (int i
= 0; i
< instr
->num_components
; i
++)
4050 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4051 base_offset
, i
* type_sz(dest
.type
));
4053 /* Even if we are loading doubles, a pull constant load will load
4054 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4055 * need to load a full dvec4 we will have to emit 2 loads. This is
4056 * similar to demote_pull_constants(), except that in that case we
4057 * see individual accesses to each component of the vector and then
4058 * we let CSE deal with duplicate loads. Here we see a vector access
4059 * and we have to split it if necessary.
4061 const unsigned type_size
= type_sz(dest
.type
);
4062 const fs_builder ubld
= bld
.exec_all().group(4, 0);
4063 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_F
);
4065 for (unsigned c
= 0; c
< instr
->num_components
;) {
4066 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
4068 /* Number of usable components in the next 16B-aligned load */
4069 const unsigned count
= MIN2(instr
->num_components
- c
,
4070 (16 - base
% 16) / type_size
);
4072 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4073 packed_consts
, surf_index
, brw_imm_ud(base
& ~15));
4075 const fs_reg consts
=
4076 retype(byte_offset(packed_consts
, base
& 15), dest
.type
);
4078 for (unsigned d
= 0; d
< count
; d
++)
4079 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4087 case nir_intrinsic_load_ssbo
: {
4088 assert(devinfo
->gen
>= 7);
4090 nir_const_value
*const_uniform_block
=
4091 nir_src_as_const_value(instr
->src
[0]);
4094 if (const_uniform_block
) {
4095 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4096 const_uniform_block
->u32
[0];
4097 surf_index
= brw_imm_ud(index
);
4098 brw_mark_surface_used(prog_data
, index
);
4100 surf_index
= vgrf(glsl_type::uint_type
);
4101 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4102 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4104 /* Assume this may touch any UBO. It would be nice to provide
4105 * a tighter bound, but the array information is already lowered away.
4107 brw_mark_surface_used(prog_data
,
4108 stage_prog_data
->binding_table
.ssbo_start
+
4109 nir
->info
->num_ssbos
- 1);
4113 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4115 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
4117 offset_reg
= get_nir_src(instr
->src
[1]);
4120 /* Read the vector */
4121 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4122 instr
->num_components
);
4127 case nir_intrinsic_store_ssbo
: {
4128 assert(devinfo
->gen
>= 7);
4130 if (stage
== MESA_SHADER_FRAGMENT
)
4131 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4135 nir_const_value
*const_uniform_block
=
4136 nir_src_as_const_value(instr
->src
[1]);
4137 if (const_uniform_block
) {
4138 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4139 const_uniform_block
->u32
[0];
4140 surf_index
= brw_imm_ud(index
);
4141 brw_mark_surface_used(prog_data
, index
);
4143 surf_index
= vgrf(glsl_type::uint_type
);
4144 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4145 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4147 brw_mark_surface_used(prog_data
,
4148 stage_prog_data
->binding_table
.ssbo_start
+
4149 nir
->info
->num_ssbos
- 1);
4153 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4156 unsigned writemask
= instr
->const_index
[0];
4158 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4159 * since the untyped writes below operate in units of 32-bits, which
4160 * means that we need to write twice as many components each time.
4161 * Also, we have to suffle 64-bit data to be in the appropriate layout
4162 * expected by our 32-bit write messages.
4164 unsigned type_size
= 4;
4165 unsigned bit_size
= instr
->src
[0].is_ssa
?
4166 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
4167 if (bit_size
== 64) {
4170 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
4171 shuffle_64bit_data_for_32bit_write(bld
,
4172 retype(tmp
, BRW_REGISTER_TYPE_F
),
4173 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
4174 instr
->num_components
);
4178 unsigned type_slots
= type_size
/ 4;
4180 /* Combine groups of consecutive enabled channels in one write
4181 * message. We use ffs to find the first enabled channel and then ffs on
4182 * the bit-inverse, down-shifted writemask to determine the length of
4183 * the block of enabled bits.
4186 unsigned first_component
= ffs(writemask
) - 1;
4187 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
4189 /* We can't write more than 2 64-bit components at once. Limit the
4190 * length of the write to what we can do and let the next iteration
4194 length
= MIN2(2, length
);
4197 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4199 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4200 type_size
* first_component
);
4202 offset_reg
= vgrf(glsl_type::uint_type
);
4204 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4205 brw_imm_ud(type_size
* first_component
));
4209 emit_untyped_write(bld
, surf_index
, offset_reg
,
4210 offset(val_reg
, bld
, first_component
* type_slots
),
4211 1 /* dims */, length
* type_slots
,
4212 BRW_PREDICATE_NONE
);
4214 /* Clear the bits in the writemask that we just wrote, then try
4215 * again to see if more channels are left.
4217 writemask
&= (15 << (first_component
+ length
));
4222 case nir_intrinsic_store_output
: {
4223 fs_reg src
= get_nir_src(instr
->src
[0]);
4225 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4226 assert(const_offset
&& "Indirect output stores not allowed");
4227 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4228 4 * const_offset
->u32
[0]), src
.type
);
4230 unsigned num_components
= instr
->num_components
;
4231 unsigned first_component
= nir_intrinsic_component(instr
);
4232 unsigned bit_size
= instr
->src
[0].is_ssa
?
4233 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
4234 if (bit_size
== 64) {
4236 fs_reg(VGRF
, alloc
.allocate(2 * num_components
),
4237 BRW_REGISTER_TYPE_F
);
4238 shuffle_64bit_data_for_32bit_write(
4239 bld
, tmp
, retype(src
, BRW_REGISTER_TYPE_DF
), num_components
);
4240 src
= retype(tmp
, src
.type
);
4241 num_components
*= 2;
4244 for (unsigned j
= 0; j
< num_components
; j
++) {
4245 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4246 offset(src
, bld
, j
));
4251 case nir_intrinsic_ssbo_atomic_add
:
4252 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4254 case nir_intrinsic_ssbo_atomic_imin
:
4255 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4257 case nir_intrinsic_ssbo_atomic_umin
:
4258 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4260 case nir_intrinsic_ssbo_atomic_imax
:
4261 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4263 case nir_intrinsic_ssbo_atomic_umax
:
4264 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4266 case nir_intrinsic_ssbo_atomic_and
:
4267 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4269 case nir_intrinsic_ssbo_atomic_or
:
4270 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4272 case nir_intrinsic_ssbo_atomic_xor
:
4273 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4275 case nir_intrinsic_ssbo_atomic_exchange
:
4276 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4278 case nir_intrinsic_ssbo_atomic_comp_swap
:
4279 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4282 case nir_intrinsic_get_buffer_size
: {
4283 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4284 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4286 /* A resinfo's sampler message is used to get the buffer size. The
4287 * SIMD8's writeback message consists of four registers and SIMD16's
4288 * writeback message consists of 8 destination registers (two per each
4289 * component). Because we are only interested on the first channel of
4290 * the first returned component, where resinfo returns the buffer size
4291 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4292 * the dispatch width.
4294 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4295 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4296 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4299 ubld
.MOV(src_payload
, brw_imm_d(0));
4301 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4302 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4303 src_payload
, brw_imm_ud(index
));
4304 inst
->header_size
= 0;
4306 inst
->size_written
= 4 * REG_SIZE
;
4308 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4309 brw_mark_surface_used(prog_data
, index
);
4313 case nir_intrinsic_load_channel_num
: {
4314 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
4315 dest
= retype(dest
, BRW_REGISTER_TYPE_UD
);
4316 const fs_builder allbld8
= bld
.group(8, 0).exec_all();
4317 allbld8
.MOV(tmp
, brw_imm_v(0x76543210));
4318 if (dispatch_width
> 8)
4319 allbld8
.ADD(byte_offset(tmp
, 16), tmp
, brw_imm_uw(8u));
4320 if (dispatch_width
> 16) {
4321 const fs_builder allbld16
= bld
.group(16, 0).exec_all();
4322 allbld16
.ADD(byte_offset(tmp
, 32), tmp
, brw_imm_uw(16u));
4329 unreachable("unknown intrinsic");
4334 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4335 int op
, nir_intrinsic_instr
*instr
)
4337 if (stage
== MESA_SHADER_FRAGMENT
)
4338 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4341 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4342 dest
= get_nir_dest(instr
->dest
);
4345 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4346 if (const_surface
) {
4347 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4348 const_surface
->u32
[0];
4349 surface
= brw_imm_ud(surf_index
);
4350 brw_mark_surface_used(prog_data
, surf_index
);
4352 surface
= vgrf(glsl_type::uint_type
);
4353 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4354 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4356 /* Assume this may touch any SSBO. This is the same we do for other
4357 * UBO/SSBO accesses with non-constant surface.
4359 brw_mark_surface_used(prog_data
,
4360 stage_prog_data
->binding_table
.ssbo_start
+
4361 nir
->info
->num_ssbos
- 1);
4364 fs_reg offset
= get_nir_src(instr
->src
[1]);
4365 fs_reg data1
= get_nir_src(instr
->src
[2]);
4367 if (op
== BRW_AOP_CMPWR
)
4368 data2
= get_nir_src(instr
->src
[3]);
4370 /* Emit the actual atomic operation */
4372 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4374 1 /* dims */, 1 /* rsize */,
4376 BRW_PREDICATE_NONE
);
4377 dest
.type
= atomic_result
.type
;
4378 bld
.MOV(dest
, atomic_result
);
4382 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4383 int op
, nir_intrinsic_instr
*instr
)
4386 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4387 dest
= get_nir_dest(instr
->dest
);
4389 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4391 fs_reg data1
= get_nir_src(instr
->src
[1]);
4393 if (op
== BRW_AOP_CMPWR
)
4394 data2
= get_nir_src(instr
->src
[2]);
4396 /* Get the offset */
4397 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4399 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4401 offset
= vgrf(glsl_type::uint_type
);
4403 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4404 brw_imm_ud(instr
->const_index
[0]));
4407 /* Emit the actual atomic operation operation */
4409 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4411 1 /* dims */, 1 /* rsize */,
4413 BRW_PREDICATE_NONE
);
4414 dest
.type
= atomic_result
.type
;
4415 bld
.MOV(dest
, atomic_result
);
4419 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4421 unsigned texture
= instr
->texture_index
;
4422 unsigned sampler
= instr
->sampler_index
;
4424 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4426 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4427 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4429 int lod_components
= 0;
4431 /* The hardware requires a LOD for buffer textures */
4432 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4433 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4435 uint32_t header_bits
= 0;
4436 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4437 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4438 switch (instr
->src
[i
].src_type
) {
4439 case nir_tex_src_bias
:
4440 srcs
[TEX_LOGICAL_SRC_LOD
] =
4441 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4443 case nir_tex_src_comparator
:
4444 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4446 case nir_tex_src_coord
:
4447 switch (instr
->op
) {
4449 case nir_texop_txf_ms
:
4450 case nir_texop_txf_ms_mcs
:
4451 case nir_texop_samples_identical
:
4452 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4455 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4459 case nir_tex_src_ddx
:
4460 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4461 lod_components
= nir_tex_instr_src_size(instr
, i
);
4463 case nir_tex_src_ddy
:
4464 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4466 case nir_tex_src_lod
:
4467 switch (instr
->op
) {
4469 srcs
[TEX_LOGICAL_SRC_LOD
] =
4470 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4473 srcs
[TEX_LOGICAL_SRC_LOD
] =
4474 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4477 srcs
[TEX_LOGICAL_SRC_LOD
] =
4478 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4482 case nir_tex_src_ms_index
:
4483 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4486 case nir_tex_src_offset
: {
4487 nir_const_value
*const_offset
=
4488 nir_src_as_const_value(instr
->src
[i
].src
);
4489 unsigned offset_bits
= 0;
4491 brw_texture_offset(const_offset
->i32
,
4492 nir_tex_instr_src_size(instr
, i
),
4494 header_bits
|= offset_bits
;
4496 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4497 retype(src
, BRW_REGISTER_TYPE_D
);
4502 case nir_tex_src_projector
:
4503 unreachable("should be lowered");
4505 case nir_tex_src_texture_offset
: {
4506 /* Figure out the highest possible texture index and mark it as used */
4507 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4508 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4509 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4511 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4513 brw_mark_surface_used(prog_data
, max_used
);
4515 /* Emit code to evaluate the actual indexing expression */
4516 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4517 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4518 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4522 case nir_tex_src_sampler_offset
: {
4523 /* Emit code to evaluate the actual indexing expression */
4524 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4525 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4526 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4530 case nir_tex_src_ms_mcs
:
4531 assert(instr
->op
== nir_texop_txf_ms
);
4532 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4535 case nir_tex_src_plane
: {
4536 nir_const_value
*const_plane
=
4537 nir_src_as_const_value(instr
->src
[i
].src
);
4538 const uint32_t plane
= const_plane
->u32
[0];
4539 const uint32_t texture_index
=
4540 instr
->texture_index
+
4541 stage_prog_data
->binding_table
.plane_start
[plane
] -
4542 stage_prog_data
->binding_table
.texture_start
;
4544 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4549 unreachable("unknown texture source");
4553 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4554 (instr
->op
== nir_texop_txf_ms
||
4555 instr
->op
== nir_texop_samples_identical
)) {
4556 if (devinfo
->gen
>= 7 &&
4557 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4558 srcs
[TEX_LOGICAL_SRC_MCS
] =
4559 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4560 instr
->coord_components
,
4561 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4563 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4567 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4568 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4570 if (instr
->op
== nir_texop_query_levels
||
4571 (instr
->op
== nir_texop_tex
&& stage
!= MESA_SHADER_FRAGMENT
)) {
4572 /* textureQueryLevels() and texture() are implemented in terms of TXS
4573 * and TXL respectively, so we need to pass a valid LOD argument.
4575 assert(srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
);
4576 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
4580 switch (instr
->op
) {
4582 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4583 SHADER_OPCODE_TXL_LOGICAL
);
4586 opcode
= FS_OPCODE_TXB_LOGICAL
;
4589 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4592 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4595 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4597 case nir_texop_txf_ms
:
4598 if ((key_tex
->msaa_16
& (1 << sampler
)))
4599 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4601 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4603 case nir_texop_txf_ms_mcs
:
4604 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4606 case nir_texop_query_levels
:
4608 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4611 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4614 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
4615 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4617 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4619 case nir_texop_texture_samples
:
4620 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4622 case nir_texop_samples_identical
: {
4623 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4625 /* If mcs is an immediate value, it means there is no MCS. In that case
4626 * just return false.
4628 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4629 bld
.MOV(dst
, brw_imm_ud(0u));
4630 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4631 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4632 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4633 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4634 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4636 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4637 BRW_CONDITIONAL_EQ
);
4642 unreachable("unknown texture opcode");
4645 if (instr
->op
== nir_texop_tg4
) {
4646 if (instr
->component
== 1 &&
4647 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4648 /* gather4 sampler is broken for green channel on RG32F --
4649 * we must ask for blue instead.
4651 header_bits
|= 2 << 16;
4653 header_bits
|= instr
->component
<< 16;
4657 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(instr
->dest_type
), 4);
4658 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4659 inst
->offset
= header_bits
;
4661 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4662 if (devinfo
->gen
>= 9 &&
4663 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4664 unsigned write_mask
= instr
->dest
.is_ssa
?
4665 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4666 (1 << dest_size
) - 1;
4667 assert(write_mask
!= 0); /* dead code should have been eliminated */
4668 inst
->size_written
= util_last_bit(write_mask
) *
4669 inst
->dst
.component_size(inst
->exec_size
);
4671 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
4674 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4675 inst
->shadow_compare
= true;
4677 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
4678 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4681 for (unsigned i
= 0; i
< dest_size
; i
++)
4682 nir_dest
[i
] = offset(dst
, bld
, i
);
4684 if (instr
->op
== nir_texop_query_levels
) {
4685 /* # levels is in .w */
4686 nir_dest
[0] = offset(dst
, bld
, 3);
4687 } else if (instr
->op
== nir_texop_txs
&&
4688 dest_size
>= 3 && devinfo
->gen
< 7) {
4689 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4690 fs_reg depth
= offset(dst
, bld
, 2);
4691 nir_dest
[2] = vgrf(glsl_type::int_type
);
4692 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4695 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4699 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4701 switch (instr
->type
) {
4702 case nir_jump_break
:
4703 bld
.emit(BRW_OPCODE_BREAK
);
4705 case nir_jump_continue
:
4706 bld
.emit(BRW_OPCODE_CONTINUE
);
4708 case nir_jump_return
:
4710 unreachable("unknown jump");
4715 * This helper takes the result of a load operation that reads 32-bit elements
4723 * and shuffles the data to get this:
4730 * Which is exactly what we want if the load is reading 64-bit components
4731 * like doubles, where x represents the low 32-bit of the x double component
4732 * and y represents the high 32-bit of the x double component (likewise with
4733 * z and w for double component y). The parameter @components represents
4734 * the number of 64-bit components present in @src. This would typically be
4735 * 2 at most, since we can only fit 2 double elements in the result of a
4738 * Notice that @dst and @src can be the same register.
4741 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4744 uint32_t components
)
4746 assert(type_sz(src
.type
) == 4);
4747 assert(type_sz(dst
.type
) == 8);
4749 /* A temporary that we will use to shuffle the 32-bit data of each
4750 * component in the vector into valid 64-bit data. We can't write directly
4751 * to dst because dst can be (and would usually be) the same as src
4752 * and in that case the first MOV in the loop below would overwrite the
4753 * data read in the second MOV.
4755 fs_reg tmp
= bld
.vgrf(dst
.type
);
4757 for (unsigned i
= 0; i
< components
; i
++) {
4758 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4760 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4761 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4763 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4768 * This helper does the inverse operation of
4769 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4771 * We need to do this when we are going to use untyped write messsages that
4772 * operate with 32-bit components in order to arrange our 64-bit data to be
4773 * in the expected layout.
4775 * Notice that callers of this function, unlike in the case of the inverse
4776 * operation, would typically need to call this with dst and src being
4777 * different registers, since they would otherwise corrupt the original
4778 * 64-bit data they are about to write. Because of this the function checks
4779 * that the src and dst regions involved in the operation do not overlap.
4782 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4785 uint32_t components
)
4787 assert(type_sz(src
.type
) == 8);
4788 assert(type_sz(dst
.type
) == 4);
4790 assert(!regions_overlap(
4791 dst
, 2 * components
* dst
.component_size(bld
.dispatch_width()),
4792 src
, components
* src
.component_size(bld
.dispatch_width())));
4794 for (unsigned i
= 0; i
< components
; i
++) {
4795 const fs_reg component_i
= offset(src
, bld
, i
);
4796 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4797 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4802 setup_imm_df(const fs_builder
&bld
, double v
)
4804 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4805 assert(devinfo
->gen
>= 7);
4807 if (devinfo
->gen
>= 8)
4808 return brw_imm_df(v
);
4810 /* gen7.5 does not support DF immediates straighforward but the DIM
4811 * instruction allows to set the 64-bit immediate value.
4813 if (devinfo
->is_haswell
) {
4814 const fs_builder ubld
= bld
.exec_all();
4815 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4816 ubld
.DIM(dst
, brw_imm_df(v
));
4817 return component(dst
, 0);
4820 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4821 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4822 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4824 * Alternatively, we could also produce a normal VGRF (without stride 0)
4825 * by writing to all the channels in the VGRF, however, that would hit the
4826 * gen7 bug where we have to split writes that span more than 1 register
4827 * into instructions with a width of 4 (otherwise the write to the second
4828 * register written runs into an execmask hardware bug) which isn't very
4841 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4842 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4843 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4844 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4846 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);