2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
30 nir_optimize(nir_shader
*nir
)
35 nir_lower_vars_to_ssa(nir
);
36 nir_validate_shader(nir
);
37 nir_lower_alu_to_scalar(nir
);
38 nir_validate_shader(nir
);
39 progress
|= nir_copy_prop(nir
);
40 nir_validate_shader(nir
);
41 nir_lower_phis_to_scalar(nir
);
42 nir_validate_shader(nir
);
43 progress
|= nir_copy_prop(nir
);
44 nir_validate_shader(nir
);
45 progress
|= nir_opt_dce(nir
);
46 nir_validate_shader(nir
);
47 progress
|= nir_opt_cse(nir
);
48 nir_validate_shader(nir
);
49 progress
|= nir_opt_peephole_select(nir
);
50 nir_validate_shader(nir
);
51 progress
|= nir_opt_algebraic(nir
);
52 nir_validate_shader(nir
);
53 progress
|= nir_opt_constant_folding(nir
);
54 nir_validate_shader(nir
);
59 count_nir_instrs_in_block(nir_block
*block
, void *state
)
61 int *count
= (int *) state
;
62 nir_foreach_instr(block
, instr
) {
69 count_nir_instrs(nir_shader
*nir
)
72 nir_foreach_overload(nir
, overload
) {
75 nir_foreach_block(overload
->impl
, count_nir_instrs_in_block
, &count
);
81 fs_visitor::emit_nir_code()
83 /* first, lower the GLSL IR shader to NIR */
84 lower_output_reads(shader
->base
.ir
);
85 nir_shader
*nir
= glsl_to_nir(shader
->base
.ir
, NULL
, true);
86 nir_validate_shader(nir
);
88 nir_lower_global_vars_to_local(nir
);
89 nir_validate_shader(nir
);
91 nir_split_var_copies(nir
);
92 nir_validate_shader(nir
);
96 /* Lower a bunch of stuff */
97 nir_lower_var_copies(nir
);
98 nir_validate_shader(nir
);
101 nir_validate_shader(nir
);
103 nir_lower_locals_to_regs(nir
);
104 nir_validate_shader(nir
);
106 nir_remove_dead_variables(nir
);
107 nir_validate_shader(nir
);
109 nir_lower_samplers(nir
, shader_prog
, shader
->base
.Program
);
110 nir_validate_shader(nir
);
112 nir_lower_system_values(nir
);
113 nir_validate_shader(nir
);
115 nir_lower_atomics(nir
);
116 nir_validate_shader(nir
);
120 nir_lower_to_source_mods(nir
);
121 nir_validate_shader(nir
);
123 nir_validate_shader(nir
);
125 if (INTEL_DEBUG
& DEBUG_WM
) {
126 fprintf(stderr
, "NIR (SSA form) for fragment shader:\n");
127 nir_print_shader(nir
, stderr
);
130 if (dispatch_width
== 8) {
131 static GLuint msg_id
= 0;
132 _mesa_gl_debug(&brw
->ctx
, &msg_id
,
133 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
134 MESA_DEBUG_TYPE_OTHER
,
135 MESA_DEBUG_SEVERITY_NOTIFICATION
,
136 "FS NIR shader: %d inst\n",
137 count_nir_instrs(nir
));
140 nir_convert_from_ssa(nir
);
141 nir_validate_shader(nir
);
143 /* emit the arrays used for inputs and outputs - load/store intrinsics will
144 * be converted to reads/writes of these arrays
147 if (nir
->num_inputs
> 0) {
148 nir_inputs
= vgrf(nir
->num_inputs
);
149 nir_setup_inputs(nir
);
152 if (nir
->num_outputs
> 0) {
153 nir_outputs
= vgrf(nir
->num_outputs
);
154 nir_setup_outputs(nir
);
157 if (nir
->num_uniforms
> 0) {
158 nir_uniforms
= fs_reg(UNIFORM
, 0);
159 nir_setup_uniforms(nir
);
162 nir_emit_system_values(nir
);
164 nir_globals
= ralloc_array(mem_ctx
, fs_reg
, nir
->reg_alloc
);
165 foreach_list_typed(nir_register
, reg
, node
, &nir
->registers
) {
166 unsigned array_elems
=
167 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
168 unsigned size
= array_elems
* reg
->num_components
;
169 nir_globals
[reg
->index
] = vgrf(size
);
172 /* get the main function and emit it */
173 nir_foreach_overload(nir
, overload
) {
174 assert(strcmp(overload
->function
->name
, "main") == 0);
175 assert(overload
->impl
);
176 nir_emit_impl(overload
->impl
);
179 if (INTEL_DEBUG
& DEBUG_WM
) {
180 fprintf(stderr
, "NIR (final form) for fragment shader:\n");
181 nir_print_shader(nir
, stderr
);
188 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
190 struct hash_entry
*entry
;
191 hash_table_foreach(shader
->inputs
, entry
) {
192 nir_variable
*var
= (nir_variable
*) entry
->data
;
193 fs_reg varying
= offset(nir_inputs
, var
->data
.driver_location
);
196 if (!strcmp(var
->name
, "gl_FragCoord")) {
197 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
198 var
->data
.origin_upper_left
);
199 emit_percomp(MOV(varying
, reg
), 0xF);
200 } else if (!strcmp(var
->name
, "gl_FrontFacing")) {
201 reg
= *emit_frontfacing_interpolation();
202 emit(MOV(retype(varying
, BRW_REGISTER_TYPE_UD
), reg
));
204 emit_general_interpolation(varying
, var
->name
, var
->type
,
205 (glsl_interp_qualifier
) var
->data
.interpolation
,
206 var
->data
.location
, var
->data
.centroid
,
213 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
215 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
217 struct hash_entry
*entry
;
218 hash_table_foreach(shader
->outputs
, entry
) {
219 nir_variable
*var
= (nir_variable
*) entry
->data
;
220 fs_reg reg
= offset(nir_outputs
, var
->data
.driver_location
);
222 if (var
->data
.index
> 0) {
223 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
224 assert(var
->data
.index
== 1);
225 this->dual_src_output
= reg
;
226 this->do_dual_src
= true;
227 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
228 /* Writing gl_FragColor outputs to all color regions. */
229 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
230 this->outputs
[i
] = reg
;
231 this->output_components
[i
] = 4;
233 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
234 this->frag_depth
= reg
;
235 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
236 this->sample_mask
= reg
;
238 /* gl_FragData or a user-defined FS output */
239 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
240 var
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
242 int vector_elements
=
243 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
244 : var
->type
->vector_elements
;
246 /* General color output. */
247 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
248 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
249 this->outputs
[output
] = offset(reg
, vector_elements
* i
);
250 this->output_components
[output
] = vector_elements
;
257 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
259 uniforms
= shader
->num_uniforms
;
260 param_size
[0] = shader
->num_uniforms
;
262 if (dispatch_width
!= 8)
265 struct hash_entry
*entry
;
266 hash_table_foreach(shader
->uniforms
, entry
) {
267 nir_variable
*var
= (nir_variable
*) entry
->data
;
269 /* UBO's and atomics don't take up space in the uniform file */
271 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
274 if (strncmp(var
->name
, "gl_", 3) == 0)
275 nir_setup_builtin_uniform(var
);
277 nir_setup_uniform(var
);
282 fs_visitor::nir_setup_uniform(nir_variable
*var
)
284 int namelen
= strlen(var
->name
);
286 /* The data for our (non-builtin) uniforms is stored in a series of
287 * gl_uniform_driver_storage structs for each subcomponent that
288 * glGetUniformLocation() could name. We know it's been set up in the
289 * same order we'd walk the type, so walk the list of storage and find
290 * anything with our name, or the prefix of a component that starts with
293 unsigned index
= var
->data
.driver_location
;
294 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
295 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
297 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
298 (storage
->name
[namelen
] != 0 &&
299 storage
->name
[namelen
] != '.' &&
300 storage
->name
[namelen
] != '[')) {
304 unsigned slots
= storage
->type
->component_slots();
305 if (storage
->array_elements
)
306 slots
*= storage
->array_elements
;
308 for (unsigned i
= 0; i
< slots
; i
++) {
309 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
313 /* Make sure we actually initialized the right amount of stuff here. */
314 assert(var
->data
.driver_location
+ var
->type
->component_slots() == index
);
318 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
320 const nir_state_slot
*const slots
= var
->state_slots
;
321 assert(var
->state_slots
!= NULL
);
323 unsigned uniform_index
= var
->data
.driver_location
;
324 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
325 /* This state reference has already been setup by ir_to_mesa, but we'll
326 * get the same index back here.
328 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
329 (gl_state_index
*)slots
[i
].tokens
);
331 /* Add each of the unique swizzles of the element as a parameter.
332 * This'll end up matching the expected layout of the
333 * array/matrix/structure we're trying to fill in.
336 for (unsigned int j
= 0; j
< 4; j
++) {
337 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
338 if (swiz
== last_swiz
)
342 stage_prog_data
->param
[uniform_index
++] =
343 &prog
->Parameters
->ParameterValues
[index
][swiz
];
349 emit_system_values_block(nir_block
*block
, void *void_visitor
)
351 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
354 nir_foreach_instr(block
, instr
) {
355 if (instr
->type
!= nir_instr_type_intrinsic
)
358 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
359 switch (intrin
->intrinsic
) {
360 case nir_intrinsic_load_sample_pos
:
361 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
362 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
363 if (reg
->file
== BAD_FILE
)
364 *reg
= *v
->emit_samplepos_setup();
367 case nir_intrinsic_load_sample_id
:
368 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
369 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
370 if (reg
->file
== BAD_FILE
)
371 *reg
= *v
->emit_sampleid_setup();
374 case nir_intrinsic_load_sample_mask_in
:
375 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
376 assert(v
->brw
->gen
>= 7);
377 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
378 if (reg
->file
== BAD_FILE
)
379 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
380 BRW_REGISTER_TYPE_D
));
392 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
394 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
395 nir_foreach_overload(shader
, overload
) {
396 assert(strcmp(overload
->function
->name
, "main") == 0);
397 assert(overload
->impl
);
398 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
403 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
405 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
406 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
407 unsigned array_elems
=
408 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
409 unsigned size
= array_elems
* reg
->num_components
;
410 nir_locals
[reg
->index
] = vgrf(size
);
413 nir_emit_cf_list(&impl
->body
);
417 fs_visitor::nir_emit_cf_list(exec_list
*list
)
419 exec_list_validate(list
);
420 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
421 switch (node
->type
) {
423 nir_emit_if(nir_cf_node_as_if(node
));
426 case nir_cf_node_loop
:
427 nir_emit_loop(nir_cf_node_as_loop(node
));
430 case nir_cf_node_block
:
431 nir_emit_block(nir_cf_node_as_block(node
));
435 unreachable("Invalid CFG node block");
441 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
443 /* first, put the condition into f0 */
444 fs_inst
*inst
= emit(MOV(reg_null_d
,
445 retype(get_nir_src(if_stmt
->condition
),
446 BRW_REGISTER_TYPE_UD
)));
447 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
449 emit(IF(BRW_PREDICATE_NORMAL
));
451 nir_emit_cf_list(&if_stmt
->then_list
);
453 /* note: if the else is empty, dead CF elimination will remove it */
454 emit(BRW_OPCODE_ELSE
);
456 nir_emit_cf_list(&if_stmt
->else_list
);
458 emit(BRW_OPCODE_ENDIF
);
460 if (!try_replace_with_sel() && brw
->gen
< 6) {
461 no16("Can't support (non-uniform) control flow on SIMD16\n");
466 fs_visitor::nir_emit_loop(nir_loop
*loop
)
469 no16("Can't support (non-uniform) control flow on SIMD16\n");
474 nir_emit_cf_list(&loop
->body
);
476 emit(BRW_OPCODE_WHILE
);
480 fs_visitor::nir_emit_block(nir_block
*block
)
482 nir_foreach_instr(block
, instr
) {
483 nir_emit_instr(instr
);
488 fs_visitor::nir_emit_instr(nir_instr
*instr
)
490 switch (instr
->type
) {
491 case nir_instr_type_alu
:
492 nir_emit_alu(nir_instr_as_alu(instr
));
495 case nir_instr_type_intrinsic
:
496 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
499 case nir_instr_type_tex
:
500 nir_emit_texture(nir_instr_as_tex(instr
));
503 case nir_instr_type_load_const
:
504 /* We can hit these, but we do nothing now and use them as
509 case nir_instr_type_jump
:
510 nir_emit_jump(nir_instr_as_jump(instr
));
514 unreachable("unknown instruction type");
519 brw_type_for_nir_type(nir_alu_type type
)
523 case nir_type_unsigned
:
524 return BRW_REGISTER_TYPE_UD
;
526 return BRW_REGISTER_TYPE_D
;
528 return BRW_REGISTER_TYPE_F
;
530 unreachable("unknown type");
533 return BRW_REGISTER_TYPE_F
;
537 fs_visitor::nir_emit_alu(nir_alu_instr
*instr
)
539 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
542 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
543 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
546 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
547 op
[i
] = get_nir_src(instr
->src
[i
].src
);
548 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
549 op
[i
].abs
= instr
->src
[i
].abs
;
550 op
[i
].negate
= instr
->src
[i
].negate
;
553 /* We get a bunch of mov's out of the from_ssa pass and they may still
554 * be vectorized. We'll handle them as a special-case. We'll also
555 * handle vecN here because it's basically the same thing.
563 fs_reg temp
= result
;
564 bool need_extra_copy
= false;
565 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
566 if (!instr
->src
[i
].src
.is_ssa
&&
567 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
568 need_extra_copy
= true;
569 temp
= retype(vgrf(4), result
.type
);
574 for (unsigned i
= 0; i
< 4; i
++) {
575 if (!(instr
->dest
.write_mask
& (1 << i
)))
578 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
579 inst
= emit(MOV(offset(temp
, i
),
580 offset(op
[0], instr
->src
[0].swizzle
[i
])));
582 inst
= emit(MOV(offset(temp
, i
),
583 offset(op
[i
], instr
->src
[i
].swizzle
[0])));
585 inst
->saturate
= instr
->dest
.saturate
;
588 /* In this case the source and destination registers were the same,
589 * so we need to insert an extra set of moves in order to deal with
592 if (need_extra_copy
) {
593 for (unsigned i
= 0; i
< 4; i
++) {
594 if (!(instr
->dest
.write_mask
& (1 << i
)))
597 emit(MOV(offset(result
, i
), offset(temp
, i
)));
606 /* At this point, we have dealt with any instruction that operates on
607 * more than a single channel. Therefore, we can just adjust the source
608 * and destination registers for that channel and emit the instruction.
610 unsigned channel
= 0;
611 if (nir_op_infos
[instr
->op
].output_size
== 0) {
612 /* Since NIR is doing the scalarizing for us, we should only ever see
613 * vectorized operations with a single channel.
615 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
616 channel
= ffs(instr
->dest
.write_mask
) - 1;
618 result
= offset(result
, channel
);
621 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
622 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
623 op
[i
] = offset(op
[i
], instr
->src
[i
].swizzle
[channel
]);
629 inst
= emit(MOV(result
, op
[0]));
630 inst
->saturate
= instr
->dest
.saturate
;
635 emit(MOV(result
, op
[0]));
639 /* AND(val, 0x80000000) gives the sign bit.
641 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
644 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
646 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
647 op
[0].type
= BRW_REGISTER_TYPE_UD
;
648 result
.type
= BRW_REGISTER_TYPE_UD
;
649 emit(AND(result_int
, op
[0], fs_reg(0x80000000u
)));
651 inst
= emit(OR(result_int
, result_int
, fs_reg(0x3f800000u
)));
652 inst
->predicate
= BRW_PREDICATE_NORMAL
;
653 if (instr
->dest
.saturate
) {
654 inst
= emit(MOV(result
, result
));
655 inst
->saturate
= true;
661 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
662 * -> non-negative val generates 0x00000000.
663 * Predicated OR sets 1 if val is positive.
665 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
));
666 emit(ASR(result
, op
[0], fs_reg(31)));
667 inst
= emit(OR(result
, result
, fs_reg(1)));
668 inst
->predicate
= BRW_PREDICATE_NORMAL
;
672 inst
= emit_math(SHADER_OPCODE_RCP
, result
, op
[0]);
673 inst
->saturate
= instr
->dest
.saturate
;
677 inst
= emit_math(SHADER_OPCODE_EXP2
, result
, op
[0]);
678 inst
->saturate
= instr
->dest
.saturate
;
682 inst
= emit_math(SHADER_OPCODE_LOG2
, result
, op
[0]);
683 inst
->saturate
= instr
->dest
.saturate
;
688 unreachable("not reached: should be handled by ir_explog_to_explog2");
691 case nir_op_fsin_reduced
:
692 inst
= emit_math(SHADER_OPCODE_SIN
, result
, op
[0]);
693 inst
->saturate
= instr
->dest
.saturate
;
697 case nir_op_fcos_reduced
:
698 inst
= emit_math(SHADER_OPCODE_COS
, result
, op
[0]);
699 inst
->saturate
= instr
->dest
.saturate
;
703 if (fs_key
->high_quality_derivatives
) {
704 inst
= emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
706 inst
= emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
708 inst
->saturate
= instr
->dest
.saturate
;
710 case nir_op_fddx_fine
:
711 inst
= emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
712 inst
->saturate
= instr
->dest
.saturate
;
714 case nir_op_fddx_coarse
:
715 inst
= emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
716 inst
->saturate
= instr
->dest
.saturate
;
719 if (fs_key
->high_quality_derivatives
) {
720 inst
= emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
721 fs_reg(fs_key
->render_to_fbo
));
723 inst
= emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
724 fs_reg(fs_key
->render_to_fbo
));
726 inst
->saturate
= instr
->dest
.saturate
;
728 case nir_op_fddy_fine
:
729 inst
= emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
730 fs_reg(fs_key
->render_to_fbo
));
731 inst
->saturate
= instr
->dest
.saturate
;
733 case nir_op_fddy_coarse
:
734 inst
= emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
735 fs_reg(fs_key
->render_to_fbo
));
736 inst
->saturate
= instr
->dest
.saturate
;
741 inst
= emit(ADD(result
, op
[0], op
[1]));
742 inst
->saturate
= instr
->dest
.saturate
;
746 inst
= emit(MUL(result
, op
[0], op
[1]));
747 inst
->saturate
= instr
->dest
.saturate
;
751 /* TODO put in the 16-bit constant optimization once we have SSA */
754 no16("SIMD16 explicit accumulator operands unsupported\n");
756 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
758 emit(MUL(acc
, op
[0], op
[1]));
759 emit(MACH(reg_null_d
, op
[0], op
[1]));
760 emit(MOV(result
, fs_reg(acc
)));
764 case nir_op_imul_high
:
765 case nir_op_umul_high
: {
767 no16("SIMD16 explicit accumulator operands unsupported\n");
769 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
771 emit(MUL(acc
, op
[0], op
[1]));
772 emit(MACH(result
, op
[0], op
[1]));
778 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
781 case nir_op_uadd_carry
: {
783 no16("SIMD16 explicit accumulator operands unsupported\n");
785 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
786 BRW_REGISTER_TYPE_UD
);
788 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
789 emit(MOV(result
, fs_reg(acc
)));
793 case nir_op_usub_borrow
: {
795 no16("SIMD16 explicit accumulator operands unsupported\n");
797 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
798 BRW_REGISTER_TYPE_UD
);
800 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
801 emit(MOV(result
, fs_reg(acc
)));
806 emit_math(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
812 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
));
818 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
));
823 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
828 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
832 emit(NOT(result
, op
[0]));
835 emit(XOR(result
, op
[0], op
[1]));
838 emit(OR(result
, op
[0], op
[1]));
841 emit(AND(result
, op
[0], op
[1]));
853 case nir_op_ball_fequal2
:
854 case nir_op_ball_iequal2
:
855 case nir_op_ball_fequal3
:
856 case nir_op_ball_iequal3
:
857 case nir_op_ball_fequal4
:
858 case nir_op_ball_iequal4
:
859 case nir_op_bany_fnequal2
:
860 case nir_op_bany_inequal2
:
861 case nir_op_bany_fnequal3
:
862 case nir_op_bany_inequal3
:
863 case nir_op_bany_fnequal4
:
864 case nir_op_bany_inequal4
:
865 unreachable("Lowered by nir_lower_alu_reductions");
867 case nir_op_fnoise1_1
:
868 case nir_op_fnoise1_2
:
869 case nir_op_fnoise1_3
:
870 case nir_op_fnoise1_4
:
871 case nir_op_fnoise2_1
:
872 case nir_op_fnoise2_2
:
873 case nir_op_fnoise2_3
:
874 case nir_op_fnoise2_4
:
875 case nir_op_fnoise3_1
:
876 case nir_op_fnoise3_2
:
877 case nir_op_fnoise3_3
:
878 case nir_op_fnoise3_4
:
879 case nir_op_fnoise4_1
:
880 case nir_op_fnoise4_2
:
881 case nir_op_fnoise4_3
:
882 case nir_op_fnoise4_4
:
883 unreachable("not reached: should be handled by lower_noise");
886 unreachable("not reached: should be handled by ldexp_to_arith()");
889 inst
= emit_math(SHADER_OPCODE_SQRT
, result
, op
[0]);
890 inst
->saturate
= instr
->dest
.saturate
;
894 inst
= emit_math(SHADER_OPCODE_RSQ
, result
, op
[0]);
895 inst
->saturate
= instr
->dest
.saturate
;
899 emit(AND(result
, op
[0], fs_reg(1)));
902 emit(AND(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0], fs_reg(0x3f800000u
)));
906 emit(CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
909 emit(CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
913 inst
= emit(RNDZ(result
, op
[0]));
914 inst
->saturate
= instr
->dest
.saturate
;
918 op
[0].negate
= !op
[0].negate
;
919 fs_reg temp
= vgrf(glsl_type::float_type
);
920 emit(RNDD(temp
, op
[0]));
922 inst
= emit(MOV(result
, temp
));
923 inst
->saturate
= instr
->dest
.saturate
;
927 inst
= emit(RNDD(result
, op
[0]));
928 inst
->saturate
= instr
->dest
.saturate
;
931 inst
= emit(FRC(result
, op
[0]));
932 inst
->saturate
= instr
->dest
.saturate
;
934 case nir_op_fround_even
:
935 inst
= emit(RNDE(result
, op
[0]));
936 inst
->saturate
= instr
->dest
.saturate
;
943 inst
= emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
944 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
946 emit(CMP(reg_null_d
, op
[0], op
[1], BRW_CONDITIONAL_L
));
947 inst
= emit(SEL(result
, op
[0], op
[1]));
949 inst
->saturate
= instr
->dest
.saturate
;
956 inst
= emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
957 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
959 emit(CMP(reg_null_d
, op
[0], op
[1], BRW_CONDITIONAL_GE
));
960 inst
= emit(SEL(result
, op
[0], op
[1]));
962 inst
->saturate
= instr
->dest
.saturate
;
965 case nir_op_pack_snorm_2x16
:
966 case nir_op_pack_snorm_4x8
:
967 case nir_op_pack_unorm_2x16
:
968 case nir_op_pack_unorm_4x8
:
969 case nir_op_unpack_snorm_2x16
:
970 case nir_op_unpack_snorm_4x8
:
971 case nir_op_unpack_unorm_2x16
:
972 case nir_op_unpack_unorm_4x8
:
973 case nir_op_unpack_half_2x16
:
974 case nir_op_pack_half_2x16
:
975 unreachable("not reached: should be handled by lower_packing_builtins");
977 case nir_op_unpack_half_2x16_split_x
:
978 inst
= emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
979 inst
->saturate
= instr
->dest
.saturate
;
981 case nir_op_unpack_half_2x16_split_y
:
982 inst
= emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
983 inst
->saturate
= instr
->dest
.saturate
;
987 inst
= emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
988 inst
->saturate
= instr
->dest
.saturate
;
991 case nir_op_bitfield_reverse
:
992 emit(BFREV(result
, op
[0]));
995 case nir_op_bit_count
:
996 emit(CBIT(result
, op
[0]));
999 case nir_op_ufind_msb
:
1000 case nir_op_ifind_msb
: {
1001 emit(FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]));
1003 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1004 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1005 * subtract the result from 31 to convert the MSB count into an LSB count.
1008 emit(CMP(reg_null_d
, result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
1009 fs_reg
neg_result(result
);
1010 neg_result
.negate
= true;
1011 inst
= emit(ADD(result
, neg_result
, fs_reg(31)));
1012 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1016 case nir_op_find_lsb
:
1017 emit(FBL(result
, op
[0]));
1020 case nir_op_ubitfield_extract
:
1021 case nir_op_ibitfield_extract
:
1022 emit(BFE(result
, op
[2], op
[1], op
[0]));
1025 emit(BFI1(result
, op
[0], op
[1]));
1028 emit(BFI2(result
, op
[0], op
[1], op
[2]));
1031 case nir_op_bitfield_insert
:
1032 unreachable("not reached: should be handled by "
1033 "lower_instructions::bitfield_insert_to_bfm_bfi");
1036 emit(SHL(result
, op
[0], op
[1]));
1039 emit(ASR(result
, op
[0], op
[1]));
1042 emit(SHR(result
, op
[0], op
[1]));
1045 case nir_op_pack_half_2x16_split
:
1046 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1050 emit(MAD(result
, op
[2], op
[1], op
[0]));
1054 /* TODO emulate for gen < 6 */
1055 emit(LRP(result
, op
[2], op
[1], op
[0]));
1059 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1060 inst
= emit(SEL(result
, op
[1], op
[2]));
1061 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1065 unreachable("unhandled instruction");
1070 fs_visitor::get_nir_src(nir_src src
)
1073 assert(src
.ssa
->parent_instr
->type
== nir_instr_type_load_const
);
1074 nir_load_const_instr
*load
= nir_instr_as_load_const(src
.ssa
->parent_instr
);
1075 fs_reg reg
= vgrf(src
.ssa
->num_components
);
1076 reg
.type
= BRW_REGISTER_TYPE_D
;
1078 for (unsigned i
= 0; i
< src
.ssa
->num_components
; ++i
)
1079 emit(MOV(offset(reg
, i
), fs_reg(load
->value
.i
[i
])));
1084 if (src
.reg
.reg
->is_global
)
1085 reg
= nir_globals
[src
.reg
.reg
->index
];
1087 reg
= nir_locals
[src
.reg
.reg
->index
];
1089 /* to avoid floating-point denorm flushing problems, set the type by
1090 * default to D - instructions that need floating point semantics will set
1091 * this to F if they need to
1093 reg
= retype(offset(reg
, src
.reg
.base_offset
), BRW_REGISTER_TYPE_D
);
1094 if (src
.reg
.indirect
) {
1095 reg
.reladdr
= new(mem_ctx
) fs_reg();
1096 *reg
.reladdr
= retype(get_nir_src(*src
.reg
.indirect
),
1097 BRW_REGISTER_TYPE_D
);
1105 fs_visitor::get_nir_dest(nir_dest dest
)
1108 if (dest
.reg
.reg
->is_global
)
1109 reg
= nir_globals
[dest
.reg
.reg
->index
];
1111 reg
= nir_locals
[dest
.reg
.reg
->index
];
1113 reg
= offset(reg
, dest
.reg
.base_offset
);
1114 if (dest
.reg
.indirect
) {
1115 reg
.reladdr
= new(mem_ctx
) fs_reg();
1116 *reg
.reladdr
= retype(get_nir_src(*dest
.reg
.indirect
),
1117 BRW_REGISTER_TYPE_D
);
1124 fs_visitor::emit_percomp(fs_inst
*inst
, unsigned wr_mask
)
1126 for (unsigned i
= 0; i
< 4; i
++) {
1127 if (!((wr_mask
>> i
) & 1))
1130 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(*inst
);
1131 new_inst
->dst
= offset(new_inst
->dst
, i
);
1132 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1133 if (inst
->src
[j
].file
== GRF
)
1134 new_inst
->src
[j
] = offset(new_inst
->src
[j
], i
);
1141 fs_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
1144 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1145 dest
= get_nir_dest(instr
->dest
);
1147 bool has_indirect
= false;
1149 switch (instr
->intrinsic
) {
1150 case nir_intrinsic_discard
: {
1151 /* We track our discarded pixels in f0.1. By predicating on it, we can
1152 * update just the flag bits that aren't yet discarded. By emitting a
1153 * CMP of g0 != g0, all our currently executing channels will get turned
1156 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1157 BRW_REGISTER_TYPE_UW
));
1158 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
1159 BRW_CONDITIONAL_NZ
));
1160 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1161 cmp
->flag_subreg
= 1;
1163 if (brw
->gen
>= 6) {
1164 /* For performance, after a discard, jump to the end of the shader.
1165 * Only jump if all relevant channels have been discarded.
1167 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1168 discard_jump
->flag_subreg
= 1;
1170 discard_jump
->predicate
= (dispatch_width
== 8)
1171 ? BRW_PREDICATE_ALIGN1_ANY8H
1172 : BRW_PREDICATE_ALIGN1_ANY16H
;
1173 discard_jump
->predicate_inverse
= true;
1179 case nir_intrinsic_atomic_counter_inc
:
1180 case nir_intrinsic_atomic_counter_dec
:
1181 case nir_intrinsic_atomic_counter_read
: {
1182 unsigned surf_index
= prog_data
->binding_table
.abo_start
+
1183 (unsigned) instr
->const_index
[0];
1184 fs_reg offset
= fs_reg(get_nir_src(instr
->src
[0]));
1186 switch (instr
->intrinsic
) {
1187 case nir_intrinsic_atomic_counter_inc
:
1188 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
1189 fs_reg(), fs_reg());
1191 case nir_intrinsic_atomic_counter_dec
:
1192 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
1193 fs_reg(), fs_reg());
1195 case nir_intrinsic_atomic_counter_read
:
1196 emit_untyped_surface_read(surf_index
, dest
, offset
);
1199 unreachable("Unreachable");
1204 case nir_intrinsic_load_front_face
:
1207 case nir_intrinsic_load_sample_mask_in
: {
1208 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1209 assert(sample_mask_in
.file
!= BAD_FILE
);
1210 dest
.type
= sample_mask_in
.type
;
1211 emit(MOV(dest
, sample_mask_in
));
1215 case nir_intrinsic_load_sample_pos
: {
1216 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1217 assert(sample_pos
.file
!= BAD_FILE
);
1218 dest
.type
= sample_pos
.type
;
1219 emit(MOV(dest
, sample_pos
));
1220 emit(MOV(offset(dest
, 1), offset(sample_pos
, 1)));
1224 case nir_intrinsic_load_sample_id
: {
1225 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1226 assert(sample_id
.file
!= BAD_FILE
);
1227 dest
.type
= sample_id
.type
;
1228 emit(MOV(dest
, sample_id
));
1232 case nir_intrinsic_load_uniform_indirect
:
1233 has_indirect
= true;
1234 case nir_intrinsic_load_uniform
: {
1236 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1237 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1238 fs_reg src
= offset(retype(nir_uniforms
, dest
.type
),
1239 instr
->const_index
[0] + index
);
1241 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1244 emit(MOV(dest
, src
));
1245 dest
= offset(dest
, 1);
1251 case nir_intrinsic_load_ubo_indirect
:
1252 has_indirect
= true;
1253 case nir_intrinsic_load_ubo
: {
1254 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1258 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1261 /* The block index is not a constant. Evaluate the index expression
1262 * per-channel and add the base UBO index; the generator will select
1263 * a value from any live channel.
1265 surf_index
= vgrf(glsl_type::uint_type
);
1266 emit(ADD(surf_index
, get_nir_src(instr
->src
[0]),
1267 fs_reg(stage_prog_data
->binding_table
.ubo_start
)))
1268 ->force_writemask_all
= true;
1270 /* Assume this may touch any UBO. It would be nice to provide
1271 * a tighter bound, but the array information is already lowered away.
1273 brw_mark_surface_used(prog_data
,
1274 stage_prog_data
->binding_table
.ubo_start
+
1275 shader_prog
->NumUniformBlocks
- 1);
1279 /* Turn the byte offset into a dword offset. */
1280 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1281 emit(SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1282 BRW_REGISTER_TYPE_D
),
1285 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1286 for (int i
= 0; i
< instr
->num_components
; i
++)
1287 emit(VARYING_PULL_CONSTANT_LOAD(offset(dest
, i
), surf_index
,
1288 base_offset
, vec4_offset
+ i
));
1290 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1291 packed_consts
.type
= dest
.type
;
1293 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1294 emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1295 surf_index
, const_offset_reg
);
1297 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1298 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1300 /* The std140 packing rules don't allow vectors to cross 16-byte
1301 * boundaries, and a reg is 32 bytes.
1303 assert(packed_consts
.subreg_offset
< 32);
1305 emit(MOV(dest
, packed_consts
));
1306 dest
= offset(dest
, 1);
1312 case nir_intrinsic_load_input_indirect
:
1313 has_indirect
= true;
1314 case nir_intrinsic_load_input
: {
1316 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1317 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1318 fs_reg src
= offset(retype(nir_inputs
, dest
.type
),
1319 instr
->const_index
[0] + index
);
1321 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1324 emit(MOV(dest
, src
));
1325 dest
= offset(dest
, 1);
1331 /* Handle ARB_gpu_shader5 interpolation intrinsics
1333 * It's worth a quick word of explanation as to why we handle the full
1334 * variable-based interpolation intrinsic rather than a lowered version
1335 * with like we do for other inputs. We have to do that because the way
1336 * we set up inputs doesn't allow us to use the already setup inputs for
1337 * interpolation. At the beginning of the shader, we go through all of
1338 * the input variables and do the initial interpolation and put it in
1339 * the nir_inputs array based on its location as determined in
1340 * nir_lower_io. If the input isn't used, dead code cleans up and
1341 * everything works fine. However, when we get to the ARB_gpu_shader5
1342 * interpolation intrinsics, we need to reinterpolate the input
1343 * differently. If we used an intrinsic that just had an index it would
1344 * only give us the offset into the nir_inputs array. However, this is
1345 * useless because that value is post-interpolation and we need
1346 * pre-interpolation. In order to get the actual location of the bits
1347 * we get from the vertex fetching hardware, we need the variable.
1349 case nir_intrinsic_interp_var_at_centroid
:
1350 case nir_intrinsic_interp_var_at_sample
:
1351 case nir_intrinsic_interp_var_at_offset
: {
1352 /* in SIMD16 mode, the pixel interpolator returns coords interleaved
1353 * 8 channels at a time, same as the barycentric coords presented in
1354 * the FS payload. this requires a bit of extra work to support.
1356 no16("interpolate_at_* not yet supported in SIMD16 mode.");
1358 fs_reg dst_x
= vgrf(2);
1359 fs_reg dst_y
= offset(dst_x
, 1);
1361 /* For most messages, we need one reg of ignored data; the hardware
1362 * requires mlen==1 even when there is no payload. in the per-slot
1363 * offset case, we'll replace this with the proper source data.
1365 fs_reg src
= vgrf(glsl_type::float_type
);
1366 int mlen
= 1; /* one reg unless overriden */
1369 switch (instr
->intrinsic
) {
1370 case nir_intrinsic_interp_var_at_centroid
:
1371 inst
= emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
, dst_x
, src
, fs_reg(0u));
1374 case nir_intrinsic_interp_var_at_sample
: {
1375 /* XXX: We should probably handle non-constant sample id's */
1376 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1377 assert(const_sample
);
1378 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1379 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_x
, src
,
1384 case nir_intrinsic_interp_var_at_offset
: {
1385 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1388 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1389 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1391 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_x
, src
,
1392 fs_reg(off_x
| (off_y
<< 4)));
1394 src
= vgrf(glsl_type::ivec2_type
);
1395 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1396 BRW_REGISTER_TYPE_F
);
1397 for (int i
= 0; i
< 2; i
++) {
1398 fs_reg temp
= vgrf(glsl_type::float_type
);
1399 emit(MUL(temp
, offset(offset_src
, i
), fs_reg(16.0f
)));
1400 fs_reg itemp
= vgrf(glsl_type::int_type
);
1401 emit(MOV(itemp
, temp
)); /* float to int */
1403 /* Clamp the upper end of the range to +7/16.
1404 * ARB_gpu_shader5 requires that we support a maximum offset
1405 * of +0.5, which isn't representable in a S0.4 value -- if
1406 * we didn't clamp it, we'd end up with -8/16, which is the
1407 * opposite of what the shader author wanted.
1409 * This is legal due to ARB_gpu_shader5's quantization
1412 * "Not all values of <offset> may be supported; x and y
1413 * offsets may be rounded to fixed-point values with the
1414 * number of fraction bits given by the
1415 * implementation-dependent constant
1416 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1419 emit(BRW_OPCODE_SEL
, offset(src
, i
), itemp
, fs_reg(7))
1420 ->conditional_mod
= BRW_CONDITIONAL_L
; /* min(src2, 7) */
1424 inst
= emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_x
, src
,
1431 unreachable("Invalid intrinsic");
1435 inst
->regs_written
= 2; /* 2 floats per slot returned */
1436 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1437 INTERP_QUALIFIER_NOPERSPECTIVE
;
1439 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1440 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1441 src
.type
= dest
.type
;
1443 emit(FS_OPCODE_LINTERP
, dest
, dst_x
, dst_y
, src
);
1444 dest
= offset(dest
, 1);
1449 case nir_intrinsic_store_output_indirect
:
1450 has_indirect
= true;
1451 case nir_intrinsic_store_output
: {
1452 fs_reg src
= get_nir_src(instr
->src
[0]);
1454 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1455 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1456 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
),
1457 instr
->const_index
[0] + index
);
1459 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1461 emit(MOV(new_dest
, src
));
1462 src
= offset(src
, 1);
1469 unreachable("unknown intrinsic");
1474 fs_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1476 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1477 unsigned sampler
= instr
->sampler_index
;
1478 fs_reg
sampler_reg(sampler
);
1480 /* FINISHME: We're failing to recompile our programs when the sampler is
1481 * updated. This only matters for the texture rectangle scale parameters
1482 * (pre-gen6, or gen6+ with GL_CLAMP).
1484 int texunit
= prog
->SamplerUnits
[sampler
];
1486 int gather_component
= instr
->component
;
1488 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1490 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1493 int lod_components
, offset_components
= 0;
1495 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, offset
;
1497 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1498 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1499 switch (instr
->src
[i
].src_type
) {
1500 case nir_tex_src_bias
:
1501 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1503 case nir_tex_src_comparitor
:
1504 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1506 case nir_tex_src_coord
:
1507 switch (instr
->op
) {
1509 case nir_texop_txf_ms
:
1510 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1513 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1517 case nir_tex_src_ddx
:
1518 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1519 lod_components
= nir_tex_instr_src_size(instr
, i
);
1521 case nir_tex_src_ddy
:
1522 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1524 case nir_tex_src_lod
:
1525 switch (instr
->op
) {
1527 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1530 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1533 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1537 case nir_tex_src_ms_index
:
1538 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1540 case nir_tex_src_offset
:
1541 offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1542 if (instr
->is_array
)
1543 offset_components
= instr
->coord_components
- 1;
1545 offset_components
= instr
->coord_components
;
1547 case nir_tex_src_projector
:
1548 unreachable("should be lowered");
1550 case nir_tex_src_sampler_offset
: {
1551 /* Figure out the highest possible sampler index and mark it as used */
1552 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1553 if (instr
->op
== nir_texop_tg4
&& brw
->gen
< 8) {
1554 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1556 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1558 brw_mark_surface_used(prog_data
, max_used
);
1560 /* Emit code to evaluate the actual indexing expression */
1561 sampler_reg
= vgrf(glsl_type::uint_type
);
1562 emit(ADD(sampler_reg
, src
, fs_reg(sampler
)))
1563 ->force_writemask_all
= true;
1568 unreachable("unknown texture source");
1572 if (instr
->op
== nir_texop_txf_ms
) {
1573 if (brw
->gen
>= 7 && key
->tex
.compressed_multisample_layout_mask
& (1<<sampler
))
1574 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1579 for (unsigned i
= 0; i
< 3; i
++) {
1580 if (instr
->const_offset
[i
] != 0) {
1581 assert(offset_components
== 0);
1582 offset
= fs_reg(brw_texture_offset(ctx
, instr
->const_offset
, 3));
1587 enum glsl_base_type dest_base_type
;
1588 switch (instr
->dest_type
) {
1589 case nir_type_float
:
1590 dest_base_type
= GLSL_TYPE_FLOAT
;
1593 dest_base_type
= GLSL_TYPE_INT
;
1595 case nir_type_unsigned
:
1596 dest_base_type
= GLSL_TYPE_UINT
;
1599 unreachable("bad type");
1602 const glsl_type
*dest_type
=
1603 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1606 ir_texture_opcode op
;
1607 switch (instr
->op
) {
1608 case nir_texop_lod
: op
= ir_lod
; break;
1609 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1610 case nir_texop_tex
: op
= ir_tex
; break;
1611 case nir_texop_tg4
: op
= ir_tg4
; break;
1612 case nir_texop_txb
: op
= ir_txb
; break;
1613 case nir_texop_txd
: op
= ir_txd
; break;
1614 case nir_texop_txf
: op
= ir_txf
; break;
1615 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1616 case nir_texop_txl
: op
= ir_txl
; break;
1617 case nir_texop_txs
: op
= ir_txs
; break;
1619 unreachable("unknown texture opcode");
1622 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1623 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1624 offset
, offset_components
, mcs
, gather_component
,
1625 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1627 fs_reg dest
= get_nir_dest(instr
->dest
);
1628 dest
.type
= this->result
.type
;
1629 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1630 emit_percomp(MOV(dest
, this->result
), (1 << num_components
) - 1);
1634 fs_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1636 switch (instr
->type
) {
1637 case nir_jump_break
:
1638 emit(BRW_OPCODE_BREAK
);
1640 case nir_jump_continue
:
1641 emit(BRW_OPCODE_CONTINUE
);
1643 case nir_jump_return
:
1645 unreachable("unknown jump");