2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "program/prog_to_nir.h"
29 #include "brw_fs_surface_builder.h"
35 fs_visitor::emit_nir_code()
37 nir_shader
*nir
= prog
->nir
;
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
42 nir_setup_inputs(nir
);
43 nir_setup_outputs(nir
);
44 nir_setup_uniforms(nir
);
45 nir_emit_system_values(nir
);
47 /* get the main function and emit it */
48 nir_foreach_overload(nir
, overload
) {
49 assert(strcmp(overload
->function
->name
, "main") == 0);
50 assert(overload
->impl
);
51 nir_emit_impl(overload
->impl
);
56 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
58 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, shader
->num_inputs
);
60 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
61 enum brw_reg_type type
= brw_type_for_base_type(var
->type
);
62 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
66 case MESA_SHADER_VERTEX
: {
67 /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
68 * stored in nir_variable::location.
70 * However, NIR's load_input intrinsics use a different index - an
71 * offset into a single contiguous array containing all inputs.
72 * This index corresponds to the nir_variable::driver_location field.
74 * So, we need to copy from fs_reg(ATTR, var->location) to
75 * offset(nir_inputs, var->data.driver_location).
77 const glsl_type
*const t
= var
->type
->without_array();
78 const unsigned components
= t
->components();
79 const unsigned cols
= t
->matrix_columns
;
80 const unsigned elts
= t
->vector_elements
;
81 unsigned array_length
= var
->type
->is_array() ? var
->type
->length
: 1;
82 for (unsigned i
= 0; i
< array_length
; i
++) {
83 for (unsigned j
= 0; j
< cols
; j
++) {
84 for (unsigned k
= 0; k
< elts
; k
++) {
85 bld
.MOV(offset(retype(input
, type
), bld
,
86 components
* i
+ elts
* j
+ k
),
87 offset(fs_reg(ATTR
, var
->data
.location
+ i
, type
),
94 case MESA_SHADER_GEOMETRY
:
95 case MESA_SHADER_COMPUTE
:
96 case MESA_SHADER_TESS_CTRL
:
97 case MESA_SHADER_TESS_EVAL
:
98 unreachable("fs_visitor not used for these stages yet.");
100 case MESA_SHADER_FRAGMENT
:
101 if (var
->data
.location
== VARYING_SLOT_POS
) {
102 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
103 var
->data
.origin_upper_left
);
104 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
107 emit_general_interpolation(input
, var
->name
, var
->type
,
108 (glsl_interp_qualifier
) var
->data
.interpolation
,
109 var
->data
.location
, var
->data
.centroid
,
118 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
120 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
122 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, shader
->num_outputs
);
124 foreach_list_typed(nir_variable
, var
, node
, &shader
->outputs
) {
125 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
127 int vector_elements
=
128 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
129 : var
->type
->vector_elements
;
132 case MESA_SHADER_VERTEX
:
133 for (int i
= 0; i
< ALIGN(type_size(var
->type
), 4) / 4; i
++) {
134 int output
= var
->data
.location
+ i
;
135 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
136 this->output_components
[output
] = vector_elements
;
139 case MESA_SHADER_FRAGMENT
:
140 if (var
->data
.index
> 0) {
141 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
142 assert(var
->data
.index
== 1);
143 this->dual_src_output
= reg
;
144 this->do_dual_src
= true;
145 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
146 /* Writing gl_FragColor outputs to all color regions. */
147 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
148 this->outputs
[i
] = reg
;
149 this->output_components
[i
] = 4;
151 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
152 this->frag_depth
= reg
;
153 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
154 this->sample_mask
= reg
;
156 /* gl_FragData or a user-defined FS output */
157 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
158 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
160 /* General color output. */
161 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
162 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
163 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
164 this->output_components
[output
] = vector_elements
;
169 unreachable("unhandled shader stage");
175 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
177 num_direct_uniforms
= shader
->num_direct_uniforms
;
179 if (dispatch_width
!= 8)
182 /* We split the uniform register file in half. The first half is
183 * entirely direct uniforms. The second half is indirect.
185 if (num_direct_uniforms
> 0)
186 param_size
[0] = num_direct_uniforms
;
187 if (shader
->num_uniforms
> num_direct_uniforms
)
188 param_size
[num_direct_uniforms
] = shader
->num_uniforms
- num_direct_uniforms
;
190 uniforms
= shader
->num_uniforms
;
193 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
194 /* UBO's and atomics don't take up space in the uniform file */
195 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
198 if (strncmp(var
->name
, "gl_", 3) == 0)
199 nir_setup_builtin_uniform(var
);
201 nir_setup_uniform(var
);
204 /* prog_to_nir doesn't create uniform variables; set param up directly. */
205 for (unsigned p
= 0; p
< prog
->Parameters
->NumParameters
; p
++) {
206 for (unsigned int i
= 0; i
< 4; i
++) {
207 stage_prog_data
->param
[4 * p
+ i
] =
208 &prog
->Parameters
->ParameterValues
[p
][i
];
215 fs_visitor::nir_setup_uniform(nir_variable
*var
)
217 int namelen
= strlen(var
->name
);
219 /* The data for our (non-builtin) uniforms is stored in a series of
220 * gl_uniform_driver_storage structs for each subcomponent that
221 * glGetUniformLocation() could name. We know it's been set up in the
222 * same order we'd walk the type, so walk the list of storage and find
223 * anything with our name, or the prefix of a component that starts with
226 unsigned index
= var
->data
.driver_location
;
227 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
228 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
230 if (storage
->builtin
)
233 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
234 (storage
->name
[namelen
] != 0 &&
235 storage
->name
[namelen
] != '.' &&
236 storage
->name
[namelen
] != '[')) {
240 unsigned slots
= storage
->type
->component_slots();
241 if (storage
->array_elements
)
242 slots
*= storage
->array_elements
;
244 for (unsigned i
= 0; i
< slots
; i
++) {
245 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
249 /* Make sure we actually initialized the right amount of stuff here. */
250 assert(var
->data
.driver_location
+ var
->type
->component_slots() == index
);
254 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
256 const nir_state_slot
*const slots
= var
->state_slots
;
257 assert(var
->state_slots
!= NULL
);
259 unsigned uniform_index
= var
->data
.driver_location
;
260 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
261 /* This state reference has already been setup by ir_to_mesa, but we'll
262 * get the same index back here.
264 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
265 (gl_state_index
*)slots
[i
].tokens
);
267 /* Add each of the unique swizzles of the element as a parameter.
268 * This'll end up matching the expected layout of the
269 * array/matrix/structure we're trying to fill in.
272 for (unsigned int j
= 0; j
< 4; j
++) {
273 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
274 if (swiz
== last_swiz
)
278 stage_prog_data
->param
[uniform_index
++] =
279 &prog
->Parameters
->ParameterValues
[index
][swiz
];
285 emit_system_values_block(nir_block
*block
, void *void_visitor
)
287 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
290 nir_foreach_instr(block
, instr
) {
291 if (instr
->type
!= nir_instr_type_intrinsic
)
294 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
295 switch (intrin
->intrinsic
) {
296 case nir_intrinsic_load_vertex_id
:
297 unreachable("should be lowered by lower_vertex_id().");
299 case nir_intrinsic_load_vertex_id_zero_base
:
300 assert(v
->stage
== MESA_SHADER_VERTEX
);
301 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
302 if (reg
->file
== BAD_FILE
)
303 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
306 case nir_intrinsic_load_base_vertex
:
307 assert(v
->stage
== MESA_SHADER_VERTEX
);
308 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
309 if (reg
->file
== BAD_FILE
)
310 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
313 case nir_intrinsic_load_instance_id
:
314 assert(v
->stage
== MESA_SHADER_VERTEX
);
315 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
316 if (reg
->file
== BAD_FILE
)
317 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
320 case nir_intrinsic_load_sample_pos
:
321 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
322 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
323 if (reg
->file
== BAD_FILE
)
324 *reg
= *v
->emit_samplepos_setup();
327 case nir_intrinsic_load_sample_id
:
328 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
329 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
330 if (reg
->file
== BAD_FILE
)
331 *reg
= *v
->emit_sampleid_setup();
334 case nir_intrinsic_load_sample_mask_in
:
335 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
336 assert(v
->devinfo
->gen
>= 7);
337 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
338 if (reg
->file
== BAD_FILE
)
339 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
340 BRW_REGISTER_TYPE_D
));
352 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
354 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
355 nir_foreach_overload(shader
, overload
) {
356 assert(strcmp(overload
->function
->name
, "main") == 0);
357 assert(overload
->impl
);
358 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
363 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
365 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
366 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
367 unsigned array_elems
=
368 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
369 unsigned size
= array_elems
* reg
->num_components
;
370 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
373 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
376 nir_emit_cf_list(&impl
->body
);
380 fs_visitor::nir_emit_cf_list(exec_list
*list
)
382 exec_list_validate(list
);
383 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
384 switch (node
->type
) {
386 nir_emit_if(nir_cf_node_as_if(node
));
389 case nir_cf_node_loop
:
390 nir_emit_loop(nir_cf_node_as_loop(node
));
393 case nir_cf_node_block
:
394 nir_emit_block(nir_cf_node_as_block(node
));
398 unreachable("Invalid CFG node block");
404 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
406 /* first, put the condition into f0 */
407 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
408 retype(get_nir_src(if_stmt
->condition
),
409 BRW_REGISTER_TYPE_D
));
410 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
412 bld
.IF(BRW_PREDICATE_NORMAL
);
414 nir_emit_cf_list(&if_stmt
->then_list
);
416 /* note: if the else is empty, dead CF elimination will remove it */
417 bld
.emit(BRW_OPCODE_ELSE
);
419 nir_emit_cf_list(&if_stmt
->else_list
);
421 bld
.emit(BRW_OPCODE_ENDIF
);
423 try_replace_with_sel();
427 fs_visitor::nir_emit_loop(nir_loop
*loop
)
429 bld
.emit(BRW_OPCODE_DO
);
431 nir_emit_cf_list(&loop
->body
);
433 bld
.emit(BRW_OPCODE_WHILE
);
437 fs_visitor::nir_emit_block(nir_block
*block
)
439 nir_foreach_instr(block
, instr
) {
440 nir_emit_instr(instr
);
445 fs_visitor::nir_emit_instr(nir_instr
*instr
)
447 const fs_builder abld
= bld
.annotate(NULL
, instr
);
449 switch (instr
->type
) {
450 case nir_instr_type_alu
:
451 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
454 case nir_instr_type_intrinsic
:
455 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
458 case nir_instr_type_tex
:
459 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
462 case nir_instr_type_load_const
:
463 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
466 case nir_instr_type_ssa_undef
:
467 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
470 case nir_instr_type_jump
:
471 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
475 unreachable("unknown instruction type");
480 brw_type_for_nir_type(nir_alu_type type
)
483 case nir_type_unsigned
:
484 return BRW_REGISTER_TYPE_UD
;
487 return BRW_REGISTER_TYPE_D
;
489 return BRW_REGISTER_TYPE_F
;
491 unreachable("unknown type");
494 return BRW_REGISTER_TYPE_F
;
498 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
499 const fs_reg
&result
)
501 if (!instr
->src
[0].src
.is_ssa
||
502 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
505 nir_intrinsic_instr
*src0
=
506 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
508 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
511 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
512 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
515 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
516 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
519 fs_reg tmp
= vgrf(glsl_type::int_type
);
521 if (devinfo
->gen
>= 6) {
522 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
523 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
525 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
527 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
528 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
530 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
532 * This negation looks like it's safe in practice, because bits 0:4 will
533 * surely be TRIANGLES
536 if (value1
->f
[0] == -1.0f
) {
540 tmp
.type
= BRW_REGISTER_TYPE_W
;
541 tmp
.subreg_offset
= 2;
544 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
545 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
547 tmp
.type
= BRW_REGISTER_TYPE_D
;
548 tmp
.subreg_offset
= 0;
551 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
552 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
554 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
556 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
557 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
559 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
561 * This negation looks like it's safe in practice, because bits 0:4 will
562 * surely be TRIANGLES
565 if (value1
->f
[0] == -1.0f
) {
569 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
571 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
577 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
579 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
582 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
583 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
586 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
587 op
[i
] = get_nir_src(instr
->src
[i
].src
);
588 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
589 op
[i
].abs
= instr
->src
[i
].abs
;
590 op
[i
].negate
= instr
->src
[i
].negate
;
593 /* We get a bunch of mov's out of the from_ssa pass and they may still
594 * be vectorized. We'll handle them as a special-case. We'll also
595 * handle vecN here because it's basically the same thing.
603 fs_reg temp
= result
;
604 bool need_extra_copy
= false;
605 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
606 if (!instr
->src
[i
].src
.is_ssa
&&
607 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
608 need_extra_copy
= true;
609 temp
= bld
.vgrf(result
.type
, 4);
614 for (unsigned i
= 0; i
< 4; i
++) {
615 if (!(instr
->dest
.write_mask
& (1 << i
)))
618 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
619 inst
= bld
.MOV(offset(temp
, bld
, i
),
620 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
622 inst
= bld
.MOV(offset(temp
, bld
, i
),
623 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
625 inst
->saturate
= instr
->dest
.saturate
;
628 /* In this case the source and destination registers were the same,
629 * so we need to insert an extra set of moves in order to deal with
632 if (need_extra_copy
) {
633 for (unsigned i
= 0; i
< 4; i
++) {
634 if (!(instr
->dest
.write_mask
& (1 << i
)))
637 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
646 /* At this point, we have dealt with any instruction that operates on
647 * more than a single channel. Therefore, we can just adjust the source
648 * and destination registers for that channel and emit the instruction.
650 unsigned channel
= 0;
651 if (nir_op_infos
[instr
->op
].output_size
== 0) {
652 /* Since NIR is doing the scalarizing for us, we should only ever see
653 * vectorized operations with a single channel.
655 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
656 channel
= ffs(instr
->dest
.write_mask
) - 1;
658 result
= offset(result
, bld
, channel
);
661 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
662 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
663 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
669 inst
= bld
.MOV(result
, op
[0]);
670 inst
->saturate
= instr
->dest
.saturate
;
675 bld
.MOV(result
, op
[0]);
679 /* AND(val, 0x80000000) gives the sign bit.
681 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
684 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
686 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
687 op
[0].type
= BRW_REGISTER_TYPE_UD
;
688 result
.type
= BRW_REGISTER_TYPE_UD
;
689 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
691 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
692 inst
->predicate
= BRW_PREDICATE_NORMAL
;
693 if (instr
->dest
.saturate
) {
694 inst
= bld
.MOV(result
, result
);
695 inst
->saturate
= true;
701 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
702 * -> non-negative val generates 0x00000000.
703 * Predicated OR sets 1 if val is positive.
705 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
706 bld
.ASR(result
, op
[0], fs_reg(31));
707 inst
= bld
.OR(result
, result
, fs_reg(1));
708 inst
->predicate
= BRW_PREDICATE_NORMAL
;
712 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
713 inst
->saturate
= instr
->dest
.saturate
;
717 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
718 inst
->saturate
= instr
->dest
.saturate
;
722 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
723 inst
->saturate
= instr
->dest
.saturate
;
727 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
728 inst
->saturate
= instr
->dest
.saturate
;
732 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
733 inst
->saturate
= instr
->dest
.saturate
;
737 if (fs_key
->high_quality_derivatives
) {
738 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
740 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
742 inst
->saturate
= instr
->dest
.saturate
;
744 case nir_op_fddx_fine
:
745 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
746 inst
->saturate
= instr
->dest
.saturate
;
748 case nir_op_fddx_coarse
:
749 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
750 inst
->saturate
= instr
->dest
.saturate
;
753 if (fs_key
->high_quality_derivatives
) {
754 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
755 fs_reg(fs_key
->render_to_fbo
));
757 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
758 fs_reg(fs_key
->render_to_fbo
));
760 inst
->saturate
= instr
->dest
.saturate
;
762 case nir_op_fddy_fine
:
763 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
764 fs_reg(fs_key
->render_to_fbo
));
765 inst
->saturate
= instr
->dest
.saturate
;
767 case nir_op_fddy_coarse
:
768 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
769 fs_reg(fs_key
->render_to_fbo
));
770 inst
->saturate
= instr
->dest
.saturate
;
775 inst
= bld
.ADD(result
, op
[0], op
[1]);
776 inst
->saturate
= instr
->dest
.saturate
;
780 inst
= bld
.MUL(result
, op
[0], op
[1]);
781 inst
->saturate
= instr
->dest
.saturate
;
785 bld
.MUL(result
, op
[0], op
[1]);
788 case nir_op_imul_high
:
789 case nir_op_umul_high
: {
790 if (devinfo
->gen
>= 7)
791 no16("SIMD16 explicit accumulator operands unsupported\n");
793 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
795 fs_inst
*mul
= bld
.MUL(acc
, op
[0], op
[1]);
796 bld
.MACH(result
, op
[0], op
[1]);
798 /* Until Gen8, integer multiplies read 32-bits from one source, and
799 * 16-bits from the other, and relying on the MACH instruction to
800 * generate the high bits of the result.
802 * On Gen8, the multiply instruction does a full 32x32-bit multiply,
803 * but in order to do a 64x64-bit multiply we have to simulate the
804 * previous behavior and then use a MACH instruction.
806 * FINISHME: Don't use source modifiers on src1.
808 if (devinfo
->gen
>= 8) {
809 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
810 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
811 if (mul
->src
[1].type
== BRW_REGISTER_TYPE_D
) {
812 mul
->src
[1].type
= BRW_REGISTER_TYPE_W
;
813 mul
->src
[1].stride
= 2;
815 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
816 mul
->src
[1].stride
= 2;
824 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
827 case nir_op_uadd_carry
:
828 unreachable("Should have been lowered by carry_to_arith().");
830 case nir_op_usub_borrow
:
831 unreachable("Should have been lowered by borrow_to_arith().");
834 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
840 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
846 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
851 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
856 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
860 if (devinfo
->gen
>= 8) {
861 resolve_source_modifiers(&op
[0]);
863 bld
.NOT(result
, op
[0]);
866 if (devinfo
->gen
>= 8) {
867 resolve_source_modifiers(&op
[0]);
868 resolve_source_modifiers(&op
[1]);
870 bld
.XOR(result
, op
[0], op
[1]);
873 if (devinfo
->gen
>= 8) {
874 resolve_source_modifiers(&op
[0]);
875 resolve_source_modifiers(&op
[1]);
877 bld
.OR(result
, op
[0], op
[1]);
880 if (devinfo
->gen
>= 8) {
881 resolve_source_modifiers(&op
[0]);
882 resolve_source_modifiers(&op
[1]);
884 bld
.AND(result
, op
[0], op
[1]);
896 case nir_op_ball_fequal2
:
897 case nir_op_ball_iequal2
:
898 case nir_op_ball_fequal3
:
899 case nir_op_ball_iequal3
:
900 case nir_op_ball_fequal4
:
901 case nir_op_ball_iequal4
:
902 case nir_op_bany_fnequal2
:
903 case nir_op_bany_inequal2
:
904 case nir_op_bany_fnequal3
:
905 case nir_op_bany_inequal3
:
906 case nir_op_bany_fnequal4
:
907 case nir_op_bany_inequal4
:
908 unreachable("Lowered by nir_lower_alu_reductions");
910 case nir_op_fnoise1_1
:
911 case nir_op_fnoise1_2
:
912 case nir_op_fnoise1_3
:
913 case nir_op_fnoise1_4
:
914 case nir_op_fnoise2_1
:
915 case nir_op_fnoise2_2
:
916 case nir_op_fnoise2_3
:
917 case nir_op_fnoise2_4
:
918 case nir_op_fnoise3_1
:
919 case nir_op_fnoise3_2
:
920 case nir_op_fnoise3_3
:
921 case nir_op_fnoise3_4
:
922 case nir_op_fnoise4_1
:
923 case nir_op_fnoise4_2
:
924 case nir_op_fnoise4_3
:
925 case nir_op_fnoise4_4
:
926 unreachable("not reached: should be handled by lower_noise");
929 unreachable("not reached: should be handled by ldexp_to_arith()");
932 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
933 inst
->saturate
= instr
->dest
.saturate
;
937 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
938 inst
->saturate
= instr
->dest
.saturate
;
943 bld
.MOV(result
, negate(op
[0]));
947 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
950 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
954 inst
= bld
.RNDZ(result
, op
[0]);
955 inst
->saturate
= instr
->dest
.saturate
;
959 op
[0].negate
= !op
[0].negate
;
960 fs_reg temp
= vgrf(glsl_type::float_type
);
961 bld
.RNDD(temp
, op
[0]);
963 inst
= bld
.MOV(result
, temp
);
964 inst
->saturate
= instr
->dest
.saturate
;
968 inst
= bld
.RNDD(result
, op
[0]);
969 inst
->saturate
= instr
->dest
.saturate
;
972 inst
= bld
.FRC(result
, op
[0]);
973 inst
->saturate
= instr
->dest
.saturate
;
975 case nir_op_fround_even
:
976 inst
= bld
.RNDE(result
, op
[0]);
977 inst
->saturate
= instr
->dest
.saturate
;
983 if (devinfo
->gen
>= 6) {
984 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
985 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
987 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
988 inst
= bld
.SEL(result
, op
[0], op
[1]);
989 inst
->predicate
= BRW_PREDICATE_NORMAL
;
991 inst
->saturate
= instr
->dest
.saturate
;
997 if (devinfo
->gen
>= 6) {
998 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
999 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1001 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
1002 inst
= bld
.SEL(result
, op
[0], op
[1]);
1003 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1005 inst
->saturate
= instr
->dest
.saturate
;
1008 case nir_op_pack_snorm_2x16
:
1009 case nir_op_pack_snorm_4x8
:
1010 case nir_op_pack_unorm_2x16
:
1011 case nir_op_pack_unorm_4x8
:
1012 case nir_op_unpack_snorm_2x16
:
1013 case nir_op_unpack_snorm_4x8
:
1014 case nir_op_unpack_unorm_2x16
:
1015 case nir_op_unpack_unorm_4x8
:
1016 case nir_op_unpack_half_2x16
:
1017 case nir_op_pack_half_2x16
:
1018 unreachable("not reached: should be handled by lower_packing_builtins");
1020 case nir_op_unpack_half_2x16_split_x
:
1021 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1022 inst
->saturate
= instr
->dest
.saturate
;
1024 case nir_op_unpack_half_2x16_split_y
:
1025 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1026 inst
->saturate
= instr
->dest
.saturate
;
1030 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1031 inst
->saturate
= instr
->dest
.saturate
;
1034 case nir_op_bitfield_reverse
:
1035 bld
.BFREV(result
, op
[0]);
1038 case nir_op_bit_count
:
1039 bld
.CBIT(result
, op
[0]);
1042 case nir_op_ufind_msb
:
1043 case nir_op_ifind_msb
: {
1044 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1046 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1047 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1048 * subtract the result from 31 to convert the MSB count into an LSB count.
1051 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
1052 fs_reg
neg_result(result
);
1053 neg_result
.negate
= true;
1054 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
1055 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1059 case nir_op_find_lsb
:
1060 bld
.FBL(result
, op
[0]);
1063 case nir_op_ubitfield_extract
:
1064 case nir_op_ibitfield_extract
:
1065 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1068 bld
.BFI1(result
, op
[0], op
[1]);
1071 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1074 case nir_op_bitfield_insert
:
1075 unreachable("not reached: should be handled by "
1076 "lower_instructions::bitfield_insert_to_bfm_bfi");
1079 bld
.SHL(result
, op
[0], op
[1]);
1082 bld
.ASR(result
, op
[0], op
[1]);
1085 bld
.SHR(result
, op
[0], op
[1]);
1088 case nir_op_pack_half_2x16_split
:
1089 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1093 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1094 inst
->saturate
= instr
->dest
.saturate
;
1098 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1099 inst
->saturate
= instr
->dest
.saturate
;
1103 if (optimize_frontfacing_ternary(instr
, result
))
1106 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
1107 inst
= bld
.SEL(result
, op
[1], op
[2]);
1108 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1112 unreachable("unhandled instruction");
1115 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1116 * to sign extend the low bit to 0/~0
1118 if (devinfo
->gen
<= 5 &&
1119 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1120 fs_reg masked
= vgrf(glsl_type::int_type
);
1121 bld
.AND(masked
, result
, fs_reg(1));
1122 masked
.negate
= true;
1123 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1128 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1129 nir_load_const_instr
*instr
)
1131 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1133 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1134 bld
.MOV(offset(reg
, bld
, i
), fs_reg(instr
->value
.i
[i
]));
1136 nir_ssa_values
[instr
->def
.index
] = reg
;
1140 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1142 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1143 instr
->def
.num_components
);
1147 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1148 unsigned base_offset
, nir_src
*indirect
)
1152 assert(!nir_reg
->is_global
);
1154 reg
= v
->nir_locals
[nir_reg
->index
];
1156 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1158 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1160 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1161 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1162 fs_reg(multiplier
));
1169 fs_visitor::get_nir_src(nir_src src
)
1173 reg
= nir_ssa_values
[src
.ssa
->index
];
1175 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1179 /* to avoid floating-point denorm flushing problems, set the type by
1180 * default to D - instructions that need floating point semantics will set
1181 * this to F if they need to
1183 return retype(reg
, BRW_REGISTER_TYPE_D
);
1187 fs_visitor::get_nir_dest(nir_dest dest
)
1190 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1191 dest
.ssa
.num_components
);
1192 return nir_ssa_values
[dest
.ssa
.index
];
1195 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1200 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1203 for (unsigned i
= 0; i
< 4; i
++) {
1204 if (!((wr_mask
>> i
) & 1))
1207 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1208 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1209 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1210 if (new_inst
->src
[j
].file
== GRF
)
1211 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1218 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1221 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1222 dest
= get_nir_dest(instr
->dest
);
1224 bool has_indirect
= false;
1226 switch (instr
->intrinsic
) {
1227 case nir_intrinsic_discard
:
1228 case nir_intrinsic_discard_if
: {
1229 /* We track our discarded pixels in f0.1. By predicating on it, we can
1230 * update just the flag bits that aren't yet discarded. If there's no
1231 * condition, we emit a CMP of g0 != g0, so all currently executing
1232 * channels will get turned off.
1235 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1236 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1237 fs_reg(0), BRW_CONDITIONAL_Z
);
1239 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1240 BRW_REGISTER_TYPE_UW
));
1241 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1243 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1244 cmp
->flag_subreg
= 1;
1246 if (devinfo
->gen
>= 6) {
1247 emit_discard_jump();
1252 case nir_intrinsic_atomic_counter_inc
:
1253 case nir_intrinsic_atomic_counter_dec
:
1254 case nir_intrinsic_atomic_counter_read
: {
1255 using namespace surface_access
;
1257 /* Get the arguments of the atomic intrinsic. */
1258 const fs_reg offset
= get_nir_src(instr
->src
[0]);
1259 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
1260 instr
->const_index
[0]);
1263 /* Emit a surface read or atomic op. */
1264 switch (instr
->intrinsic
) {
1265 case nir_intrinsic_atomic_counter_read
:
1266 tmp
= emit_untyped_read(bld
, fs_reg(surface
), offset
, 1, 1);
1269 case nir_intrinsic_atomic_counter_inc
:
1270 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1271 fs_reg(), 1, 1, BRW_AOP_INC
);
1274 case nir_intrinsic_atomic_counter_dec
:
1275 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1276 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
1280 unreachable("Unreachable");
1283 /* Assign the result. */
1284 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
1286 /* Mark the surface as used. */
1287 brw_mark_surface_used(stage_prog_data
, surface
);
1291 case nir_intrinsic_memory_barrier
: {
1292 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
1293 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
1298 case nir_intrinsic_load_front_face
:
1299 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1300 *emit_frontfacing_interpolation());
1303 case nir_intrinsic_load_vertex_id
:
1304 unreachable("should be lowered by lower_vertex_id()");
1306 case nir_intrinsic_load_vertex_id_zero_base
: {
1307 fs_reg vertex_id
= nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
1308 assert(vertex_id
.file
!= BAD_FILE
);
1309 dest
.type
= vertex_id
.type
;
1310 bld
.MOV(dest
, vertex_id
);
1314 case nir_intrinsic_load_base_vertex
: {
1315 fs_reg base_vertex
= nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
1316 assert(base_vertex
.file
!= BAD_FILE
);
1317 dest
.type
= base_vertex
.type
;
1318 bld
.MOV(dest
, base_vertex
);
1322 case nir_intrinsic_load_instance_id
: {
1323 fs_reg instance_id
= nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
1324 assert(instance_id
.file
!= BAD_FILE
);
1325 dest
.type
= instance_id
.type
;
1326 bld
.MOV(dest
, instance_id
);
1330 case nir_intrinsic_load_sample_mask_in
: {
1331 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1332 assert(sample_mask_in
.file
!= BAD_FILE
);
1333 dest
.type
= sample_mask_in
.type
;
1334 bld
.MOV(dest
, sample_mask_in
);
1338 case nir_intrinsic_load_sample_pos
: {
1339 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1340 assert(sample_pos
.file
!= BAD_FILE
);
1341 dest
.type
= sample_pos
.type
;
1342 bld
.MOV(dest
, sample_pos
);
1343 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1347 case nir_intrinsic_load_sample_id
: {
1348 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1349 assert(sample_id
.file
!= BAD_FILE
);
1350 dest
.type
= sample_id
.type
;
1351 bld
.MOV(dest
, sample_id
);
1355 case nir_intrinsic_load_uniform_indirect
:
1356 has_indirect
= true;
1358 case nir_intrinsic_load_uniform
: {
1359 unsigned index
= instr
->const_index
[0];
1362 if (index
< num_direct_uniforms
) {
1363 uniform_reg
= fs_reg(UNIFORM
, 0);
1365 uniform_reg
= fs_reg(UNIFORM
, num_direct_uniforms
);
1366 index
-= num_direct_uniforms
;
1369 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1370 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, index
);
1372 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1376 dest
= offset(dest
, bld
, 1);
1381 case nir_intrinsic_load_ubo_indirect
:
1382 has_indirect
= true;
1384 case nir_intrinsic_load_ubo
: {
1385 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1389 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1392 /* The block index is not a constant. Evaluate the index expression
1393 * per-channel and add the base UBO index; we have to select a value
1394 * from any live channel.
1396 surf_index
= vgrf(glsl_type::uint_type
);
1397 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1398 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1399 surf_index
= bld
.emit_uniformize(surf_index
);
1401 /* Assume this may touch any UBO. It would be nice to provide
1402 * a tighter bound, but the array information is already lowered away.
1404 brw_mark_surface_used(prog_data
,
1405 stage_prog_data
->binding_table
.ubo_start
+
1406 shader_prog
->NumUniformBlocks
- 1);
1410 /* Turn the byte offset into a dword offset. */
1411 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1412 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1413 BRW_REGISTER_TYPE_D
),
1416 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1417 for (int i
= 0; i
< instr
->num_components
; i
++)
1418 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
1419 base_offset
, vec4_offset
+ i
);
1421 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1422 packed_consts
.type
= dest
.type
;
1424 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1425 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1426 surf_index
, const_offset_reg
);
1428 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1429 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1431 /* The std140 packing rules don't allow vectors to cross 16-byte
1432 * boundaries, and a reg is 32 bytes.
1434 assert(packed_consts
.subreg_offset
< 32);
1436 bld
.MOV(dest
, packed_consts
);
1437 dest
= offset(dest
, bld
, 1);
1443 case nir_intrinsic_load_input_indirect
:
1444 has_indirect
= true;
1446 case nir_intrinsic_load_input
: {
1448 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1449 fs_reg src
= offset(retype(nir_inputs
, dest
.type
), bld
,
1450 instr
->const_index
[0] + index
);
1452 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1456 dest
= offset(dest
, bld
, 1);
1461 /* Handle ARB_gpu_shader5 interpolation intrinsics
1463 * It's worth a quick word of explanation as to why we handle the full
1464 * variable-based interpolation intrinsic rather than a lowered version
1465 * with like we do for other inputs. We have to do that because the way
1466 * we set up inputs doesn't allow us to use the already setup inputs for
1467 * interpolation. At the beginning of the shader, we go through all of
1468 * the input variables and do the initial interpolation and put it in
1469 * the nir_inputs array based on its location as determined in
1470 * nir_lower_io. If the input isn't used, dead code cleans up and
1471 * everything works fine. However, when we get to the ARB_gpu_shader5
1472 * interpolation intrinsics, we need to reinterpolate the input
1473 * differently. If we used an intrinsic that just had an index it would
1474 * only give us the offset into the nir_inputs array. However, this is
1475 * useless because that value is post-interpolation and we need
1476 * pre-interpolation. In order to get the actual location of the bits
1477 * we get from the vertex fetching hardware, we need the variable.
1479 case nir_intrinsic_interp_var_at_centroid
:
1480 case nir_intrinsic_interp_var_at_sample
:
1481 case nir_intrinsic_interp_var_at_offset
: {
1482 assert(stage
== MESA_SHADER_FRAGMENT
);
1484 ((struct brw_wm_prog_data
*) prog_data
)->pulls_bary
= true;
1486 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1488 /* For most messages, we need one reg of ignored data; the hardware
1489 * requires mlen==1 even when there is no payload. in the per-slot
1490 * offset case, we'll replace this with the proper source data.
1492 fs_reg src
= vgrf(glsl_type::float_type
);
1493 int mlen
= 1; /* one reg unless overriden */
1496 switch (instr
->intrinsic
) {
1497 case nir_intrinsic_interp_var_at_centroid
:
1498 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1499 dst_xy
, src
, fs_reg(0u));
1502 case nir_intrinsic_interp_var_at_sample
: {
1503 /* XXX: We should probably handle non-constant sample id's */
1504 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1505 assert(const_sample
);
1506 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1507 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_xy
, src
,
1512 case nir_intrinsic_interp_var_at_offset
: {
1513 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1516 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1517 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1519 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_xy
, src
,
1520 fs_reg(off_x
| (off_y
<< 4)));
1522 src
= vgrf(glsl_type::ivec2_type
);
1523 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1524 BRW_REGISTER_TYPE_F
);
1525 for (int i
= 0; i
< 2; i
++) {
1526 fs_reg temp
= vgrf(glsl_type::float_type
);
1527 bld
.MUL(temp
, offset(offset_src
, bld
, i
), fs_reg(16.0f
));
1528 fs_reg itemp
= vgrf(glsl_type::int_type
);
1529 bld
.MOV(itemp
, temp
); /* float to int */
1531 /* Clamp the upper end of the range to +7/16.
1532 * ARB_gpu_shader5 requires that we support a maximum offset
1533 * of +0.5, which isn't representable in a S0.4 value -- if
1534 * we didn't clamp it, we'd end up with -8/16, which is the
1535 * opposite of what the shader author wanted.
1537 * This is legal due to ARB_gpu_shader5's quantization
1540 * "Not all values of <offset> may be supported; x and y
1541 * offsets may be rounded to fixed-point values with the
1542 * number of fraction bits given by the
1543 * implementation-dependent constant
1544 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1546 set_condmod(BRW_CONDITIONAL_L
,
1547 bld
.SEL(offset(src
, bld
, i
), itemp
, fs_reg(7)));
1550 mlen
= 2 * dispatch_width
/ 8;
1551 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_xy
, src
,
1558 unreachable("Invalid intrinsic");
1562 /* 2 floats per slot returned */
1563 inst
->regs_written
= 2 * dispatch_width
/ 8;
1564 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1565 INTERP_QUALIFIER_NOPERSPECTIVE
;
1567 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1568 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1569 src
.type
= dest
.type
;
1571 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1572 dest
= offset(dest
, bld
, 1);
1577 case nir_intrinsic_store_output_indirect
:
1578 has_indirect
= true;
1580 case nir_intrinsic_store_output
: {
1581 fs_reg src
= get_nir_src(instr
->src
[0]);
1583 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1584 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
1585 instr
->const_index
[0] + index
);
1587 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1589 bld
.MOV(new_dest
, src
);
1590 src
= offset(src
, bld
, 1);
1595 case nir_intrinsic_barrier
:
1600 unreachable("unknown intrinsic");
1605 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1607 unsigned sampler
= instr
->sampler_index
;
1608 fs_reg
sampler_reg(sampler
);
1610 /* FINISHME: We're failing to recompile our programs when the sampler is
1611 * updated. This only matters for the texture rectangle scale parameters
1612 * (pre-gen6, or gen6+ with GL_CLAMP).
1614 int texunit
= prog
->SamplerUnits
[sampler
];
1616 int gather_component
= instr
->component
;
1618 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1620 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1623 int lod_components
= 0;
1624 int UNUSED offset_components
= 0;
1626 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1628 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1629 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1630 switch (instr
->src
[i
].src_type
) {
1631 case nir_tex_src_bias
:
1632 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1634 case nir_tex_src_comparitor
:
1635 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1637 case nir_tex_src_coord
:
1638 switch (instr
->op
) {
1640 case nir_texop_txf_ms
:
1641 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1644 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1648 case nir_tex_src_ddx
:
1649 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1650 lod_components
= nir_tex_instr_src_size(instr
, i
);
1652 case nir_tex_src_ddy
:
1653 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1655 case nir_tex_src_lod
:
1656 switch (instr
->op
) {
1658 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1661 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1664 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1668 case nir_tex_src_ms_index
:
1669 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1671 case nir_tex_src_offset
:
1672 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1673 if (instr
->is_array
)
1674 offset_components
= instr
->coord_components
- 1;
1676 offset_components
= instr
->coord_components
;
1678 case nir_tex_src_projector
:
1679 unreachable("should be lowered");
1681 case nir_tex_src_sampler_offset
: {
1682 /* Figure out the highest possible sampler index and mark it as used */
1683 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1684 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
1685 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1687 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1689 brw_mark_surface_used(prog_data
, max_used
);
1691 /* Emit code to evaluate the actual indexing expression */
1692 sampler_reg
= vgrf(glsl_type::uint_type
);
1693 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
1694 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
1699 unreachable("unknown texture source");
1703 if (instr
->op
== nir_texop_txf_ms
) {
1704 if (devinfo
->gen
>= 7 &&
1705 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1706 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1712 for (unsigned i
= 0; i
< 3; i
++) {
1713 if (instr
->const_offset
[i
] != 0) {
1714 assert(offset_components
== 0);
1715 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
1720 enum glsl_base_type dest_base_type
;
1721 switch (instr
->dest_type
) {
1722 case nir_type_float
:
1723 dest_base_type
= GLSL_TYPE_FLOAT
;
1726 dest_base_type
= GLSL_TYPE_INT
;
1728 case nir_type_unsigned
:
1729 dest_base_type
= GLSL_TYPE_UINT
;
1732 unreachable("bad type");
1735 const glsl_type
*dest_type
=
1736 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1739 ir_texture_opcode op
;
1740 switch (instr
->op
) {
1741 case nir_texop_lod
: op
= ir_lod
; break;
1742 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1743 case nir_texop_tex
: op
= ir_tex
; break;
1744 case nir_texop_tg4
: op
= ir_tg4
; break;
1745 case nir_texop_txb
: op
= ir_txb
; break;
1746 case nir_texop_txd
: op
= ir_txd
; break;
1747 case nir_texop_txf
: op
= ir_txf
; break;
1748 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1749 case nir_texop_txl
: op
= ir_txl
; break;
1750 case nir_texop_txs
: op
= ir_txs
; break;
1752 unreachable("unknown texture opcode");
1755 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1756 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1757 tex_offset
, mcs
, gather_component
,
1758 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1760 fs_reg dest
= get_nir_dest(instr
->dest
);
1761 dest
.type
= this->result
.type
;
1762 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1763 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
1764 dest
, this->result
),
1765 (1 << num_components
) - 1);
1769 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
1771 switch (instr
->type
) {
1772 case nir_jump_break
:
1773 bld
.emit(BRW_OPCODE_BREAK
);
1775 case nir_jump_continue
:
1776 bld
.emit(BRW_OPCODE_CONTINUE
);
1778 case nir_jump_return
:
1780 unreachable("unknown jump");