2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "main/shaderimage.h"
28 #include "program/prog_to_nir.h"
30 #include "brw_fs_surface_builder.h"
31 #include "brw_vec4_gs_visitor.h"
33 #include "brw_fs_surface_builder.h"
34 #include "brw_vec4_gs_visitor.h"
37 using namespace brw::surface_access
;
40 fs_visitor::emit_nir_code()
42 /* emit the arrays used for inputs and outputs - load/store intrinsics will
43 * be converted to reads/writes of these arrays
48 nir_emit_system_values();
50 /* get the main function and emit it */
51 nir_foreach_overload(nir
, overload
) {
52 assert(strcmp(overload
->function
->name
, "main") == 0);
53 assert(overload
->impl
);
54 nir_emit_impl(overload
->impl
);
59 fs_visitor::nir_setup_inputs()
61 if (stage
!= MESA_SHADER_FRAGMENT
)
64 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
66 nir_foreach_variable(var
, &nir
->inputs
) {
67 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
70 if (var
->data
.location
== VARYING_SLOT_POS
) {
71 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
72 var
->data
.origin_upper_left
);
73 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
75 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
76 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
77 reg
.type
= BRW_REGISTER_TYPE_D
;
78 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
79 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
80 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
81 reg
.type
= BRW_REGISTER_TYPE_D
;
82 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
84 emit_general_interpolation(input
, var
->name
, var
->type
,
85 (glsl_interp_qualifier
) var
->data
.interpolation
,
86 var
->data
.location
, var
->data
.centroid
,
93 fs_visitor::nir_setup_outputs()
95 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
97 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
99 nir_foreach_variable(var
, &nir
->outputs
) {
100 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
102 int vector_elements
= var
->type
->without_array()->vector_elements
;
105 case MESA_SHADER_VERTEX
:
106 case MESA_SHADER_GEOMETRY
:
107 for (int i
= 0; i
< type_size_vec4(var
->type
); i
++) {
108 int output
= var
->data
.location
+ i
;
109 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
110 this->output_components
[output
] = vector_elements
;
113 case MESA_SHADER_FRAGMENT
:
114 if (var
->data
.index
> 0) {
115 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
116 assert(var
->data
.index
== 1);
117 this->dual_src_output
= reg
;
118 this->do_dual_src
= true;
119 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
120 /* Writing gl_FragColor outputs to all color regions. */
121 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
122 this->outputs
[i
] = reg
;
123 this->output_components
[i
] = 4;
125 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
126 this->frag_depth
= reg
;
127 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
128 this->frag_stencil
= reg
;
129 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
130 this->sample_mask
= reg
;
132 /* gl_FragData or a user-defined FS output */
133 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
134 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
136 /* General color output. */
137 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
138 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
139 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
140 this->output_components
[output
] = vector_elements
;
145 unreachable("unhandled shader stage");
151 fs_visitor::nir_setup_uniforms()
153 if (dispatch_width
!= 8)
156 uniforms
= nir
->num_uniforms
;
158 nir_foreach_variable(var
, &nir
->uniforms
) {
159 /* UBO's and atomics don't take up space in the uniform file */
160 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
163 if (type_size_scalar(var
->type
) > 0)
164 param_size
[var
->data
.driver_location
] = type_size_scalar(var
->type
);
169 emit_system_values_block(nir_block
*block
, void *void_visitor
)
171 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
174 nir_foreach_instr(block
, instr
) {
175 if (instr
->type
!= nir_instr_type_intrinsic
)
178 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
179 switch (intrin
->intrinsic
) {
180 case nir_intrinsic_load_vertex_id
:
181 unreachable("should be lowered by lower_vertex_id().");
183 case nir_intrinsic_load_vertex_id_zero_base
:
184 assert(v
->stage
== MESA_SHADER_VERTEX
);
185 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
186 if (reg
->file
== BAD_FILE
)
187 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
190 case nir_intrinsic_load_base_vertex
:
191 assert(v
->stage
== MESA_SHADER_VERTEX
);
192 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
193 if (reg
->file
== BAD_FILE
)
194 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
197 case nir_intrinsic_load_instance_id
:
198 assert(v
->stage
== MESA_SHADER_VERTEX
);
199 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
200 if (reg
->file
== BAD_FILE
)
201 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
204 case nir_intrinsic_load_invocation_id
:
205 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
206 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
207 if (reg
->file
== BAD_FILE
) {
208 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
209 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
210 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
211 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
216 case nir_intrinsic_load_sample_pos
:
217 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
218 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
219 if (reg
->file
== BAD_FILE
)
220 *reg
= *v
->emit_samplepos_setup();
223 case nir_intrinsic_load_sample_id
:
224 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
225 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
226 if (reg
->file
== BAD_FILE
)
227 *reg
= *v
->emit_sampleid_setup();
230 case nir_intrinsic_load_sample_mask_in
:
231 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
232 assert(v
->devinfo
->gen
>= 7);
233 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
234 if (reg
->file
== BAD_FILE
)
235 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
236 BRW_REGISTER_TYPE_D
));
239 case nir_intrinsic_load_local_invocation_id
:
240 assert(v
->stage
== MESA_SHADER_COMPUTE
);
241 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
242 if (reg
->file
== BAD_FILE
)
243 *reg
= *v
->emit_cs_local_invocation_id_setup();
246 case nir_intrinsic_load_work_group_id
:
247 assert(v
->stage
== MESA_SHADER_COMPUTE
);
248 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
249 if (reg
->file
== BAD_FILE
)
250 *reg
= *v
->emit_cs_work_group_id_setup();
262 fs_visitor::nir_emit_system_values()
264 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
265 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
266 nir_system_values
[i
] = fs_reg();
269 nir_foreach_overload(nir
, overload
) {
270 assert(strcmp(overload
->function
->name
, "main") == 0);
271 assert(overload
->impl
);
272 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
277 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
279 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
280 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
281 nir_locals
[i
] = fs_reg();
284 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
285 unsigned array_elems
=
286 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
287 unsigned size
= array_elems
* reg
->num_components
;
288 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
291 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
294 nir_emit_cf_list(&impl
->body
);
298 fs_visitor::nir_emit_cf_list(exec_list
*list
)
300 exec_list_validate(list
);
301 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
302 switch (node
->type
) {
304 nir_emit_if(nir_cf_node_as_if(node
));
307 case nir_cf_node_loop
:
308 nir_emit_loop(nir_cf_node_as_loop(node
));
311 case nir_cf_node_block
:
312 nir_emit_block(nir_cf_node_as_block(node
));
316 unreachable("Invalid CFG node block");
322 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
324 /* first, put the condition into f0 */
325 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
326 retype(get_nir_src(if_stmt
->condition
),
327 BRW_REGISTER_TYPE_D
));
328 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
330 bld
.IF(BRW_PREDICATE_NORMAL
);
332 nir_emit_cf_list(&if_stmt
->then_list
);
334 /* note: if the else is empty, dead CF elimination will remove it */
335 bld
.emit(BRW_OPCODE_ELSE
);
337 nir_emit_cf_list(&if_stmt
->else_list
);
339 bld
.emit(BRW_OPCODE_ENDIF
);
343 fs_visitor::nir_emit_loop(nir_loop
*loop
)
345 bld
.emit(BRW_OPCODE_DO
);
347 nir_emit_cf_list(&loop
->body
);
349 bld
.emit(BRW_OPCODE_WHILE
);
353 fs_visitor::nir_emit_block(nir_block
*block
)
355 nir_foreach_instr(block
, instr
) {
356 nir_emit_instr(instr
);
361 fs_visitor::nir_emit_instr(nir_instr
*instr
)
363 const fs_builder abld
= bld
.annotate(NULL
, instr
);
365 switch (instr
->type
) {
366 case nir_instr_type_alu
:
367 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
370 case nir_instr_type_intrinsic
:
372 case MESA_SHADER_VERTEX
:
373 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
375 case MESA_SHADER_GEOMETRY
:
376 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
378 case MESA_SHADER_FRAGMENT
:
379 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
381 case MESA_SHADER_COMPUTE
:
382 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
385 unreachable("unsupported shader stage");
389 case nir_instr_type_tex
:
390 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
393 case nir_instr_type_load_const
:
394 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
397 case nir_instr_type_ssa_undef
:
398 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
401 case nir_instr_type_jump
:
402 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
406 unreachable("unknown instruction type");
411 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
412 const fs_reg
&result
)
414 if (!instr
->src
[0].src
.is_ssa
||
415 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
418 nir_intrinsic_instr
*src0
=
419 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
421 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
424 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
425 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
428 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
429 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
432 fs_reg tmp
= vgrf(glsl_type::int_type
);
434 if (devinfo
->gen
>= 6) {
435 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
436 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
438 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
440 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
441 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
443 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
445 * This negation looks like it's safe in practice, because bits 0:4 will
446 * surely be TRIANGLES
449 if (value1
->f
[0] == -1.0f
) {
453 tmp
.type
= BRW_REGISTER_TYPE_W
;
454 tmp
.subreg_offset
= 2;
457 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
459 tmp
.type
= BRW_REGISTER_TYPE_D
;
460 tmp
.subreg_offset
= 0;
463 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
464 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
466 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
468 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
469 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
471 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
473 * This negation looks like it's safe in practice, because bits 0:4 will
474 * surely be TRIANGLES
477 if (value1
->f
[0] == -1.0f
) {
481 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
483 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
489 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
491 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
494 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
495 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
498 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
499 op
[i
] = get_nir_src(instr
->src
[i
].src
);
500 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
501 op
[i
].abs
= instr
->src
[i
].abs
;
502 op
[i
].negate
= instr
->src
[i
].negate
;
505 /* We get a bunch of mov's out of the from_ssa pass and they may still
506 * be vectorized. We'll handle them as a special-case. We'll also
507 * handle vecN here because it's basically the same thing.
515 fs_reg temp
= result
;
516 bool need_extra_copy
= false;
517 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
518 if (!instr
->src
[i
].src
.is_ssa
&&
519 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
520 need_extra_copy
= true;
521 temp
= bld
.vgrf(result
.type
, 4);
526 for (unsigned i
= 0; i
< 4; i
++) {
527 if (!(instr
->dest
.write_mask
& (1 << i
)))
530 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
531 inst
= bld
.MOV(offset(temp
, bld
, i
),
532 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
534 inst
= bld
.MOV(offset(temp
, bld
, i
),
535 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
537 inst
->saturate
= instr
->dest
.saturate
;
540 /* In this case the source and destination registers were the same,
541 * so we need to insert an extra set of moves in order to deal with
544 if (need_extra_copy
) {
545 for (unsigned i
= 0; i
< 4; i
++) {
546 if (!(instr
->dest
.write_mask
& (1 << i
)))
549 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
558 /* At this point, we have dealt with any instruction that operates on
559 * more than a single channel. Therefore, we can just adjust the source
560 * and destination registers for that channel and emit the instruction.
562 unsigned channel
= 0;
563 if (nir_op_infos
[instr
->op
].output_size
== 0) {
564 /* Since NIR is doing the scalarizing for us, we should only ever see
565 * vectorized operations with a single channel.
567 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
568 channel
= ffs(instr
->dest
.write_mask
) - 1;
570 result
= offset(result
, bld
, channel
);
573 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
574 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
575 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
581 inst
= bld
.MOV(result
, op
[0]);
582 inst
->saturate
= instr
->dest
.saturate
;
587 bld
.MOV(result
, op
[0]);
591 /* AND(val, 0x80000000) gives the sign bit.
593 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
596 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
598 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
599 op
[0].type
= BRW_REGISTER_TYPE_UD
;
600 result
.type
= BRW_REGISTER_TYPE_UD
;
601 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
603 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
604 inst
->predicate
= BRW_PREDICATE_NORMAL
;
605 if (instr
->dest
.saturate
) {
606 inst
= bld
.MOV(result
, result
);
607 inst
->saturate
= true;
613 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
614 * -> non-negative val generates 0x00000000.
615 * Predicated OR sets 1 if val is positive.
617 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
618 bld
.ASR(result
, op
[0], brw_imm_d(31));
619 inst
= bld
.OR(result
, result
, brw_imm_d(1));
620 inst
->predicate
= BRW_PREDICATE_NORMAL
;
624 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
625 inst
->saturate
= instr
->dest
.saturate
;
629 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
630 inst
->saturate
= instr
->dest
.saturate
;
634 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
635 inst
->saturate
= instr
->dest
.saturate
;
639 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
640 inst
->saturate
= instr
->dest
.saturate
;
644 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
645 inst
->saturate
= instr
->dest
.saturate
;
649 if (fs_key
->high_quality_derivatives
) {
650 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
652 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
654 inst
->saturate
= instr
->dest
.saturate
;
656 case nir_op_fddx_fine
:
657 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
658 inst
->saturate
= instr
->dest
.saturate
;
660 case nir_op_fddx_coarse
:
661 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
662 inst
->saturate
= instr
->dest
.saturate
;
665 if (fs_key
->high_quality_derivatives
) {
666 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
667 brw_imm_d(fs_key
->render_to_fbo
));
669 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
670 brw_imm_d(fs_key
->render_to_fbo
));
672 inst
->saturate
= instr
->dest
.saturate
;
674 case nir_op_fddy_fine
:
675 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
676 brw_imm_d(fs_key
->render_to_fbo
));
677 inst
->saturate
= instr
->dest
.saturate
;
679 case nir_op_fddy_coarse
:
680 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
681 brw_imm_d(fs_key
->render_to_fbo
));
682 inst
->saturate
= instr
->dest
.saturate
;
687 inst
= bld
.ADD(result
, op
[0], op
[1]);
688 inst
->saturate
= instr
->dest
.saturate
;
692 inst
= bld
.MUL(result
, op
[0], op
[1]);
693 inst
->saturate
= instr
->dest
.saturate
;
697 bld
.MUL(result
, op
[0], op
[1]);
700 case nir_op_imul_high
:
701 case nir_op_umul_high
:
702 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
707 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
710 case nir_op_uadd_carry
:
711 unreachable("Should have been lowered by carry_to_arith().");
713 case nir_op_usub_borrow
:
714 unreachable("Should have been lowered by borrow_to_arith().");
717 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
723 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
729 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
734 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
739 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
743 if (devinfo
->gen
>= 8) {
744 op
[0] = resolve_source_modifiers(op
[0]);
746 bld
.NOT(result
, op
[0]);
749 if (devinfo
->gen
>= 8) {
750 op
[0] = resolve_source_modifiers(op
[0]);
751 op
[1] = resolve_source_modifiers(op
[1]);
753 bld
.XOR(result
, op
[0], op
[1]);
756 if (devinfo
->gen
>= 8) {
757 op
[0] = resolve_source_modifiers(op
[0]);
758 op
[1] = resolve_source_modifiers(op
[1]);
760 bld
.OR(result
, op
[0], op
[1]);
763 if (devinfo
->gen
>= 8) {
764 op
[0] = resolve_source_modifiers(op
[0]);
765 op
[1] = resolve_source_modifiers(op
[1]);
767 bld
.AND(result
, op
[0], op
[1]);
779 case nir_op_ball_fequal2
:
780 case nir_op_ball_iequal2
:
781 case nir_op_ball_fequal3
:
782 case nir_op_ball_iequal3
:
783 case nir_op_ball_fequal4
:
784 case nir_op_ball_iequal4
:
785 case nir_op_bany_fnequal2
:
786 case nir_op_bany_inequal2
:
787 case nir_op_bany_fnequal3
:
788 case nir_op_bany_inequal3
:
789 case nir_op_bany_fnequal4
:
790 case nir_op_bany_inequal4
:
791 unreachable("Lowered by nir_lower_alu_reductions");
793 case nir_op_fnoise1_1
:
794 case nir_op_fnoise1_2
:
795 case nir_op_fnoise1_3
:
796 case nir_op_fnoise1_4
:
797 case nir_op_fnoise2_1
:
798 case nir_op_fnoise2_2
:
799 case nir_op_fnoise2_3
:
800 case nir_op_fnoise2_4
:
801 case nir_op_fnoise3_1
:
802 case nir_op_fnoise3_2
:
803 case nir_op_fnoise3_3
:
804 case nir_op_fnoise3_4
:
805 case nir_op_fnoise4_1
:
806 case nir_op_fnoise4_2
:
807 case nir_op_fnoise4_3
:
808 case nir_op_fnoise4_4
:
809 unreachable("not reached: should be handled by lower_noise");
812 unreachable("not reached: should be handled by ldexp_to_arith()");
815 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
816 inst
->saturate
= instr
->dest
.saturate
;
820 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
821 inst
->saturate
= instr
->dest
.saturate
;
826 bld
.MOV(result
, negate(op
[0]));
830 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
833 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
837 inst
= bld
.RNDZ(result
, op
[0]);
838 inst
->saturate
= instr
->dest
.saturate
;
842 op
[0].negate
= !op
[0].negate
;
843 fs_reg temp
= vgrf(glsl_type::float_type
);
844 bld
.RNDD(temp
, op
[0]);
846 inst
= bld
.MOV(result
, temp
);
847 inst
->saturate
= instr
->dest
.saturate
;
851 inst
= bld
.RNDD(result
, op
[0]);
852 inst
->saturate
= instr
->dest
.saturate
;
855 inst
= bld
.FRC(result
, op
[0]);
856 inst
->saturate
= instr
->dest
.saturate
;
858 case nir_op_fround_even
:
859 inst
= bld
.RNDE(result
, op
[0]);
860 inst
->saturate
= instr
->dest
.saturate
;
866 if (devinfo
->gen
>= 6) {
867 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
868 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
870 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
871 inst
= bld
.SEL(result
, op
[0], op
[1]);
872 inst
->predicate
= BRW_PREDICATE_NORMAL
;
874 inst
->saturate
= instr
->dest
.saturate
;
880 if (devinfo
->gen
>= 6) {
881 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
882 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
884 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
885 inst
= bld
.SEL(result
, op
[0], op
[1]);
886 inst
->predicate
= BRW_PREDICATE_NORMAL
;
888 inst
->saturate
= instr
->dest
.saturate
;
891 case nir_op_pack_snorm_2x16
:
892 case nir_op_pack_snorm_4x8
:
893 case nir_op_pack_unorm_2x16
:
894 case nir_op_pack_unorm_4x8
:
895 case nir_op_unpack_snorm_2x16
:
896 case nir_op_unpack_snorm_4x8
:
897 case nir_op_unpack_unorm_2x16
:
898 case nir_op_unpack_unorm_4x8
:
899 case nir_op_unpack_half_2x16
:
900 case nir_op_pack_half_2x16
:
901 unreachable("not reached: should be handled by lower_packing_builtins");
903 case nir_op_unpack_half_2x16_split_x
:
904 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
905 inst
->saturate
= instr
->dest
.saturate
;
907 case nir_op_unpack_half_2x16_split_y
:
908 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
909 inst
->saturate
= instr
->dest
.saturate
;
913 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
914 inst
->saturate
= instr
->dest
.saturate
;
917 case nir_op_bitfield_reverse
:
918 bld
.BFREV(result
, op
[0]);
921 case nir_op_bit_count
:
922 bld
.CBIT(result
, op
[0]);
925 case nir_op_ufind_msb
:
926 case nir_op_ifind_msb
: {
927 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
929 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
930 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
931 * subtract the result from 31 to convert the MSB count into an LSB count.
933 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
935 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
936 inst
->predicate
= BRW_PREDICATE_NORMAL
;
937 inst
->src
[0].negate
= true;
941 case nir_op_find_lsb
:
942 bld
.FBL(result
, op
[0]);
945 case nir_op_ubitfield_extract
:
946 case nir_op_ibitfield_extract
:
947 bld
.BFE(result
, op
[2], op
[1], op
[0]);
950 bld
.BFI1(result
, op
[0], op
[1]);
953 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
956 case nir_op_bitfield_insert
:
957 unreachable("not reached: should be handled by "
958 "lower_instructions::bitfield_insert_to_bfm_bfi");
961 bld
.SHL(result
, op
[0], op
[1]);
964 bld
.ASR(result
, op
[0], op
[1]);
967 bld
.SHR(result
, op
[0], op
[1]);
970 case nir_op_pack_half_2x16_split
:
971 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
975 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
976 inst
->saturate
= instr
->dest
.saturate
;
980 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
981 inst
->saturate
= instr
->dest
.saturate
;
985 if (optimize_frontfacing_ternary(instr
, result
))
988 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
989 inst
= bld
.SEL(result
, op
[1], op
[2]);
990 inst
->predicate
= BRW_PREDICATE_NORMAL
;
994 unreachable("unhandled instruction");
997 /* If we need to do a boolean resolve, replace the result with -(x & 1)
998 * to sign extend the low bit to 0/~0
1000 if (devinfo
->gen
<= 5 &&
1001 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1002 fs_reg masked
= vgrf(glsl_type::int_type
);
1003 bld
.AND(masked
, result
, brw_imm_d(1));
1004 masked
.negate
= true;
1005 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1010 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1011 nir_load_const_instr
*instr
)
1013 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1015 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1016 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i
[i
]));
1018 nir_ssa_values
[instr
->def
.index
] = reg
;
1022 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1024 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1025 instr
->def
.num_components
);
1029 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1030 unsigned base_offset
, nir_src
*indirect
)
1034 assert(!nir_reg
->is_global
);
1036 reg
= v
->nir_locals
[nir_reg
->index
];
1038 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1040 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1042 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1043 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1044 brw_imm_d(multiplier
));
1051 fs_visitor::get_nir_src(nir_src src
)
1055 reg
= nir_ssa_values
[src
.ssa
->index
];
1057 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1061 /* to avoid floating-point denorm flushing problems, set the type by
1062 * default to D - instructions that need floating point semantics will set
1063 * this to F if they need to
1065 return retype(reg
, BRW_REGISTER_TYPE_D
);
1069 fs_visitor::get_nir_dest(nir_dest dest
)
1072 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1073 dest
.ssa
.num_components
);
1074 return nir_ssa_values
[dest
.ssa
.index
];
1077 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1082 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1084 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
,
1085 BRW_REGISTER_TYPE_UD
);
1087 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1088 tail
= tail
->child
) {
1089 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1090 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1091 const unsigned size
= glsl_get_length(tail
->type
);
1092 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1093 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1094 image
= offset(image
, bld
, base
* element_size
);
1096 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1097 fs_reg tmp
= vgrf(glsl_type::int_type
);
1099 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1100 /* IVB hangs when trying to access an invalid surface index with
1101 * the dataport. According to the spec "if the index used to
1102 * select an individual element is negative or greater than or
1103 * equal to the size of the array, the results of the operation
1104 * are undefined but may not lead to termination" -- which is one
1105 * of the possible outcomes of the hang. Clamp the index to
1106 * prevent access outside of the array bounds.
1108 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1109 BRW_REGISTER_TYPE_UD
),
1110 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1112 bld
.MOV(tmp
, get_nir_src(deref_array
->indirect
));
1115 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
));
1117 bld
.ADD(*image
.reladdr
, *image
.reladdr
, tmp
);
1119 image
.reladdr
= new(mem_ctx
) fs_reg(tmp
);
1127 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1130 for (unsigned i
= 0; i
< 4; i
++) {
1131 if (!((wr_mask
>> i
) & 1))
1134 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1135 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1136 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1137 if (new_inst
->src
[j
].file
== VGRF
)
1138 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1145 * Get the matching channel register datatype for an image intrinsic of the
1146 * specified GLSL image type.
1149 get_image_base_type(const glsl_type
*type
)
1151 switch ((glsl_base_type
)type
->sampler_type
) {
1152 case GLSL_TYPE_UINT
:
1153 return BRW_REGISTER_TYPE_UD
;
1155 return BRW_REGISTER_TYPE_D
;
1156 case GLSL_TYPE_FLOAT
:
1157 return BRW_REGISTER_TYPE_F
;
1159 unreachable("Not reached.");
1164 * Get the appropriate atomic op for an image atomic intrinsic.
1167 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1170 case nir_intrinsic_image_atomic_add
:
1172 case nir_intrinsic_image_atomic_min
:
1173 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1174 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1175 case nir_intrinsic_image_atomic_max
:
1176 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1177 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1178 case nir_intrinsic_image_atomic_and
:
1180 case nir_intrinsic_image_atomic_or
:
1182 case nir_intrinsic_image_atomic_xor
:
1184 case nir_intrinsic_image_atomic_exchange
:
1186 case nir_intrinsic_image_atomic_comp_swap
:
1187 return BRW_AOP_CMPWR
;
1189 unreachable("Not reachable.");
1194 emit_pixel_interpolater_send(const fs_builder
&bld
,
1199 glsl_interp_qualifier interpolation
)
1205 if (src
.file
== BAD_FILE
) {
1207 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1211 mlen
= 2 * bld
.dispatch_width() / 8;
1214 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1216 /* 2 floats per slot returned */
1217 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1218 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1224 * Computes 1 << x, given a D/UD register containing some value x.
1227 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1229 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1231 fs_reg result
= bld
.vgrf(x
.type
, 1);
1232 fs_reg one
= bld
.vgrf(x
.type
, 1);
1234 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1235 bld
.SHL(result
, one
, x
);
1240 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1242 assert(stage
== MESA_SHADER_GEOMETRY
);
1244 struct brw_gs_prog_data
*gs_prog_data
=
1245 (struct brw_gs_prog_data
*) prog_data
;
1247 /* We can only do EndPrimitive() functionality when the control data
1248 * consists of cut bits. Fortunately, the only time it isn't is when the
1249 * output type is points, in which case EndPrimitive() is a no-op.
1251 if (gs_prog_data
->control_data_format
!=
1252 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1256 /* Cut bits use one bit per vertex. */
1257 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1259 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1260 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1262 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1263 * vertex n, 0 otherwise. So all we need to do here is mark bit
1264 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1265 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1266 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1268 * Note that if EndPrimitive() is called before emitting any vertices, this
1269 * will cause us to set bit 31 of the control_data_bits register to 1.
1270 * That's fine because:
1272 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1273 * output, so the hardware will ignore cut bit 31.
1275 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1276 * last vertex, so setting cut bit 31 has no effect (since the primitive
1277 * is automatically ended when the GS terminates).
1279 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1280 * control_data_bits register to 0 when the first vertex is emitted.
1283 const fs_builder abld
= bld
.annotate("end primitive");
1285 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1286 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1287 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1288 fs_reg mask
= intexp2(abld
, prev_count
);
1289 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1290 * attention to the lower 5 bits of its second source argument, so on this
1291 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1292 * ((vertex_count - 1) % 32).
1294 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1298 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1300 assert(stage
== MESA_SHADER_GEOMETRY
);
1301 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1303 struct brw_gs_prog_data
*gs_prog_data
=
1304 (struct brw_gs_prog_data
*) prog_data
;
1306 const fs_builder abld
= bld
.annotate("emit control data bits");
1307 const fs_builder fwa_bld
= bld
.exec_all();
1309 /* We use a single UD register to accumulate control data bits (32 bits
1310 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1313 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1314 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1315 * use the Channel Mask phase to enable/disable which DWord within that
1316 * group to write. (Remember, different SIMD8 channels may have emitted
1317 * different numbers of vertices, so we may need per-slot offsets.)
1319 * Channel masking presents an annoying problem: we may have to replicate
1320 * the data up to 4 times:
1322 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1324 * To avoid penalizing shaders that emit a small number of vertices, we
1325 * can avoid these sometimes: if the size of the control data header is
1326 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1327 * land in the same 128-bit group, so we can skip per-slot offsets.
1329 * Similarly, if the control data header is <= 32 bits, there is only one
1330 * DWord, so we can skip channel masks.
1332 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1334 fs_reg channel_mask
, per_slot_offset
;
1336 if (gs_compile
->control_data_header_size_bits
> 32) {
1337 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1338 channel_mask
= vgrf(glsl_type::uint_type
);
1341 if (gs_compile
->control_data_header_size_bits
> 128) {
1342 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1343 per_slot_offset
= vgrf(glsl_type::uint_type
);
1346 /* Figure out which DWord we're trying to write to using the formula:
1348 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1350 * Since bits_per_vertex is a power of two, and is known at compile
1351 * time, this can be optimized to:
1353 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1355 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1356 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1357 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1358 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1359 unsigned log2_bits_per_vertex
=
1360 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1361 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1363 if (per_slot_offset
.file
!= BAD_FILE
) {
1364 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1365 * the appropriate OWord within the control data header.
1367 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1370 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1371 * write to the appropriate DWORD within the OWORD.
1373 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1374 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1375 channel_mask
= intexp2(fwa_bld
, channel
);
1376 /* Then the channel masks need to be in bits 23:16. */
1377 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1380 /* Store the control data bits in the message payload and send it. */
1382 if (channel_mask
.file
!= BAD_FILE
)
1383 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1384 if (per_slot_offset
.file
!= BAD_FILE
)
1387 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1388 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1390 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1391 if (per_slot_offset
.file
!= BAD_FILE
)
1392 sources
[i
++] = per_slot_offset
;
1393 if (channel_mask
.file
!= BAD_FILE
)
1394 sources
[i
++] = channel_mask
;
1396 sources
[i
++] = this->control_data_bits
;
1399 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1400 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1402 /* We need to increment Global Offset by 256-bits to make room for
1403 * Broadwell's extra "Vertex Count" payload at the beginning of the
1404 * URB entry. Since this is an OWord message, Global Offset is counted
1405 * in 128-bit units, so we must set it to 2.
1407 if (gs_prog_data
->static_vertex_count
== -1)
1412 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1415 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1417 /* Note: we are calling this *before* increasing vertex_count, so
1418 * this->vertex_count == vertex_count - 1 in the formula above.
1421 /* Stream mode uses 2 bits per vertex */
1422 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1424 /* Must be a valid stream */
1425 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1427 /* Control data bits are initialized to 0 so we don't have to set any
1428 * bits when sending vertices to stream 0.
1433 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1435 /* reg::sid = stream_id */
1436 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1437 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1439 /* reg:shift_count = 2 * (vertex_count - 1) */
1440 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1441 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1443 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1444 * attention to the lower 5 bits of its second source argument, so on this
1445 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1446 * stream_id << ((2 * (vertex_count - 1)) % 32).
1448 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1449 abld
.SHL(mask
, sid
, shift_count
);
1450 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1454 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1457 assert(stage
== MESA_SHADER_GEOMETRY
);
1459 struct brw_gs_prog_data
*gs_prog_data
=
1460 (struct brw_gs_prog_data
*) prog_data
;
1462 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1463 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1465 /* Haswell and later hardware ignores the "Render Stream Select" bits
1466 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1467 * and instead sends all primitives down the pipeline for rasterization.
1468 * If the SOL stage is enabled, "Render Stream Select" is honored and
1469 * primitives bound to non-zero streams are discarded after stream output.
1471 * Since the only purpose of primives sent to non-zero streams is to
1472 * be recorded by transform feedback, we can simply discard all geometry
1473 * bound to these streams when transform feedback is disabled.
1475 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1478 /* If we're outputting 32 control data bits or less, then we can wait
1479 * until the shader is over to output them all. Otherwise we need to
1480 * output them as we go. Now is the time to do it, since we're about to
1481 * output the vertex_count'th vertex, so it's guaranteed that the
1482 * control data bits associated with the (vertex_count - 1)th vertex are
1485 if (gs_compile
->control_data_header_size_bits
> 32) {
1486 const fs_builder abld
=
1487 bld
.annotate("emit vertex: emit control data bits");
1489 /* Only emit control data bits if we've finished accumulating a batch
1490 * of 32 bits. This is the case when:
1492 * (vertex_count * bits_per_vertex) % 32 == 0
1494 * (in other words, when the last 5 bits of vertex_count *
1495 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1496 * integer n (which is always the case, since bits_per_vertex is
1497 * always 1 or 2), this is equivalent to requiring that the last 5-n
1498 * bits of vertex_count are 0:
1500 * vertex_count & (2^(5-n) - 1) == 0
1502 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1505 * vertex_count & (32 / bits_per_vertex - 1) == 0
1507 * TODO: If vertex_count is an immediate, we could do some of this math
1508 * at compile time...
1511 abld
.AND(bld
.null_reg_d(), vertex_count
,
1512 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1513 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1515 abld
.IF(BRW_PREDICATE_NORMAL
);
1516 /* If vertex_count is 0, then no control data bits have been
1517 * accumulated yet, so we can skip emitting them.
1519 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1520 BRW_CONDITIONAL_NEQ
);
1521 abld
.IF(BRW_PREDICATE_NORMAL
);
1522 emit_gs_control_data_bits(vertex_count
);
1523 abld
.emit(BRW_OPCODE_ENDIF
);
1525 /* Reset control_data_bits to 0 so we can start accumulating a new
1528 * Note: in the case where vertex_count == 0, this neutralizes the
1529 * effect of any call to EndPrimitive() that the shader may have
1530 * made before outputting its first vertex.
1532 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1533 inst
->force_writemask_all
= true;
1534 abld
.emit(BRW_OPCODE_ENDIF
);
1537 emit_urb_writes(vertex_count
);
1539 /* In stream mode we have to set control data bits for all vertices
1540 * unless we have disabled control data bits completely (which we do
1541 * do for GL_POINTS outputs that don't use streams).
1543 if (gs_compile
->control_data_header_size_bits
> 0 &&
1544 gs_prog_data
->control_data_format
==
1545 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1546 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1551 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1552 const nir_src
&vertex_src
,
1553 const fs_reg
&indirect_offset
,
1554 unsigned imm_offset
,
1555 unsigned num_components
)
1557 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1559 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1560 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1561 * gl_PointSize is available as a GS input, however, so it must be that.
1563 const bool is_point_size
=
1564 indirect_offset
.file
== BAD_FILE
&& imm_offset
== 0;
1566 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1567 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1569 if (indirect_offset
.file
== BAD_FILE
&& vertex_const
!= NULL
&&
1570 4 * imm_offset
< push_reg_count
) {
1571 imm_offset
= 4 * imm_offset
+ vertex_const
->u
[0] * push_reg_count
;
1572 /* This input was pushed into registers. */
1573 if (is_point_size
) {
1574 /* gl_PointSize comes in .w */
1575 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1577 for (unsigned i
= 0; i
< num_components
; i
++) {
1578 bld
.MOV(offset(dst
, bld
, i
),
1579 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1583 /* Resort to the pull model. Ensure the VUE handles are provided. */
1584 gs_prog_data
->base
.include_vue_handles
= true;
1586 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1590 /* The vertex index is constant; just select the proper URB handle. */
1592 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i
[0], 0),
1593 BRW_REGISTER_TYPE_UD
);
1595 /* The vertex index is non-constant. We need to use indirect
1596 * addressing to fetch the proper URB handle.
1598 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1599 * indicating that channel <n> should read the handle from
1600 * DWord <n>. We convert that to bytes by multiplying by 4.
1602 * Next, we convert the vertex index to bytes by multiplying
1603 * by 32 (shifting by 5), and add the two together. This is
1604 * the final indirect byte offset.
1606 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1607 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1608 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1609 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1610 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1612 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1613 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1614 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1615 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1616 /* Convert vertex_index to bytes (multiply by 32) */
1617 bld
.SHL(vertex_offset_bytes
,
1618 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1620 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1622 /* Use first_icp_handle as the base offset. There is one register
1623 * of URB handles per vertex, so inform the register allocator that
1624 * we might read up to nir->info.gs.vertices_in registers.
1626 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1627 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1628 fs_reg(icp_offset_bytes
),
1629 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1633 if (indirect_offset
.file
== BAD_FILE
) {
1634 /* Constant indexing - use global offset. */
1635 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1636 inst
->offset
= imm_offset
;
1637 inst
->base_mrf
= -1;
1639 inst
->regs_written
= num_components
;
1641 /* Indirect indexing - use per-slot offsets as well. */
1642 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
1643 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1644 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1646 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1647 inst
->offset
= imm_offset
;
1648 inst
->base_mrf
= -1;
1650 inst
->regs_written
= num_components
;
1653 if (is_point_size
) {
1654 /* Read the whole VUE header (because of alignment) and read .w. */
1655 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1657 inst
->regs_written
= 4;
1658 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1664 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1665 nir_intrinsic_instr
*instr
)
1667 assert(stage
== MESA_SHADER_VERTEX
);
1670 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1671 dest
= get_nir_dest(instr
->dest
);
1673 switch (instr
->intrinsic
) {
1674 case nir_intrinsic_load_vertex_id
:
1675 unreachable("should be lowered by lower_vertex_id()");
1677 case nir_intrinsic_load_vertex_id_zero_base
:
1678 case nir_intrinsic_load_base_vertex
:
1679 case nir_intrinsic_load_instance_id
: {
1680 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1681 fs_reg val
= nir_system_values
[sv
];
1682 assert(val
.file
!= BAD_FILE
);
1683 dest
.type
= val
.type
;
1689 nir_emit_intrinsic(bld
, instr
);
1695 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
1696 nir_intrinsic_instr
*instr
)
1698 assert(stage
== MESA_SHADER_GEOMETRY
);
1699 fs_reg indirect_offset
;
1702 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1703 dest
= get_nir_dest(instr
->dest
);
1705 switch (instr
->intrinsic
) {
1706 case nir_intrinsic_load_primitive_id
:
1707 assert(stage
== MESA_SHADER_GEOMETRY
);
1708 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
1709 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
1710 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
1713 case nir_intrinsic_load_input_indirect
:
1714 case nir_intrinsic_load_input
:
1715 unreachable("load_input intrinsics are invalid for the GS stage");
1717 case nir_intrinsic_load_per_vertex_input_indirect
:
1718 indirect_offset
= retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_D
);
1720 case nir_intrinsic_load_per_vertex_input
:
1721 emit_gs_input_load(dest
, instr
->src
[0],
1722 indirect_offset
, instr
->const_index
[0],
1723 instr
->num_components
);
1726 case nir_intrinsic_emit_vertex_with_counter
:
1727 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
1730 case nir_intrinsic_end_primitive_with_counter
:
1731 emit_gs_end_primitive(instr
->src
[0]);
1734 case nir_intrinsic_set_vertex_count
:
1735 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
1738 case nir_intrinsic_load_invocation_id
: {
1739 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
1740 assert(val
.file
!= BAD_FILE
);
1741 dest
.type
= val
.type
;
1747 nir_emit_intrinsic(bld
, instr
);
1753 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
1754 nir_intrinsic_instr
*instr
)
1756 assert(stage
== MESA_SHADER_FRAGMENT
);
1757 struct brw_wm_prog_data
*wm_prog_data
=
1758 (struct brw_wm_prog_data
*) prog_data
;
1761 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1762 dest
= get_nir_dest(instr
->dest
);
1764 switch (instr
->intrinsic
) {
1765 case nir_intrinsic_load_front_face
:
1766 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1767 *emit_frontfacing_interpolation());
1770 case nir_intrinsic_load_sample_pos
: {
1771 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1772 assert(sample_pos
.file
!= BAD_FILE
);
1773 dest
.type
= sample_pos
.type
;
1774 bld
.MOV(dest
, sample_pos
);
1775 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1779 case nir_intrinsic_load_sample_mask_in
:
1780 case nir_intrinsic_load_sample_id
: {
1781 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1782 fs_reg val
= nir_system_values
[sv
];
1783 assert(val
.file
!= BAD_FILE
);
1784 dest
.type
= val
.type
;
1789 case nir_intrinsic_discard
:
1790 case nir_intrinsic_discard_if
: {
1791 /* We track our discarded pixels in f0.1. By predicating on it, we can
1792 * update just the flag bits that aren't yet discarded. If there's no
1793 * condition, we emit a CMP of g0 != g0, so all currently executing
1794 * channels will get turned off.
1797 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1798 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1799 brw_imm_d(0), BRW_CONDITIONAL_Z
);
1801 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1802 BRW_REGISTER_TYPE_UW
));
1803 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1805 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1806 cmp
->flag_subreg
= 1;
1808 if (devinfo
->gen
>= 6) {
1809 emit_discard_jump();
1814 case nir_intrinsic_interp_var_at_centroid
:
1815 case nir_intrinsic_interp_var_at_sample
:
1816 case nir_intrinsic_interp_var_at_offset
: {
1817 /* Handle ARB_gpu_shader5 interpolation intrinsics
1819 * It's worth a quick word of explanation as to why we handle the full
1820 * variable-based interpolation intrinsic rather than a lowered version
1821 * with like we do for other inputs. We have to do that because the way
1822 * we set up inputs doesn't allow us to use the already setup inputs for
1823 * interpolation. At the beginning of the shader, we go through all of
1824 * the input variables and do the initial interpolation and put it in
1825 * the nir_inputs array based on its location as determined in
1826 * nir_lower_io. If the input isn't used, dead code cleans up and
1827 * everything works fine. However, when we get to the ARB_gpu_shader5
1828 * interpolation intrinsics, we need to reinterpolate the input
1829 * differently. If we used an intrinsic that just had an index it would
1830 * only give us the offset into the nir_inputs array. However, this is
1831 * useless because that value is post-interpolation and we need
1832 * pre-interpolation. In order to get the actual location of the bits
1833 * we get from the vertex fetching hardware, we need the variable.
1835 wm_prog_data
->pulls_bary
= true;
1837 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1838 const glsl_interp_qualifier interpolation
=
1839 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
1841 switch (instr
->intrinsic
) {
1842 case nir_intrinsic_interp_var_at_centroid
:
1843 emit_pixel_interpolater_send(bld
,
1844 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1851 case nir_intrinsic_interp_var_at_sample
: {
1852 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1855 unsigned msg_data
= const_sample
->i
[0] << 4;
1857 emit_pixel_interpolater_send(bld
,
1858 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1861 brw_imm_ud(msg_data
),
1864 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
1865 BRW_REGISTER_TYPE_UD
);
1867 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
1868 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1869 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1870 bld
.exec_all().group(1, 0)
1871 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
1872 emit_pixel_interpolater_send(bld
,
1873 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1879 /* Make a loop that sends a message to the pixel interpolater
1880 * for the sample number in each live channel. If there are
1881 * multiple channels with the same sample number then these
1882 * will be handled simultaneously with a single interation of
1885 bld
.emit(BRW_OPCODE_DO
);
1887 /* Get the next live sample number into sample_id_reg */
1888 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1890 /* Set the flag register so that we can perform the send
1891 * message on all channels that have the same sample number
1893 bld
.CMP(bld
.null_reg_ud(),
1894 sample_src
, sample_id
,
1895 BRW_CONDITIONAL_EQ
);
1896 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1897 bld
.exec_all().group(1, 0)
1898 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
1900 emit_pixel_interpolater_send(bld
,
1901 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1906 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
1908 /* Continue the loop if there are any live channels left */
1909 set_predicate_inv(BRW_PREDICATE_NORMAL
,
1911 bld
.emit(BRW_OPCODE_WHILE
));
1918 case nir_intrinsic_interp_var_at_offset
: {
1919 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1922 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1923 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1925 emit_pixel_interpolater_send(bld
,
1926 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
1929 brw_imm_ud(off_x
| (off_y
<< 4)),
1932 fs_reg src
= vgrf(glsl_type::ivec2_type
);
1933 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1934 BRW_REGISTER_TYPE_F
);
1935 for (int i
= 0; i
< 2; i
++) {
1936 fs_reg temp
= vgrf(glsl_type::float_type
);
1937 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
1938 fs_reg itemp
= vgrf(glsl_type::int_type
);
1939 bld
.MOV(itemp
, temp
); /* float to int */
1941 /* Clamp the upper end of the range to +7/16.
1942 * ARB_gpu_shader5 requires that we support a maximum offset
1943 * of +0.5, which isn't representable in a S0.4 value -- if
1944 * we didn't clamp it, we'd end up with -8/16, which is the
1945 * opposite of what the shader author wanted.
1947 * This is legal due to ARB_gpu_shader5's quantization
1950 * "Not all values of <offset> may be supported; x and y
1951 * offsets may be rounded to fixed-point values with the
1952 * number of fraction bits given by the
1953 * implementation-dependent constant
1954 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1956 set_condmod(BRW_CONDITIONAL_L
,
1957 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
1960 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
1961 emit_pixel_interpolater_send(bld
,
1972 unreachable("Invalid intrinsic");
1975 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1976 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1977 src
.type
= dest
.type
;
1979 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1980 dest
= offset(dest
, bld
, 1);
1985 nir_emit_intrinsic(bld
, instr
);
1991 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
1992 nir_intrinsic_instr
*instr
)
1994 assert(stage
== MESA_SHADER_COMPUTE
);
1995 struct brw_cs_prog_data
*cs_prog_data
=
1996 (struct brw_cs_prog_data
*) prog_data
;
1999 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2000 dest
= get_nir_dest(instr
->dest
);
2002 switch (instr
->intrinsic
) {
2003 case nir_intrinsic_barrier
:
2005 cs_prog_data
->uses_barrier
= true;
2008 case nir_intrinsic_load_local_invocation_id
:
2009 case nir_intrinsic_load_work_group_id
: {
2010 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2011 fs_reg val
= nir_system_values
[sv
];
2012 assert(val
.file
!= BAD_FILE
);
2013 dest
.type
= val
.type
;
2014 for (unsigned i
= 0; i
< 3; i
++)
2015 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2019 case nir_intrinsic_load_num_work_groups
: {
2020 const unsigned surface
=
2021 cs_prog_data
->binding_table
.work_groups_start
;
2023 cs_prog_data
->uses_num_work_groups
= true;
2025 fs_reg surf_index
= brw_imm_ud(surface
);
2026 brw_mark_surface_used(prog_data
, surface
);
2028 /* Read the 3 GLuint components of gl_NumWorkGroups */
2029 for (unsigned i
= 0; i
< 3; i
++) {
2030 fs_reg read_result
=
2031 emit_untyped_read(bld
, surf_index
,
2033 1 /* dims */, 1 /* size */,
2034 BRW_PREDICATE_NONE
);
2035 read_result
.type
= dest
.type
;
2036 bld
.MOV(dest
, read_result
);
2037 dest
= offset(dest
, bld
, 1);
2043 nir_emit_intrinsic(bld
, instr
);
2049 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2052 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2053 dest
= get_nir_dest(instr
->dest
);
2055 bool has_indirect
= false;
2057 switch (instr
->intrinsic
) {
2058 case nir_intrinsic_atomic_counter_inc
:
2059 case nir_intrinsic_atomic_counter_dec
:
2060 case nir_intrinsic_atomic_counter_read
: {
2061 using namespace surface_access
;
2063 /* Get the arguments of the atomic intrinsic. */
2064 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2065 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2066 instr
->const_index
[0]);
2069 /* Emit a surface read or atomic op. */
2070 switch (instr
->intrinsic
) {
2071 case nir_intrinsic_atomic_counter_read
:
2072 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2075 case nir_intrinsic_atomic_counter_inc
:
2076 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2077 fs_reg(), 1, 1, BRW_AOP_INC
);
2080 case nir_intrinsic_atomic_counter_dec
:
2081 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2082 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2086 unreachable("Unreachable");
2089 /* Assign the result. */
2090 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2092 /* Mark the surface as used. */
2093 brw_mark_surface_used(stage_prog_data
, surface
);
2097 case nir_intrinsic_image_load
:
2098 case nir_intrinsic_image_store
:
2099 case nir_intrinsic_image_atomic_add
:
2100 case nir_intrinsic_image_atomic_min
:
2101 case nir_intrinsic_image_atomic_max
:
2102 case nir_intrinsic_image_atomic_and
:
2103 case nir_intrinsic_image_atomic_or
:
2104 case nir_intrinsic_image_atomic_xor
:
2105 case nir_intrinsic_image_atomic_exchange
:
2106 case nir_intrinsic_image_atomic_comp_swap
: {
2107 using namespace image_access
;
2109 /* Get the referenced image variable and type. */
2110 const nir_variable
*var
= instr
->variables
[0]->var
;
2111 const glsl_type
*type
= var
->type
->without_array();
2112 const brw_reg_type base_type
= get_image_base_type(type
);
2114 /* Get some metadata from the image intrinsic. */
2115 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2116 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2117 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2118 const mesa_format format
=
2119 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
2120 _mesa_get_shader_image_format(var
->data
.image
.format
));
2122 /* Get the arguments of the image intrinsic. */
2123 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2124 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2125 BRW_REGISTER_TYPE_UD
);
2126 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2127 retype(get_nir_src(instr
->src
[2]), base_type
) :
2129 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2130 retype(get_nir_src(instr
->src
[3]), base_type
) :
2134 /* Emit an image load, store or atomic op. */
2135 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2136 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2138 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2139 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
2142 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2143 surf_dims
, arr_dims
, info
->dest_components
,
2144 get_image_atomic_op(instr
->intrinsic
, type
));
2146 /* Assign the result. */
2147 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2148 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2149 offset(tmp
, bld
, c
));
2153 case nir_intrinsic_memory_barrier_atomic_counter
:
2154 case nir_intrinsic_memory_barrier_buffer
:
2155 case nir_intrinsic_memory_barrier_image
:
2156 case nir_intrinsic_memory_barrier
: {
2157 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2158 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2163 case nir_intrinsic_group_memory_barrier
:
2164 case nir_intrinsic_memory_barrier_shared
:
2165 /* We treat these workgroup-level barriers as no-ops. This should be
2166 * safe at present and as long as:
2168 * - Memory access instructions are not subsequently reordered by the
2169 * compiler back-end.
2171 * - All threads from a given compute shader workgroup fit within a
2172 * single subslice and therefore talk to the same HDC shared unit
2173 * what supposedly guarantees ordering and coherency between threads
2174 * from the same workgroup. This may change in the future when we
2175 * start splitting workgroups across multiple subslices.
2177 * - The context is not in fault-and-stream mode, which could cause
2178 * memory transactions (including to SLM) prior to the barrier to be
2179 * replayed after the barrier if a pagefault occurs. This shouldn't
2180 * be a problem up to and including SKL because fault-and-stream is
2181 * not usable due to hardware issues, but that's likely to change in
2186 case nir_intrinsic_shader_clock
: {
2187 /* We cannot do anything if there is an event, so ignore it for now */
2188 fs_reg shader_clock
= get_timestamp(bld
);
2189 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2191 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2195 case nir_intrinsic_image_size
: {
2196 /* Get the referenced image variable and type. */
2197 const nir_variable
*var
= instr
->variables
[0]->var
;
2198 const glsl_type
*type
= var
->type
->without_array();
2200 /* Get the size of the image. */
2201 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2202 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
2204 /* For 1DArray image types, the array index is stored in the Z component.
2205 * Fix this by swizzling the Z component to the Y component.
2207 const bool is_1d_array_image
=
2208 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
2209 type
->sampler_array
;
2211 /* For CubeArray images, we should count the number of cubes instead
2212 * of the number of faces. Fix it by dividing the (Z component) by 6.
2214 const bool is_cube_array_image
=
2215 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2216 type
->sampler_array
;
2218 /* Copy all the components. */
2219 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2220 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
2221 if ((int)c
>= type
->coordinate_components()) {
2222 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2224 } else if (c
== 1 && is_1d_array_image
) {
2225 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2226 offset(size
, bld
, 2));
2227 } else if (c
== 2 && is_cube_array_image
) {
2228 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
2229 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2230 offset(size
, bld
, c
), brw_imm_d(6));
2232 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2233 offset(size
, bld
, c
));
2240 case nir_intrinsic_image_samples
:
2241 /* The driver does not support multi-sampled images. */
2242 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
2245 case nir_intrinsic_load_uniform_indirect
:
2246 has_indirect
= true;
2248 case nir_intrinsic_load_uniform
: {
2249 fs_reg
uniform_reg(UNIFORM
, instr
->const_index
[0]);
2250 uniform_reg
.reg_offset
= instr
->const_index
[1];
2252 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2253 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, j
);
2255 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
2258 dest
= offset(dest
, bld
, 1);
2263 case nir_intrinsic_load_ubo_indirect
:
2264 has_indirect
= true;
2266 case nir_intrinsic_load_ubo
: {
2267 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
2271 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
2273 surf_index
= brw_imm_ud(index
);
2274 brw_mark_surface_used(prog_data
, index
);
2276 /* The block index is not a constant. Evaluate the index expression
2277 * per-channel and add the base UBO index; we have to select a value
2278 * from any live channel.
2280 surf_index
= vgrf(glsl_type::uint_type
);
2281 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2282 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
2283 surf_index
= bld
.emit_uniformize(surf_index
);
2285 /* Assume this may touch any UBO. It would be nice to provide
2286 * a tighter bound, but the array information is already lowered away.
2288 brw_mark_surface_used(prog_data
,
2289 stage_prog_data
->binding_table
.ubo_start
+
2290 nir
->info
.num_ubos
- 1);
2294 /* Turn the byte offset into a dword offset. */
2295 fs_reg base_offset
= vgrf(glsl_type::int_type
);
2296 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
2297 BRW_REGISTER_TYPE_D
),
2300 unsigned vec4_offset
= instr
->const_index
[0] / 4;
2301 for (int i
= 0; i
< instr
->num_components
; i
++)
2302 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
2303 base_offset
, vec4_offset
+ i
);
2305 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
2306 packed_consts
.type
= dest
.type
;
2308 struct brw_reg const_offset_reg
= brw_imm_ud(instr
->const_index
[0] & ~15);
2309 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
2310 surf_index
, const_offset_reg
);
2312 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2313 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
2315 /* The std140 packing rules don't allow vectors to cross 16-byte
2316 * boundaries, and a reg is 32 bytes.
2318 assert(packed_consts
.subreg_offset
< 32);
2320 bld
.MOV(dest
, packed_consts
);
2321 dest
= offset(dest
, bld
, 1);
2327 case nir_intrinsic_load_ssbo_indirect
:
2328 has_indirect
= true;
2330 case nir_intrinsic_load_ssbo
: {
2331 assert(devinfo
->gen
>= 7);
2333 nir_const_value
*const_uniform_block
=
2334 nir_src_as_const_value(instr
->src
[0]);
2337 if (const_uniform_block
) {
2338 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2339 const_uniform_block
->u
[0];
2340 surf_index
= brw_imm_ud(index
);
2341 brw_mark_surface_used(prog_data
, index
);
2343 surf_index
= vgrf(glsl_type::uint_type
);
2344 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2345 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2347 /* Assume this may touch any UBO. It would be nice to provide
2348 * a tighter bound, but the array information is already lowered away.
2350 brw_mark_surface_used(prog_data
,
2351 stage_prog_data
->binding_table
.ssbo_start
+
2352 nir
->info
.num_ssbos
- 1);
2355 /* Get the offset to read from */
2358 offset_reg
= get_nir_src(instr
->src
[1]);
2360 offset_reg
= brw_imm_ud(instr
->const_index
[0]);
2363 /* Read the vector */
2364 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2366 instr
->num_components
,
2367 BRW_PREDICATE_NONE
);
2368 read_result
.type
= dest
.type
;
2369 for (int i
= 0; i
< instr
->num_components
; i
++)
2370 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2375 case nir_intrinsic_load_input_indirect
:
2376 has_indirect
= true;
2378 case nir_intrinsic_load_input
: {
2380 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2382 if (stage
== MESA_SHADER_VERTEX
) {
2383 src
= offset(fs_reg(ATTR
, instr
->const_index
[0], dest
.type
), bld
, index
);
2385 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
2386 instr
->const_index
[0] + index
);
2389 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
2393 dest
= offset(dest
, bld
, 1);
2398 case nir_intrinsic_store_ssbo_indirect
:
2399 has_indirect
= true;
2401 case nir_intrinsic_store_ssbo
: {
2402 assert(devinfo
->gen
>= 7);
2406 nir_const_value
*const_uniform_block
=
2407 nir_src_as_const_value(instr
->src
[1]);
2408 if (const_uniform_block
) {
2409 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2410 const_uniform_block
->u
[0];
2411 surf_index
= brw_imm_ud(index
);
2412 brw_mark_surface_used(prog_data
, index
);
2414 surf_index
= vgrf(glsl_type::uint_type
);
2415 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
2416 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2418 brw_mark_surface_used(prog_data
,
2419 stage_prog_data
->binding_table
.ssbo_start
+
2420 nir
->info
.num_ssbos
- 1);
2424 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2427 unsigned writemask
= instr
->const_index
[1];
2429 /* Combine groups of consecutive enabled channels in one write
2430 * message. We use ffs to find the first enabled channel and then ffs on
2431 * the bit-inverse, down-shifted writemask to determine the length of
2432 * the block of enabled bits.
2435 unsigned first_component
= ffs(writemask
) - 1;
2436 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2439 if (!has_indirect
) {
2440 offset_reg
= brw_imm_ud(instr
->const_index
[0] + 4 * first_component
);
2442 offset_reg
= vgrf(glsl_type::uint_type
);
2444 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
2445 brw_imm_ud(4 * first_component
));
2448 emit_untyped_write(bld
, surf_index
, offset_reg
,
2449 offset(val_reg
, bld
, first_component
),
2450 1 /* dims */, length
,
2451 BRW_PREDICATE_NONE
);
2453 /* Clear the bits in the writemask that we just wrote, then try
2454 * again to see if more channels are left.
2456 writemask
&= (15 << (first_component
+ length
));
2461 case nir_intrinsic_store_output_indirect
:
2462 has_indirect
= true;
2464 case nir_intrinsic_store_output
: {
2465 fs_reg src
= get_nir_src(instr
->src
[0]);
2467 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2468 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
2469 instr
->const_index
[0] + index
);
2471 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
2473 bld
.MOV(new_dest
, src
);
2474 src
= offset(src
, bld
, 1);
2479 case nir_intrinsic_ssbo_atomic_add
:
2480 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
2482 case nir_intrinsic_ssbo_atomic_imin
:
2483 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
2485 case nir_intrinsic_ssbo_atomic_umin
:
2486 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
2488 case nir_intrinsic_ssbo_atomic_imax
:
2489 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
2491 case nir_intrinsic_ssbo_atomic_umax
:
2492 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
2494 case nir_intrinsic_ssbo_atomic_and
:
2495 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
2497 case nir_intrinsic_ssbo_atomic_or
:
2498 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
2500 case nir_intrinsic_ssbo_atomic_xor
:
2501 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
2503 case nir_intrinsic_ssbo_atomic_exchange
:
2504 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
2506 case nir_intrinsic_ssbo_atomic_comp_swap
:
2507 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2510 case nir_intrinsic_get_buffer_size
: {
2511 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
2512 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
2513 int reg_width
= dispatch_width
/ 8;
2516 fs_reg source
= brw_imm_d(0);
2518 int mlen
= 1 * reg_width
;
2520 /* A resinfo's sampler message is used to get the buffer size.
2521 * The SIMD8's writeback message consists of four registers and
2522 * SIMD16's writeback message consists of 8 destination registers
2523 * (two per each component), although we are only interested on the
2524 * first component, where resinfo returns the buffer size for
2527 int regs_written
= 4 * mlen
;
2528 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
2529 BRW_REGISTER_TYPE_UD
);
2530 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
2531 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
2532 BRW_REGISTER_TYPE_UD
);
2533 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
2534 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
2535 src_payload
, brw_imm_ud(index
));
2536 inst
->header_size
= 0;
2538 inst
->regs_written
= regs_written
;
2540 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
2542 brw_mark_surface_used(prog_data
, index
);
2547 unreachable("unknown intrinsic");
2552 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
2553 int op
, nir_intrinsic_instr
*instr
)
2556 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2557 dest
= get_nir_dest(instr
->dest
);
2560 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
2561 if (const_surface
) {
2562 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
2563 const_surface
->u
[0];
2564 surface
= brw_imm_ud(surf_index
);
2565 brw_mark_surface_used(prog_data
, surf_index
);
2567 surface
= vgrf(glsl_type::uint_type
);
2568 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
2569 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2571 /* Assume this may touch any SSBO. This is the same we do for other
2572 * UBO/SSBO accesses with non-constant surface.
2574 brw_mark_surface_used(prog_data
,
2575 stage_prog_data
->binding_table
.ssbo_start
+
2576 nir
->info
.num_ssbos
- 1);
2579 fs_reg offset
= get_nir_src(instr
->src
[1]);
2580 fs_reg data1
= get_nir_src(instr
->src
[2]);
2582 if (op
== BRW_AOP_CMPWR
)
2583 data2
= get_nir_src(instr
->src
[3]);
2585 /* Emit the actual atomic operation operation */
2587 fs_reg atomic_result
=
2588 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2590 1 /* dims */, 1 /* rsize */,
2592 BRW_PREDICATE_NONE
);
2593 dest
.type
= atomic_result
.type
;
2594 bld
.MOV(dest
, atomic_result
);
2598 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
2600 unsigned sampler
= instr
->sampler_index
;
2601 fs_reg
sampler_reg(brw_imm_ud(sampler
));
2603 int gather_component
= instr
->component
;
2605 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
2607 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
2610 int lod_components
= 0;
2611 int UNUSED offset_components
= 0;
2613 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
2615 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2616 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
2617 switch (instr
->src
[i
].src_type
) {
2618 case nir_tex_src_bias
:
2619 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2621 case nir_tex_src_comparitor
:
2622 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
2624 case nir_tex_src_coord
:
2625 switch (instr
->op
) {
2627 case nir_texop_txf_ms
:
2628 case nir_texop_samples_identical
:
2629 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
2632 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
2636 case nir_tex_src_ddx
:
2637 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2638 lod_components
= nir_tex_instr_src_size(instr
, i
);
2640 case nir_tex_src_ddy
:
2641 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
2643 case nir_tex_src_lod
:
2644 switch (instr
->op
) {
2646 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
2649 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
2652 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2656 case nir_tex_src_ms_index
:
2657 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
2659 case nir_tex_src_offset
:
2660 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
2661 if (instr
->is_array
)
2662 offset_components
= instr
->coord_components
- 1;
2664 offset_components
= instr
->coord_components
;
2666 case nir_tex_src_projector
:
2667 unreachable("should be lowered");
2669 case nir_tex_src_sampler_offset
: {
2670 /* Figure out the highest possible sampler index and mark it as used */
2671 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
2672 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
2673 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
2675 max_used
+= stage_prog_data
->binding_table
.texture_start
;
2677 brw_mark_surface_used(prog_data
, max_used
);
2679 /* Emit code to evaluate the actual indexing expression */
2680 sampler_reg
= vgrf(glsl_type::uint_type
);
2681 bld
.ADD(sampler_reg
, src
, brw_imm_ud(sampler
));
2682 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
2687 unreachable("unknown texture source");
2691 if (instr
->op
== nir_texop_txf_ms
||
2692 instr
->op
== nir_texop_samples_identical
) {
2693 if (devinfo
->gen
>= 7 &&
2694 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
2695 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
2697 mcs
= brw_imm_ud(0u);
2701 for (unsigned i
= 0; i
< 3; i
++) {
2702 if (instr
->const_offset
[i
] != 0) {
2703 assert(offset_components
== 0);
2704 tex_offset
= brw_imm_ud(brw_texture_offset(instr
->const_offset
, 3));
2709 enum glsl_base_type dest_base_type
=
2710 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
2712 const glsl_type
*dest_type
=
2713 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
2716 ir_texture_opcode op
;
2717 switch (instr
->op
) {
2718 case nir_texop_lod
: op
= ir_lod
; break;
2719 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2720 case nir_texop_tex
: op
= ir_tex
; break;
2721 case nir_texop_tg4
: op
= ir_tg4
; break;
2722 case nir_texop_txb
: op
= ir_txb
; break;
2723 case nir_texop_txd
: op
= ir_txd
; break;
2724 case nir_texop_txf
: op
= ir_txf
; break;
2725 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2726 case nir_texop_txl
: op
= ir_txl
; break;
2727 case nir_texop_txs
: op
= ir_txs
; break;
2728 case nir_texop_texture_samples
: {
2729 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
2730 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
2731 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
2734 inst
->header_size
= 1;
2735 inst
->base_mrf
= -1;
2738 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2740 unreachable("unknown texture opcode");
2743 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
2744 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
2745 tex_offset
, mcs
, gather_component
,
2746 is_cube_array
, is_rect
, sampler
, sampler_reg
);
2748 fs_reg dest
= get_nir_dest(instr
->dest
);
2749 dest
.type
= this->result
.type
;
2750 unsigned num_components
= nir_tex_instr_dest_size(instr
);
2751 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
2752 dest
, this->result
),
2753 (1 << num_components
) - 1);
2757 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
2759 switch (instr
->type
) {
2760 case nir_jump_break
:
2761 bld
.emit(BRW_OPCODE_BREAK
);
2763 case nir_jump_continue
:
2764 bld
.emit(BRW_OPCODE_CONTINUE
);
2766 case nir_jump_return
:
2768 unreachable("unknown jump");