2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
30 nir_optimize(nir_shader
*nir
)
35 nir_lower_vars_to_ssa(nir
);
36 nir_validate_shader(nir
);
37 nir_lower_alu_to_scalar(nir
);
38 nir_validate_shader(nir
);
39 progress
|= nir_copy_prop(nir
);
40 nir_validate_shader(nir
);
41 nir_lower_phis_to_scalar(nir
);
42 nir_validate_shader(nir
);
43 progress
|= nir_copy_prop(nir
);
44 nir_validate_shader(nir
);
45 progress
|= nir_opt_dce(nir
);
46 nir_validate_shader(nir
);
47 progress
|= nir_opt_cse(nir
);
48 nir_validate_shader(nir
);
49 progress
|= nir_opt_peephole_select(nir
);
50 nir_validate_shader(nir
);
51 progress
|= nir_opt_algebraic(nir
);
52 nir_validate_shader(nir
);
53 progress
|= nir_opt_constant_folding(nir
);
54 nir_validate_shader(nir
);
55 progress
|= nir_opt_remove_phis(nir
);
56 nir_validate_shader(nir
);
61 count_nir_instrs_in_block(nir_block
*block
, void *state
)
63 int *count
= (int *) state
;
64 nir_foreach_instr(block
, instr
) {
71 count_nir_instrs(nir_shader
*nir
)
74 nir_foreach_overload(nir
, overload
) {
77 nir_foreach_block(overload
->impl
, count_nir_instrs_in_block
, &count
);
83 fs_visitor::emit_nir_code()
85 const nir_shader_compiler_options
*options
=
86 ctx
->Const
.ShaderCompilerOptions
[stage
].NirOptions
;
88 /* first, lower the GLSL IR shader to NIR */
89 lower_output_reads(shader
->base
.ir
);
90 nir_shader
*nir
= glsl_to_nir(&shader
->base
, options
);
91 nir_validate_shader(nir
);
93 nir_lower_global_vars_to_local(nir
);
94 nir_validate_shader(nir
);
96 nir_split_var_copies(nir
);
97 nir_validate_shader(nir
);
101 /* Lower a bunch of stuff */
102 nir_lower_var_copies(nir
);
103 nir_validate_shader(nir
);
105 /* Get rid of split copies */
109 nir_validate_shader(nir
);
111 nir_remove_dead_variables(nir
);
112 nir_validate_shader(nir
);
114 nir_lower_samplers(nir
, shader_prog
, shader
->base
.Program
);
115 nir_validate_shader(nir
);
117 nir_lower_system_values(nir
);
118 nir_validate_shader(nir
);
120 nir_lower_atomics(nir
);
121 nir_validate_shader(nir
);
125 nir_lower_locals_to_regs(nir
);
126 nir_validate_shader(nir
);
128 nir_lower_to_source_mods(nir
);
129 nir_validate_shader(nir
);
131 nir_validate_shader(nir
);
133 if (unlikely(debug_enabled
)) {
134 fprintf(stderr
, "NIR (SSA form) for %s shader:\n", stage_name
);
135 nir_print_shader(nir
, stderr
);
138 if (dispatch_width
== 8) {
139 static GLuint msg_id
= 0;
140 _mesa_gl_debug(&brw
->ctx
, &msg_id
,
141 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
142 MESA_DEBUG_TYPE_OTHER
,
143 MESA_DEBUG_SEVERITY_NOTIFICATION
,
144 "%s NIR shader: %d inst\n",
146 count_nir_instrs(nir
));
149 nir_convert_from_ssa(nir
);
150 nir_validate_shader(nir
);
152 /* emit the arrays used for inputs and outputs - load/store intrinsics will
153 * be converted to reads/writes of these arrays
156 if (nir
->num_inputs
> 0) {
157 nir_inputs
= vgrf(nir
->num_inputs
);
158 nir_setup_inputs(nir
);
161 if (nir
->num_outputs
> 0) {
162 nir_outputs
= vgrf(nir
->num_outputs
);
163 nir_setup_outputs(nir
);
166 if (nir
->num_uniforms
> 0) {
167 nir_uniforms
= fs_reg(UNIFORM
, 0);
168 nir_setup_uniforms(nir
);
171 nir_emit_system_values(nir
);
173 nir_globals
= ralloc_array(mem_ctx
, fs_reg
, nir
->reg_alloc
);
174 foreach_list_typed(nir_register
, reg
, node
, &nir
->registers
) {
175 unsigned array_elems
=
176 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
177 unsigned size
= array_elems
* reg
->num_components
;
178 nir_globals
[reg
->index
] = vgrf(size
);
181 /* get the main function and emit it */
182 nir_foreach_overload(nir
, overload
) {
183 assert(strcmp(overload
->function
->name
, "main") == 0);
184 assert(overload
->impl
);
185 nir_emit_impl(overload
->impl
);
188 if (unlikely(debug_enabled
)) {
189 fprintf(stderr
, "NIR (final form) for %s shader:\n", stage_name
);
190 nir_print_shader(nir
, stderr
);
197 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
199 struct hash_entry
*entry
;
200 hash_table_foreach(shader
->inputs
, entry
) {
201 nir_variable
*var
= (nir_variable
*) entry
->data
;
202 fs_reg varying
= offset(nir_inputs
, var
->data
.driver_location
);
205 if (var
->data
.location
== VARYING_SLOT_POS
) {
206 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
207 var
->data
.origin_upper_left
);
208 emit_percomp(MOV(varying
, reg
), 0xF);
210 emit_general_interpolation(varying
, var
->name
, var
->type
,
211 (glsl_interp_qualifier
) var
->data
.interpolation
,
212 var
->data
.location
, var
->data
.centroid
,
219 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
221 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
223 struct hash_entry
*entry
;
224 hash_table_foreach(shader
->outputs
, entry
) {
225 nir_variable
*var
= (nir_variable
*) entry
->data
;
226 fs_reg reg
= offset(nir_outputs
, var
->data
.driver_location
);
228 if (var
->data
.index
> 0) {
229 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
230 assert(var
->data
.index
== 1);
231 this->dual_src_output
= reg
;
232 this->do_dual_src
= true;
233 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
234 /* Writing gl_FragColor outputs to all color regions. */
235 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
236 this->outputs
[i
] = reg
;
237 this->output_components
[i
] = 4;
239 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
240 this->frag_depth
= reg
;
241 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
242 this->sample_mask
= reg
;
244 /* gl_FragData or a user-defined FS output */
245 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
246 var
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
248 int vector_elements
=
249 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
250 : var
->type
->vector_elements
;
252 /* General color output. */
253 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
254 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
255 this->outputs
[output
] = offset(reg
, vector_elements
* i
);
256 this->output_components
[output
] = vector_elements
;
263 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
265 uniforms
= shader
->num_uniforms
;
266 param_size
[0] = shader
->num_uniforms
;
268 if (dispatch_width
!= 8)
271 struct hash_entry
*entry
;
272 hash_table_foreach(shader
->uniforms
, entry
) {
273 nir_variable
*var
= (nir_variable
*) entry
->data
;
275 /* UBO's and atomics don't take up space in the uniform file */
277 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
280 if (strncmp(var
->name
, "gl_", 3) == 0)
281 nir_setup_builtin_uniform(var
);
283 nir_setup_uniform(var
);
288 fs_visitor::nir_setup_uniform(nir_variable
*var
)
290 int namelen
= strlen(var
->name
);
292 /* The data for our (non-builtin) uniforms is stored in a series of
293 * gl_uniform_driver_storage structs for each subcomponent that
294 * glGetUniformLocation() could name. We know it's been set up in the
295 * same order we'd walk the type, so walk the list of storage and find
296 * anything with our name, or the prefix of a component that starts with
299 unsigned index
= var
->data
.driver_location
;
300 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
301 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
303 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
304 (storage
->name
[namelen
] != 0 &&
305 storage
->name
[namelen
] != '.' &&
306 storage
->name
[namelen
] != '[')) {
310 unsigned slots
= storage
->type
->component_slots();
311 if (storage
->array_elements
)
312 slots
*= storage
->array_elements
;
314 for (unsigned i
= 0; i
< slots
; i
++) {
315 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
319 /* Make sure we actually initialized the right amount of stuff here. */
320 assert(var
->data
.driver_location
+ var
->type
->component_slots() == index
);
324 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
326 const nir_state_slot
*const slots
= var
->state_slots
;
327 assert(var
->state_slots
!= NULL
);
329 unsigned uniform_index
= var
->data
.driver_location
;
330 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
331 /* This state reference has already been setup by ir_to_mesa, but we'll
332 * get the same index back here.
334 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
335 (gl_state_index
*)slots
[i
].tokens
);
337 /* Add each of the unique swizzles of the element as a parameter.
338 * This'll end up matching the expected layout of the
339 * array/matrix/structure we're trying to fill in.
342 for (unsigned int j
= 0; j
< 4; j
++) {
343 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
344 if (swiz
== last_swiz
)
348 stage_prog_data
->param
[uniform_index
++] =
349 &prog
->Parameters
->ParameterValues
[index
][swiz
];
355 emit_system_values_block(nir_block
*block
, void *void_visitor
)
357 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
360 nir_foreach_instr(block
, instr
) {
361 if (instr
->type
!= nir_instr_type_intrinsic
)
364 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
365 switch (intrin
->intrinsic
) {
366 case nir_intrinsic_load_sample_pos
:
367 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
368 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
369 if (reg
->file
== BAD_FILE
)
370 *reg
= *v
->emit_samplepos_setup();
373 case nir_intrinsic_load_sample_id
:
374 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
375 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
376 if (reg
->file
== BAD_FILE
)
377 *reg
= *v
->emit_sampleid_setup();
380 case nir_intrinsic_load_sample_mask_in
:
381 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
382 assert(v
->brw
->gen
>= 7);
383 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
384 if (reg
->file
== BAD_FILE
)
385 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
386 BRW_REGISTER_TYPE_D
));
398 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
400 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
401 nir_foreach_overload(shader
, overload
) {
402 assert(strcmp(overload
->function
->name
, "main") == 0);
403 assert(overload
->impl
);
404 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
409 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
411 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
412 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
413 unsigned array_elems
=
414 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
415 unsigned size
= array_elems
* reg
->num_components
;
416 nir_locals
[reg
->index
] = vgrf(size
);
419 nir_emit_cf_list(&impl
->body
);
423 fs_visitor::nir_emit_cf_list(exec_list
*list
)
425 exec_list_validate(list
);
426 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
427 switch (node
->type
) {
429 nir_emit_if(nir_cf_node_as_if(node
));
432 case nir_cf_node_loop
:
433 nir_emit_loop(nir_cf_node_as_loop(node
));
436 case nir_cf_node_block
:
437 nir_emit_block(nir_cf_node_as_block(node
));
441 unreachable("Invalid CFG node block");
447 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
449 /* first, put the condition into f0 */
450 fs_inst
*inst
= emit(MOV(reg_null_d
,
451 retype(get_nir_src(if_stmt
->condition
),
452 BRW_REGISTER_TYPE_UD
)));
453 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
455 emit(IF(BRW_PREDICATE_NORMAL
));
457 nir_emit_cf_list(&if_stmt
->then_list
);
459 /* note: if the else is empty, dead CF elimination will remove it */
460 emit(BRW_OPCODE_ELSE
);
462 nir_emit_cf_list(&if_stmt
->else_list
);
464 emit(BRW_OPCODE_ENDIF
);
466 if (!try_replace_with_sel() && brw
->gen
< 6) {
467 no16("Can't support (non-uniform) control flow on SIMD16\n");
472 fs_visitor::nir_emit_loop(nir_loop
*loop
)
475 no16("Can't support (non-uniform) control flow on SIMD16\n");
480 nir_emit_cf_list(&loop
->body
);
482 emit(BRW_OPCODE_WHILE
);
486 fs_visitor::nir_emit_block(nir_block
*block
)
488 nir_foreach_instr(block
, instr
) {
489 nir_emit_instr(instr
);
494 fs_visitor::nir_emit_instr(nir_instr
*instr
)
496 switch (instr
->type
) {
497 case nir_instr_type_alu
:
498 nir_emit_alu(nir_instr_as_alu(instr
));
501 case nir_instr_type_intrinsic
:
502 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
505 case nir_instr_type_tex
:
506 nir_emit_texture(nir_instr_as_tex(instr
));
509 case nir_instr_type_load_const
:
510 /* We can hit these, but we do nothing now and use them as
515 case nir_instr_type_jump
:
516 nir_emit_jump(nir_instr_as_jump(instr
));
520 unreachable("unknown instruction type");
525 brw_type_for_nir_type(nir_alu_type type
)
529 case nir_type_unsigned
:
530 return BRW_REGISTER_TYPE_UD
;
532 return BRW_REGISTER_TYPE_D
;
534 return BRW_REGISTER_TYPE_F
;
536 unreachable("unknown type");
539 return BRW_REGISTER_TYPE_F
;
543 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
544 const fs_reg
&result
)
546 if (instr
->src
[0].src
.is_ssa
||
547 !instr
->src
[0].src
.reg
.reg
||
548 !instr
->src
[0].src
.reg
.reg
->parent_instr
)
551 if (instr
->src
[0].src
.reg
.reg
->parent_instr
->type
!=
552 nir_instr_type_intrinsic
)
555 nir_intrinsic_instr
*src0
=
556 nir_instr_as_intrinsic(instr
->src
[0].src
.reg
.reg
->parent_instr
);
558 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
561 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
562 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
565 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
566 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
569 fs_reg tmp
= vgrf(glsl_type::int_type
);
572 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
573 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
575 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
577 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
578 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
580 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
582 * This negation looks like it's safe in practice, because bits 0:4 will
583 * surely be TRIANGLES
586 if (value1
->f
[0] == -1.0f
) {
590 tmp
.type
= BRW_REGISTER_TYPE_W
;
591 tmp
.subreg_offset
= 2;
594 fs_inst
*or_inst
= emit(OR(tmp
, g0
, fs_reg(0x3f80)));
595 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
597 tmp
.type
= BRW_REGISTER_TYPE_D
;
598 tmp
.subreg_offset
= 0;
601 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
602 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
604 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
606 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
607 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
609 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
611 * This negation looks like it's safe in practice, because bits 0:4 will
612 * surely be TRIANGLES
615 if (value1
->f
[0] == -1.0f
) {
619 emit(OR(tmp
, g1_6
, fs_reg(0x3f800000)));
621 emit(AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000)));
627 fs_visitor::nir_emit_alu(nir_alu_instr
*instr
)
629 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
632 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
633 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
636 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
637 op
[i
] = get_nir_src(instr
->src
[i
].src
);
638 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
639 op
[i
].abs
= instr
->src
[i
].abs
;
640 op
[i
].negate
= instr
->src
[i
].negate
;
643 /* We get a bunch of mov's out of the from_ssa pass and they may still
644 * be vectorized. We'll handle them as a special-case. We'll also
645 * handle vecN here because it's basically the same thing.
653 fs_reg temp
= result
;
654 bool need_extra_copy
= false;
655 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
656 if (!instr
->src
[i
].src
.is_ssa
&&
657 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
658 need_extra_copy
= true;
659 temp
= retype(vgrf(4), result
.type
);
664 for (unsigned i
= 0; i
< 4; i
++) {
665 if (!(instr
->dest
.write_mask
& (1 << i
)))
668 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
669 inst
= emit(MOV(offset(temp
, i
),
670 offset(op
[0], instr
->src
[0].swizzle
[i
])));
672 inst
= emit(MOV(offset(temp
, i
),
673 offset(op
[i
], instr
->src
[i
].swizzle
[0])));
675 inst
->saturate
= instr
->dest
.saturate
;
678 /* In this case the source and destination registers were the same,
679 * so we need to insert an extra set of moves in order to deal with
682 if (need_extra_copy
) {
683 for (unsigned i
= 0; i
< 4; i
++) {
684 if (!(instr
->dest
.write_mask
& (1 << i
)))
687 emit(MOV(offset(result
, i
), offset(temp
, i
)));
696 /* At this point, we have dealt with any instruction that operates on
697 * more than a single channel. Therefore, we can just adjust the source
698 * and destination registers for that channel and emit the instruction.
700 unsigned channel
= 0;
701 if (nir_op_infos
[instr
->op
].output_size
== 0) {
702 /* Since NIR is doing the scalarizing for us, we should only ever see
703 * vectorized operations with a single channel.
705 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
706 channel
= ffs(instr
->dest
.write_mask
) - 1;
708 result
= offset(result
, channel
);
711 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
712 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
713 op
[i
] = offset(op
[i
], instr
->src
[i
].swizzle
[channel
]);
719 inst
= emit(MOV(result
, op
[0]));
720 inst
->saturate
= instr
->dest
.saturate
;
725 emit(MOV(result
, op
[0]));
729 /* AND(val, 0x80000000) gives the sign bit.
731 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
734 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
736 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
737 op
[0].type
= BRW_REGISTER_TYPE_UD
;
738 result
.type
= BRW_REGISTER_TYPE_UD
;
739 emit(AND(result_int
, op
[0], fs_reg(0x80000000u
)));
741 inst
= emit(OR(result_int
, result_int
, fs_reg(0x3f800000u
)));
742 inst
->predicate
= BRW_PREDICATE_NORMAL
;
743 if (instr
->dest
.saturate
) {
744 inst
= emit(MOV(result
, result
));
745 inst
->saturate
= true;
751 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
752 * -> non-negative val generates 0x00000000.
753 * Predicated OR sets 1 if val is positive.
755 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
));
756 emit(ASR(result
, op
[0], fs_reg(31)));
757 inst
= emit(OR(result
, result
, fs_reg(1)));
758 inst
->predicate
= BRW_PREDICATE_NORMAL
;
762 inst
= emit_math(SHADER_OPCODE_RCP
, result
, op
[0]);
763 inst
->saturate
= instr
->dest
.saturate
;
767 inst
= emit_math(SHADER_OPCODE_EXP2
, result
, op
[0]);
768 inst
->saturate
= instr
->dest
.saturate
;
772 inst
= emit_math(SHADER_OPCODE_LOG2
, result
, op
[0]);
773 inst
->saturate
= instr
->dest
.saturate
;
778 unreachable("not reached: should be handled by ir_explog_to_explog2");
781 case nir_op_fsin_reduced
:
782 inst
= emit_math(SHADER_OPCODE_SIN
, result
, op
[0]);
783 inst
->saturate
= instr
->dest
.saturate
;
787 case nir_op_fcos_reduced
:
788 inst
= emit_math(SHADER_OPCODE_COS
, result
, op
[0]);
789 inst
->saturate
= instr
->dest
.saturate
;
793 if (fs_key
->high_quality_derivatives
) {
794 inst
= emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
796 inst
= emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
798 inst
->saturate
= instr
->dest
.saturate
;
800 case nir_op_fddx_fine
:
801 inst
= emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
802 inst
->saturate
= instr
->dest
.saturate
;
804 case nir_op_fddx_coarse
:
805 inst
= emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
806 inst
->saturate
= instr
->dest
.saturate
;
809 if (fs_key
->high_quality_derivatives
) {
810 inst
= emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
811 fs_reg(fs_key
->render_to_fbo
));
813 inst
= emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
814 fs_reg(fs_key
->render_to_fbo
));
816 inst
->saturate
= instr
->dest
.saturate
;
818 case nir_op_fddy_fine
:
819 inst
= emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
820 fs_reg(fs_key
->render_to_fbo
));
821 inst
->saturate
= instr
->dest
.saturate
;
823 case nir_op_fddy_coarse
:
824 inst
= emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
825 fs_reg(fs_key
->render_to_fbo
));
826 inst
->saturate
= instr
->dest
.saturate
;
831 inst
= emit(ADD(result
, op
[0], op
[1]));
832 inst
->saturate
= instr
->dest
.saturate
;
836 inst
= emit(MUL(result
, op
[0], op
[1]));
837 inst
->saturate
= instr
->dest
.saturate
;
842 emit(MUL(result
, op
[0], op
[1]));
845 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
846 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
848 if (value0
&& value0
->u
[0] < (1 << 16)) {
850 emit(MUL(result
, op
[0], op
[1]));
852 emit(MUL(result
, op
[1], op
[0]));
855 } else if (value1
&& value1
->u
[0] < (1 << 16)) {
857 emit(MUL(result
, op
[1], op
[0]));
859 emit(MUL(result
, op
[0], op
[1]));
866 no16("SIMD16 explicit accumulator operands unsupported\n");
868 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
870 emit(MUL(acc
, op
[0], op
[1]));
871 emit(MACH(reg_null_d
, op
[0], op
[1]));
872 emit(MOV(result
, fs_reg(acc
)));
876 case nir_op_imul_high
:
877 case nir_op_umul_high
: {
879 no16("SIMD16 explicit accumulator operands unsupported\n");
881 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
883 emit(MUL(acc
, op
[0], op
[1]));
884 emit(MACH(result
, op
[0], op
[1]));
890 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
893 case nir_op_uadd_carry
: {
895 no16("SIMD16 explicit accumulator operands unsupported\n");
897 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
898 BRW_REGISTER_TYPE_UD
);
900 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
901 emit(MOV(result
, fs_reg(acc
)));
905 case nir_op_usub_borrow
: {
907 no16("SIMD16 explicit accumulator operands unsupported\n");
909 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
910 BRW_REGISTER_TYPE_UD
);
912 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
913 emit(MOV(result
, fs_reg(acc
)));
918 emit_math(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
924 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
));
930 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
));
935 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
940 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
945 resolve_source_modifiers(&op
[0]);
947 emit(NOT(result
, op
[0]));
951 resolve_source_modifiers(&op
[0]);
952 resolve_source_modifiers(&op
[1]);
954 emit(XOR(result
, op
[0], op
[1]));
958 resolve_source_modifiers(&op
[0]);
959 resolve_source_modifiers(&op
[1]);
961 emit(OR(result
, op
[0], op
[1]));
965 resolve_source_modifiers(&op
[0]);
966 resolve_source_modifiers(&op
[1]);
968 emit(AND(result
, op
[0], op
[1]));
980 case nir_op_ball_fequal2
:
981 case nir_op_ball_iequal2
:
982 case nir_op_ball_fequal3
:
983 case nir_op_ball_iequal3
:
984 case nir_op_ball_fequal4
:
985 case nir_op_ball_iequal4
:
986 case nir_op_bany_fnequal2
:
987 case nir_op_bany_inequal2
:
988 case nir_op_bany_fnequal3
:
989 case nir_op_bany_inequal3
:
990 case nir_op_bany_fnequal4
:
991 case nir_op_bany_inequal4
:
992 unreachable("Lowered by nir_lower_alu_reductions");
994 case nir_op_fnoise1_1
:
995 case nir_op_fnoise1_2
:
996 case nir_op_fnoise1_3
:
997 case nir_op_fnoise1_4
:
998 case nir_op_fnoise2_1
:
999 case nir_op_fnoise2_2
:
1000 case nir_op_fnoise2_3
:
1001 case nir_op_fnoise2_4
:
1002 case nir_op_fnoise3_1
:
1003 case nir_op_fnoise3_2
:
1004 case nir_op_fnoise3_3
:
1005 case nir_op_fnoise3_4
:
1006 case nir_op_fnoise4_1
:
1007 case nir_op_fnoise4_2
:
1008 case nir_op_fnoise4_3
:
1009 case nir_op_fnoise4_4
:
1010 unreachable("not reached: should be handled by lower_noise");
1013 unreachable("not reached: should be handled by ldexp_to_arith()");
1016 inst
= emit_math(SHADER_OPCODE_SQRT
, result
, op
[0]);
1017 inst
->saturate
= instr
->dest
.saturate
;
1021 inst
= emit_math(SHADER_OPCODE_RSQ
, result
, op
[0]);
1022 inst
->saturate
= instr
->dest
.saturate
;
1026 emit(AND(result
, op
[0], fs_reg(1)));
1029 emit(AND(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0], fs_reg(0x3f800000u
)));
1033 emit(CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1036 emit(CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1040 inst
= emit(RNDZ(result
, op
[0]));
1041 inst
->saturate
= instr
->dest
.saturate
;
1044 case nir_op_fceil
: {
1045 op
[0].negate
= !op
[0].negate
;
1046 fs_reg temp
= vgrf(glsl_type::float_type
);
1047 emit(RNDD(temp
, op
[0]));
1049 inst
= emit(MOV(result
, temp
));
1050 inst
->saturate
= instr
->dest
.saturate
;
1054 inst
= emit(RNDD(result
, op
[0]));
1055 inst
->saturate
= instr
->dest
.saturate
;
1058 inst
= emit(FRC(result
, op
[0]));
1059 inst
->saturate
= instr
->dest
.saturate
;
1061 case nir_op_fround_even
:
1062 inst
= emit(RNDE(result
, op
[0]));
1063 inst
->saturate
= instr
->dest
.saturate
;
1069 if (brw
->gen
>= 6) {
1070 inst
= emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1071 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1073 emit(CMP(reg_null_d
, op
[0], op
[1], BRW_CONDITIONAL_L
));
1074 inst
= emit(SEL(result
, op
[0], op
[1]));
1076 inst
->saturate
= instr
->dest
.saturate
;
1082 if (brw
->gen
>= 6) {
1083 inst
= emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1084 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1086 emit(CMP(reg_null_d
, op
[0], op
[1], BRW_CONDITIONAL_GE
));
1087 inst
= emit(SEL(result
, op
[0], op
[1]));
1089 inst
->saturate
= instr
->dest
.saturate
;
1092 case nir_op_pack_snorm_2x16
:
1093 case nir_op_pack_snorm_4x8
:
1094 case nir_op_pack_unorm_2x16
:
1095 case nir_op_pack_unorm_4x8
:
1096 case nir_op_unpack_snorm_2x16
:
1097 case nir_op_unpack_snorm_4x8
:
1098 case nir_op_unpack_unorm_2x16
:
1099 case nir_op_unpack_unorm_4x8
:
1100 case nir_op_unpack_half_2x16
:
1101 case nir_op_pack_half_2x16
:
1102 unreachable("not reached: should be handled by lower_packing_builtins");
1104 case nir_op_unpack_half_2x16_split_x
:
1105 inst
= emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1106 inst
->saturate
= instr
->dest
.saturate
;
1108 case nir_op_unpack_half_2x16_split_y
:
1109 inst
= emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1110 inst
->saturate
= instr
->dest
.saturate
;
1114 inst
= emit_math(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1115 inst
->saturate
= instr
->dest
.saturate
;
1118 case nir_op_bitfield_reverse
:
1119 emit(BFREV(result
, op
[0]));
1122 case nir_op_bit_count
:
1123 emit(CBIT(result
, op
[0]));
1126 case nir_op_ufind_msb
:
1127 case nir_op_ifind_msb
: {
1128 emit(FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]));
1130 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1131 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1132 * subtract the result from 31 to convert the MSB count into an LSB count.
1135 emit(CMP(reg_null_d
, result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
1136 fs_reg
neg_result(result
);
1137 neg_result
.negate
= true;
1138 inst
= emit(ADD(result
, neg_result
, fs_reg(31)));
1139 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1143 case nir_op_find_lsb
:
1144 emit(FBL(result
, op
[0]));
1147 case nir_op_ubitfield_extract
:
1148 case nir_op_ibitfield_extract
:
1149 emit(BFE(result
, op
[2], op
[1], op
[0]));
1152 emit(BFI1(result
, op
[0], op
[1]));
1155 emit(BFI2(result
, op
[0], op
[1], op
[2]));
1158 case nir_op_bitfield_insert
:
1159 unreachable("not reached: should be handled by "
1160 "lower_instructions::bitfield_insert_to_bfm_bfi");
1163 emit(SHL(result
, op
[0], op
[1]));
1166 emit(ASR(result
, op
[0], op
[1]));
1169 emit(SHR(result
, op
[0], op
[1]));
1172 case nir_op_pack_half_2x16_split
:
1173 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1177 inst
= emit(MAD(result
, op
[2], op
[1], op
[0]));
1178 inst
->saturate
= instr
->dest
.saturate
;
1182 /* TODO emulate for gen < 6 */
1183 inst
= emit(LRP(result
, op
[2], op
[1], op
[0]));
1184 inst
->saturate
= instr
->dest
.saturate
;
1188 if (optimize_frontfacing_ternary(instr
, result
))
1191 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1192 inst
= emit(SEL(result
, op
[1], op
[2]));
1193 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1197 unreachable("unhandled instruction");
1202 fs_visitor::get_nir_src(nir_src src
)
1205 assert(src
.ssa
->parent_instr
->type
== nir_instr_type_load_const
);
1206 nir_load_const_instr
*load
= nir_instr_as_load_const(src
.ssa
->parent_instr
);
1207 fs_reg reg
= vgrf(src
.ssa
->num_components
);
1208 reg
.type
= BRW_REGISTER_TYPE_D
;
1210 for (unsigned i
= 0; i
< src
.ssa
->num_components
; ++i
)
1211 emit(MOV(offset(reg
, i
), fs_reg(load
->value
.i
[i
])));
1216 if (src
.reg
.reg
->is_global
)
1217 reg
= nir_globals
[src
.reg
.reg
->index
];
1219 reg
= nir_locals
[src
.reg
.reg
->index
];
1221 /* to avoid floating-point denorm flushing problems, set the type by
1222 * default to D - instructions that need floating point semantics will set
1223 * this to F if they need to
1225 reg
= retype(offset(reg
, src
.reg
.base_offset
), BRW_REGISTER_TYPE_D
);
1226 if (src
.reg
.indirect
) {
1227 reg
.reladdr
= new(mem_ctx
) fs_reg();
1228 *reg
.reladdr
= retype(get_nir_src(*src
.reg
.indirect
),
1229 BRW_REGISTER_TYPE_D
);
1237 fs_visitor::get_nir_dest(nir_dest dest
)
1240 if (dest
.reg
.reg
->is_global
)
1241 reg
= nir_globals
[dest
.reg
.reg
->index
];
1243 reg
= nir_locals
[dest
.reg
.reg
->index
];
1245 reg
= offset(reg
, dest
.reg
.base_offset
);
1246 if (dest
.reg
.indirect
) {
1247 reg
.reladdr
= new(mem_ctx
) fs_reg();
1248 *reg
.reladdr
= retype(get_nir_src(*dest
.reg
.indirect
),
1249 BRW_REGISTER_TYPE_D
);
1256 fs_visitor::emit_percomp(fs_inst
*inst
, unsigned wr_mask
)
1258 for (unsigned i
= 0; i
< 4; i
++) {
1259 if (!((wr_mask
>> i
) & 1))
1262 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(*inst
);
1263 new_inst
->dst
= offset(new_inst
->dst
, i
);
1264 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1265 if (inst
->src
[j
].file
== GRF
)
1266 new_inst
->src
[j
] = offset(new_inst
->src
[j
], i
);
1273 fs_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
1276 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1277 dest
= get_nir_dest(instr
->dest
);
1279 bool has_indirect
= false;
1281 switch (instr
->intrinsic
) {
1282 case nir_intrinsic_discard
:
1283 case nir_intrinsic_discard_if
: {
1284 /* We track our discarded pixels in f0.1. By predicating on it, we can
1285 * update just the flag bits that aren't yet discarded. If there's no
1286 * condition, we emit a CMP of g0 != g0, so all currently executing
1287 * channels will get turned off.
1290 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1291 cmp
= emit(CMP(reg_null_f
, get_nir_src(instr
->src
[0]),
1292 fs_reg(0), BRW_CONDITIONAL_Z
));
1294 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1295 BRW_REGISTER_TYPE_UW
));
1296 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
, BRW_CONDITIONAL_NZ
));
1298 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1299 cmp
->flag_subreg
= 1;
1301 if (brw
->gen
>= 6) {
1302 /* For performance, after a discard, jump to the end of the shader.
1303 * Only jump if all relevant channels have been discarded.
1305 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1306 discard_jump
->flag_subreg
= 1;
1308 discard_jump
->predicate
= (dispatch_width
== 8)
1309 ? BRW_PREDICATE_ALIGN1_ANY8H
1310 : BRW_PREDICATE_ALIGN1_ANY16H
;
1311 discard_jump
->predicate_inverse
= true;
1317 case nir_intrinsic_atomic_counter_inc
:
1318 case nir_intrinsic_atomic_counter_dec
:
1319 case nir_intrinsic_atomic_counter_read
: {
1320 unsigned surf_index
= prog_data
->binding_table
.abo_start
+
1321 (unsigned) instr
->const_index
[0];
1322 fs_reg offset
= fs_reg(get_nir_src(instr
->src
[0]));
1324 switch (instr
->intrinsic
) {
1325 case nir_intrinsic_atomic_counter_inc
:
1326 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
1327 fs_reg(), fs_reg());
1329 case nir_intrinsic_atomic_counter_dec
:
1330 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
1331 fs_reg(), fs_reg());
1333 case nir_intrinsic_atomic_counter_read
:
1334 emit_untyped_surface_read(surf_index
, dest
, offset
);
1337 unreachable("Unreachable");
1342 case nir_intrinsic_load_front_face
:
1343 emit(MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1344 *emit_frontfacing_interpolation()));
1347 case nir_intrinsic_load_sample_mask_in
: {
1348 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1349 assert(sample_mask_in
.file
!= BAD_FILE
);
1350 dest
.type
= sample_mask_in
.type
;
1351 emit(MOV(dest
, sample_mask_in
));
1355 case nir_intrinsic_load_sample_pos
: {
1356 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1357 assert(sample_pos
.file
!= BAD_FILE
);
1358 dest
.type
= sample_pos
.type
;
1359 emit(MOV(dest
, sample_pos
));
1360 emit(MOV(offset(dest
, 1), offset(sample_pos
, 1)));
1364 case nir_intrinsic_load_sample_id
: {
1365 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1366 assert(sample_id
.file
!= BAD_FILE
);
1367 dest
.type
= sample_id
.type
;
1368 emit(MOV(dest
, sample_id
));
1372 case nir_intrinsic_load_uniform_indirect
:
1373 has_indirect
= true;
1374 case nir_intrinsic_load_uniform
: {
1376 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1377 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1378 fs_reg src
= offset(retype(nir_uniforms
, dest
.type
),
1379 instr
->const_index
[0] + index
);
1381 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1384 emit(MOV(dest
, src
));
1385 dest
= offset(dest
, 1);
1391 case nir_intrinsic_load_ubo_indirect
:
1392 has_indirect
= true;
1394 case nir_intrinsic_load_ubo
: {
1395 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1399 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1402 /* The block index is not a constant. Evaluate the index expression
1403 * per-channel and add the base UBO index; the generator will select
1404 * a value from any live channel.
1406 surf_index
= vgrf(glsl_type::uint_type
);
1407 emit(ADD(surf_index
, get_nir_src(instr
->src
[0]),
1408 fs_reg(stage_prog_data
->binding_table
.ubo_start
)))
1409 ->force_writemask_all
= true;
1411 /* Assume this may touch any UBO. It would be nice to provide
1412 * a tighter bound, but the array information is already lowered away.
1414 brw_mark_surface_used(prog_data
,
1415 stage_prog_data
->binding_table
.ubo_start
+
1416 shader_prog
->NumUniformBlocks
- 1);
1420 /* Turn the byte offset into a dword offset. */
1421 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1422 emit(SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1423 BRW_REGISTER_TYPE_D
),
1426 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1427 for (int i
= 0; i
< instr
->num_components
; i
++)
1428 emit(VARYING_PULL_CONSTANT_LOAD(offset(dest
, i
), surf_index
,
1429 base_offset
, vec4_offset
+ i
));
1431 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1432 packed_consts
.type
= dest
.type
;
1434 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1435 emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1436 surf_index
, const_offset_reg
);
1438 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1439 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1441 /* The std140 packing rules don't allow vectors to cross 16-byte
1442 * boundaries, and a reg is 32 bytes.
1444 assert(packed_consts
.subreg_offset
< 32);
1446 emit(MOV(dest
, packed_consts
));
1447 dest
= offset(dest
, 1);
1453 case nir_intrinsic_load_input_indirect
:
1454 has_indirect
= true;
1456 case nir_intrinsic_load_input
: {
1458 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1459 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1460 fs_reg src
= offset(retype(nir_inputs
, dest
.type
),
1461 instr
->const_index
[0] + index
);
1463 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1466 emit(MOV(dest
, src
));
1467 dest
= offset(dest
, 1);
1473 /* Handle ARB_gpu_shader5 interpolation intrinsics
1475 * It's worth a quick word of explanation as to why we handle the full
1476 * variable-based interpolation intrinsic rather than a lowered version
1477 * with like we do for other inputs. We have to do that because the way
1478 * we set up inputs doesn't allow us to use the already setup inputs for
1479 * interpolation. At the beginning of the shader, we go through all of
1480 * the input variables and do the initial interpolation and put it in
1481 * the nir_inputs array based on its location as determined in
1482 * nir_lower_io. If the input isn't used, dead code cleans up and
1483 * everything works fine. However, when we get to the ARB_gpu_shader5
1484 * interpolation intrinsics, we need to reinterpolate the input
1485 * differently. If we used an intrinsic that just had an index it would
1486 * only give us the offset into the nir_inputs array. However, this is
1487 * useless because that value is post-interpolation and we need
1488 * pre-interpolation. In order to get the actual location of the bits
1489 * we get from the vertex fetching hardware, we need the variable.
1491 case nir_intrinsic_interp_var_at_centroid
:
1492 case nir_intrinsic_interp_var_at_sample
:
1493 case nir_intrinsic_interp_var_at_offset
: {
1494 /* in SIMD16 mode, the pixel interpolator returns coords interleaved
1495 * 8 channels at a time, same as the barycentric coords presented in
1496 * the FS payload. this requires a bit of extra work to support.
1498 no16("interpolate_at_* not yet supported in SIMD16 mode.");
1500 fs_reg dst_x
= vgrf(2);
1501 fs_reg dst_y
= offset(dst_x
, 1);
1503 /* For most messages, we need one reg of ignored data; the hardware
1504 * requires mlen==1 even when there is no payload. in the per-slot
1505 * offset case, we'll replace this with the proper source data.
1507 fs_reg src
= vgrf(glsl_type::float_type
);
1508 int mlen
= 1; /* one reg unless overriden */
1511 switch (instr
->intrinsic
) {
1512 case nir_intrinsic_interp_var_at_centroid
:
1513 inst
= emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
, dst_x
, src
, fs_reg(0u));
1516 case nir_intrinsic_interp_var_at_sample
: {
1517 /* XXX: We should probably handle non-constant sample id's */
1518 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1519 assert(const_sample
);
1520 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1521 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_x
, src
,
1526 case nir_intrinsic_interp_var_at_offset
: {
1527 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1530 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1531 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1533 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_x
, src
,
1534 fs_reg(off_x
| (off_y
<< 4)));
1536 src
= vgrf(glsl_type::ivec2_type
);
1537 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1538 BRW_REGISTER_TYPE_F
);
1539 for (int i
= 0; i
< 2; i
++) {
1540 fs_reg temp
= vgrf(glsl_type::float_type
);
1541 emit(MUL(temp
, offset(offset_src
, i
), fs_reg(16.0f
)));
1542 fs_reg itemp
= vgrf(glsl_type::int_type
);
1543 emit(MOV(itemp
, temp
)); /* float to int */
1545 /* Clamp the upper end of the range to +7/16.
1546 * ARB_gpu_shader5 requires that we support a maximum offset
1547 * of +0.5, which isn't representable in a S0.4 value -- if
1548 * we didn't clamp it, we'd end up with -8/16, which is the
1549 * opposite of what the shader author wanted.
1551 * This is legal due to ARB_gpu_shader5's quantization
1554 * "Not all values of <offset> may be supported; x and y
1555 * offsets may be rounded to fixed-point values with the
1556 * number of fraction bits given by the
1557 * implementation-dependent constant
1558 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1561 emit(BRW_OPCODE_SEL
, offset(src
, i
), itemp
, fs_reg(7))
1562 ->conditional_mod
= BRW_CONDITIONAL_L
; /* min(src2, 7) */
1566 inst
= emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_x
, src
,
1573 unreachable("Invalid intrinsic");
1577 inst
->regs_written
= 2; /* 2 floats per slot returned */
1578 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1579 INTERP_QUALIFIER_NOPERSPECTIVE
;
1581 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1582 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1583 src
.type
= dest
.type
;
1585 emit(FS_OPCODE_LINTERP
, dest
, dst_x
, dst_y
, src
);
1586 dest
= offset(dest
, 1);
1591 case nir_intrinsic_store_output_indirect
:
1592 has_indirect
= true;
1593 case nir_intrinsic_store_output
: {
1594 fs_reg src
= get_nir_src(instr
->src
[0]);
1596 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1597 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1598 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
),
1599 instr
->const_index
[0] + index
);
1601 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1603 emit(MOV(new_dest
, src
));
1604 src
= offset(src
, 1);
1611 unreachable("unknown intrinsic");
1616 fs_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1618 unsigned sampler
= instr
->sampler_index
;
1619 fs_reg
sampler_reg(sampler
);
1621 /* FINISHME: We're failing to recompile our programs when the sampler is
1622 * updated. This only matters for the texture rectangle scale parameters
1623 * (pre-gen6, or gen6+ with GL_CLAMP).
1625 int texunit
= prog
->SamplerUnits
[sampler
];
1627 int gather_component
= instr
->component
;
1629 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1631 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1634 int lod_components
= 0, offset_components
= 0;
1636 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, offset
;
1638 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1639 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1640 switch (instr
->src
[i
].src_type
) {
1641 case nir_tex_src_bias
:
1642 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1644 case nir_tex_src_comparitor
:
1645 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1647 case nir_tex_src_coord
:
1648 switch (instr
->op
) {
1650 case nir_texop_txf_ms
:
1651 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1654 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1658 case nir_tex_src_ddx
:
1659 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1660 lod_components
= nir_tex_instr_src_size(instr
, i
);
1662 case nir_tex_src_ddy
:
1663 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1665 case nir_tex_src_lod
:
1666 switch (instr
->op
) {
1668 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1671 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1674 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1678 case nir_tex_src_ms_index
:
1679 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1681 case nir_tex_src_offset
:
1682 offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1683 if (instr
->is_array
)
1684 offset_components
= instr
->coord_components
- 1;
1686 offset_components
= instr
->coord_components
;
1688 case nir_tex_src_projector
:
1689 unreachable("should be lowered");
1691 case nir_tex_src_sampler_offset
: {
1692 /* Figure out the highest possible sampler index and mark it as used */
1693 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1694 if (instr
->op
== nir_texop_tg4
&& brw
->gen
< 8) {
1695 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1697 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1699 brw_mark_surface_used(prog_data
, max_used
);
1701 /* Emit code to evaluate the actual indexing expression */
1702 sampler_reg
= vgrf(glsl_type::uint_type
);
1703 emit(ADD(sampler_reg
, src
, fs_reg(sampler
)))
1704 ->force_writemask_all
= true;
1709 unreachable("unknown texture source");
1713 if (instr
->op
== nir_texop_txf_ms
) {
1714 if (brw
->gen
>= 7 &&
1715 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1716 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1722 for (unsigned i
= 0; i
< 3; i
++) {
1723 if (instr
->const_offset
[i
] != 0) {
1724 assert(offset_components
== 0);
1725 offset
= fs_reg(brw_texture_offset(ctx
, instr
->const_offset
, 3));
1730 enum glsl_base_type dest_base_type
;
1731 switch (instr
->dest_type
) {
1732 case nir_type_float
:
1733 dest_base_type
= GLSL_TYPE_FLOAT
;
1736 dest_base_type
= GLSL_TYPE_INT
;
1738 case nir_type_unsigned
:
1739 dest_base_type
= GLSL_TYPE_UINT
;
1742 unreachable("bad type");
1745 const glsl_type
*dest_type
=
1746 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1749 ir_texture_opcode op
;
1750 switch (instr
->op
) {
1751 case nir_texop_lod
: op
= ir_lod
; break;
1752 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1753 case nir_texop_tex
: op
= ir_tex
; break;
1754 case nir_texop_tg4
: op
= ir_tg4
; break;
1755 case nir_texop_txb
: op
= ir_txb
; break;
1756 case nir_texop_txd
: op
= ir_txd
; break;
1757 case nir_texop_txf
: op
= ir_txf
; break;
1758 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1759 case nir_texop_txl
: op
= ir_txl
; break;
1760 case nir_texop_txs
: op
= ir_txs
; break;
1762 unreachable("unknown texture opcode");
1765 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1766 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1767 offset
, mcs
, gather_component
,
1768 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1770 fs_reg dest
= get_nir_dest(instr
->dest
);
1771 dest
.type
= this->result
.type
;
1772 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1773 emit_percomp(MOV(dest
, this->result
), (1 << num_components
) - 1);
1777 fs_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1779 switch (instr
->type
) {
1780 case nir_jump_break
:
1781 emit(BRW_OPCODE_BREAK
);
1783 case nir_jump_continue
:
1784 emit(BRW_OPCODE_CONTINUE
);
1786 case nir_jump_return
:
1788 unreachable("unknown jump");