2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "program/prog_to_nir.h"
29 #include "brw_fs_surface_builder.h"
35 fs_visitor::emit_nir_code()
37 nir_shader
*nir
= prog
->nir
;
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
43 if (nir
->num_inputs
> 0) {
44 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
45 nir_setup_inputs(nir
);
48 if (nir
->num_outputs
> 0) {
49 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
50 nir_setup_outputs(nir
);
53 if (nir
->num_uniforms
> 0) {
54 nir_setup_uniforms(nir
);
57 nir_emit_system_values(nir
);
59 /* get the main function and emit it */
60 nir_foreach_overload(nir
, overload
) {
61 assert(strcmp(overload
->function
->name
, "main") == 0);
62 assert(overload
->impl
);
63 nir_emit_impl(overload
->impl
);
68 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
70 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
71 enum brw_reg_type type
= brw_type_for_base_type(var
->type
);
72 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
76 case MESA_SHADER_VERTEX
: {
77 /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
78 * stored in nir_variable::location.
80 * However, NIR's load_input intrinsics use a different index - an
81 * offset into a single contiguous array containing all inputs.
82 * This index corresponds to the nir_variable::driver_location field.
84 * So, we need to copy from fs_reg(ATTR, var->location) to
85 * offset(nir_inputs, var->data.driver_location).
87 const glsl_type
*const t
= var
->type
->without_array();
88 const unsigned components
= t
->components();
89 const unsigned cols
= t
->matrix_columns
;
90 const unsigned elts
= t
->vector_elements
;
91 unsigned array_length
= var
->type
->is_array() ? var
->type
->length
: 1;
92 for (unsigned i
= 0; i
< array_length
; i
++) {
93 for (unsigned j
= 0; j
< cols
; j
++) {
94 for (unsigned k
= 0; k
< elts
; k
++) {
95 bld
.MOV(offset(retype(input
, type
), bld
,
96 components
* i
+ elts
* j
+ k
),
97 offset(fs_reg(ATTR
, var
->data
.location
+ i
, type
),
104 case MESA_SHADER_GEOMETRY
:
105 case MESA_SHADER_COMPUTE
:
106 case MESA_SHADER_TESS_CTRL
:
107 case MESA_SHADER_TESS_EVAL
:
108 unreachable("fs_visitor not used for these stages yet.");
110 case MESA_SHADER_FRAGMENT
:
111 if (var
->data
.location
== VARYING_SLOT_POS
) {
112 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
113 var
->data
.origin_upper_left
);
114 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
117 emit_general_interpolation(input
, var
->name
, var
->type
,
118 (glsl_interp_qualifier
) var
->data
.interpolation
,
119 var
->data
.location
, var
->data
.centroid
,
128 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
130 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
132 foreach_list_typed(nir_variable
, var
, node
, &shader
->outputs
) {
133 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
135 int vector_elements
=
136 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
137 : var
->type
->vector_elements
;
140 case MESA_SHADER_VERTEX
:
141 for (int i
= 0; i
< ALIGN(type_size(var
->type
), 4) / 4; i
++) {
142 int output
= var
->data
.location
+ i
;
143 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
144 this->output_components
[output
] = vector_elements
;
147 case MESA_SHADER_FRAGMENT
:
148 if (var
->data
.index
> 0) {
149 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
150 assert(var
->data
.index
== 1);
151 this->dual_src_output
= reg
;
152 this->do_dual_src
= true;
153 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
154 /* Writing gl_FragColor outputs to all color regions. */
155 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
156 this->outputs
[i
] = reg
;
157 this->output_components
[i
] = 4;
159 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
160 this->frag_depth
= reg
;
161 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
162 this->sample_mask
= reg
;
164 /* gl_FragData or a user-defined FS output */
165 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
166 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
168 /* General color output. */
169 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
170 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
171 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
172 this->output_components
[output
] = vector_elements
;
177 unreachable("unhandled shader stage");
183 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
185 uniforms
= shader
->num_uniforms
;
186 num_direct_uniforms
= shader
->num_direct_uniforms
;
188 /* We split the uniform register file in half. The first half is
189 * entirely direct uniforms. The second half is indirect.
191 param_size
[0] = num_direct_uniforms
;
192 if (shader
->num_uniforms
> num_direct_uniforms
)
193 param_size
[num_direct_uniforms
] = shader
->num_uniforms
- num_direct_uniforms
;
195 if (dispatch_width
!= 8)
199 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
200 /* UBO's and atomics don't take up space in the uniform file */
201 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
204 if (strncmp(var
->name
, "gl_", 3) == 0)
205 nir_setup_builtin_uniform(var
);
207 nir_setup_uniform(var
);
210 /* prog_to_nir doesn't create uniform variables; set param up directly. */
211 for (unsigned p
= 0; p
< prog
->Parameters
->NumParameters
; p
++) {
212 for (unsigned int i
= 0; i
< 4; i
++) {
213 stage_prog_data
->param
[4 * p
+ i
] =
214 &prog
->Parameters
->ParameterValues
[p
][i
];
221 fs_visitor::nir_setup_uniform(nir_variable
*var
)
223 int namelen
= strlen(var
->name
);
225 /* The data for our (non-builtin) uniforms is stored in a series of
226 * gl_uniform_driver_storage structs for each subcomponent that
227 * glGetUniformLocation() could name. We know it's been set up in the
228 * same order we'd walk the type, so walk the list of storage and find
229 * anything with our name, or the prefix of a component that starts with
232 unsigned index
= var
->data
.driver_location
;
233 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
234 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
236 if (storage
->builtin
)
239 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
240 (storage
->name
[namelen
] != 0 &&
241 storage
->name
[namelen
] != '.' &&
242 storage
->name
[namelen
] != '[')) {
246 unsigned slots
= storage
->type
->component_slots();
247 if (storage
->array_elements
)
248 slots
*= storage
->array_elements
;
250 for (unsigned i
= 0; i
< slots
; i
++) {
251 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
255 /* Make sure we actually initialized the right amount of stuff here. */
256 assert(var
->data
.driver_location
+ var
->type
->component_slots() == index
);
260 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
262 const nir_state_slot
*const slots
= var
->state_slots
;
263 assert(var
->state_slots
!= NULL
);
265 unsigned uniform_index
= var
->data
.driver_location
;
266 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
267 /* This state reference has already been setup by ir_to_mesa, but we'll
268 * get the same index back here.
270 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
271 (gl_state_index
*)slots
[i
].tokens
);
273 /* Add each of the unique swizzles of the element as a parameter.
274 * This'll end up matching the expected layout of the
275 * array/matrix/structure we're trying to fill in.
278 for (unsigned int j
= 0; j
< 4; j
++) {
279 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
280 if (swiz
== last_swiz
)
284 stage_prog_data
->param
[uniform_index
++] =
285 &prog
->Parameters
->ParameterValues
[index
][swiz
];
291 emit_system_values_block(nir_block
*block
, void *void_visitor
)
293 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
296 nir_foreach_instr(block
, instr
) {
297 if (instr
->type
!= nir_instr_type_intrinsic
)
300 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
301 switch (intrin
->intrinsic
) {
302 case nir_intrinsic_load_vertex_id
:
303 unreachable("should be lowered by lower_vertex_id().");
305 case nir_intrinsic_load_vertex_id_zero_base
:
306 assert(v
->stage
== MESA_SHADER_VERTEX
);
307 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
308 if (reg
->file
== BAD_FILE
)
309 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
312 case nir_intrinsic_load_base_vertex
:
313 assert(v
->stage
== MESA_SHADER_VERTEX
);
314 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
315 if (reg
->file
== BAD_FILE
)
316 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
319 case nir_intrinsic_load_instance_id
:
320 assert(v
->stage
== MESA_SHADER_VERTEX
);
321 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
322 if (reg
->file
== BAD_FILE
)
323 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
326 case nir_intrinsic_load_sample_pos
:
327 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
328 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
329 if (reg
->file
== BAD_FILE
)
330 *reg
= *v
->emit_samplepos_setup();
333 case nir_intrinsic_load_sample_id
:
334 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
335 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
336 if (reg
->file
== BAD_FILE
)
337 *reg
= *v
->emit_sampleid_setup();
340 case nir_intrinsic_load_sample_mask_in
:
341 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
342 assert(v
->devinfo
->gen
>= 7);
343 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
344 if (reg
->file
== BAD_FILE
)
345 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
346 BRW_REGISTER_TYPE_D
));
358 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
360 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
361 nir_foreach_overload(shader
, overload
) {
362 assert(strcmp(overload
->function
->name
, "main") == 0);
363 assert(overload
->impl
);
364 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
369 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
371 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
372 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
373 unsigned array_elems
=
374 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
375 unsigned size
= array_elems
* reg
->num_components
;
376 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
379 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
382 nir_emit_cf_list(&impl
->body
);
386 fs_visitor::nir_emit_cf_list(exec_list
*list
)
388 exec_list_validate(list
);
389 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
390 switch (node
->type
) {
392 nir_emit_if(nir_cf_node_as_if(node
));
395 case nir_cf_node_loop
:
396 nir_emit_loop(nir_cf_node_as_loop(node
));
399 case nir_cf_node_block
:
400 nir_emit_block(nir_cf_node_as_block(node
));
404 unreachable("Invalid CFG node block");
410 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
412 /* first, put the condition into f0 */
413 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
414 retype(get_nir_src(if_stmt
->condition
),
415 BRW_REGISTER_TYPE_D
));
416 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
418 bld
.IF(BRW_PREDICATE_NORMAL
);
420 nir_emit_cf_list(&if_stmt
->then_list
);
422 /* note: if the else is empty, dead CF elimination will remove it */
423 bld
.emit(BRW_OPCODE_ELSE
);
425 nir_emit_cf_list(&if_stmt
->else_list
);
427 bld
.emit(BRW_OPCODE_ENDIF
);
429 try_replace_with_sel();
433 fs_visitor::nir_emit_loop(nir_loop
*loop
)
435 bld
.emit(BRW_OPCODE_DO
);
437 nir_emit_cf_list(&loop
->body
);
439 bld
.emit(BRW_OPCODE_WHILE
);
443 fs_visitor::nir_emit_block(nir_block
*block
)
445 nir_foreach_instr(block
, instr
) {
446 nir_emit_instr(instr
);
451 fs_visitor::nir_emit_instr(nir_instr
*instr
)
453 const fs_builder abld
= bld
.annotate(NULL
, instr
);
455 switch (instr
->type
) {
456 case nir_instr_type_alu
:
457 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
460 case nir_instr_type_intrinsic
:
461 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
464 case nir_instr_type_tex
:
465 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
468 case nir_instr_type_load_const
:
469 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
472 case nir_instr_type_ssa_undef
:
473 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
476 case nir_instr_type_jump
:
477 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
481 unreachable("unknown instruction type");
486 brw_type_for_nir_type(nir_alu_type type
)
489 case nir_type_unsigned
:
490 return BRW_REGISTER_TYPE_UD
;
493 return BRW_REGISTER_TYPE_D
;
495 return BRW_REGISTER_TYPE_F
;
497 unreachable("unknown type");
500 return BRW_REGISTER_TYPE_F
;
504 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
505 const fs_reg
&result
)
507 if (!instr
->src
[0].src
.is_ssa
||
508 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
511 nir_intrinsic_instr
*src0
=
512 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
514 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
517 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
518 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
521 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
522 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
525 fs_reg tmp
= vgrf(glsl_type::int_type
);
527 if (devinfo
->gen
>= 6) {
528 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
529 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
531 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
533 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
534 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
536 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
538 * This negation looks like it's safe in practice, because bits 0:4 will
539 * surely be TRIANGLES
542 if (value1
->f
[0] == -1.0f
) {
546 tmp
.type
= BRW_REGISTER_TYPE_W
;
547 tmp
.subreg_offset
= 2;
550 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
551 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
553 tmp
.type
= BRW_REGISTER_TYPE_D
;
554 tmp
.subreg_offset
= 0;
557 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
558 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
560 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
562 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
563 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
565 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
567 * This negation looks like it's safe in practice, because bits 0:4 will
568 * surely be TRIANGLES
571 if (value1
->f
[0] == -1.0f
) {
575 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
577 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
583 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
585 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
588 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
589 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
592 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
593 op
[i
] = get_nir_src(instr
->src
[i
].src
);
594 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
595 op
[i
].abs
= instr
->src
[i
].abs
;
596 op
[i
].negate
= instr
->src
[i
].negate
;
599 /* We get a bunch of mov's out of the from_ssa pass and they may still
600 * be vectorized. We'll handle them as a special-case. We'll also
601 * handle vecN here because it's basically the same thing.
609 fs_reg temp
= result
;
610 bool need_extra_copy
= false;
611 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
612 if (!instr
->src
[i
].src
.is_ssa
&&
613 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
614 need_extra_copy
= true;
615 temp
= bld
.vgrf(result
.type
, 4);
620 for (unsigned i
= 0; i
< 4; i
++) {
621 if (!(instr
->dest
.write_mask
& (1 << i
)))
624 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
625 inst
= bld
.MOV(offset(temp
, bld
, i
),
626 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
628 inst
= bld
.MOV(offset(temp
, bld
, i
),
629 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
631 inst
->saturate
= instr
->dest
.saturate
;
634 /* In this case the source and destination registers were the same,
635 * so we need to insert an extra set of moves in order to deal with
638 if (need_extra_copy
) {
639 for (unsigned i
= 0; i
< 4; i
++) {
640 if (!(instr
->dest
.write_mask
& (1 << i
)))
643 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
652 /* At this point, we have dealt with any instruction that operates on
653 * more than a single channel. Therefore, we can just adjust the source
654 * and destination registers for that channel and emit the instruction.
656 unsigned channel
= 0;
657 if (nir_op_infos
[instr
->op
].output_size
== 0) {
658 /* Since NIR is doing the scalarizing for us, we should only ever see
659 * vectorized operations with a single channel.
661 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
662 channel
= ffs(instr
->dest
.write_mask
) - 1;
664 result
= offset(result
, bld
, channel
);
667 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
668 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
669 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
675 inst
= bld
.MOV(result
, op
[0]);
676 inst
->saturate
= instr
->dest
.saturate
;
681 bld
.MOV(result
, op
[0]);
685 /* AND(val, 0x80000000) gives the sign bit.
687 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
690 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
692 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
693 op
[0].type
= BRW_REGISTER_TYPE_UD
;
694 result
.type
= BRW_REGISTER_TYPE_UD
;
695 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
697 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
698 inst
->predicate
= BRW_PREDICATE_NORMAL
;
699 if (instr
->dest
.saturate
) {
700 inst
= bld
.MOV(result
, result
);
701 inst
->saturate
= true;
707 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
708 * -> non-negative val generates 0x00000000.
709 * Predicated OR sets 1 if val is positive.
711 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
712 bld
.ASR(result
, op
[0], fs_reg(31));
713 inst
= bld
.OR(result
, result
, fs_reg(1));
714 inst
->predicate
= BRW_PREDICATE_NORMAL
;
718 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
719 inst
->saturate
= instr
->dest
.saturate
;
723 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
724 inst
->saturate
= instr
->dest
.saturate
;
728 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
729 inst
->saturate
= instr
->dest
.saturate
;
733 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
734 inst
->saturate
= instr
->dest
.saturate
;
738 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
739 inst
->saturate
= instr
->dest
.saturate
;
743 if (fs_key
->high_quality_derivatives
) {
744 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
746 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
748 inst
->saturate
= instr
->dest
.saturate
;
750 case nir_op_fddx_fine
:
751 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
752 inst
->saturate
= instr
->dest
.saturate
;
754 case nir_op_fddx_coarse
:
755 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
756 inst
->saturate
= instr
->dest
.saturate
;
759 if (fs_key
->high_quality_derivatives
) {
760 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
761 fs_reg(fs_key
->render_to_fbo
));
763 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
764 fs_reg(fs_key
->render_to_fbo
));
766 inst
->saturate
= instr
->dest
.saturate
;
768 case nir_op_fddy_fine
:
769 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
770 fs_reg(fs_key
->render_to_fbo
));
771 inst
->saturate
= instr
->dest
.saturate
;
773 case nir_op_fddy_coarse
:
774 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
775 fs_reg(fs_key
->render_to_fbo
));
776 inst
->saturate
= instr
->dest
.saturate
;
781 inst
= bld
.ADD(result
, op
[0], op
[1]);
782 inst
->saturate
= instr
->dest
.saturate
;
786 inst
= bld
.MUL(result
, op
[0], op
[1]);
787 inst
->saturate
= instr
->dest
.saturate
;
791 bld
.MUL(result
, op
[0], op
[1]);
794 case nir_op_imul_high
:
795 case nir_op_umul_high
: {
796 if (devinfo
->gen
>= 7)
797 no16("SIMD16 explicit accumulator operands unsupported\n");
799 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
801 fs_inst
*mul
= bld
.MUL(acc
, op
[0], op
[1]);
802 bld
.MACH(result
, op
[0], op
[1]);
804 /* Until Gen8, integer multiplies read 32-bits from one source, and
805 * 16-bits from the other, and relying on the MACH instruction to
806 * generate the high bits of the result.
808 * On Gen8, the multiply instruction does a full 32x32-bit multiply,
809 * but in order to do a 64x64-bit multiply we have to simulate the
810 * previous behavior and then use a MACH instruction.
812 * FINISHME: Don't use source modifiers on src1.
814 if (devinfo
->gen
>= 8) {
815 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
816 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
817 if (mul
->src
[1].type
== BRW_REGISTER_TYPE_D
) {
818 mul
->src
[1].type
= BRW_REGISTER_TYPE_W
;
819 mul
->src
[1].stride
= 2;
821 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
822 mul
->src
[1].stride
= 2;
830 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
833 case nir_op_uadd_carry
:
834 unreachable("Should have been lowered by carry_to_arith().");
836 case nir_op_usub_borrow
:
837 unreachable("Should have been lowered by borrow_to_arith().");
840 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
846 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
852 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
857 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
862 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
866 if (devinfo
->gen
>= 8) {
867 resolve_source_modifiers(&op
[0]);
869 bld
.NOT(result
, op
[0]);
872 if (devinfo
->gen
>= 8) {
873 resolve_source_modifiers(&op
[0]);
874 resolve_source_modifiers(&op
[1]);
876 bld
.XOR(result
, op
[0], op
[1]);
879 if (devinfo
->gen
>= 8) {
880 resolve_source_modifiers(&op
[0]);
881 resolve_source_modifiers(&op
[1]);
883 bld
.OR(result
, op
[0], op
[1]);
886 if (devinfo
->gen
>= 8) {
887 resolve_source_modifiers(&op
[0]);
888 resolve_source_modifiers(&op
[1]);
890 bld
.AND(result
, op
[0], op
[1]);
902 case nir_op_ball_fequal2
:
903 case nir_op_ball_iequal2
:
904 case nir_op_ball_fequal3
:
905 case nir_op_ball_iequal3
:
906 case nir_op_ball_fequal4
:
907 case nir_op_ball_iequal4
:
908 case nir_op_bany_fnequal2
:
909 case nir_op_bany_inequal2
:
910 case nir_op_bany_fnequal3
:
911 case nir_op_bany_inequal3
:
912 case nir_op_bany_fnequal4
:
913 case nir_op_bany_inequal4
:
914 unreachable("Lowered by nir_lower_alu_reductions");
916 case nir_op_fnoise1_1
:
917 case nir_op_fnoise1_2
:
918 case nir_op_fnoise1_3
:
919 case nir_op_fnoise1_4
:
920 case nir_op_fnoise2_1
:
921 case nir_op_fnoise2_2
:
922 case nir_op_fnoise2_3
:
923 case nir_op_fnoise2_4
:
924 case nir_op_fnoise3_1
:
925 case nir_op_fnoise3_2
:
926 case nir_op_fnoise3_3
:
927 case nir_op_fnoise3_4
:
928 case nir_op_fnoise4_1
:
929 case nir_op_fnoise4_2
:
930 case nir_op_fnoise4_3
:
931 case nir_op_fnoise4_4
:
932 unreachable("not reached: should be handled by lower_noise");
935 unreachable("not reached: should be handled by ldexp_to_arith()");
938 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
939 inst
->saturate
= instr
->dest
.saturate
;
943 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
944 inst
->saturate
= instr
->dest
.saturate
;
949 bld
.MOV(result
, negate(op
[0]));
953 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
956 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
960 inst
= bld
.RNDZ(result
, op
[0]);
961 inst
->saturate
= instr
->dest
.saturate
;
965 op
[0].negate
= !op
[0].negate
;
966 fs_reg temp
= vgrf(glsl_type::float_type
);
967 bld
.RNDD(temp
, op
[0]);
969 inst
= bld
.MOV(result
, temp
);
970 inst
->saturate
= instr
->dest
.saturate
;
974 inst
= bld
.RNDD(result
, op
[0]);
975 inst
->saturate
= instr
->dest
.saturate
;
978 inst
= bld
.FRC(result
, op
[0]);
979 inst
->saturate
= instr
->dest
.saturate
;
981 case nir_op_fround_even
:
982 inst
= bld
.RNDE(result
, op
[0]);
983 inst
->saturate
= instr
->dest
.saturate
;
989 if (devinfo
->gen
>= 6) {
990 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
991 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
993 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
994 inst
= bld
.SEL(result
, op
[0], op
[1]);
995 inst
->predicate
= BRW_PREDICATE_NORMAL
;
997 inst
->saturate
= instr
->dest
.saturate
;
1003 if (devinfo
->gen
>= 6) {
1004 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1005 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1007 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
1008 inst
= bld
.SEL(result
, op
[0], op
[1]);
1009 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1011 inst
->saturate
= instr
->dest
.saturate
;
1014 case nir_op_pack_snorm_2x16
:
1015 case nir_op_pack_snorm_4x8
:
1016 case nir_op_pack_unorm_2x16
:
1017 case nir_op_pack_unorm_4x8
:
1018 case nir_op_unpack_snorm_2x16
:
1019 case nir_op_unpack_snorm_4x8
:
1020 case nir_op_unpack_unorm_2x16
:
1021 case nir_op_unpack_unorm_4x8
:
1022 case nir_op_unpack_half_2x16
:
1023 case nir_op_pack_half_2x16
:
1024 unreachable("not reached: should be handled by lower_packing_builtins");
1026 case nir_op_unpack_half_2x16_split_x
:
1027 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1028 inst
->saturate
= instr
->dest
.saturate
;
1030 case nir_op_unpack_half_2x16_split_y
:
1031 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1032 inst
->saturate
= instr
->dest
.saturate
;
1036 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1037 inst
->saturate
= instr
->dest
.saturate
;
1040 case nir_op_bitfield_reverse
:
1041 bld
.BFREV(result
, op
[0]);
1044 case nir_op_bit_count
:
1045 bld
.CBIT(result
, op
[0]);
1048 case nir_op_ufind_msb
:
1049 case nir_op_ifind_msb
: {
1050 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1052 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1053 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1054 * subtract the result from 31 to convert the MSB count into an LSB count.
1057 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
1058 fs_reg
neg_result(result
);
1059 neg_result
.negate
= true;
1060 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
1061 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1065 case nir_op_find_lsb
:
1066 bld
.FBL(result
, op
[0]);
1069 case nir_op_ubitfield_extract
:
1070 case nir_op_ibitfield_extract
:
1071 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1074 bld
.BFI1(result
, op
[0], op
[1]);
1077 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1080 case nir_op_bitfield_insert
:
1081 unreachable("not reached: should be handled by "
1082 "lower_instructions::bitfield_insert_to_bfm_bfi");
1085 bld
.SHL(result
, op
[0], op
[1]);
1088 bld
.ASR(result
, op
[0], op
[1]);
1091 bld
.SHR(result
, op
[0], op
[1]);
1094 case nir_op_pack_half_2x16_split
:
1095 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1099 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1100 inst
->saturate
= instr
->dest
.saturate
;
1104 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1105 inst
->saturate
= instr
->dest
.saturate
;
1109 if (optimize_frontfacing_ternary(instr
, result
))
1112 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
1113 inst
= bld
.SEL(result
, op
[1], op
[2]);
1114 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1118 unreachable("unhandled instruction");
1121 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1122 * to sign extend the low bit to 0/~0
1124 if (devinfo
->gen
<= 5 &&
1125 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1126 fs_reg masked
= vgrf(glsl_type::int_type
);
1127 bld
.AND(masked
, result
, fs_reg(1));
1128 masked
.negate
= true;
1129 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1134 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1135 nir_load_const_instr
*instr
)
1137 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1139 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1140 bld
.MOV(offset(reg
, bld
, i
), fs_reg(instr
->value
.i
[i
]));
1142 nir_ssa_values
[instr
->def
.index
] = reg
;
1146 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1148 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1149 instr
->def
.num_components
);
1153 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1154 unsigned base_offset
, nir_src
*indirect
)
1158 assert(!nir_reg
->is_global
);
1160 reg
= v
->nir_locals
[nir_reg
->index
];
1162 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1164 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1166 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1167 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1168 fs_reg(multiplier
));
1175 fs_visitor::get_nir_src(nir_src src
)
1179 reg
= nir_ssa_values
[src
.ssa
->index
];
1181 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1185 /* to avoid floating-point denorm flushing problems, set the type by
1186 * default to D - instructions that need floating point semantics will set
1187 * this to F if they need to
1189 return retype(reg
, BRW_REGISTER_TYPE_D
);
1193 fs_visitor::get_nir_dest(nir_dest dest
)
1196 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1197 dest
.ssa
.num_components
);
1198 return nir_ssa_values
[dest
.ssa
.index
];
1201 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1206 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1209 for (unsigned i
= 0; i
< 4; i
++) {
1210 if (!((wr_mask
>> i
) & 1))
1213 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1214 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1215 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1216 if (new_inst
->src
[j
].file
== GRF
)
1217 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1224 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1227 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1228 dest
= get_nir_dest(instr
->dest
);
1230 bool has_indirect
= false;
1232 switch (instr
->intrinsic
) {
1233 case nir_intrinsic_discard
:
1234 case nir_intrinsic_discard_if
: {
1235 /* We track our discarded pixels in f0.1. By predicating on it, we can
1236 * update just the flag bits that aren't yet discarded. If there's no
1237 * condition, we emit a CMP of g0 != g0, so all currently executing
1238 * channels will get turned off.
1241 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1242 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1243 fs_reg(0), BRW_CONDITIONAL_Z
);
1245 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1246 BRW_REGISTER_TYPE_UW
));
1247 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1249 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1250 cmp
->flag_subreg
= 1;
1252 if (devinfo
->gen
>= 6) {
1253 emit_discard_jump();
1258 case nir_intrinsic_atomic_counter_inc
:
1259 case nir_intrinsic_atomic_counter_dec
:
1260 case nir_intrinsic_atomic_counter_read
: {
1261 using namespace surface_access
;
1263 /* Get the arguments of the atomic intrinsic. */
1264 const fs_reg offset
= get_nir_src(instr
->src
[0]);
1265 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
1266 instr
->const_index
[0]);
1269 /* Emit a surface read or atomic op. */
1270 switch (instr
->intrinsic
) {
1271 case nir_intrinsic_atomic_counter_read
:
1272 tmp
= surface_access::emit_untyped_read(
1273 bld
, fs_reg(surface
), offset
, 1, 1);
1276 case nir_intrinsic_atomic_counter_inc
:
1277 tmp
= surface_access::emit_untyped_atomic(
1278 bld
, fs_reg(surface
), offset
, fs_reg(),
1279 fs_reg(), 1, 1, BRW_AOP_INC
);
1282 case nir_intrinsic_atomic_counter_dec
:
1283 tmp
= surface_access::emit_untyped_atomic(
1284 bld
, fs_reg(surface
), offset
, fs_reg(),
1285 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
1289 unreachable("Unreachable");
1292 /* Assign the result. */
1293 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
1295 /* Mark the surface as used. */
1296 brw_mark_surface_used(stage_prog_data
, surface
);
1300 case nir_intrinsic_load_front_face
:
1301 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1302 *emit_frontfacing_interpolation());
1305 case nir_intrinsic_load_vertex_id
:
1306 unreachable("should be lowered by lower_vertex_id()");
1308 case nir_intrinsic_load_vertex_id_zero_base
: {
1309 fs_reg vertex_id
= nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
1310 assert(vertex_id
.file
!= BAD_FILE
);
1311 dest
.type
= vertex_id
.type
;
1312 bld
.MOV(dest
, vertex_id
);
1316 case nir_intrinsic_load_base_vertex
: {
1317 fs_reg base_vertex
= nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
1318 assert(base_vertex
.file
!= BAD_FILE
);
1319 dest
.type
= base_vertex
.type
;
1320 bld
.MOV(dest
, base_vertex
);
1324 case nir_intrinsic_load_instance_id
: {
1325 fs_reg instance_id
= nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
1326 assert(instance_id
.file
!= BAD_FILE
);
1327 dest
.type
= instance_id
.type
;
1328 bld
.MOV(dest
, instance_id
);
1332 case nir_intrinsic_load_sample_mask_in
: {
1333 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1334 assert(sample_mask_in
.file
!= BAD_FILE
);
1335 dest
.type
= sample_mask_in
.type
;
1336 bld
.MOV(dest
, sample_mask_in
);
1340 case nir_intrinsic_load_sample_pos
: {
1341 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1342 assert(sample_pos
.file
!= BAD_FILE
);
1343 dest
.type
= sample_pos
.type
;
1344 bld
.MOV(dest
, sample_pos
);
1345 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1349 case nir_intrinsic_load_sample_id
: {
1350 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1351 assert(sample_id
.file
!= BAD_FILE
);
1352 dest
.type
= sample_id
.type
;
1353 bld
.MOV(dest
, sample_id
);
1357 case nir_intrinsic_load_uniform_indirect
:
1358 has_indirect
= true;
1360 case nir_intrinsic_load_uniform
: {
1361 unsigned index
= instr
->const_index
[0];
1364 if (index
< num_direct_uniforms
) {
1365 uniform_reg
= fs_reg(UNIFORM
, 0);
1367 uniform_reg
= fs_reg(UNIFORM
, num_direct_uniforms
);
1368 index
-= num_direct_uniforms
;
1371 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1372 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, index
);
1374 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1378 dest
= offset(dest
, bld
, 1);
1383 case nir_intrinsic_load_ubo_indirect
:
1384 has_indirect
= true;
1386 case nir_intrinsic_load_ubo
: {
1387 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1391 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1394 /* The block index is not a constant. Evaluate the index expression
1395 * per-channel and add the base UBO index; we have to select a value
1396 * from any live channel.
1398 surf_index
= vgrf(glsl_type::uint_type
);
1399 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1400 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1401 surf_index
= bld
.emit_uniformize(surf_index
);
1403 /* Assume this may touch any UBO. It would be nice to provide
1404 * a tighter bound, but the array information is already lowered away.
1406 brw_mark_surface_used(prog_data
,
1407 stage_prog_data
->binding_table
.ubo_start
+
1408 shader_prog
->NumUniformBlocks
- 1);
1412 /* Turn the byte offset into a dword offset. */
1413 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1414 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1415 BRW_REGISTER_TYPE_D
),
1418 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1419 for (int i
= 0; i
< instr
->num_components
; i
++)
1420 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
1421 base_offset
, vec4_offset
+ i
);
1423 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1424 packed_consts
.type
= dest
.type
;
1426 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1427 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1428 surf_index
, const_offset_reg
);
1430 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1431 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1433 /* The std140 packing rules don't allow vectors to cross 16-byte
1434 * boundaries, and a reg is 32 bytes.
1436 assert(packed_consts
.subreg_offset
< 32);
1438 bld
.MOV(dest
, packed_consts
);
1439 dest
= offset(dest
, bld
, 1);
1445 case nir_intrinsic_load_input_indirect
:
1446 has_indirect
= true;
1448 case nir_intrinsic_load_input
: {
1450 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1451 fs_reg src
= offset(retype(nir_inputs
, dest
.type
), bld
,
1452 instr
->const_index
[0] + index
);
1454 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1458 dest
= offset(dest
, bld
, 1);
1463 /* Handle ARB_gpu_shader5 interpolation intrinsics
1465 * It's worth a quick word of explanation as to why we handle the full
1466 * variable-based interpolation intrinsic rather than a lowered version
1467 * with like we do for other inputs. We have to do that because the way
1468 * we set up inputs doesn't allow us to use the already setup inputs for
1469 * interpolation. At the beginning of the shader, we go through all of
1470 * the input variables and do the initial interpolation and put it in
1471 * the nir_inputs array based on its location as determined in
1472 * nir_lower_io. If the input isn't used, dead code cleans up and
1473 * everything works fine. However, when we get to the ARB_gpu_shader5
1474 * interpolation intrinsics, we need to reinterpolate the input
1475 * differently. If we used an intrinsic that just had an index it would
1476 * only give us the offset into the nir_inputs array. However, this is
1477 * useless because that value is post-interpolation and we need
1478 * pre-interpolation. In order to get the actual location of the bits
1479 * we get from the vertex fetching hardware, we need the variable.
1481 case nir_intrinsic_interp_var_at_centroid
:
1482 case nir_intrinsic_interp_var_at_sample
:
1483 case nir_intrinsic_interp_var_at_offset
: {
1484 assert(stage
== MESA_SHADER_FRAGMENT
);
1486 ((struct brw_wm_prog_data
*) prog_data
)->pulls_bary
= true;
1488 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1490 /* For most messages, we need one reg of ignored data; the hardware
1491 * requires mlen==1 even when there is no payload. in the per-slot
1492 * offset case, we'll replace this with the proper source data.
1494 fs_reg src
= vgrf(glsl_type::float_type
);
1495 int mlen
= 1; /* one reg unless overriden */
1498 switch (instr
->intrinsic
) {
1499 case nir_intrinsic_interp_var_at_centroid
:
1500 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1501 dst_xy
, src
, fs_reg(0u));
1504 case nir_intrinsic_interp_var_at_sample
: {
1505 /* XXX: We should probably handle non-constant sample id's */
1506 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1507 assert(const_sample
);
1508 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1509 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_xy
, src
,
1514 case nir_intrinsic_interp_var_at_offset
: {
1515 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1518 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1519 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1521 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_xy
, src
,
1522 fs_reg(off_x
| (off_y
<< 4)));
1524 src
= vgrf(glsl_type::ivec2_type
);
1525 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1526 BRW_REGISTER_TYPE_F
);
1527 for (int i
= 0; i
< 2; i
++) {
1528 fs_reg temp
= vgrf(glsl_type::float_type
);
1529 bld
.MUL(temp
, offset(offset_src
, bld
, i
), fs_reg(16.0f
));
1530 fs_reg itemp
= vgrf(glsl_type::int_type
);
1531 bld
.MOV(itemp
, temp
); /* float to int */
1533 /* Clamp the upper end of the range to +7/16.
1534 * ARB_gpu_shader5 requires that we support a maximum offset
1535 * of +0.5, which isn't representable in a S0.4 value -- if
1536 * we didn't clamp it, we'd end up with -8/16, which is the
1537 * opposite of what the shader author wanted.
1539 * This is legal due to ARB_gpu_shader5's quantization
1542 * "Not all values of <offset> may be supported; x and y
1543 * offsets may be rounded to fixed-point values with the
1544 * number of fraction bits given by the
1545 * implementation-dependent constant
1546 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1548 set_condmod(BRW_CONDITIONAL_L
,
1549 bld
.SEL(offset(src
, bld
, i
), itemp
, fs_reg(7)));
1552 mlen
= 2 * dispatch_width
/ 8;
1553 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_xy
, src
,
1560 unreachable("Invalid intrinsic");
1564 /* 2 floats per slot returned */
1565 inst
->regs_written
= 2 * dispatch_width
/ 8;
1566 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1567 INTERP_QUALIFIER_NOPERSPECTIVE
;
1569 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1570 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1571 src
.type
= dest
.type
;
1573 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1574 dest
= offset(dest
, bld
, 1);
1579 case nir_intrinsic_store_output_indirect
:
1580 has_indirect
= true;
1582 case nir_intrinsic_store_output
: {
1583 fs_reg src
= get_nir_src(instr
->src
[0]);
1585 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1586 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
1587 instr
->const_index
[0] + index
);
1589 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1591 bld
.MOV(new_dest
, src
);
1592 src
= offset(src
, bld
, 1);
1597 case nir_intrinsic_barrier
:
1602 unreachable("unknown intrinsic");
1607 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1609 unsigned sampler
= instr
->sampler_index
;
1610 fs_reg
sampler_reg(sampler
);
1612 /* FINISHME: We're failing to recompile our programs when the sampler is
1613 * updated. This only matters for the texture rectangle scale parameters
1614 * (pre-gen6, or gen6+ with GL_CLAMP).
1616 int texunit
= prog
->SamplerUnits
[sampler
];
1618 int gather_component
= instr
->component
;
1620 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1622 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1625 int lod_components
= 0;
1626 int UNUSED offset_components
= 0;
1628 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1630 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1631 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1632 switch (instr
->src
[i
].src_type
) {
1633 case nir_tex_src_bias
:
1634 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1636 case nir_tex_src_comparitor
:
1637 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1639 case nir_tex_src_coord
:
1640 switch (instr
->op
) {
1642 case nir_texop_txf_ms
:
1643 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1646 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1650 case nir_tex_src_ddx
:
1651 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1652 lod_components
= nir_tex_instr_src_size(instr
, i
);
1654 case nir_tex_src_ddy
:
1655 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1657 case nir_tex_src_lod
:
1658 switch (instr
->op
) {
1660 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1663 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1666 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1670 case nir_tex_src_ms_index
:
1671 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1673 case nir_tex_src_offset
:
1674 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1675 if (instr
->is_array
)
1676 offset_components
= instr
->coord_components
- 1;
1678 offset_components
= instr
->coord_components
;
1680 case nir_tex_src_projector
:
1681 unreachable("should be lowered");
1683 case nir_tex_src_sampler_offset
: {
1684 /* Figure out the highest possible sampler index and mark it as used */
1685 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1686 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
1687 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1689 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1691 brw_mark_surface_used(prog_data
, max_used
);
1693 /* Emit code to evaluate the actual indexing expression */
1694 sampler_reg
= vgrf(glsl_type::uint_type
);
1695 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
1696 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
1701 unreachable("unknown texture source");
1705 if (instr
->op
== nir_texop_txf_ms
) {
1706 if (devinfo
->gen
>= 7 &&
1707 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1708 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1714 for (unsigned i
= 0; i
< 3; i
++) {
1715 if (instr
->const_offset
[i
] != 0) {
1716 assert(offset_components
== 0);
1717 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
1722 enum glsl_base_type dest_base_type
;
1723 switch (instr
->dest_type
) {
1724 case nir_type_float
:
1725 dest_base_type
= GLSL_TYPE_FLOAT
;
1728 dest_base_type
= GLSL_TYPE_INT
;
1730 case nir_type_unsigned
:
1731 dest_base_type
= GLSL_TYPE_UINT
;
1734 unreachable("bad type");
1737 const glsl_type
*dest_type
=
1738 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1741 ir_texture_opcode op
;
1742 switch (instr
->op
) {
1743 case nir_texop_lod
: op
= ir_lod
; break;
1744 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1745 case nir_texop_tex
: op
= ir_tex
; break;
1746 case nir_texop_tg4
: op
= ir_tg4
; break;
1747 case nir_texop_txb
: op
= ir_txb
; break;
1748 case nir_texop_txd
: op
= ir_txd
; break;
1749 case nir_texop_txf
: op
= ir_txf
; break;
1750 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1751 case nir_texop_txl
: op
= ir_txl
; break;
1752 case nir_texop_txs
: op
= ir_txs
; break;
1754 unreachable("unknown texture opcode");
1757 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1758 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1759 tex_offset
, mcs
, gather_component
,
1760 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1762 fs_reg dest
= get_nir_dest(instr
->dest
);
1763 dest
.type
= this->result
.type
;
1764 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1765 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
1766 dest
, this->result
),
1767 (1 << num_components
) - 1);
1771 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
1773 switch (instr
->type
) {
1774 case nir_jump_break
:
1775 bld
.emit(BRW_OPCODE_BREAK
);
1777 case nir_jump_continue
:
1778 bld
.emit(BRW_OPCODE_CONTINUE
);
1780 case nir_jump_return
:
1782 unreachable("unknown jump");