2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "main/shaderimage.h"
28 #include "program/prog_to_nir.h"
30 #include "brw_fs_surface_builder.h"
36 fs_visitor::emit_nir_code()
38 nir_shader
*nir
= prog
->nir
;
40 /* emit the arrays used for inputs and outputs - load/store intrinsics will
41 * be converted to reads/writes of these arrays
43 nir_setup_inputs(nir
);
44 nir_setup_outputs(nir
);
45 uniforms
= nir
->num_uniforms
;
46 //nir_setup_uniforms(nir);
47 nir_emit_system_values(nir
);
49 /* get the main function and emit it */
50 nir_foreach_overload(nir
, overload
) {
51 assert(strcmp(overload
->function
->name
, "main") == 0);
52 assert(overload
->impl
);
53 nir_emit_impl(overload
->impl
);
58 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
60 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, shader
->num_inputs
);
62 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
63 enum brw_reg_type type
= brw_type_for_base_type(var
->type
);
64 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
68 case MESA_SHADER_VERTEX
: {
69 /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
70 * stored in nir_variable::location.
72 * However, NIR's load_input intrinsics use a different index - an
73 * offset into a single contiguous array containing all inputs.
74 * This index corresponds to the nir_variable::driver_location field.
76 * So, we need to copy from fs_reg(ATTR, var->location) to
77 * offset(nir_inputs, var->data.driver_location).
79 const glsl_type
*const t
= var
->type
->without_array();
80 const unsigned components
= t
->components();
81 const unsigned cols
= t
->matrix_columns
;
82 const unsigned elts
= t
->vector_elements
;
83 unsigned array_length
= var
->type
->is_array() ? var
->type
->length
: 1;
84 for (unsigned i
= 0; i
< array_length
; i
++) {
85 for (unsigned j
= 0; j
< cols
; j
++) {
86 for (unsigned k
= 0; k
< elts
; k
++) {
87 bld
.MOV(offset(retype(input
, type
), bld
,
88 components
* i
+ elts
* j
+ k
),
89 offset(fs_reg(ATTR
, var
->data
.location
+ i
, type
),
96 case MESA_SHADER_GEOMETRY
:
97 case MESA_SHADER_COMPUTE
:
98 case MESA_SHADER_TESS_CTRL
:
99 case MESA_SHADER_TESS_EVAL
:
100 unreachable("fs_visitor not used for these stages yet.");
102 case MESA_SHADER_FRAGMENT
:
103 if (var
->data
.location
== VARYING_SLOT_POS
) {
104 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
105 var
->data
.origin_upper_left
);
106 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
109 emit_general_interpolation(input
, var
->name
, var
->type
,
110 (glsl_interp_qualifier
) var
->data
.interpolation
,
111 var
->data
.location
, var
->data
.centroid
,
120 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
122 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
124 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, shader
->num_outputs
);
126 foreach_list_typed(nir_variable
, var
, node
, &shader
->outputs
) {
127 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
129 int vector_elements
=
130 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
131 : var
->type
->vector_elements
;
134 case MESA_SHADER_VERTEX
:
135 for (unsigned int i
= 0; i
< ALIGN(type_size_scalar(var
->type
), 4) / 4; i
++) {
136 int output
= var
->data
.location
+ i
;
137 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
138 this->output_components
[output
] = vector_elements
;
141 case MESA_SHADER_FRAGMENT
:
142 if (var
->data
.index
> 0) {
143 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
144 assert(var
->data
.index
== 1);
145 this->dual_src_output
= reg
;
146 this->do_dual_src
= true;
147 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
148 /* Writing gl_FragColor outputs to all color regions. */
149 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
150 this->outputs
[i
] = reg
;
151 this->output_components
[i
] = 4;
153 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
154 this->frag_depth
= reg
;
155 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
156 this->sample_mask
= reg
;
158 /* gl_FragData or a user-defined FS output */
159 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
160 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
162 /* General color output. */
163 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
164 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
165 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
166 this->output_components
[output
] = vector_elements
;
171 unreachable("unhandled shader stage");
177 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
179 if (dispatch_width
!= 8)
182 uniforms
= shader
->num_uniforms
;
185 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
186 /* UBO's and atomics don't take up space in the uniform file */
187 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
190 if (strncmp(var
->name
, "gl_", 3) == 0)
191 nir_setup_builtin_uniform(var
);
193 nir_setup_uniform(var
);
194 if(type_size_scalar(var
->type
) > 0)
195 param_size
[var
->data
.driver_location
] = type_size_scalar(var
->type
);
198 /* prog_to_nir only creates a single giant uniform variable so we can
199 * just set param up directly. */
200 for (unsigned p
= 0; p
< prog
->Parameters
->NumParameters
; p
++) {
201 for (unsigned int i
= 0; i
< 4; i
++) {
202 stage_prog_data
->param
[4 * p
+ i
] =
203 &prog
->Parameters
->ParameterValues
[p
][i
];
206 if(prog
->Parameters
->NumParameters
> 0)
207 param_size
[0] = prog
->Parameters
->NumParameters
* 4;
212 fs_visitor::nir_setup_uniform(nir_variable
*var
)
214 int namelen
= strlen(var
->name
);
216 /* The data for our (non-builtin) uniforms is stored in a series of
217 * gl_uniform_driver_storage structs for each subcomponent that
218 * glGetUniformLocation() could name. We know it's been set up in the
219 * same order we'd walk the type, so walk the list of storage and find
220 * anything with our name, or the prefix of a component that starts with
223 unsigned index
= var
->data
.driver_location
;
224 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
225 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
227 if (storage
->builtin
)
230 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
231 (storage
->name
[namelen
] != 0 &&
232 storage
->name
[namelen
] != '.' &&
233 storage
->name
[namelen
] != '[')) {
237 if (storage
->type
->is_image()) {
238 setup_image_uniform_values(index
, storage
);
240 unsigned slots
= storage
->type
->component_slots();
241 if (storage
->array_elements
)
242 slots
*= storage
->array_elements
;
244 for (unsigned i
= 0; i
< slots
; i
++) {
245 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
252 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
254 const nir_state_slot
*const slots
= var
->state_slots
;
255 assert(var
->state_slots
!= NULL
);
257 unsigned uniform_index
= var
->data
.driver_location
;
258 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
259 /* This state reference has already been setup by ir_to_mesa, but we'll
260 * get the same index back here.
262 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
263 (gl_state_index
*)slots
[i
].tokens
);
265 /* Add each of the unique swizzles of the element as a parameter.
266 * This'll end up matching the expected layout of the
267 * array/matrix/structure we're trying to fill in.
270 for (unsigned int j
= 0; j
< 4; j
++) {
271 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
272 if (swiz
== last_swiz
)
276 stage_prog_data
->param
[uniform_index
++] =
277 &prog
->Parameters
->ParameterValues
[index
][swiz
];
283 emit_system_values_block(nir_block
*block
, void *void_visitor
)
285 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
288 nir_foreach_instr(block
, instr
) {
289 if (instr
->type
!= nir_instr_type_intrinsic
)
292 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
293 switch (intrin
->intrinsic
) {
294 case nir_intrinsic_load_vertex_id
:
295 unreachable("should be lowered by lower_vertex_id().");
297 case nir_intrinsic_load_vertex_id_zero_base
:
298 assert(v
->stage
== MESA_SHADER_VERTEX
);
299 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
300 if (reg
->file
== BAD_FILE
)
301 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
304 case nir_intrinsic_load_base_vertex
:
305 assert(v
->stage
== MESA_SHADER_VERTEX
);
306 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
307 if (reg
->file
== BAD_FILE
)
308 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
311 case nir_intrinsic_load_instance_id
:
312 assert(v
->stage
== MESA_SHADER_VERTEX
);
313 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
314 if (reg
->file
== BAD_FILE
)
315 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
318 case nir_intrinsic_load_sample_pos
:
319 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
320 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
321 if (reg
->file
== BAD_FILE
)
322 *reg
= *v
->emit_samplepos_setup();
325 case nir_intrinsic_load_sample_id
:
326 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
327 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
328 if (reg
->file
== BAD_FILE
)
329 *reg
= *v
->emit_sampleid_setup();
332 case nir_intrinsic_load_sample_mask_in
:
333 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
334 assert(v
->devinfo
->gen
>= 7);
335 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
336 if (reg
->file
== BAD_FILE
)
337 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
338 BRW_REGISTER_TYPE_D
));
350 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
352 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
353 nir_foreach_overload(shader
, overload
) {
354 assert(strcmp(overload
->function
->name
, "main") == 0);
355 assert(overload
->impl
);
356 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
361 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
363 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
364 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
365 unsigned array_elems
=
366 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
367 unsigned size
= array_elems
* reg
->num_components
;
368 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
371 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
374 nir_emit_cf_list(&impl
->body
);
378 fs_visitor::nir_emit_cf_list(exec_list
*list
)
380 exec_list_validate(list
);
381 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
382 switch (node
->type
) {
384 nir_emit_if(nir_cf_node_as_if(node
));
387 case nir_cf_node_loop
:
388 nir_emit_loop(nir_cf_node_as_loop(node
));
391 case nir_cf_node_block
:
392 nir_emit_block(nir_cf_node_as_block(node
));
396 unreachable("Invalid CFG node block");
402 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
404 /* first, put the condition into f0 */
405 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
406 retype(get_nir_src(if_stmt
->condition
),
407 BRW_REGISTER_TYPE_D
));
408 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
410 bld
.IF(BRW_PREDICATE_NORMAL
);
412 nir_emit_cf_list(&if_stmt
->then_list
);
414 /* note: if the else is empty, dead CF elimination will remove it */
415 bld
.emit(BRW_OPCODE_ELSE
);
417 nir_emit_cf_list(&if_stmt
->else_list
);
419 bld
.emit(BRW_OPCODE_ENDIF
);
423 fs_visitor::nir_emit_loop(nir_loop
*loop
)
425 bld
.emit(BRW_OPCODE_DO
);
427 nir_emit_cf_list(&loop
->body
);
429 bld
.emit(BRW_OPCODE_WHILE
);
433 fs_visitor::nir_emit_block(nir_block
*block
)
435 nir_foreach_instr(block
, instr
) {
436 nir_emit_instr(instr
);
441 fs_visitor::nir_emit_instr(nir_instr
*instr
)
443 const fs_builder abld
= bld
.annotate(NULL
, instr
);
445 switch (instr
->type
) {
446 case nir_instr_type_alu
:
447 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
450 case nir_instr_type_intrinsic
:
451 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
454 case nir_instr_type_tex
:
455 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
458 case nir_instr_type_load_const
:
459 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
462 case nir_instr_type_ssa_undef
:
463 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
466 case nir_instr_type_jump
:
467 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
471 unreachable("unknown instruction type");
476 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
477 const fs_reg
&result
)
479 if (!instr
->src
[0].src
.is_ssa
||
480 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
483 nir_intrinsic_instr
*src0
=
484 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
486 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
489 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
490 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
493 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
494 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
497 fs_reg tmp
= vgrf(glsl_type::int_type
);
499 if (devinfo
->gen
>= 6) {
500 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
501 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
503 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
505 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
506 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
508 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
510 * This negation looks like it's safe in practice, because bits 0:4 will
511 * surely be TRIANGLES
514 if (value1
->f
[0] == -1.0f
) {
518 tmp
.type
= BRW_REGISTER_TYPE_W
;
519 tmp
.subreg_offset
= 2;
522 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
523 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
525 tmp
.type
= BRW_REGISTER_TYPE_D
;
526 tmp
.subreg_offset
= 0;
529 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
530 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
532 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
534 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
535 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
537 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
539 * This negation looks like it's safe in practice, because bits 0:4 will
540 * surely be TRIANGLES
543 if (value1
->f
[0] == -1.0f
) {
547 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
549 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
555 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
557 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
560 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
561 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
564 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
565 op
[i
] = get_nir_src(instr
->src
[i
].src
);
566 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
567 op
[i
].abs
= instr
->src
[i
].abs
;
568 op
[i
].negate
= instr
->src
[i
].negate
;
571 /* We get a bunch of mov's out of the from_ssa pass and they may still
572 * be vectorized. We'll handle them as a special-case. We'll also
573 * handle vecN here because it's basically the same thing.
581 fs_reg temp
= result
;
582 bool need_extra_copy
= false;
583 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
584 if (!instr
->src
[i
].src
.is_ssa
&&
585 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
586 need_extra_copy
= true;
587 temp
= bld
.vgrf(result
.type
, 4);
592 for (unsigned i
= 0; i
< 4; i
++) {
593 if (!(instr
->dest
.write_mask
& (1 << i
)))
596 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
597 inst
= bld
.MOV(offset(temp
, bld
, i
),
598 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
600 inst
= bld
.MOV(offset(temp
, bld
, i
),
601 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
603 inst
->saturate
= instr
->dest
.saturate
;
606 /* In this case the source and destination registers were the same,
607 * so we need to insert an extra set of moves in order to deal with
610 if (need_extra_copy
) {
611 for (unsigned i
= 0; i
< 4; i
++) {
612 if (!(instr
->dest
.write_mask
& (1 << i
)))
615 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
624 /* At this point, we have dealt with any instruction that operates on
625 * more than a single channel. Therefore, we can just adjust the source
626 * and destination registers for that channel and emit the instruction.
628 unsigned channel
= 0;
629 if (nir_op_infos
[instr
->op
].output_size
== 0) {
630 /* Since NIR is doing the scalarizing for us, we should only ever see
631 * vectorized operations with a single channel.
633 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
634 channel
= ffs(instr
->dest
.write_mask
) - 1;
636 result
= offset(result
, bld
, channel
);
639 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
640 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
641 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
647 inst
= bld
.MOV(result
, op
[0]);
648 inst
->saturate
= instr
->dest
.saturate
;
653 bld
.MOV(result
, op
[0]);
657 /* AND(val, 0x80000000) gives the sign bit.
659 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
662 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
664 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
665 op
[0].type
= BRW_REGISTER_TYPE_UD
;
666 result
.type
= BRW_REGISTER_TYPE_UD
;
667 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
669 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
670 inst
->predicate
= BRW_PREDICATE_NORMAL
;
671 if (instr
->dest
.saturate
) {
672 inst
= bld
.MOV(result
, result
);
673 inst
->saturate
= true;
679 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
680 * -> non-negative val generates 0x00000000.
681 * Predicated OR sets 1 if val is positive.
683 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
684 bld
.ASR(result
, op
[0], fs_reg(31));
685 inst
= bld
.OR(result
, result
, fs_reg(1));
686 inst
->predicate
= BRW_PREDICATE_NORMAL
;
690 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
691 inst
->saturate
= instr
->dest
.saturate
;
695 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
696 inst
->saturate
= instr
->dest
.saturate
;
700 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
701 inst
->saturate
= instr
->dest
.saturate
;
705 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
706 inst
->saturate
= instr
->dest
.saturate
;
710 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
711 inst
->saturate
= instr
->dest
.saturate
;
715 if (fs_key
->high_quality_derivatives
) {
716 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
718 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
720 inst
->saturate
= instr
->dest
.saturate
;
722 case nir_op_fddx_fine
:
723 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
724 inst
->saturate
= instr
->dest
.saturate
;
726 case nir_op_fddx_coarse
:
727 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
728 inst
->saturate
= instr
->dest
.saturate
;
731 if (fs_key
->high_quality_derivatives
) {
732 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
733 fs_reg(fs_key
->render_to_fbo
));
735 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
736 fs_reg(fs_key
->render_to_fbo
));
738 inst
->saturate
= instr
->dest
.saturate
;
740 case nir_op_fddy_fine
:
741 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
742 fs_reg(fs_key
->render_to_fbo
));
743 inst
->saturate
= instr
->dest
.saturate
;
745 case nir_op_fddy_coarse
:
746 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
747 fs_reg(fs_key
->render_to_fbo
));
748 inst
->saturate
= instr
->dest
.saturate
;
753 inst
= bld
.ADD(result
, op
[0], op
[1]);
754 inst
->saturate
= instr
->dest
.saturate
;
758 inst
= bld
.MUL(result
, op
[0], op
[1]);
759 inst
->saturate
= instr
->dest
.saturate
;
763 bld
.MUL(result
, op
[0], op
[1]);
766 case nir_op_imul_high
:
767 case nir_op_umul_high
:
768 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
773 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
776 case nir_op_uadd_carry
:
777 unreachable("Should have been lowered by carry_to_arith().");
779 case nir_op_usub_borrow
:
780 unreachable("Should have been lowered by borrow_to_arith().");
783 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
789 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
795 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
800 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
805 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
809 if (devinfo
->gen
>= 8) {
810 op
[0] = resolve_source_modifiers(op
[0]);
812 bld
.NOT(result
, op
[0]);
815 if (devinfo
->gen
>= 8) {
816 op
[0] = resolve_source_modifiers(op
[0]);
817 op
[1] = resolve_source_modifiers(op
[1]);
819 bld
.XOR(result
, op
[0], op
[1]);
822 if (devinfo
->gen
>= 8) {
823 op
[0] = resolve_source_modifiers(op
[0]);
824 op
[1] = resolve_source_modifiers(op
[1]);
826 bld
.OR(result
, op
[0], op
[1]);
829 if (devinfo
->gen
>= 8) {
830 op
[0] = resolve_source_modifiers(op
[0]);
831 op
[1] = resolve_source_modifiers(op
[1]);
833 bld
.AND(result
, op
[0], op
[1]);
845 case nir_op_ball_fequal2
:
846 case nir_op_ball_iequal2
:
847 case nir_op_ball_fequal3
:
848 case nir_op_ball_iequal3
:
849 case nir_op_ball_fequal4
:
850 case nir_op_ball_iequal4
:
851 case nir_op_bany_fnequal2
:
852 case nir_op_bany_inequal2
:
853 case nir_op_bany_fnequal3
:
854 case nir_op_bany_inequal3
:
855 case nir_op_bany_fnequal4
:
856 case nir_op_bany_inequal4
:
857 unreachable("Lowered by nir_lower_alu_reductions");
859 case nir_op_fnoise1_1
:
860 case nir_op_fnoise1_2
:
861 case nir_op_fnoise1_3
:
862 case nir_op_fnoise1_4
:
863 case nir_op_fnoise2_1
:
864 case nir_op_fnoise2_2
:
865 case nir_op_fnoise2_3
:
866 case nir_op_fnoise2_4
:
867 case nir_op_fnoise3_1
:
868 case nir_op_fnoise3_2
:
869 case nir_op_fnoise3_3
:
870 case nir_op_fnoise3_4
:
871 case nir_op_fnoise4_1
:
872 case nir_op_fnoise4_2
:
873 case nir_op_fnoise4_3
:
874 case nir_op_fnoise4_4
:
875 unreachable("not reached: should be handled by lower_noise");
878 unreachable("not reached: should be handled by ldexp_to_arith()");
881 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
882 inst
->saturate
= instr
->dest
.saturate
;
886 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
887 inst
->saturate
= instr
->dest
.saturate
;
892 bld
.MOV(result
, negate(op
[0]));
896 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
899 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
903 inst
= bld
.RNDZ(result
, op
[0]);
904 inst
->saturate
= instr
->dest
.saturate
;
908 op
[0].negate
= !op
[0].negate
;
909 fs_reg temp
= vgrf(glsl_type::float_type
);
910 bld
.RNDD(temp
, op
[0]);
912 inst
= bld
.MOV(result
, temp
);
913 inst
->saturate
= instr
->dest
.saturate
;
917 inst
= bld
.RNDD(result
, op
[0]);
918 inst
->saturate
= instr
->dest
.saturate
;
921 inst
= bld
.FRC(result
, op
[0]);
922 inst
->saturate
= instr
->dest
.saturate
;
924 case nir_op_fround_even
:
925 inst
= bld
.RNDE(result
, op
[0]);
926 inst
->saturate
= instr
->dest
.saturate
;
932 if (devinfo
->gen
>= 6) {
933 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
934 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
936 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
937 inst
= bld
.SEL(result
, op
[0], op
[1]);
938 inst
->predicate
= BRW_PREDICATE_NORMAL
;
940 inst
->saturate
= instr
->dest
.saturate
;
946 if (devinfo
->gen
>= 6) {
947 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
948 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
950 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
951 inst
= bld
.SEL(result
, op
[0], op
[1]);
952 inst
->predicate
= BRW_PREDICATE_NORMAL
;
954 inst
->saturate
= instr
->dest
.saturate
;
957 case nir_op_pack_snorm_2x16
:
958 case nir_op_pack_snorm_4x8
:
959 case nir_op_pack_unorm_2x16
:
960 case nir_op_pack_unorm_4x8
:
961 case nir_op_unpack_snorm_2x16
:
962 case nir_op_unpack_snorm_4x8
:
963 case nir_op_unpack_unorm_2x16
:
964 case nir_op_unpack_unorm_4x8
:
965 case nir_op_unpack_half_2x16
:
966 case nir_op_pack_half_2x16
:
967 unreachable("not reached: should be handled by lower_packing_builtins");
969 case nir_op_unpack_half_2x16_split_x
:
970 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
971 inst
->saturate
= instr
->dest
.saturate
;
973 case nir_op_unpack_half_2x16_split_y
:
974 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
975 inst
->saturate
= instr
->dest
.saturate
;
979 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
980 inst
->saturate
= instr
->dest
.saturate
;
983 case nir_op_bitfield_reverse
:
984 bld
.BFREV(result
, op
[0]);
987 case nir_op_bit_count
:
988 bld
.CBIT(result
, op
[0]);
991 case nir_op_ufind_msb
:
992 case nir_op_ifind_msb
: {
993 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
995 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
996 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
997 * subtract the result from 31 to convert the MSB count into an LSB count.
1000 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
1001 fs_reg
neg_result(result
);
1002 neg_result
.negate
= true;
1003 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
1004 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1008 case nir_op_find_lsb
:
1009 bld
.FBL(result
, op
[0]);
1012 case nir_op_ubitfield_extract
:
1013 case nir_op_ibitfield_extract
:
1014 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1017 bld
.BFI1(result
, op
[0], op
[1]);
1020 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1023 case nir_op_bitfield_insert
:
1024 unreachable("not reached: should be handled by "
1025 "lower_instructions::bitfield_insert_to_bfm_bfi");
1028 bld
.SHL(result
, op
[0], op
[1]);
1031 bld
.ASR(result
, op
[0], op
[1]);
1034 bld
.SHR(result
, op
[0], op
[1]);
1037 case nir_op_pack_half_2x16_split
:
1038 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1042 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1043 inst
->saturate
= instr
->dest
.saturate
;
1047 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1048 inst
->saturate
= instr
->dest
.saturate
;
1052 if (optimize_frontfacing_ternary(instr
, result
))
1055 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
1056 inst
= bld
.SEL(result
, op
[1], op
[2]);
1057 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1061 unreachable("unhandled instruction");
1064 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1065 * to sign extend the low bit to 0/~0
1067 if (devinfo
->gen
<= 5 &&
1068 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1069 fs_reg masked
= vgrf(glsl_type::int_type
);
1070 bld
.AND(masked
, result
, fs_reg(1));
1071 masked
.negate
= true;
1072 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1077 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1078 nir_load_const_instr
*instr
)
1080 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1082 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1083 bld
.MOV(offset(reg
, bld
, i
), fs_reg(instr
->value
.i
[i
]));
1085 nir_ssa_values
[instr
->def
.index
] = reg
;
1089 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1091 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1092 instr
->def
.num_components
);
1096 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1097 unsigned base_offset
, nir_src
*indirect
)
1101 assert(!nir_reg
->is_global
);
1103 reg
= v
->nir_locals
[nir_reg
->index
];
1105 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1107 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1109 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1110 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1111 fs_reg(multiplier
));
1118 fs_visitor::get_nir_src(nir_src src
)
1122 reg
= nir_ssa_values
[src
.ssa
->index
];
1124 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1128 /* to avoid floating-point denorm flushing problems, set the type by
1129 * default to D - instructions that need floating point semantics will set
1130 * this to F if they need to
1132 return retype(reg
, BRW_REGISTER_TYPE_D
);
1136 fs_visitor::get_nir_dest(nir_dest dest
)
1139 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1140 dest
.ssa
.num_components
);
1141 return nir_ssa_values
[dest
.ssa
.index
];
1144 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1149 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1151 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
,
1152 BRW_REGISTER_TYPE_UD
);
1154 if (deref
->deref
.child
) {
1155 const nir_deref_array
*deref_array
=
1156 nir_deref_as_array(deref
->deref
.child
);
1157 assert(deref
->deref
.child
->deref_type
== nir_deref_type_array
&&
1158 deref_array
->deref
.child
== NULL
);
1159 const unsigned size
= glsl_get_length(deref
->var
->type
);
1160 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1162 image
= offset(image
, bld
, base
* BRW_IMAGE_PARAM_SIZE
);
1164 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1165 fs_reg
*tmp
= new(mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1167 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1168 /* IVB hangs when trying to access an invalid surface index with
1169 * the dataport. According to the spec "if the index used to
1170 * select an individual element is negative or greater than or
1171 * equal to the size of the array, the results of the operation
1172 * are undefined but may not lead to termination" -- which is one
1173 * of the possible outcomes of the hang. Clamp the index to
1174 * prevent access outside of the array bounds.
1176 bld
.emit_minmax(*tmp
, retype(get_nir_src(deref_array
->indirect
),
1177 BRW_REGISTER_TYPE_UD
),
1178 fs_reg(size
- base
- 1), BRW_CONDITIONAL_L
);
1180 bld
.MOV(*tmp
, get_nir_src(deref_array
->indirect
));
1183 bld
.MUL(*tmp
, *tmp
, fs_reg(BRW_IMAGE_PARAM_SIZE
));
1184 image
.reladdr
= tmp
;
1192 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1195 for (unsigned i
= 0; i
< 4; i
++) {
1196 if (!((wr_mask
>> i
) & 1))
1199 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1200 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1201 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1202 if (new_inst
->src
[j
].file
== GRF
)
1203 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1210 * Get the matching channel register datatype for an image intrinsic of the
1211 * specified GLSL image type.
1214 get_image_base_type(const glsl_type
*type
)
1216 switch ((glsl_base_type
)type
->sampler_type
) {
1217 case GLSL_TYPE_UINT
:
1218 return BRW_REGISTER_TYPE_UD
;
1220 return BRW_REGISTER_TYPE_D
;
1221 case GLSL_TYPE_FLOAT
:
1222 return BRW_REGISTER_TYPE_F
;
1224 unreachable("Not reached.");
1229 * Get the appropriate atomic op for an image atomic intrinsic.
1232 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1235 case nir_intrinsic_image_atomic_add
:
1237 case nir_intrinsic_image_atomic_min
:
1238 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1239 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1240 case nir_intrinsic_image_atomic_max
:
1241 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1242 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1243 case nir_intrinsic_image_atomic_and
:
1245 case nir_intrinsic_image_atomic_or
:
1247 case nir_intrinsic_image_atomic_xor
:
1249 case nir_intrinsic_image_atomic_exchange
:
1251 case nir_intrinsic_image_atomic_comp_swap
:
1252 return BRW_AOP_CMPWR
;
1254 unreachable("Not reachable.");
1259 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1262 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1263 dest
= get_nir_dest(instr
->dest
);
1265 bool has_indirect
= false;
1267 switch (instr
->intrinsic
) {
1268 case nir_intrinsic_discard
:
1269 case nir_intrinsic_discard_if
: {
1270 /* We track our discarded pixels in f0.1. By predicating on it, we can
1271 * update just the flag bits that aren't yet discarded. If there's no
1272 * condition, we emit a CMP of g0 != g0, so all currently executing
1273 * channels will get turned off.
1276 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1277 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1278 fs_reg(0), BRW_CONDITIONAL_Z
);
1280 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1281 BRW_REGISTER_TYPE_UW
));
1282 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1284 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1285 cmp
->flag_subreg
= 1;
1287 if (devinfo
->gen
>= 6) {
1288 emit_discard_jump();
1293 case nir_intrinsic_atomic_counter_inc
:
1294 case nir_intrinsic_atomic_counter_dec
:
1295 case nir_intrinsic_atomic_counter_read
: {
1296 using namespace surface_access
;
1298 /* Get the arguments of the atomic intrinsic. */
1299 const fs_reg offset
= get_nir_src(instr
->src
[0]);
1300 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
1301 instr
->const_index
[0]);
1304 /* Emit a surface read or atomic op. */
1305 switch (instr
->intrinsic
) {
1306 case nir_intrinsic_atomic_counter_read
:
1307 tmp
= emit_untyped_read(bld
, fs_reg(surface
), offset
, 1, 1);
1310 case nir_intrinsic_atomic_counter_inc
:
1311 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1312 fs_reg(), 1, 1, BRW_AOP_INC
);
1315 case nir_intrinsic_atomic_counter_dec
:
1316 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1317 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
1321 unreachable("Unreachable");
1324 /* Assign the result. */
1325 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
1327 /* Mark the surface as used. */
1328 brw_mark_surface_used(stage_prog_data
, surface
);
1332 case nir_intrinsic_image_load
:
1333 case nir_intrinsic_image_store
:
1334 case nir_intrinsic_image_atomic_add
:
1335 case nir_intrinsic_image_atomic_min
:
1336 case nir_intrinsic_image_atomic_max
:
1337 case nir_intrinsic_image_atomic_and
:
1338 case nir_intrinsic_image_atomic_or
:
1339 case nir_intrinsic_image_atomic_xor
:
1340 case nir_intrinsic_image_atomic_exchange
:
1341 case nir_intrinsic_image_atomic_comp_swap
: {
1342 using namespace image_access
;
1344 /* Get the referenced image variable and type. */
1345 const nir_variable
*var
= instr
->variables
[0]->var
;
1346 const glsl_type
*type
= var
->type
->without_array();
1347 const brw_reg_type base_type
= get_image_base_type(type
);
1349 /* Get some metadata from the image intrinsic. */
1350 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
1351 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
1352 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
1353 const mesa_format format
=
1354 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
1355 _mesa_get_shader_image_format(var
->data
.image
.format
));
1357 /* Get the arguments of the image intrinsic. */
1358 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
1359 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
1360 BRW_REGISTER_TYPE_UD
);
1361 const fs_reg src0
= (info
->num_srcs
>= 3 ?
1362 retype(get_nir_src(instr
->src
[2]), base_type
) :
1364 const fs_reg src1
= (info
->num_srcs
>= 4 ?
1365 retype(get_nir_src(instr
->src
[3]), base_type
) :
1369 /* Emit an image load, store or atomic op. */
1370 if (instr
->intrinsic
== nir_intrinsic_image_load
)
1371 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
1373 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
1374 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
1377 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
1378 surf_dims
, arr_dims
, info
->dest_components
,
1379 get_image_atomic_op(instr
->intrinsic
, type
));
1381 /* Assign the result. */
1382 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
1383 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
1384 offset(tmp
, bld
, c
));
1388 case nir_intrinsic_memory_barrier
: {
1389 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
1390 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
1395 case nir_intrinsic_image_size
: {
1396 /* Get the referenced image variable and type. */
1397 const nir_variable
*var
= instr
->variables
[0]->var
;
1398 const glsl_type
*type
= var
->type
->without_array();
1400 /* Get the size of the image. */
1401 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
1402 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
1404 /* For 1DArray image types, the array index is stored in the Z component.
1405 * Fix this by swizzling the Z component to the Y component.
1407 const bool is_1d_array_image
=
1408 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
1409 type
->sampler_array
;
1411 /* For CubeArray images, we should count the number of cubes instead
1412 * of the number of faces. Fix it by dividing the (Z component) by 6.
1414 const bool is_cube_array_image
=
1415 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1416 type
->sampler_array
;
1418 /* Copy all the components. */
1419 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
1420 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
1421 if ((int)c
>= type
->coordinate_components()) {
1422 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1424 } else if (c
== 1 && is_1d_array_image
) {
1425 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1426 offset(size
, bld
, 2));
1427 } else if (c
== 2 && is_cube_array_image
) {
1428 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
1429 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1430 offset(size
, bld
, c
), fs_reg(6));
1432 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1433 offset(size
, bld
, c
));
1440 case nir_intrinsic_load_front_face
:
1441 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1442 *emit_frontfacing_interpolation());
1445 case nir_intrinsic_load_vertex_id
:
1446 unreachable("should be lowered by lower_vertex_id()");
1448 case nir_intrinsic_load_vertex_id_zero_base
: {
1449 fs_reg vertex_id
= nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
1450 assert(vertex_id
.file
!= BAD_FILE
);
1451 dest
.type
= vertex_id
.type
;
1452 bld
.MOV(dest
, vertex_id
);
1456 case nir_intrinsic_load_base_vertex
: {
1457 fs_reg base_vertex
= nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
1458 assert(base_vertex
.file
!= BAD_FILE
);
1459 dest
.type
= base_vertex
.type
;
1460 bld
.MOV(dest
, base_vertex
);
1464 case nir_intrinsic_load_instance_id
: {
1465 fs_reg instance_id
= nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
1466 assert(instance_id
.file
!= BAD_FILE
);
1467 dest
.type
= instance_id
.type
;
1468 bld
.MOV(dest
, instance_id
);
1472 case nir_intrinsic_load_sample_mask_in
: {
1473 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1474 assert(sample_mask_in
.file
!= BAD_FILE
);
1475 dest
.type
= sample_mask_in
.type
;
1476 bld
.MOV(dest
, sample_mask_in
);
1480 case nir_intrinsic_load_sample_pos
: {
1481 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1482 assert(sample_pos
.file
!= BAD_FILE
);
1483 dest
.type
= sample_pos
.type
;
1484 bld
.MOV(dest
, sample_pos
);
1485 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1489 case nir_intrinsic_load_sample_id
: {
1490 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1491 assert(sample_id
.file
!= BAD_FILE
);
1492 dest
.type
= sample_id
.type
;
1493 bld
.MOV(dest
, sample_id
);
1497 case nir_intrinsic_load_uniform_indirect
:
1498 has_indirect
= true;
1500 case nir_intrinsic_load_uniform
: {
1501 fs_reg
uniform_reg(UNIFORM
, instr
->const_index
[0]);
1502 uniform_reg
.reg_offset
= instr
->const_index
[1];
1504 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1505 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, j
);
1507 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1510 dest
= offset(dest
, bld
, 1);
1515 case nir_intrinsic_load_ubo_indirect
:
1516 has_indirect
= true;
1518 case nir_intrinsic_load_ubo
: {
1519 uint32_t set
= instr
->const_index
[0];
1520 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1524 uint32_t binding
= const_index
->u
[0];
1526 /* FIXME: We should probably assert here, but dota2 seems to hit
1527 * it and we'd like to keep going.
1529 if (binding
>= stage_prog_data
->bind_map
[set
].index_count
)
1532 surf_index
= fs_reg(stage_prog_data
->bind_map
[set
].index
[binding
]);
1534 assert(0 && "need more info from the ir for this.");
1535 /* The block index is not a constant. Evaluate the index expression
1536 * per-channel and add the base UBO index; we have to select a value
1537 * from any live channel.
1539 surf_index
= vgrf(glsl_type::uint_type
);
1540 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1541 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1542 surf_index
= bld
.emit_uniformize(surf_index
);
1544 /* Assume this may touch any UBO. It would be nice to provide
1545 * a tighter bound, but the array information is already lowered away.
1547 brw_mark_surface_used(prog_data
,
1548 stage_prog_data
->binding_table
.ubo_start
+
1549 shader_prog
->NumUniformBlocks
- 1);
1553 /* Turn the byte offset into a dword offset. */
1554 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1555 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1556 BRW_REGISTER_TYPE_D
),
1559 unsigned vec4_offset
= instr
->const_index
[1] / 4;
1560 for (int i
= 0; i
< instr
->num_components
; i
++)
1561 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
1562 base_offset
, vec4_offset
+ i
);
1564 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1565 packed_consts
.type
= dest
.type
;
1567 fs_reg
const_offset_reg((unsigned) instr
->const_index
[1] & ~15);
1568 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1569 surf_index
, const_offset_reg
);
1571 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1572 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1574 /* The std140 packing rules don't allow vectors to cross 16-byte
1575 * boundaries, and a reg is 32 bytes.
1577 assert(packed_consts
.subreg_offset
< 32);
1579 bld
.MOV(dest
, packed_consts
);
1580 dest
= offset(dest
, bld
, 1);
1586 case nir_intrinsic_load_input_indirect
:
1587 has_indirect
= true;
1589 case nir_intrinsic_load_input
: {
1591 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1592 fs_reg src
= offset(retype(nir_inputs
, dest
.type
), bld
,
1593 instr
->const_index
[0] + index
);
1595 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1599 dest
= offset(dest
, bld
, 1);
1604 /* Handle ARB_gpu_shader5 interpolation intrinsics
1606 * It's worth a quick word of explanation as to why we handle the full
1607 * variable-based interpolation intrinsic rather than a lowered version
1608 * with like we do for other inputs. We have to do that because the way
1609 * we set up inputs doesn't allow us to use the already setup inputs for
1610 * interpolation. At the beginning of the shader, we go through all of
1611 * the input variables and do the initial interpolation and put it in
1612 * the nir_inputs array based on its location as determined in
1613 * nir_lower_io. If the input isn't used, dead code cleans up and
1614 * everything works fine. However, when we get to the ARB_gpu_shader5
1615 * interpolation intrinsics, we need to reinterpolate the input
1616 * differently. If we used an intrinsic that just had an index it would
1617 * only give us the offset into the nir_inputs array. However, this is
1618 * useless because that value is post-interpolation and we need
1619 * pre-interpolation. In order to get the actual location of the bits
1620 * we get from the vertex fetching hardware, we need the variable.
1622 case nir_intrinsic_interp_var_at_centroid
:
1623 case nir_intrinsic_interp_var_at_sample
:
1624 case nir_intrinsic_interp_var_at_offset
: {
1625 assert(stage
== MESA_SHADER_FRAGMENT
);
1627 ((struct brw_wm_prog_data
*) prog_data
)->pulls_bary
= true;
1629 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1631 /* For most messages, we need one reg of ignored data; the hardware
1632 * requires mlen==1 even when there is no payload. in the per-slot
1633 * offset case, we'll replace this with the proper source data.
1635 fs_reg src
= vgrf(glsl_type::float_type
);
1636 int mlen
= 1; /* one reg unless overriden */
1639 switch (instr
->intrinsic
) {
1640 case nir_intrinsic_interp_var_at_centroid
:
1641 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1642 dst_xy
, src
, fs_reg(0u));
1645 case nir_intrinsic_interp_var_at_sample
: {
1646 /* XXX: We should probably handle non-constant sample id's */
1647 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1648 assert(const_sample
);
1649 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1650 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_xy
, src
,
1655 case nir_intrinsic_interp_var_at_offset
: {
1656 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1659 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1660 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1662 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_xy
, src
,
1663 fs_reg(off_x
| (off_y
<< 4)));
1665 src
= vgrf(glsl_type::ivec2_type
);
1666 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1667 BRW_REGISTER_TYPE_F
);
1668 for (int i
= 0; i
< 2; i
++) {
1669 fs_reg temp
= vgrf(glsl_type::float_type
);
1670 bld
.MUL(temp
, offset(offset_src
, bld
, i
), fs_reg(16.0f
));
1671 fs_reg itemp
= vgrf(glsl_type::int_type
);
1672 bld
.MOV(itemp
, temp
); /* float to int */
1674 /* Clamp the upper end of the range to +7/16.
1675 * ARB_gpu_shader5 requires that we support a maximum offset
1676 * of +0.5, which isn't representable in a S0.4 value -- if
1677 * we didn't clamp it, we'd end up with -8/16, which is the
1678 * opposite of what the shader author wanted.
1680 * This is legal due to ARB_gpu_shader5's quantization
1683 * "Not all values of <offset> may be supported; x and y
1684 * offsets may be rounded to fixed-point values with the
1685 * number of fraction bits given by the
1686 * implementation-dependent constant
1687 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1689 set_condmod(BRW_CONDITIONAL_L
,
1690 bld
.SEL(offset(src
, bld
, i
), itemp
, fs_reg(7)));
1693 mlen
= 2 * dispatch_width
/ 8;
1694 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_xy
, src
,
1701 unreachable("Invalid intrinsic");
1705 /* 2 floats per slot returned */
1706 inst
->regs_written
= 2 * dispatch_width
/ 8;
1707 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1708 INTERP_QUALIFIER_NOPERSPECTIVE
;
1710 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1711 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1712 src
.type
= dest
.type
;
1714 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1715 dest
= offset(dest
, bld
, 1);
1720 case nir_intrinsic_store_output_indirect
:
1721 has_indirect
= true;
1723 case nir_intrinsic_store_output
: {
1724 fs_reg src
= get_nir_src(instr
->src
[0]);
1726 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1727 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
1728 instr
->const_index
[0] + index
);
1730 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1732 bld
.MOV(new_dest
, src
);
1733 src
= offset(src
, bld
, 1);
1738 case nir_intrinsic_barrier
:
1743 unreachable("unknown intrinsic");
1748 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1750 uint32_t set
= instr
->sampler_set
;
1751 uint32_t binding
= instr
->sampler_index
;
1753 assert(binding
< stage_prog_data
->bind_map
[set
].index_count
);
1754 assert(stage_prog_data
->bind_map
[set
].index
[binding
] < 1000);
1756 unsigned sampler
= stage_prog_data
->bind_map
[set
].index
[binding
];
1757 fs_reg
sampler_reg(sampler
);
1759 /* FINISHME: We're failing to recompile our programs when the sampler is
1760 * updated. This only matters for the texture rectangle scale parameters
1761 * (pre-gen6, or gen6+ with GL_CLAMP).
1763 int texunit
= prog
->SamplerUnits
[sampler
];
1765 int gather_component
= instr
->component
;
1767 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1769 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1772 int lod_components
= 0;
1773 int UNUSED offset_components
= 0;
1775 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1777 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1778 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1779 switch (instr
->src
[i
].src_type
) {
1780 case nir_tex_src_bias
:
1781 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1783 case nir_tex_src_comparitor
:
1784 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1786 case nir_tex_src_coord
:
1787 switch (instr
->op
) {
1789 case nir_texop_txf_ms
:
1790 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1793 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1797 case nir_tex_src_ddx
:
1798 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1799 lod_components
= nir_tex_instr_src_size(instr
, i
);
1801 case nir_tex_src_ddy
:
1802 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1804 case nir_tex_src_lod
:
1805 switch (instr
->op
) {
1807 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1810 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1813 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1817 case nir_tex_src_ms_index
:
1818 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1820 case nir_tex_src_offset
:
1821 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1822 if (instr
->is_array
)
1823 offset_components
= instr
->coord_components
- 1;
1825 offset_components
= instr
->coord_components
;
1827 case nir_tex_src_projector
:
1828 unreachable("should be lowered");
1830 case nir_tex_src_sampler_offset
: {
1831 /* Figure out the highest possible sampler index and mark it as used */
1832 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1833 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
1834 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1836 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1838 brw_mark_surface_used(prog_data
, max_used
);
1840 /* Emit code to evaluate the actual indexing expression */
1841 sampler_reg
= vgrf(glsl_type::uint_type
);
1842 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
1843 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
1848 unreachable("unknown texture source");
1852 if (instr
->op
== nir_texop_txf_ms
) {
1853 if (devinfo
->gen
>= 7 &&
1854 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1855 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1861 for (unsigned i
= 0; i
< 3; i
++) {
1862 if (instr
->const_offset
[i
] != 0) {
1863 assert(offset_components
== 0);
1864 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
1869 enum glsl_base_type dest_base_type
=
1870 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
1872 const glsl_type
*dest_type
=
1873 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1876 ir_texture_opcode op
;
1877 switch (instr
->op
) {
1878 case nir_texop_lod
: op
= ir_lod
; break;
1879 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1880 case nir_texop_tex
: op
= ir_tex
; break;
1881 case nir_texop_tg4
: op
= ir_tg4
; break;
1882 case nir_texop_txb
: op
= ir_txb
; break;
1883 case nir_texop_txd
: op
= ir_txd
; break;
1884 case nir_texop_txf
: op
= ir_txf
; break;
1885 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1886 case nir_texop_txl
: op
= ir_txl
; break;
1887 case nir_texop_txs
: op
= ir_txs
; break;
1889 unreachable("unknown texture opcode");
1892 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1893 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1894 tex_offset
, mcs
, gather_component
,
1895 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1897 fs_reg dest
= get_nir_dest(instr
->dest
);
1898 dest
.type
= this->result
.type
;
1899 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1900 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
1901 dest
, this->result
),
1902 (1 << num_components
) - 1);
1906 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
1908 switch (instr
->type
) {
1909 case nir_jump_break
:
1910 bld
.emit(BRW_OPCODE_BREAK
);
1912 case nir_jump_continue
:
1913 bld
.emit(BRW_OPCODE_CONTINUE
);
1915 case nir_jump_return
:
1916 /* This has to be the last block in the shader. We don't handle
1919 assert(nir_cf_node_next(&instr
->instr
.block
->cf_node
) == NULL
&&
1920 instr
->instr
.block
->cf_node
.parent
->type
== nir_cf_node_function
);
1923 unreachable("unknown jump");