2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "program/prog_to_nir.h"
34 fs_visitor::emit_nir_code()
36 nir_shader
*nir
= prog
->nir
;
38 /* emit the arrays used for inputs and outputs - load/store intrinsics will
39 * be converted to reads/writes of these arrays
42 if (nir
->num_inputs
> 0) {
43 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
44 nir_setup_inputs(nir
);
47 if (nir
->num_outputs
> 0) {
48 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
49 nir_setup_outputs(nir
);
52 if (nir
->num_uniforms
> 0) {
53 nir_setup_uniforms(nir
);
56 nir_emit_system_values(nir
);
58 nir_globals
= ralloc_array(mem_ctx
, fs_reg
, nir
->reg_alloc
);
59 foreach_list_typed(nir_register
, reg
, node
, &nir
->registers
) {
60 unsigned array_elems
=
61 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
62 unsigned size
= array_elems
* reg
->num_components
;
63 nir_globals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
66 /* get the main function and emit it */
67 nir_foreach_overload(nir
, overload
) {
68 assert(strcmp(overload
->function
->name
, "main") == 0);
69 assert(overload
->impl
);
70 nir_emit_impl(overload
->impl
);
75 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
77 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
78 enum brw_reg_type type
= brw_type_for_base_type(var
->type
);
79 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
83 case MESA_SHADER_VERTEX
: {
84 /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
85 * stored in nir_variable::location.
87 * However, NIR's load_input intrinsics use a different index - an
88 * offset into a single contiguous array containing all inputs.
89 * This index corresponds to the nir_variable::driver_location field.
91 * So, we need to copy from fs_reg(ATTR, var->location) to
92 * offset(nir_inputs, var->data.driver_location).
94 unsigned components
= var
->type
->without_array()->components();
95 unsigned array_length
= var
->type
->is_array() ? var
->type
->length
: 1;
96 for (unsigned i
= 0; i
< array_length
; i
++) {
97 for (unsigned j
= 0; j
< components
; j
++) {
98 bld
.MOV(retype(offset(input
, bld
, components
* i
+ j
), type
),
99 offset(fs_reg(ATTR
, var
->data
.location
+ i
, type
), bld
, j
));
104 case MESA_SHADER_GEOMETRY
:
105 case MESA_SHADER_COMPUTE
:
106 unreachable("fs_visitor not used for these stages yet.");
108 case MESA_SHADER_FRAGMENT
:
109 if (var
->data
.location
== VARYING_SLOT_POS
) {
110 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
111 var
->data
.origin_upper_left
);
112 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
115 emit_general_interpolation(input
, var
->name
, var
->type
,
116 (glsl_interp_qualifier
) var
->data
.interpolation
,
117 var
->data
.location
, var
->data
.centroid
,
126 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
128 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
130 foreach_list_typed(nir_variable
, var
, node
, &shader
->outputs
) {
131 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
133 int vector_elements
=
134 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
135 : var
->type
->vector_elements
;
137 if (stage
== MESA_SHADER_VERTEX
) {
138 for (int i
= 0; i
< ALIGN(type_size(var
->type
), 4) / 4; i
++) {
139 int output
= var
->data
.location
+ i
;
140 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
141 this->output_components
[output
] = vector_elements
;
143 } else if (var
->data
.index
> 0) {
144 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
145 assert(var
->data
.index
== 1);
146 this->dual_src_output
= reg
;
147 this->do_dual_src
= true;
148 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
149 /* Writing gl_FragColor outputs to all color regions. */
150 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
151 this->outputs
[i
] = reg
;
152 this->output_components
[i
] = 4;
154 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
155 this->frag_depth
= reg
;
156 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
157 this->sample_mask
= reg
;
159 /* gl_FragData or a user-defined FS output */
160 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
161 var
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
163 /* General color output. */
164 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
165 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
166 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
167 this->output_components
[output
] = vector_elements
;
174 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
176 uniforms
= shader
->num_uniforms
;
177 num_direct_uniforms
= shader
->num_direct_uniforms
;
179 /* We split the uniform register file in half. The first half is
180 * entirely direct uniforms. The second half is indirect.
182 param_size
[0] = num_direct_uniforms
;
183 if (shader
->num_uniforms
> num_direct_uniforms
)
184 param_size
[num_direct_uniforms
] = shader
->num_uniforms
- num_direct_uniforms
;
186 if (dispatch_width
!= 8)
190 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
191 /* UBO's and atomics don't take up space in the uniform file */
192 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
195 if (strncmp(var
->name
, "gl_", 3) == 0)
196 nir_setup_builtin_uniform(var
);
198 nir_setup_uniform(var
);
201 /* prog_to_nir doesn't create uniform variables; set param up directly. */
202 for (unsigned p
= 0; p
< prog
->Parameters
->NumParameters
; p
++) {
203 for (unsigned int i
= 0; i
< 4; i
++) {
204 stage_prog_data
->param
[4 * p
+ i
] =
205 &prog
->Parameters
->ParameterValues
[p
][i
];
212 fs_visitor::nir_setup_uniform(nir_variable
*var
)
214 int namelen
= strlen(var
->name
);
216 /* The data for our (non-builtin) uniforms is stored in a series of
217 * gl_uniform_driver_storage structs for each subcomponent that
218 * glGetUniformLocation() could name. We know it's been set up in the
219 * same order we'd walk the type, so walk the list of storage and find
220 * anything with our name, or the prefix of a component that starts with
223 unsigned index
= var
->data
.driver_location
;
224 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
225 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
227 if (storage
->builtin
)
230 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
231 (storage
->name
[namelen
] != 0 &&
232 storage
->name
[namelen
] != '.' &&
233 storage
->name
[namelen
] != '[')) {
237 unsigned slots
= storage
->type
->component_slots();
238 if (storage
->array_elements
)
239 slots
*= storage
->array_elements
;
241 for (unsigned i
= 0; i
< slots
; i
++) {
242 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
246 /* Make sure we actually initialized the right amount of stuff here. */
247 assert(var
->data
.driver_location
+ var
->type
->component_slots() == index
);
251 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
253 const nir_state_slot
*const slots
= var
->state_slots
;
254 assert(var
->state_slots
!= NULL
);
256 unsigned uniform_index
= var
->data
.driver_location
;
257 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
258 /* This state reference has already been setup by ir_to_mesa, but we'll
259 * get the same index back here.
261 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
262 (gl_state_index
*)slots
[i
].tokens
);
264 /* Add each of the unique swizzles of the element as a parameter.
265 * This'll end up matching the expected layout of the
266 * array/matrix/structure we're trying to fill in.
269 for (unsigned int j
= 0; j
< 4; j
++) {
270 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
271 if (swiz
== last_swiz
)
275 stage_prog_data
->param
[uniform_index
++] =
276 &prog
->Parameters
->ParameterValues
[index
][swiz
];
282 emit_system_values_block(nir_block
*block
, void *void_visitor
)
284 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
287 nir_foreach_instr(block
, instr
) {
288 if (instr
->type
!= nir_instr_type_intrinsic
)
291 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
292 switch (intrin
->intrinsic
) {
293 case nir_intrinsic_load_vertex_id
:
294 unreachable("should be lowered by lower_vertex_id().");
296 case nir_intrinsic_load_vertex_id_zero_base
:
297 assert(v
->stage
== MESA_SHADER_VERTEX
);
298 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
299 if (reg
->file
== BAD_FILE
)
300 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
303 case nir_intrinsic_load_base_vertex
:
304 assert(v
->stage
== MESA_SHADER_VERTEX
);
305 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
306 if (reg
->file
== BAD_FILE
)
307 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
310 case nir_intrinsic_load_instance_id
:
311 assert(v
->stage
== MESA_SHADER_VERTEX
);
312 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
313 if (reg
->file
== BAD_FILE
)
314 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
317 case nir_intrinsic_load_sample_pos
:
318 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
319 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
320 if (reg
->file
== BAD_FILE
)
321 *reg
= *v
->emit_samplepos_setup();
324 case nir_intrinsic_load_sample_id
:
325 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
326 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
327 if (reg
->file
== BAD_FILE
)
328 *reg
= *v
->emit_sampleid_setup();
331 case nir_intrinsic_load_sample_mask_in
:
332 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
333 assert(v
->devinfo
->gen
>= 7);
334 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
335 if (reg
->file
== BAD_FILE
)
336 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
337 BRW_REGISTER_TYPE_D
));
349 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
351 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
352 nir_foreach_overload(shader
, overload
) {
353 assert(strcmp(overload
->function
->name
, "main") == 0);
354 assert(overload
->impl
);
355 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
360 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
362 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
363 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
364 unsigned array_elems
=
365 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
366 unsigned size
= array_elems
* reg
->num_components
;
367 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
370 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
373 nir_emit_cf_list(&impl
->body
);
377 fs_visitor::nir_emit_cf_list(exec_list
*list
)
379 exec_list_validate(list
);
380 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
381 switch (node
->type
) {
383 nir_emit_if(nir_cf_node_as_if(node
));
386 case nir_cf_node_loop
:
387 nir_emit_loop(nir_cf_node_as_loop(node
));
390 case nir_cf_node_block
:
391 nir_emit_block(nir_cf_node_as_block(node
));
395 unreachable("Invalid CFG node block");
401 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
403 /* first, put the condition into f0 */
404 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
405 retype(get_nir_src(if_stmt
->condition
),
406 BRW_REGISTER_TYPE_D
));
407 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
409 bld
.IF(BRW_PREDICATE_NORMAL
);
411 nir_emit_cf_list(&if_stmt
->then_list
);
413 /* note: if the else is empty, dead CF elimination will remove it */
414 bld
.emit(BRW_OPCODE_ELSE
);
416 nir_emit_cf_list(&if_stmt
->else_list
);
418 bld
.emit(BRW_OPCODE_ENDIF
);
420 try_replace_with_sel();
424 fs_visitor::nir_emit_loop(nir_loop
*loop
)
426 bld
.emit(BRW_OPCODE_DO
);
428 nir_emit_cf_list(&loop
->body
);
430 bld
.emit(BRW_OPCODE_WHILE
);
434 fs_visitor::nir_emit_block(nir_block
*block
)
436 nir_foreach_instr(block
, instr
) {
437 nir_emit_instr(instr
);
442 fs_visitor::nir_emit_instr(nir_instr
*instr
)
444 const fs_builder abld
= bld
.annotate(NULL
, instr
);
446 switch (instr
->type
) {
447 case nir_instr_type_alu
:
448 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
451 case nir_instr_type_intrinsic
:
452 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
455 case nir_instr_type_tex
:
456 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
459 case nir_instr_type_load_const
:
460 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
463 case nir_instr_type_ssa_undef
:
464 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
467 case nir_instr_type_jump
:
468 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
472 unreachable("unknown instruction type");
477 brw_type_for_nir_type(nir_alu_type type
)
480 case nir_type_unsigned
:
481 return BRW_REGISTER_TYPE_UD
;
484 return BRW_REGISTER_TYPE_D
;
486 return BRW_REGISTER_TYPE_F
;
488 unreachable("unknown type");
491 return BRW_REGISTER_TYPE_F
;
495 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
496 const fs_reg
&result
)
498 if (!instr
->src
[0].src
.is_ssa
||
499 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
502 nir_intrinsic_instr
*src0
=
503 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
505 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
508 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
509 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
512 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
513 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
516 fs_reg tmp
= vgrf(glsl_type::int_type
);
518 if (devinfo
->gen
>= 6) {
519 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
520 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
522 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
524 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
525 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
527 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
529 * This negation looks like it's safe in practice, because bits 0:4 will
530 * surely be TRIANGLES
533 if (value1
->f
[0] == -1.0f
) {
537 tmp
.type
= BRW_REGISTER_TYPE_W
;
538 tmp
.subreg_offset
= 2;
541 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
542 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
544 tmp
.type
= BRW_REGISTER_TYPE_D
;
545 tmp
.subreg_offset
= 0;
548 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
549 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
551 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
553 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
554 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
556 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
558 * This negation looks like it's safe in practice, because bits 0:4 will
559 * surely be TRIANGLES
562 if (value1
->f
[0] == -1.0f
) {
566 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
568 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
574 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
576 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
579 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
580 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
583 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
584 op
[i
] = get_nir_src(instr
->src
[i
].src
);
585 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
586 op
[i
].abs
= instr
->src
[i
].abs
;
587 op
[i
].negate
= instr
->src
[i
].negate
;
590 /* We get a bunch of mov's out of the from_ssa pass and they may still
591 * be vectorized. We'll handle them as a special-case. We'll also
592 * handle vecN here because it's basically the same thing.
600 fs_reg temp
= result
;
601 bool need_extra_copy
= false;
602 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
603 if (!instr
->src
[i
].src
.is_ssa
&&
604 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
605 need_extra_copy
= true;
606 temp
= bld
.vgrf(result
.type
, 4);
611 for (unsigned i
= 0; i
< 4; i
++) {
612 if (!(instr
->dest
.write_mask
& (1 << i
)))
615 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
616 inst
= bld
.MOV(offset(temp
, bld
, i
),
617 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
619 inst
= bld
.MOV(offset(temp
, bld
, i
),
620 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
622 inst
->saturate
= instr
->dest
.saturate
;
625 /* In this case the source and destination registers were the same,
626 * so we need to insert an extra set of moves in order to deal with
629 if (need_extra_copy
) {
630 for (unsigned i
= 0; i
< 4; i
++) {
631 if (!(instr
->dest
.write_mask
& (1 << i
)))
634 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
643 /* At this point, we have dealt with any instruction that operates on
644 * more than a single channel. Therefore, we can just adjust the source
645 * and destination registers for that channel and emit the instruction.
647 unsigned channel
= 0;
648 if (nir_op_infos
[instr
->op
].output_size
== 0) {
649 /* Since NIR is doing the scalarizing for us, we should only ever see
650 * vectorized operations with a single channel.
652 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
653 channel
= ffs(instr
->dest
.write_mask
) - 1;
655 result
= offset(result
, bld
, channel
);
658 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
659 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
660 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
666 inst
= bld
.MOV(result
, op
[0]);
667 inst
->saturate
= instr
->dest
.saturate
;
672 bld
.MOV(result
, op
[0]);
676 /* AND(val, 0x80000000) gives the sign bit.
678 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
681 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
683 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
684 op
[0].type
= BRW_REGISTER_TYPE_UD
;
685 result
.type
= BRW_REGISTER_TYPE_UD
;
686 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
688 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
689 inst
->predicate
= BRW_PREDICATE_NORMAL
;
690 if (instr
->dest
.saturate
) {
691 inst
= bld
.MOV(result
, result
);
692 inst
->saturate
= true;
698 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
699 * -> non-negative val generates 0x00000000.
700 * Predicated OR sets 1 if val is positive.
702 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
703 bld
.ASR(result
, op
[0], fs_reg(31));
704 inst
= bld
.OR(result
, result
, fs_reg(1));
705 inst
->predicate
= BRW_PREDICATE_NORMAL
;
709 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
710 inst
->saturate
= instr
->dest
.saturate
;
714 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
715 inst
->saturate
= instr
->dest
.saturate
;
719 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
720 inst
->saturate
= instr
->dest
.saturate
;
724 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
725 inst
->saturate
= instr
->dest
.saturate
;
729 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
730 inst
->saturate
= instr
->dest
.saturate
;
734 if (fs_key
->high_quality_derivatives
) {
735 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
737 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
739 inst
->saturate
= instr
->dest
.saturate
;
741 case nir_op_fddx_fine
:
742 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
743 inst
->saturate
= instr
->dest
.saturate
;
745 case nir_op_fddx_coarse
:
746 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
747 inst
->saturate
= instr
->dest
.saturate
;
750 if (fs_key
->high_quality_derivatives
) {
751 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
752 fs_reg(fs_key
->render_to_fbo
));
754 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
755 fs_reg(fs_key
->render_to_fbo
));
757 inst
->saturate
= instr
->dest
.saturate
;
759 case nir_op_fddy_fine
:
760 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
761 fs_reg(fs_key
->render_to_fbo
));
762 inst
->saturate
= instr
->dest
.saturate
;
764 case nir_op_fddy_coarse
:
765 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
766 fs_reg(fs_key
->render_to_fbo
));
767 inst
->saturate
= instr
->dest
.saturate
;
772 inst
= bld
.ADD(result
, op
[0], op
[1]);
773 inst
->saturate
= instr
->dest
.saturate
;
777 inst
= bld
.MUL(result
, op
[0], op
[1]);
778 inst
->saturate
= instr
->dest
.saturate
;
782 bld
.MUL(result
, op
[0], op
[1]);
785 case nir_op_imul_high
:
786 case nir_op_umul_high
: {
787 if (devinfo
->gen
>= 7)
788 no16("SIMD16 explicit accumulator operands unsupported\n");
790 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
792 fs_inst
*mul
= bld
.MUL(acc
, op
[0], op
[1]);
793 bld
.MACH(result
, op
[0], op
[1]);
795 /* Until Gen8, integer multiplies read 32-bits from one source, and
796 * 16-bits from the other, and relying on the MACH instruction to
797 * generate the high bits of the result.
799 * On Gen8, the multiply instruction does a full 32x32-bit multiply,
800 * but in order to do a 64x64-bit multiply we have to simulate the
801 * previous behavior and then use a MACH instruction.
803 * FINISHME: Don't use source modifiers on src1.
805 if (devinfo
->gen
>= 8) {
806 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
807 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
808 if (mul
->src
[1].type
== BRW_REGISTER_TYPE_D
) {
809 mul
->src
[1].type
= BRW_REGISTER_TYPE_W
;
810 mul
->src
[1].stride
= 2;
812 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
813 mul
->src
[1].stride
= 2;
821 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
824 case nir_op_uadd_carry
: {
825 if (devinfo
->gen
>= 7)
826 no16("SIMD16 explicit accumulator operands unsupported\n");
828 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
829 BRW_REGISTER_TYPE_UD
);
831 bld
.ADDC(bld
.null_reg_ud(), op
[0], op
[1]);
832 bld
.MOV(result
, fs_reg(acc
));
836 case nir_op_usub_borrow
: {
837 if (devinfo
->gen
>= 7)
838 no16("SIMD16 explicit accumulator operands unsupported\n");
840 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
841 BRW_REGISTER_TYPE_UD
);
843 bld
.SUBB(bld
.null_reg_ud(), op
[0], op
[1]);
844 bld
.MOV(result
, fs_reg(acc
));
849 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
855 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
861 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
866 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
871 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
875 if (devinfo
->gen
>= 8) {
876 resolve_source_modifiers(&op
[0]);
878 bld
.NOT(result
, op
[0]);
881 if (devinfo
->gen
>= 8) {
882 resolve_source_modifiers(&op
[0]);
883 resolve_source_modifiers(&op
[1]);
885 bld
.XOR(result
, op
[0], op
[1]);
888 if (devinfo
->gen
>= 8) {
889 resolve_source_modifiers(&op
[0]);
890 resolve_source_modifiers(&op
[1]);
892 bld
.OR(result
, op
[0], op
[1]);
895 if (devinfo
->gen
>= 8) {
896 resolve_source_modifiers(&op
[0]);
897 resolve_source_modifiers(&op
[1]);
899 bld
.AND(result
, op
[0], op
[1]);
911 case nir_op_ball_fequal2
:
912 case nir_op_ball_iequal2
:
913 case nir_op_ball_fequal3
:
914 case nir_op_ball_iequal3
:
915 case nir_op_ball_fequal4
:
916 case nir_op_ball_iequal4
:
917 case nir_op_bany_fnequal2
:
918 case nir_op_bany_inequal2
:
919 case nir_op_bany_fnequal3
:
920 case nir_op_bany_inequal3
:
921 case nir_op_bany_fnequal4
:
922 case nir_op_bany_inequal4
:
923 unreachable("Lowered by nir_lower_alu_reductions");
925 case nir_op_fnoise1_1
:
926 case nir_op_fnoise1_2
:
927 case nir_op_fnoise1_3
:
928 case nir_op_fnoise1_4
:
929 case nir_op_fnoise2_1
:
930 case nir_op_fnoise2_2
:
931 case nir_op_fnoise2_3
:
932 case nir_op_fnoise2_4
:
933 case nir_op_fnoise3_1
:
934 case nir_op_fnoise3_2
:
935 case nir_op_fnoise3_3
:
936 case nir_op_fnoise3_4
:
937 case nir_op_fnoise4_1
:
938 case nir_op_fnoise4_2
:
939 case nir_op_fnoise4_3
:
940 case nir_op_fnoise4_4
:
941 unreachable("not reached: should be handled by lower_noise");
944 unreachable("not reached: should be handled by ldexp_to_arith()");
947 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
948 inst
->saturate
= instr
->dest
.saturate
;
952 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
953 inst
->saturate
= instr
->dest
.saturate
;
957 bld
.AND(result
, op
[0], fs_reg(1));
960 bld
.AND(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0], fs_reg(0x3f800000u
));
964 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
967 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
971 inst
= bld
.RNDZ(result
, op
[0]);
972 inst
->saturate
= instr
->dest
.saturate
;
976 op
[0].negate
= !op
[0].negate
;
977 fs_reg temp
= vgrf(glsl_type::float_type
);
978 bld
.RNDD(temp
, op
[0]);
980 inst
= bld
.MOV(result
, temp
);
981 inst
->saturate
= instr
->dest
.saturate
;
985 inst
= bld
.RNDD(result
, op
[0]);
986 inst
->saturate
= instr
->dest
.saturate
;
989 inst
= bld
.FRC(result
, op
[0]);
990 inst
->saturate
= instr
->dest
.saturate
;
992 case nir_op_fround_even
:
993 inst
= bld
.RNDE(result
, op
[0]);
994 inst
->saturate
= instr
->dest
.saturate
;
1000 if (devinfo
->gen
>= 6) {
1001 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1002 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1004 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
1005 inst
= bld
.SEL(result
, op
[0], op
[1]);
1006 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1008 inst
->saturate
= instr
->dest
.saturate
;
1014 if (devinfo
->gen
>= 6) {
1015 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1016 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1018 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
1019 inst
= bld
.SEL(result
, op
[0], op
[1]);
1020 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1022 inst
->saturate
= instr
->dest
.saturate
;
1025 case nir_op_pack_snorm_2x16
:
1026 case nir_op_pack_snorm_4x8
:
1027 case nir_op_pack_unorm_2x16
:
1028 case nir_op_pack_unorm_4x8
:
1029 case nir_op_unpack_snorm_2x16
:
1030 case nir_op_unpack_snorm_4x8
:
1031 case nir_op_unpack_unorm_2x16
:
1032 case nir_op_unpack_unorm_4x8
:
1033 case nir_op_unpack_half_2x16
:
1034 case nir_op_pack_half_2x16
:
1035 unreachable("not reached: should be handled by lower_packing_builtins");
1037 case nir_op_unpack_half_2x16_split_x
:
1038 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1039 inst
->saturate
= instr
->dest
.saturate
;
1041 case nir_op_unpack_half_2x16_split_y
:
1042 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1043 inst
->saturate
= instr
->dest
.saturate
;
1047 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1048 inst
->saturate
= instr
->dest
.saturate
;
1051 case nir_op_bitfield_reverse
:
1052 bld
.BFREV(result
, op
[0]);
1055 case nir_op_bit_count
:
1056 bld
.CBIT(result
, op
[0]);
1059 case nir_op_ufind_msb
:
1060 case nir_op_ifind_msb
: {
1061 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1063 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1064 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1065 * subtract the result from 31 to convert the MSB count into an LSB count.
1068 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
1069 fs_reg
neg_result(result
);
1070 neg_result
.negate
= true;
1071 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
1072 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1076 case nir_op_find_lsb
:
1077 bld
.FBL(result
, op
[0]);
1080 case nir_op_ubitfield_extract
:
1081 case nir_op_ibitfield_extract
:
1082 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1085 bld
.BFI1(result
, op
[0], op
[1]);
1088 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1091 case nir_op_bitfield_insert
:
1092 unreachable("not reached: should be handled by "
1093 "lower_instructions::bitfield_insert_to_bfm_bfi");
1096 bld
.SHL(result
, op
[0], op
[1]);
1099 bld
.ASR(result
, op
[0], op
[1]);
1102 bld
.SHR(result
, op
[0], op
[1]);
1105 case nir_op_pack_half_2x16_split
:
1106 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1110 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1111 inst
->saturate
= instr
->dest
.saturate
;
1115 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1116 inst
->saturate
= instr
->dest
.saturate
;
1120 if (optimize_frontfacing_ternary(instr
, result
))
1123 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
1124 inst
= bld
.SEL(result
, op
[1], op
[2]);
1125 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1129 unreachable("unhandled instruction");
1132 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1133 * to sign extend the low bit to 0/~0
1135 if (devinfo
->gen
<= 5 &&
1136 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1137 fs_reg masked
= vgrf(glsl_type::int_type
);
1138 bld
.AND(masked
, result
, fs_reg(1));
1139 masked
.negate
= true;
1140 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1145 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1146 nir_load_const_instr
*instr
)
1148 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1150 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1151 bld
.MOV(offset(reg
, bld
, i
), fs_reg(instr
->value
.i
[i
]));
1153 nir_ssa_values
[instr
->def
.index
] = reg
;
1157 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1159 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1160 instr
->def
.num_components
);
1164 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1165 unsigned base_offset
, nir_src
*indirect
)
1168 if (nir_reg
->is_global
)
1169 reg
= v
->nir_globals
[nir_reg
->index
];
1171 reg
= v
->nir_locals
[nir_reg
->index
];
1173 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1175 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1177 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1178 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1179 fs_reg(multiplier
));
1186 fs_visitor::get_nir_src(nir_src src
)
1190 reg
= nir_ssa_values
[src
.ssa
->index
];
1192 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1196 /* to avoid floating-point denorm flushing problems, set the type by
1197 * default to D - instructions that need floating point semantics will set
1198 * this to F if they need to
1200 return retype(reg
, BRW_REGISTER_TYPE_D
);
1204 fs_visitor::get_nir_dest(nir_dest dest
)
1207 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1208 dest
.ssa
.num_components
);
1209 return nir_ssa_values
[dest
.ssa
.index
];
1212 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1217 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1220 for (unsigned i
= 0; i
< 4; i
++) {
1221 if (!((wr_mask
>> i
) & 1))
1224 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1225 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1226 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1227 if (new_inst
->src
[j
].file
== GRF
)
1228 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1235 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1238 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1239 dest
= get_nir_dest(instr
->dest
);
1241 bool has_indirect
= false;
1243 switch (instr
->intrinsic
) {
1244 case nir_intrinsic_discard
:
1245 case nir_intrinsic_discard_if
: {
1246 /* We track our discarded pixels in f0.1. By predicating on it, we can
1247 * update just the flag bits that aren't yet discarded. If there's no
1248 * condition, we emit a CMP of g0 != g0, so all currently executing
1249 * channels will get turned off.
1252 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1253 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1254 fs_reg(0), BRW_CONDITIONAL_Z
);
1256 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1257 BRW_REGISTER_TYPE_UW
));
1258 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1260 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1261 cmp
->flag_subreg
= 1;
1263 if (devinfo
->gen
>= 6) {
1264 emit_discard_jump();
1269 case nir_intrinsic_atomic_counter_inc
:
1270 case nir_intrinsic_atomic_counter_dec
:
1271 case nir_intrinsic_atomic_counter_read
: {
1272 unsigned surf_index
= prog_data
->binding_table
.abo_start
+
1273 (unsigned) instr
->const_index
[0];
1274 fs_reg offset
= fs_reg(get_nir_src(instr
->src
[0]));
1276 switch (instr
->intrinsic
) {
1277 case nir_intrinsic_atomic_counter_inc
:
1278 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
1279 fs_reg(), fs_reg());
1281 case nir_intrinsic_atomic_counter_dec
:
1282 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
1283 fs_reg(), fs_reg());
1285 case nir_intrinsic_atomic_counter_read
:
1286 emit_untyped_surface_read(surf_index
, dest
, offset
);
1289 unreachable("Unreachable");
1294 case nir_intrinsic_load_front_face
:
1295 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1296 *emit_frontfacing_interpolation());
1299 case nir_intrinsic_load_vertex_id
:
1300 unreachable("should be lowered by lower_vertex_id()");
1302 case nir_intrinsic_load_vertex_id_zero_base
: {
1303 fs_reg vertex_id
= nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
1304 assert(vertex_id
.file
!= BAD_FILE
);
1305 dest
.type
= vertex_id
.type
;
1306 bld
.MOV(dest
, vertex_id
);
1310 case nir_intrinsic_load_base_vertex
: {
1311 fs_reg base_vertex
= nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
1312 assert(base_vertex
.file
!= BAD_FILE
);
1313 dest
.type
= base_vertex
.type
;
1314 bld
.MOV(dest
, base_vertex
);
1318 case nir_intrinsic_load_instance_id
: {
1319 fs_reg instance_id
= nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
1320 assert(instance_id
.file
!= BAD_FILE
);
1321 dest
.type
= instance_id
.type
;
1322 bld
.MOV(dest
, instance_id
);
1326 case nir_intrinsic_load_sample_mask_in
: {
1327 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1328 assert(sample_mask_in
.file
!= BAD_FILE
);
1329 dest
.type
= sample_mask_in
.type
;
1330 bld
.MOV(dest
, sample_mask_in
);
1334 case nir_intrinsic_load_sample_pos
: {
1335 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1336 assert(sample_pos
.file
!= BAD_FILE
);
1337 dest
.type
= sample_pos
.type
;
1338 bld
.MOV(dest
, sample_pos
);
1339 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1343 case nir_intrinsic_load_sample_id
: {
1344 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1345 assert(sample_id
.file
!= BAD_FILE
);
1346 dest
.type
= sample_id
.type
;
1347 bld
.MOV(dest
, sample_id
);
1351 case nir_intrinsic_load_uniform_indirect
:
1352 has_indirect
= true;
1354 case nir_intrinsic_load_uniform
: {
1355 unsigned index
= instr
->const_index
[0];
1358 if (index
< num_direct_uniforms
) {
1359 uniform_reg
= fs_reg(UNIFORM
, 0);
1361 uniform_reg
= fs_reg(UNIFORM
, num_direct_uniforms
);
1362 index
-= num_direct_uniforms
;
1365 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1366 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, index
);
1368 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1372 dest
= offset(dest
, bld
, 1);
1377 case nir_intrinsic_load_ubo_indirect
:
1378 has_indirect
= true;
1380 case nir_intrinsic_load_ubo
: {
1381 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1385 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1388 /* The block index is not a constant. Evaluate the index expression
1389 * per-channel and add the base UBO index; we have to select a value
1390 * from any live channel.
1392 surf_index
= vgrf(glsl_type::uint_type
);
1393 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1394 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1395 bld
.emit_uniformize(surf_index
, surf_index
);
1397 /* Assume this may touch any UBO. It would be nice to provide
1398 * a tighter bound, but the array information is already lowered away.
1400 brw_mark_surface_used(prog_data
,
1401 stage_prog_data
->binding_table
.ubo_start
+
1402 shader_prog
->NumUniformBlocks
- 1);
1406 /* Turn the byte offset into a dword offset. */
1407 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1408 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1409 BRW_REGISTER_TYPE_D
),
1412 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1413 for (int i
= 0; i
< instr
->num_components
; i
++)
1414 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
1415 base_offset
, vec4_offset
+ i
);
1417 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1418 packed_consts
.type
= dest
.type
;
1420 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1421 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1422 surf_index
, const_offset_reg
);
1424 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1425 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1427 /* The std140 packing rules don't allow vectors to cross 16-byte
1428 * boundaries, and a reg is 32 bytes.
1430 assert(packed_consts
.subreg_offset
< 32);
1432 bld
.MOV(dest
, packed_consts
);
1433 dest
= offset(dest
, bld
, 1);
1439 case nir_intrinsic_load_input_indirect
:
1440 has_indirect
= true;
1442 case nir_intrinsic_load_input
: {
1444 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1445 fs_reg src
= offset(retype(nir_inputs
, dest
.type
), bld
,
1446 instr
->const_index
[0] + index
);
1448 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1452 dest
= offset(dest
, bld
, 1);
1457 /* Handle ARB_gpu_shader5 interpolation intrinsics
1459 * It's worth a quick word of explanation as to why we handle the full
1460 * variable-based interpolation intrinsic rather than a lowered version
1461 * with like we do for other inputs. We have to do that because the way
1462 * we set up inputs doesn't allow us to use the already setup inputs for
1463 * interpolation. At the beginning of the shader, we go through all of
1464 * the input variables and do the initial interpolation and put it in
1465 * the nir_inputs array based on its location as determined in
1466 * nir_lower_io. If the input isn't used, dead code cleans up and
1467 * everything works fine. However, when we get to the ARB_gpu_shader5
1468 * interpolation intrinsics, we need to reinterpolate the input
1469 * differently. If we used an intrinsic that just had an index it would
1470 * only give us the offset into the nir_inputs array. However, this is
1471 * useless because that value is post-interpolation and we need
1472 * pre-interpolation. In order to get the actual location of the bits
1473 * we get from the vertex fetching hardware, we need the variable.
1475 case nir_intrinsic_interp_var_at_centroid
:
1476 case nir_intrinsic_interp_var_at_sample
:
1477 case nir_intrinsic_interp_var_at_offset
: {
1478 assert(stage
== MESA_SHADER_FRAGMENT
);
1480 ((struct brw_wm_prog_data
*) prog_data
)->pulls_bary
= true;
1482 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1484 /* For most messages, we need one reg of ignored data; the hardware
1485 * requires mlen==1 even when there is no payload. in the per-slot
1486 * offset case, we'll replace this with the proper source data.
1488 fs_reg src
= vgrf(glsl_type::float_type
);
1489 int mlen
= 1; /* one reg unless overriden */
1492 switch (instr
->intrinsic
) {
1493 case nir_intrinsic_interp_var_at_centroid
:
1494 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1495 dst_xy
, src
, fs_reg(0u));
1498 case nir_intrinsic_interp_var_at_sample
: {
1499 /* XXX: We should probably handle non-constant sample id's */
1500 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1501 assert(const_sample
);
1502 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1503 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_xy
, src
,
1508 case nir_intrinsic_interp_var_at_offset
: {
1509 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1512 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1513 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1515 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_xy
, src
,
1516 fs_reg(off_x
| (off_y
<< 4)));
1518 src
= vgrf(glsl_type::ivec2_type
);
1519 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1520 BRW_REGISTER_TYPE_F
);
1521 for (int i
= 0; i
< 2; i
++) {
1522 fs_reg temp
= vgrf(glsl_type::float_type
);
1523 bld
.MUL(temp
, offset(offset_src
, bld
, i
), fs_reg(16.0f
));
1524 fs_reg itemp
= vgrf(glsl_type::int_type
);
1525 bld
.MOV(itemp
, temp
); /* float to int */
1527 /* Clamp the upper end of the range to +7/16.
1528 * ARB_gpu_shader5 requires that we support a maximum offset
1529 * of +0.5, which isn't representable in a S0.4 value -- if
1530 * we didn't clamp it, we'd end up with -8/16, which is the
1531 * opposite of what the shader author wanted.
1533 * This is legal due to ARB_gpu_shader5's quantization
1536 * "Not all values of <offset> may be supported; x and y
1537 * offsets may be rounded to fixed-point values with the
1538 * number of fraction bits given by the
1539 * implementation-dependent constant
1540 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1542 set_condmod(BRW_CONDITIONAL_L
,
1543 bld
.SEL(offset(src
, bld
, i
), itemp
, fs_reg(7)));
1546 mlen
= 2 * dispatch_width
/ 8;
1547 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_xy
, src
,
1554 unreachable("Invalid intrinsic");
1558 /* 2 floats per slot returned */
1559 inst
->regs_written
= 2 * dispatch_width
/ 8;
1560 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1561 INTERP_QUALIFIER_NOPERSPECTIVE
;
1563 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1564 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1565 src
.type
= dest
.type
;
1567 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1568 dest
= offset(dest
, bld
, 1);
1573 case nir_intrinsic_store_output_indirect
:
1574 has_indirect
= true;
1576 case nir_intrinsic_store_output
: {
1577 fs_reg src
= get_nir_src(instr
->src
[0]);
1579 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1580 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
1581 instr
->const_index
[0] + index
);
1583 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1585 bld
.MOV(new_dest
, src
);
1586 src
= offset(src
, bld
, 1);
1591 case nir_intrinsic_barrier
:
1596 unreachable("unknown intrinsic");
1601 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1603 unsigned sampler
= instr
->sampler_index
;
1604 fs_reg
sampler_reg(sampler
);
1606 /* FINISHME: We're failing to recompile our programs when the sampler is
1607 * updated. This only matters for the texture rectangle scale parameters
1608 * (pre-gen6, or gen6+ with GL_CLAMP).
1610 int texunit
= prog
->SamplerUnits
[sampler
];
1612 int gather_component
= instr
->component
;
1614 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1616 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1619 int lod_components
= 0;
1620 int UNUSED offset_components
= 0;
1622 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1624 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1625 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1626 switch (instr
->src
[i
].src_type
) {
1627 case nir_tex_src_bias
:
1628 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1630 case nir_tex_src_comparitor
:
1631 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1633 case nir_tex_src_coord
:
1634 switch (instr
->op
) {
1636 case nir_texop_txf_ms
:
1637 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1640 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1644 case nir_tex_src_ddx
:
1645 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1646 lod_components
= nir_tex_instr_src_size(instr
, i
);
1648 case nir_tex_src_ddy
:
1649 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1651 case nir_tex_src_lod
:
1652 switch (instr
->op
) {
1654 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1657 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1660 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1664 case nir_tex_src_ms_index
:
1665 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1667 case nir_tex_src_offset
:
1668 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1669 if (instr
->is_array
)
1670 offset_components
= instr
->coord_components
- 1;
1672 offset_components
= instr
->coord_components
;
1674 case nir_tex_src_projector
:
1675 unreachable("should be lowered");
1677 case nir_tex_src_sampler_offset
: {
1678 /* Figure out the highest possible sampler index and mark it as used */
1679 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1680 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
1681 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1683 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1685 brw_mark_surface_used(prog_data
, max_used
);
1687 /* Emit code to evaluate the actual indexing expression */
1688 sampler_reg
= vgrf(glsl_type::uint_type
);
1689 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
1690 bld
.emit_uniformize(sampler_reg
, sampler_reg
);
1695 unreachable("unknown texture source");
1699 if (instr
->op
== nir_texop_txf_ms
) {
1700 if (devinfo
->gen
>= 7 &&
1701 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1702 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1708 for (unsigned i
= 0; i
< 3; i
++) {
1709 if (instr
->const_offset
[i
] != 0) {
1710 assert(offset_components
== 0);
1711 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
1716 enum glsl_base_type dest_base_type
;
1717 switch (instr
->dest_type
) {
1718 case nir_type_float
:
1719 dest_base_type
= GLSL_TYPE_FLOAT
;
1722 dest_base_type
= GLSL_TYPE_INT
;
1724 case nir_type_unsigned
:
1725 dest_base_type
= GLSL_TYPE_UINT
;
1728 unreachable("bad type");
1731 const glsl_type
*dest_type
=
1732 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1735 ir_texture_opcode op
;
1736 switch (instr
->op
) {
1737 case nir_texop_lod
: op
= ir_lod
; break;
1738 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1739 case nir_texop_tex
: op
= ir_tex
; break;
1740 case nir_texop_tg4
: op
= ir_tg4
; break;
1741 case nir_texop_txb
: op
= ir_txb
; break;
1742 case nir_texop_txd
: op
= ir_txd
; break;
1743 case nir_texop_txf
: op
= ir_txf
; break;
1744 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1745 case nir_texop_txl
: op
= ir_txl
; break;
1746 case nir_texop_txs
: op
= ir_txs
; break;
1748 unreachable("unknown texture opcode");
1751 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1752 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1753 tex_offset
, mcs
, gather_component
,
1754 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1756 fs_reg dest
= get_nir_dest(instr
->dest
);
1757 dest
.type
= this->result
.type
;
1758 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1759 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
1760 dest
, this->result
),
1761 (1 << num_components
) - 1);
1765 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
1767 switch (instr
->type
) {
1768 case nir_jump_break
:
1769 bld
.emit(BRW_OPCODE_BREAK
);
1771 case nir_jump_continue
:
1772 bld
.emit(BRW_OPCODE_CONTINUE
);
1774 case nir_jump_return
:
1776 unreachable("unknown jump");