2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "main/shaderimage.h"
27 #include "brw_fs_surface_builder.h"
29 #include "brw_program.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
43 nir_emit_system_values();
45 /* get the main function and emit it */
46 nir_foreach_function(nir
, function
) {
47 assert(strcmp(function
->name
, "main") == 0);
48 assert(function
->impl
);
49 nir_emit_impl(function
->impl
);
54 fs_visitor::nir_setup_inputs()
56 if (stage
!= MESA_SHADER_FRAGMENT
)
59 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
61 nir_foreach_variable(var
, &nir
->inputs
) {
62 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
65 if (var
->data
.location
== VARYING_SLOT_POS
) {
66 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
67 var
->data
.origin_upper_left
);
68 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
70 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
71 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
72 reg
.type
= BRW_REGISTER_TYPE_D
;
73 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
74 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
75 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
76 reg
.type
= BRW_REGISTER_TYPE_D
;
77 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
79 int location
= var
->data
.location
;
80 emit_general_interpolation(&input
, var
->name
, var
->type
,
81 (glsl_interp_qualifier
) var
->data
.interpolation
,
82 &location
, var
->data
.centroid
,
89 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
90 const glsl_type
*type
,
93 if (type
->is_array() || type
->is_matrix()) {
94 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
95 const unsigned length
= glsl_get_length(type
);
97 for (unsigned i
= 0; i
< length
; i
++) {
98 nir_setup_single_output_varying(reg
, elem_type
, location
);
100 } else if (type
->is_record()) {
101 for (unsigned i
= 0; i
< type
->length
; i
++) {
102 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
103 nir_setup_single_output_varying(reg
, field_type
, location
);
106 assert(type
->is_scalar() || type
->is_vector());
107 this->outputs
[*location
] = *reg
;
108 this->output_components
[*location
] = type
->vector_elements
;
109 *reg
= offset(*reg
, bld
, 4);
115 fs_visitor::nir_setup_outputs()
117 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
119 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
121 nir_foreach_variable(var
, &nir
->outputs
) {
122 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
125 case MESA_SHADER_VERTEX
:
126 case MESA_SHADER_TESS_EVAL
:
127 case MESA_SHADER_GEOMETRY
: {
128 unsigned location
= var
->data
.location
;
129 nir_setup_single_output_varying(®
, var
->type
, &location
);
132 case MESA_SHADER_FRAGMENT
:
133 if (var
->data
.index
> 0) {
134 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
135 assert(var
->data
.index
== 1);
136 this->dual_src_output
= reg
;
137 this->do_dual_src
= true;
138 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
139 /* Writing gl_FragColor outputs to all color regions. */
140 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
141 this->outputs
[i
] = reg
;
142 this->output_components
[i
] = 4;
144 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
145 this->frag_depth
= reg
;
146 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
147 this->frag_stencil
= reg
;
148 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
149 this->sample_mask
= reg
;
151 int vector_elements
= var
->type
->without_array()->vector_elements
;
153 /* gl_FragData or a user-defined FS output */
154 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
155 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
157 /* General color output. */
158 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
159 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
160 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
161 this->output_components
[output
] = vector_elements
;
166 unreachable("unhandled shader stage");
172 fs_visitor::nir_setup_uniforms()
174 if (dispatch_width
!= 8)
177 uniforms
= nir
->num_uniforms
/ 4;
181 emit_system_values_block(nir_block
*block
, void *void_visitor
)
183 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
186 nir_foreach_instr(block
, instr
) {
187 if (instr
->type
!= nir_instr_type_intrinsic
)
190 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
191 switch (intrin
->intrinsic
) {
192 case nir_intrinsic_load_vertex_id
:
193 unreachable("should be lowered by lower_vertex_id().");
195 case nir_intrinsic_load_vertex_id_zero_base
:
196 assert(v
->stage
== MESA_SHADER_VERTEX
);
197 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
198 if (reg
->file
== BAD_FILE
)
199 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
202 case nir_intrinsic_load_base_vertex
:
203 assert(v
->stage
== MESA_SHADER_VERTEX
);
204 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
205 if (reg
->file
== BAD_FILE
)
206 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
209 case nir_intrinsic_load_instance_id
:
210 assert(v
->stage
== MESA_SHADER_VERTEX
);
211 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
212 if (reg
->file
== BAD_FILE
)
213 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
216 case nir_intrinsic_load_base_instance
:
217 assert(v
->stage
== MESA_SHADER_VERTEX
);
218 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
219 if (reg
->file
== BAD_FILE
)
220 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
223 case nir_intrinsic_load_draw_id
:
224 assert(v
->stage
== MESA_SHADER_VERTEX
);
225 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
226 if (reg
->file
== BAD_FILE
)
227 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
230 case nir_intrinsic_load_invocation_id
:
231 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
232 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
233 if (reg
->file
== BAD_FILE
) {
234 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
235 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
236 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
237 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
242 case nir_intrinsic_load_sample_pos
:
243 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
244 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
245 if (reg
->file
== BAD_FILE
)
246 *reg
= *v
->emit_samplepos_setup();
249 case nir_intrinsic_load_sample_id
:
250 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
251 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
252 if (reg
->file
== BAD_FILE
)
253 *reg
= *v
->emit_sampleid_setup();
256 case nir_intrinsic_load_sample_mask_in
:
257 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
258 assert(v
->devinfo
->gen
>= 7);
259 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
260 if (reg
->file
== BAD_FILE
)
261 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
262 BRW_REGISTER_TYPE_D
));
265 case nir_intrinsic_load_local_invocation_id
:
266 assert(v
->stage
== MESA_SHADER_COMPUTE
);
267 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
268 if (reg
->file
== BAD_FILE
)
269 *reg
= *v
->emit_cs_local_invocation_id_setup();
272 case nir_intrinsic_load_work_group_id
:
273 assert(v
->stage
== MESA_SHADER_COMPUTE
);
274 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
275 if (reg
->file
== BAD_FILE
)
276 *reg
= *v
->emit_cs_work_group_id_setup();
279 case nir_intrinsic_load_helper_invocation
:
280 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
281 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
282 if (reg
->file
== BAD_FILE
) {
283 const fs_builder abld
=
284 v
->bld
.annotate("gl_HelperInvocation", NULL
);
286 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
287 * pixel mask is in g1.7 of the thread payload.
289 * We move the per-channel pixel enable bit to the low bit of each
290 * channel by shifting the byte containing the pixel mask by the
291 * vector immediate 0x76543210UV.
293 * The region of <1,8,0> reads only 1 byte (the pixel masks for
294 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
295 * masks for 2 and 3) in SIMD16.
297 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
299 stride(byte_offset(retype(brw_vec1_grf(1, 0),
300 BRW_REGISTER_TYPE_UB
), 28),
302 brw_imm_uv(0x76543210));
304 /* A set bit in the pixel mask means the channel is enabled, but
305 * that is the opposite of gl_HelperInvocation so we need to invert
308 * The negate source-modifier bit of logical instructions on Gen8+
309 * performs 1's complement negation, so we can use that instead of
312 fs_reg inverted
= negate(shifted
);
313 if (v
->devinfo
->gen
< 8) {
314 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
315 abld
.NOT(inverted
, shifted
);
318 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
319 * with 1 and negating.
321 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
322 abld
.AND(anded
, inverted
, brw_imm_uw(1));
324 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
325 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
339 fs_visitor::nir_emit_system_values()
341 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
342 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
343 nir_system_values
[i
] = fs_reg();
346 nir_foreach_function(nir
, function
) {
347 assert(strcmp(function
->name
, "main") == 0);
348 assert(function
->impl
);
349 nir_foreach_block(function
->impl
, emit_system_values_block
, this);
354 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
356 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
357 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
358 nir_locals
[i
] = fs_reg();
361 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
362 unsigned array_elems
=
363 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
364 unsigned size
= array_elems
* reg
->num_components
;
365 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
368 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
371 nir_emit_cf_list(&impl
->body
);
375 fs_visitor::nir_emit_cf_list(exec_list
*list
)
377 exec_list_validate(list
);
378 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
379 switch (node
->type
) {
381 nir_emit_if(nir_cf_node_as_if(node
));
384 case nir_cf_node_loop
:
385 nir_emit_loop(nir_cf_node_as_loop(node
));
388 case nir_cf_node_block
:
389 nir_emit_block(nir_cf_node_as_block(node
));
393 unreachable("Invalid CFG node block");
399 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
401 /* first, put the condition into f0 */
402 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
403 retype(get_nir_src(if_stmt
->condition
),
404 BRW_REGISTER_TYPE_D
));
405 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
407 bld
.IF(BRW_PREDICATE_NORMAL
);
409 nir_emit_cf_list(&if_stmt
->then_list
);
411 /* note: if the else is empty, dead CF elimination will remove it */
412 bld
.emit(BRW_OPCODE_ELSE
);
414 nir_emit_cf_list(&if_stmt
->else_list
);
416 bld
.emit(BRW_OPCODE_ENDIF
);
420 fs_visitor::nir_emit_loop(nir_loop
*loop
)
422 bld
.emit(BRW_OPCODE_DO
);
424 nir_emit_cf_list(&loop
->body
);
426 bld
.emit(BRW_OPCODE_WHILE
);
430 fs_visitor::nir_emit_block(nir_block
*block
)
432 nir_foreach_instr(block
, instr
) {
433 nir_emit_instr(instr
);
438 fs_visitor::nir_emit_instr(nir_instr
*instr
)
440 const fs_builder abld
= bld
.annotate(NULL
, instr
);
442 switch (instr
->type
) {
443 case nir_instr_type_alu
:
444 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
447 case nir_instr_type_intrinsic
:
449 case MESA_SHADER_VERTEX
:
450 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
452 case MESA_SHADER_TESS_EVAL
:
453 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
455 case MESA_SHADER_GEOMETRY
:
456 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
458 case MESA_SHADER_FRAGMENT
:
459 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
461 case MESA_SHADER_COMPUTE
:
462 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 unreachable("unsupported shader stage");
469 case nir_instr_type_tex
:
470 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
473 case nir_instr_type_load_const
:
474 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
477 case nir_instr_type_ssa_undef
:
478 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
481 case nir_instr_type_jump
:
482 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
486 unreachable("unknown instruction type");
491 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
492 const fs_reg
&result
)
494 if (!instr
->src
[0].src
.is_ssa
||
495 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
498 nir_intrinsic_instr
*src0
=
499 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
501 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
504 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
505 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
508 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
509 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
512 fs_reg tmp
= vgrf(glsl_type::int_type
);
514 if (devinfo
->gen
>= 6) {
515 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
516 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
518 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
520 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
521 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
523 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
525 * This negation looks like it's safe in practice, because bits 0:4 will
526 * surely be TRIANGLES
529 if (value1
->f
[0] == -1.0f
) {
533 tmp
.type
= BRW_REGISTER_TYPE_W
;
534 tmp
.subreg_offset
= 2;
537 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
539 tmp
.type
= BRW_REGISTER_TYPE_D
;
540 tmp
.subreg_offset
= 0;
543 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
544 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
546 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
548 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
549 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
551 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
553 * This negation looks like it's safe in practice, because bits 0:4 will
554 * surely be TRIANGLES
557 if (value1
->f
[0] == -1.0f
) {
561 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
563 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
569 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
571 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
574 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
575 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
578 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
579 op
[i
] = get_nir_src(instr
->src
[i
].src
);
580 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
581 op
[i
].abs
= instr
->src
[i
].abs
;
582 op
[i
].negate
= instr
->src
[i
].negate
;
585 /* We get a bunch of mov's out of the from_ssa pass and they may still
586 * be vectorized. We'll handle them as a special-case. We'll also
587 * handle vecN here because it's basically the same thing.
595 fs_reg temp
= result
;
596 bool need_extra_copy
= false;
597 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
598 if (!instr
->src
[i
].src
.is_ssa
&&
599 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
600 need_extra_copy
= true;
601 temp
= bld
.vgrf(result
.type
, 4);
606 for (unsigned i
= 0; i
< 4; i
++) {
607 if (!(instr
->dest
.write_mask
& (1 << i
)))
610 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
611 inst
= bld
.MOV(offset(temp
, bld
, i
),
612 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
614 inst
= bld
.MOV(offset(temp
, bld
, i
),
615 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
617 inst
->saturate
= instr
->dest
.saturate
;
620 /* In this case the source and destination registers were the same,
621 * so we need to insert an extra set of moves in order to deal with
624 if (need_extra_copy
) {
625 for (unsigned i
= 0; i
< 4; i
++) {
626 if (!(instr
->dest
.write_mask
& (1 << i
)))
629 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
638 /* At this point, we have dealt with any instruction that operates on
639 * more than a single channel. Therefore, we can just adjust the source
640 * and destination registers for that channel and emit the instruction.
642 unsigned channel
= 0;
643 if (nir_op_infos
[instr
->op
].output_size
== 0) {
644 /* Since NIR is doing the scalarizing for us, we should only ever see
645 * vectorized operations with a single channel.
647 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
648 channel
= ffs(instr
->dest
.write_mask
) - 1;
650 result
= offset(result
, bld
, channel
);
653 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
654 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
655 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
661 inst
= bld
.MOV(result
, op
[0]);
662 inst
->saturate
= instr
->dest
.saturate
;
667 bld
.MOV(result
, op
[0]);
671 /* AND(val, 0x80000000) gives the sign bit.
673 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
676 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
678 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
679 op
[0].type
= BRW_REGISTER_TYPE_UD
;
680 result
.type
= BRW_REGISTER_TYPE_UD
;
681 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
683 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
684 inst
->predicate
= BRW_PREDICATE_NORMAL
;
685 if (instr
->dest
.saturate
) {
686 inst
= bld
.MOV(result
, result
);
687 inst
->saturate
= true;
693 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
694 * -> non-negative val generates 0x00000000.
695 * Predicated OR sets 1 if val is positive.
697 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
698 bld
.ASR(result
, op
[0], brw_imm_d(31));
699 inst
= bld
.OR(result
, result
, brw_imm_d(1));
700 inst
->predicate
= BRW_PREDICATE_NORMAL
;
704 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
705 inst
->saturate
= instr
->dest
.saturate
;
709 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
710 inst
->saturate
= instr
->dest
.saturate
;
714 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
715 inst
->saturate
= instr
->dest
.saturate
;
719 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
720 inst
->saturate
= instr
->dest
.saturate
;
724 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
725 inst
->saturate
= instr
->dest
.saturate
;
729 if (fs_key
->high_quality_derivatives
) {
730 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
732 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
734 inst
->saturate
= instr
->dest
.saturate
;
736 case nir_op_fddx_fine
:
737 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
738 inst
->saturate
= instr
->dest
.saturate
;
740 case nir_op_fddx_coarse
:
741 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
742 inst
->saturate
= instr
->dest
.saturate
;
745 if (fs_key
->high_quality_derivatives
) {
746 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
747 brw_imm_d(fs_key
->render_to_fbo
));
749 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
750 brw_imm_d(fs_key
->render_to_fbo
));
752 inst
->saturate
= instr
->dest
.saturate
;
754 case nir_op_fddy_fine
:
755 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
756 brw_imm_d(fs_key
->render_to_fbo
));
757 inst
->saturate
= instr
->dest
.saturate
;
759 case nir_op_fddy_coarse
:
760 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
761 brw_imm_d(fs_key
->render_to_fbo
));
762 inst
->saturate
= instr
->dest
.saturate
;
767 inst
= bld
.ADD(result
, op
[0], op
[1]);
768 inst
->saturate
= instr
->dest
.saturate
;
772 inst
= bld
.MUL(result
, op
[0], op
[1]);
773 inst
->saturate
= instr
->dest
.saturate
;
777 bld
.MUL(result
, op
[0], op
[1]);
780 case nir_op_imul_high
:
781 case nir_op_umul_high
:
782 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
787 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
790 case nir_op_uadd_carry
:
791 unreachable("Should have been lowered by carry_to_arith().");
793 case nir_op_usub_borrow
:
794 unreachable("Should have been lowered by borrow_to_arith().");
798 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
799 * appears that our hardware just does the right thing for signed
802 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
806 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
807 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
809 /* Math instructions don't support conditional mod */
810 inst
= bld
.MOV(bld
.null_reg_d(), result
);
811 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
813 /* Now, we need to determine if signs of the sources are different.
814 * When we XOR the sources, the top bit is 0 if they are the same and 1
815 * if they are different. We can then use a conditional modifier to
816 * turn that into a predicate. This leads us to an XOR.l instruction.
818 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
819 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
820 inst
->predicate
= BRW_PREDICATE_NORMAL
;
821 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
823 /* If the result of the initial remainder operation is non-zero and the
824 * two sources have different signs, add in a copy of op[1] to get the
825 * final integer modulus value.
827 inst
= bld
.ADD(result
, result
, op
[1]);
828 inst
->predicate
= BRW_PREDICATE_NORMAL
;
835 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
841 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
846 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
851 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
855 if (devinfo
->gen
>= 8) {
856 op
[0] = resolve_source_modifiers(op
[0]);
858 bld
.NOT(result
, op
[0]);
861 if (devinfo
->gen
>= 8) {
862 op
[0] = resolve_source_modifiers(op
[0]);
863 op
[1] = resolve_source_modifiers(op
[1]);
865 bld
.XOR(result
, op
[0], op
[1]);
868 if (devinfo
->gen
>= 8) {
869 op
[0] = resolve_source_modifiers(op
[0]);
870 op
[1] = resolve_source_modifiers(op
[1]);
872 bld
.OR(result
, op
[0], op
[1]);
875 if (devinfo
->gen
>= 8) {
876 op
[0] = resolve_source_modifiers(op
[0]);
877 op
[1] = resolve_source_modifiers(op
[1]);
879 bld
.AND(result
, op
[0], op
[1]);
885 case nir_op_ball_fequal2
:
886 case nir_op_ball_iequal2
:
887 case nir_op_ball_fequal3
:
888 case nir_op_ball_iequal3
:
889 case nir_op_ball_fequal4
:
890 case nir_op_ball_iequal4
:
891 case nir_op_bany_fnequal2
:
892 case nir_op_bany_inequal2
:
893 case nir_op_bany_fnequal3
:
894 case nir_op_bany_inequal3
:
895 case nir_op_bany_fnequal4
:
896 case nir_op_bany_inequal4
:
897 unreachable("Lowered by nir_lower_alu_reductions");
899 case nir_op_fnoise1_1
:
900 case nir_op_fnoise1_2
:
901 case nir_op_fnoise1_3
:
902 case nir_op_fnoise1_4
:
903 case nir_op_fnoise2_1
:
904 case nir_op_fnoise2_2
:
905 case nir_op_fnoise2_3
:
906 case nir_op_fnoise2_4
:
907 case nir_op_fnoise3_1
:
908 case nir_op_fnoise3_2
:
909 case nir_op_fnoise3_3
:
910 case nir_op_fnoise3_4
:
911 case nir_op_fnoise4_1
:
912 case nir_op_fnoise4_2
:
913 case nir_op_fnoise4_3
:
914 case nir_op_fnoise4_4
:
915 unreachable("not reached: should be handled by lower_noise");
918 unreachable("not reached: should be handled by ldexp_to_arith()");
921 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
922 inst
->saturate
= instr
->dest
.saturate
;
926 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
927 inst
->saturate
= instr
->dest
.saturate
;
932 bld
.MOV(result
, negate(op
[0]));
936 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
939 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
943 inst
= bld
.RNDZ(result
, op
[0]);
944 inst
->saturate
= instr
->dest
.saturate
;
948 op
[0].negate
= !op
[0].negate
;
949 fs_reg temp
= vgrf(glsl_type::float_type
);
950 bld
.RNDD(temp
, op
[0]);
952 inst
= bld
.MOV(result
, temp
);
953 inst
->saturate
= instr
->dest
.saturate
;
957 inst
= bld
.RNDD(result
, op
[0]);
958 inst
->saturate
= instr
->dest
.saturate
;
961 inst
= bld
.FRC(result
, op
[0]);
962 inst
->saturate
= instr
->dest
.saturate
;
964 case nir_op_fround_even
:
965 inst
= bld
.RNDE(result
, op
[0]);
966 inst
->saturate
= instr
->dest
.saturate
;
969 case nir_op_fquantize2f16
: {
970 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
972 /* The destination stride must be at least as big as the source stride. */
973 tmp
.type
= BRW_REGISTER_TYPE_W
;
976 bld
.emit(BRW_OPCODE_F32TO16
, tmp
, op
[0]);
977 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
, tmp
);
978 inst
->saturate
= instr
->dest
.saturate
;
985 if (devinfo
->gen
>= 6) {
986 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
987 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
989 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
990 inst
= bld
.SEL(result
, op
[0], op
[1]);
991 inst
->predicate
= BRW_PREDICATE_NORMAL
;
993 inst
->saturate
= instr
->dest
.saturate
;
999 if (devinfo
->gen
>= 6) {
1000 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1001 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1003 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
1004 inst
= bld
.SEL(result
, op
[0], op
[1]);
1005 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1007 inst
->saturate
= instr
->dest
.saturate
;
1010 case nir_op_pack_snorm_2x16
:
1011 case nir_op_pack_snorm_4x8
:
1012 case nir_op_pack_unorm_2x16
:
1013 case nir_op_pack_unorm_4x8
:
1014 case nir_op_unpack_snorm_2x16
:
1015 case nir_op_unpack_snorm_4x8
:
1016 case nir_op_unpack_unorm_2x16
:
1017 case nir_op_unpack_unorm_4x8
:
1018 case nir_op_unpack_half_2x16
:
1019 case nir_op_pack_half_2x16
:
1020 unreachable("not reached: should be handled by lower_packing_builtins");
1022 case nir_op_unpack_half_2x16_split_x
:
1023 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1024 inst
->saturate
= instr
->dest
.saturate
;
1026 case nir_op_unpack_half_2x16_split_y
:
1027 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1028 inst
->saturate
= instr
->dest
.saturate
;
1032 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1033 inst
->saturate
= instr
->dest
.saturate
;
1036 case nir_op_bitfield_reverse
:
1037 bld
.BFREV(result
, op
[0]);
1040 case nir_op_bit_count
:
1041 bld
.CBIT(result
, op
[0]);
1044 case nir_op_ufind_msb
:
1045 case nir_op_ifind_msb
: {
1046 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1048 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1049 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1050 * subtract the result from 31 to convert the MSB count into an LSB count.
1052 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1054 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1055 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1056 inst
->src
[0].negate
= true;
1060 case nir_op_find_lsb
:
1061 bld
.FBL(result
, op
[0]);
1064 case nir_op_ubitfield_extract
:
1065 case nir_op_ibitfield_extract
:
1066 unreachable("should have been lowered");
1069 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1072 bld
.BFI1(result
, op
[0], op
[1]);
1075 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1078 case nir_op_bitfield_insert
:
1079 unreachable("not reached: should have been lowered");
1082 bld
.SHL(result
, op
[0], op
[1]);
1085 bld
.ASR(result
, op
[0], op
[1]);
1088 bld
.SHR(result
, op
[0], op
[1]);
1091 case nir_op_pack_half_2x16_split
:
1092 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1096 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1097 inst
->saturate
= instr
->dest
.saturate
;
1101 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1102 inst
->saturate
= instr
->dest
.saturate
;
1106 if (optimize_frontfacing_ternary(instr
, result
))
1109 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1110 inst
= bld
.SEL(result
, op
[1], op
[2]);
1111 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1115 unreachable("unhandled instruction");
1118 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1119 * to sign extend the low bit to 0/~0
1121 if (devinfo
->gen
<= 5 &&
1122 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1123 fs_reg masked
= vgrf(glsl_type::int_type
);
1124 bld
.AND(masked
, result
, brw_imm_d(1));
1125 masked
.negate
= true;
1126 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1131 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1132 nir_load_const_instr
*instr
)
1134 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1136 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1137 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i
[i
]));
1139 nir_ssa_values
[instr
->def
.index
] = reg
;
1143 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1145 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1146 instr
->def
.num_components
);
1150 fs_visitor::get_nir_src(nir_src src
)
1154 reg
= nir_ssa_values
[src
.ssa
->index
];
1156 /* We don't handle indirects on locals */
1157 assert(src
.reg
.indirect
== NULL
);
1158 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1159 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1162 /* to avoid floating-point denorm flushing problems, set the type by
1163 * default to D - instructions that need floating point semantics will set
1164 * this to F if they need to
1166 return retype(reg
, BRW_REGISTER_TYPE_D
);
1170 fs_visitor::get_nir_dest(nir_dest dest
)
1173 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1174 dest
.ssa
.num_components
);
1175 return nir_ssa_values
[dest
.ssa
.index
];
1177 /* We don't handle indirects on locals */
1178 assert(dest
.reg
.indirect
== NULL
);
1179 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1180 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1185 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1187 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1188 BRW_REGISTER_TYPE_UD
);
1190 unsigned indirect_max
= 0;
1192 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1193 tail
= tail
->child
) {
1194 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1195 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1196 const unsigned size
= glsl_get_length(tail
->type
);
1197 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1198 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1199 image
= offset(image
, bld
, base
* element_size
);
1201 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1202 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1204 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1205 /* IVB hangs when trying to access an invalid surface index with
1206 * the dataport. According to the spec "if the index used to
1207 * select an individual element is negative or greater than or
1208 * equal to the size of the array, the results of the operation
1209 * are undefined but may not lead to termination" -- which is one
1210 * of the possible outcomes of the hang. Clamp the index to
1211 * prevent access outside of the array bounds.
1213 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1214 BRW_REGISTER_TYPE_UD
),
1215 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1217 bld
.MOV(tmp
, get_nir_src(deref_array
->indirect
));
1220 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1222 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1223 if (indirect
.file
== BAD_FILE
) {
1226 bld
.ADD(indirect
, indirect
, tmp
);
1231 if (indirect
.file
== BAD_FILE
) {
1234 /* Emit a pile of MOVs to load the uniform into a temporary. The
1235 * dead-code elimination pass will get rid of what we don't use.
1237 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1238 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1239 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1240 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1241 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1248 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1251 for (unsigned i
= 0; i
< 4; i
++) {
1252 if (!((wr_mask
>> i
) & 1))
1255 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1256 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1257 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1258 if (new_inst
->src
[j
].file
== VGRF
)
1259 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1266 * Get the matching channel register datatype for an image intrinsic of the
1267 * specified GLSL image type.
1270 get_image_base_type(const glsl_type
*type
)
1272 switch ((glsl_base_type
)type
->sampler_type
) {
1273 case GLSL_TYPE_UINT
:
1274 return BRW_REGISTER_TYPE_UD
;
1276 return BRW_REGISTER_TYPE_D
;
1277 case GLSL_TYPE_FLOAT
:
1278 return BRW_REGISTER_TYPE_F
;
1280 unreachable("Not reached.");
1285 * Get the appropriate atomic op for an image atomic intrinsic.
1288 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1291 case nir_intrinsic_image_atomic_add
:
1293 case nir_intrinsic_image_atomic_min
:
1294 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1295 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1296 case nir_intrinsic_image_atomic_max
:
1297 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1298 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1299 case nir_intrinsic_image_atomic_and
:
1301 case nir_intrinsic_image_atomic_or
:
1303 case nir_intrinsic_image_atomic_xor
:
1305 case nir_intrinsic_image_atomic_exchange
:
1307 case nir_intrinsic_image_atomic_comp_swap
:
1308 return BRW_AOP_CMPWR
;
1310 unreachable("Not reachable.");
1315 emit_pixel_interpolater_send(const fs_builder
&bld
,
1320 glsl_interp_qualifier interpolation
)
1326 if (src
.file
== BAD_FILE
) {
1328 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1332 mlen
= 2 * bld
.dispatch_width() / 8;
1335 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1337 /* 2 floats per slot returned */
1338 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1339 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1345 * Computes 1 << x, given a D/UD register containing some value x.
1348 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1350 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1352 fs_reg result
= bld
.vgrf(x
.type
, 1);
1353 fs_reg one
= bld
.vgrf(x
.type
, 1);
1355 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1356 bld
.SHL(result
, one
, x
);
1361 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1363 assert(stage
== MESA_SHADER_GEOMETRY
);
1365 struct brw_gs_prog_data
*gs_prog_data
=
1366 (struct brw_gs_prog_data
*) prog_data
;
1368 /* We can only do EndPrimitive() functionality when the control data
1369 * consists of cut bits. Fortunately, the only time it isn't is when the
1370 * output type is points, in which case EndPrimitive() is a no-op.
1372 if (gs_prog_data
->control_data_format
!=
1373 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1377 /* Cut bits use one bit per vertex. */
1378 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1380 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1381 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1383 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1384 * vertex n, 0 otherwise. So all we need to do here is mark bit
1385 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1386 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1387 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1389 * Note that if EndPrimitive() is called before emitting any vertices, this
1390 * will cause us to set bit 31 of the control_data_bits register to 1.
1391 * That's fine because:
1393 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1394 * output, so the hardware will ignore cut bit 31.
1396 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1397 * last vertex, so setting cut bit 31 has no effect (since the primitive
1398 * is automatically ended when the GS terminates).
1400 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1401 * control_data_bits register to 0 when the first vertex is emitted.
1404 const fs_builder abld
= bld
.annotate("end primitive");
1406 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1407 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1408 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1409 fs_reg mask
= intexp2(abld
, prev_count
);
1410 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1411 * attention to the lower 5 bits of its second source argument, so on this
1412 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1413 * ((vertex_count - 1) % 32).
1415 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1419 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1421 assert(stage
== MESA_SHADER_GEOMETRY
);
1422 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1424 struct brw_gs_prog_data
*gs_prog_data
=
1425 (struct brw_gs_prog_data
*) prog_data
;
1427 const fs_builder abld
= bld
.annotate("emit control data bits");
1428 const fs_builder fwa_bld
= bld
.exec_all();
1430 /* We use a single UD register to accumulate control data bits (32 bits
1431 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1434 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1435 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1436 * use the Channel Mask phase to enable/disable which DWord within that
1437 * group to write. (Remember, different SIMD8 channels may have emitted
1438 * different numbers of vertices, so we may need per-slot offsets.)
1440 * Channel masking presents an annoying problem: we may have to replicate
1441 * the data up to 4 times:
1443 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1445 * To avoid penalizing shaders that emit a small number of vertices, we
1446 * can avoid these sometimes: if the size of the control data header is
1447 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1448 * land in the same 128-bit group, so we can skip per-slot offsets.
1450 * Similarly, if the control data header is <= 32 bits, there is only one
1451 * DWord, so we can skip channel masks.
1453 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1455 fs_reg channel_mask
, per_slot_offset
;
1457 if (gs_compile
->control_data_header_size_bits
> 32) {
1458 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1459 channel_mask
= vgrf(glsl_type::uint_type
);
1462 if (gs_compile
->control_data_header_size_bits
> 128) {
1463 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1464 per_slot_offset
= vgrf(glsl_type::uint_type
);
1467 /* Figure out which DWord we're trying to write to using the formula:
1469 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1471 * Since bits_per_vertex is a power of two, and is known at compile
1472 * time, this can be optimized to:
1474 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1476 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1477 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1478 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1479 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1480 unsigned log2_bits_per_vertex
=
1481 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1482 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1484 if (per_slot_offset
.file
!= BAD_FILE
) {
1485 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1486 * the appropriate OWord within the control data header.
1488 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1491 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1492 * write to the appropriate DWORD within the OWORD.
1494 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1495 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1496 channel_mask
= intexp2(fwa_bld
, channel
);
1497 /* Then the channel masks need to be in bits 23:16. */
1498 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1501 /* Store the control data bits in the message payload and send it. */
1503 if (channel_mask
.file
!= BAD_FILE
)
1504 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1505 if (per_slot_offset
.file
!= BAD_FILE
)
1508 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1509 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1511 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1512 if (per_slot_offset
.file
!= BAD_FILE
)
1513 sources
[i
++] = per_slot_offset
;
1514 if (channel_mask
.file
!= BAD_FILE
)
1515 sources
[i
++] = channel_mask
;
1517 sources
[i
++] = this->control_data_bits
;
1520 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1521 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1523 /* We need to increment Global Offset by 256-bits to make room for
1524 * Broadwell's extra "Vertex Count" payload at the beginning of the
1525 * URB entry. Since this is an OWord message, Global Offset is counted
1526 * in 128-bit units, so we must set it to 2.
1528 if (gs_prog_data
->static_vertex_count
== -1)
1533 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1536 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1538 /* Note: we are calling this *before* increasing vertex_count, so
1539 * this->vertex_count == vertex_count - 1 in the formula above.
1542 /* Stream mode uses 2 bits per vertex */
1543 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1545 /* Must be a valid stream */
1546 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1548 /* Control data bits are initialized to 0 so we don't have to set any
1549 * bits when sending vertices to stream 0.
1554 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1556 /* reg::sid = stream_id */
1557 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1558 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1560 /* reg:shift_count = 2 * (vertex_count - 1) */
1561 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1562 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1564 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1565 * attention to the lower 5 bits of its second source argument, so on this
1566 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1567 * stream_id << ((2 * (vertex_count - 1)) % 32).
1569 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1570 abld
.SHL(mask
, sid
, shift_count
);
1571 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1575 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1578 assert(stage
== MESA_SHADER_GEOMETRY
);
1580 struct brw_gs_prog_data
*gs_prog_data
=
1581 (struct brw_gs_prog_data
*) prog_data
;
1583 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1584 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1586 /* Haswell and later hardware ignores the "Render Stream Select" bits
1587 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1588 * and instead sends all primitives down the pipeline for rasterization.
1589 * If the SOL stage is enabled, "Render Stream Select" is honored and
1590 * primitives bound to non-zero streams are discarded after stream output.
1592 * Since the only purpose of primives sent to non-zero streams is to
1593 * be recorded by transform feedback, we can simply discard all geometry
1594 * bound to these streams when transform feedback is disabled.
1596 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1599 /* If we're outputting 32 control data bits or less, then we can wait
1600 * until the shader is over to output them all. Otherwise we need to
1601 * output them as we go. Now is the time to do it, since we're about to
1602 * output the vertex_count'th vertex, so it's guaranteed that the
1603 * control data bits associated with the (vertex_count - 1)th vertex are
1606 if (gs_compile
->control_data_header_size_bits
> 32) {
1607 const fs_builder abld
=
1608 bld
.annotate("emit vertex: emit control data bits");
1610 /* Only emit control data bits if we've finished accumulating a batch
1611 * of 32 bits. This is the case when:
1613 * (vertex_count * bits_per_vertex) % 32 == 0
1615 * (in other words, when the last 5 bits of vertex_count *
1616 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1617 * integer n (which is always the case, since bits_per_vertex is
1618 * always 1 or 2), this is equivalent to requiring that the last 5-n
1619 * bits of vertex_count are 0:
1621 * vertex_count & (2^(5-n) - 1) == 0
1623 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1626 * vertex_count & (32 / bits_per_vertex - 1) == 0
1628 * TODO: If vertex_count is an immediate, we could do some of this math
1629 * at compile time...
1632 abld
.AND(bld
.null_reg_d(), vertex_count
,
1633 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1634 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1636 abld
.IF(BRW_PREDICATE_NORMAL
);
1637 /* If vertex_count is 0, then no control data bits have been
1638 * accumulated yet, so we can skip emitting them.
1640 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1641 BRW_CONDITIONAL_NEQ
);
1642 abld
.IF(BRW_PREDICATE_NORMAL
);
1643 emit_gs_control_data_bits(vertex_count
);
1644 abld
.emit(BRW_OPCODE_ENDIF
);
1646 /* Reset control_data_bits to 0 so we can start accumulating a new
1649 * Note: in the case where vertex_count == 0, this neutralizes the
1650 * effect of any call to EndPrimitive() that the shader may have
1651 * made before outputting its first vertex.
1653 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1654 inst
->force_writemask_all
= true;
1655 abld
.emit(BRW_OPCODE_ENDIF
);
1658 emit_urb_writes(vertex_count
);
1660 /* In stream mode we have to set control data bits for all vertices
1661 * unless we have disabled control data bits completely (which we do
1662 * do for GL_POINTS outputs that don't use streams).
1664 if (gs_compile
->control_data_header_size_bits
> 0 &&
1665 gs_prog_data
->control_data_format
==
1666 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1667 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1672 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1673 const nir_src
&vertex_src
,
1674 unsigned base_offset
,
1675 const nir_src
&offset_src
,
1676 unsigned num_components
)
1678 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1680 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1681 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1682 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1684 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1685 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1686 * gl_PointSize is available as a GS input, however, so it must be that.
1688 const bool is_point_size
= (base_offset
== 0);
1690 if (offset_const
!= NULL
&& vertex_const
!= NULL
&&
1691 4 * (base_offset
+ offset_const
->u
[0]) < push_reg_count
) {
1692 int imm_offset
= (base_offset
+ offset_const
->u
[0]) * 4 +
1693 vertex_const
->u
[0] * push_reg_count
;
1694 /* This input was pushed into registers. */
1695 if (is_point_size
) {
1696 /* gl_PointSize comes in .w */
1697 assert(imm_offset
== 0);
1698 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1700 for (unsigned i
= 0; i
< num_components
; i
++) {
1701 bld
.MOV(offset(dst
, bld
, i
),
1702 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1706 /* Resort to the pull model. Ensure the VUE handles are provided. */
1707 gs_prog_data
->base
.include_vue_handles
= true;
1709 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1713 /* The vertex index is constant; just select the proper URB handle. */
1715 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i
[0], 0),
1716 BRW_REGISTER_TYPE_UD
);
1718 /* The vertex index is non-constant. We need to use indirect
1719 * addressing to fetch the proper URB handle.
1721 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1722 * indicating that channel <n> should read the handle from
1723 * DWord <n>. We convert that to bytes by multiplying by 4.
1725 * Next, we convert the vertex index to bytes by multiplying
1726 * by 32 (shifting by 5), and add the two together. This is
1727 * the final indirect byte offset.
1729 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1730 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1731 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1732 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1733 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1735 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1736 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1737 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1738 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1739 /* Convert vertex_index to bytes (multiply by 32) */
1740 bld
.SHL(vertex_offset_bytes
,
1741 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1743 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1745 /* Use first_icp_handle as the base offset. There is one register
1746 * of URB handles per vertex, so inform the register allocator that
1747 * we might read up to nir->info.gs.vertices_in registers.
1749 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1750 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1751 fs_reg(icp_offset_bytes
),
1752 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1757 /* Constant indexing - use global offset. */
1758 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1759 inst
->offset
= base_offset
+ offset_const
->u
[0];
1760 inst
->base_mrf
= -1;
1762 inst
->regs_written
= num_components
;
1764 /* Indirect indexing - use per-slot offsets as well. */
1765 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
1766 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1767 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1769 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1770 inst
->offset
= base_offset
;
1771 inst
->base_mrf
= -1;
1773 inst
->regs_written
= num_components
;
1776 if (is_point_size
) {
1777 /* Read the whole VUE header (because of alignment) and read .w. */
1778 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1780 inst
->regs_written
= 4;
1781 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1787 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
1789 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
1790 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
1793 /* The only constant offset we should find is 0. brw_nir.c's
1794 * add_const_offset_to_base() will fold other constant offsets
1795 * into instr->const_index[0].
1797 assert(const_value
->u
[0] == 0);
1801 return get_nir_src(*offset_src
);
1805 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1806 nir_intrinsic_instr
*instr
)
1808 assert(stage
== MESA_SHADER_VERTEX
);
1811 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1812 dest
= get_nir_dest(instr
->dest
);
1814 switch (instr
->intrinsic
) {
1815 case nir_intrinsic_load_vertex_id
:
1816 unreachable("should be lowered by lower_vertex_id()");
1818 case nir_intrinsic_load_vertex_id_zero_base
:
1819 case nir_intrinsic_load_base_vertex
:
1820 case nir_intrinsic_load_instance_id
:
1821 case nir_intrinsic_load_base_instance
:
1822 case nir_intrinsic_load_draw_id
: {
1823 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1824 fs_reg val
= nir_system_values
[sv
];
1825 assert(val
.file
!= BAD_FILE
);
1826 dest
.type
= val
.type
;
1832 nir_emit_intrinsic(bld
, instr
);
1838 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
1839 nir_intrinsic_instr
*instr
)
1841 assert(stage
== MESA_SHADER_TESS_EVAL
);
1842 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
1845 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1846 dest
= get_nir_dest(instr
->dest
);
1848 switch (instr
->intrinsic
) {
1849 case nir_intrinsic_load_primitive_id
:
1850 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
1852 case nir_intrinsic_load_tess_coord
:
1853 /* gl_TessCoord is part of the payload in g1-3 */
1854 for (unsigned i
= 0; i
< 3; i
++) {
1855 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
1859 case nir_intrinsic_load_tess_level_outer
:
1860 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
1861 * appears as a push-model input. So, we can simply use the ATTR file
1862 * rather than issuing URB read messages. The data is stored in the
1863 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
1866 switch (tes_prog_data
->domain
) {
1867 case BRW_TESS_DOMAIN_QUAD
:
1868 for (unsigned i
= 0; i
< 4; i
++)
1869 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1871 case BRW_TESS_DOMAIN_TRI
:
1872 for (unsigned i
= 0; i
< 3; i
++)
1873 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1875 case BRW_TESS_DOMAIN_ISOLINE
:
1876 for (unsigned i
= 0; i
< 2; i
++)
1877 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1882 case nir_intrinsic_load_tess_level_inner
:
1883 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
1884 * appears as a push-model input. So, we can simply use the ATTR file
1885 * rather than issuing URB read messages.
1887 switch (tes_prog_data
->domain
) {
1888 case BRW_TESS_DOMAIN_QUAD
:
1889 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
1890 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
1892 case BRW_TESS_DOMAIN_TRI
:
1893 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
1895 case BRW_TESS_DOMAIN_ISOLINE
:
1896 /* ignore - value is undefined */
1901 case nir_intrinsic_load_input
:
1902 case nir_intrinsic_load_per_vertex_input
: {
1903 fs_reg indirect_offset
= get_indirect_offset(instr
);
1904 unsigned imm_offset
= instr
->const_index
[0];
1907 if (indirect_offset
.file
== BAD_FILE
) {
1908 /* Arbitrarily only push up to 32 vec4 slots worth of data,
1909 * which is 16 registers (since each holds 2 vec4 slots).
1911 const unsigned max_push_slots
= 32;
1912 if (imm_offset
< max_push_slots
) {
1913 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
1914 for (int i
= 0; i
< instr
->num_components
; i
++) {
1915 bld
.MOV(offset(dest
, bld
, i
),
1916 component(src
, 4 * (imm_offset
% 2) + i
));
1918 tes_prog_data
->base
.urb_read_length
=
1919 MAX2(tes_prog_data
->base
.urb_read_length
,
1920 DIV_ROUND_UP(imm_offset
+ 1, 2));
1922 /* Replicate the patch handle to all enabled channels */
1923 const fs_reg srcs
[] = {
1924 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
1926 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1927 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
1929 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
1931 inst
->offset
= imm_offset
;
1932 inst
->base_mrf
= -1;
1933 inst
->regs_written
= instr
->num_components
;
1936 /* Indirect indexing - use per-slot offsets as well. */
1937 const fs_reg srcs
[] = {
1938 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
1941 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1942 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1944 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
1946 inst
->offset
= imm_offset
;
1947 inst
->base_mrf
= -1;
1948 inst
->regs_written
= instr
->num_components
;
1953 nir_emit_intrinsic(bld
, instr
);
1959 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
1960 nir_intrinsic_instr
*instr
)
1962 assert(stage
== MESA_SHADER_GEOMETRY
);
1963 fs_reg indirect_offset
;
1966 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1967 dest
= get_nir_dest(instr
->dest
);
1969 switch (instr
->intrinsic
) {
1970 case nir_intrinsic_load_primitive_id
:
1971 assert(stage
== MESA_SHADER_GEOMETRY
);
1972 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
1973 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
1974 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
1977 case nir_intrinsic_load_input
:
1978 unreachable("load_input intrinsics are invalid for the GS stage");
1980 case nir_intrinsic_load_per_vertex_input
:
1981 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
1982 instr
->src
[1], instr
->num_components
);
1985 case nir_intrinsic_emit_vertex_with_counter
:
1986 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
1989 case nir_intrinsic_end_primitive_with_counter
:
1990 emit_gs_end_primitive(instr
->src
[0]);
1993 case nir_intrinsic_set_vertex_count
:
1994 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
1997 case nir_intrinsic_load_invocation_id
: {
1998 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
1999 assert(val
.file
!= BAD_FILE
);
2000 dest
.type
= val
.type
;
2006 nir_emit_intrinsic(bld
, instr
);
2012 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
2013 nir_intrinsic_instr
*instr
)
2015 assert(stage
== MESA_SHADER_FRAGMENT
);
2016 struct brw_wm_prog_data
*wm_prog_data
=
2017 (struct brw_wm_prog_data
*) prog_data
;
2020 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2021 dest
= get_nir_dest(instr
->dest
);
2023 switch (instr
->intrinsic
) {
2024 case nir_intrinsic_load_front_face
:
2025 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
2026 *emit_frontfacing_interpolation());
2029 case nir_intrinsic_load_sample_pos
: {
2030 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
2031 assert(sample_pos
.file
!= BAD_FILE
);
2032 dest
.type
= sample_pos
.type
;
2033 bld
.MOV(dest
, sample_pos
);
2034 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
2038 case nir_intrinsic_load_helper_invocation
:
2039 case nir_intrinsic_load_sample_mask_in
:
2040 case nir_intrinsic_load_sample_id
: {
2041 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2042 fs_reg val
= nir_system_values
[sv
];
2043 assert(val
.file
!= BAD_FILE
);
2044 dest
.type
= val
.type
;
2049 case nir_intrinsic_discard
:
2050 case nir_intrinsic_discard_if
: {
2051 /* We track our discarded pixels in f0.1. By predicating on it, we can
2052 * update just the flag bits that aren't yet discarded. If there's no
2053 * condition, we emit a CMP of g0 != g0, so all currently executing
2054 * channels will get turned off.
2057 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
2058 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
2059 brw_imm_d(0), BRW_CONDITIONAL_Z
);
2061 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2062 BRW_REGISTER_TYPE_UW
));
2063 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
2065 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2066 cmp
->flag_subreg
= 1;
2068 if (devinfo
->gen
>= 6) {
2069 emit_discard_jump();
2074 case nir_intrinsic_interp_var_at_centroid
:
2075 case nir_intrinsic_interp_var_at_sample
:
2076 case nir_intrinsic_interp_var_at_offset
: {
2077 /* Handle ARB_gpu_shader5 interpolation intrinsics
2079 * It's worth a quick word of explanation as to why we handle the full
2080 * variable-based interpolation intrinsic rather than a lowered version
2081 * with like we do for other inputs. We have to do that because the way
2082 * we set up inputs doesn't allow us to use the already setup inputs for
2083 * interpolation. At the beginning of the shader, we go through all of
2084 * the input variables and do the initial interpolation and put it in
2085 * the nir_inputs array based on its location as determined in
2086 * nir_lower_io. If the input isn't used, dead code cleans up and
2087 * everything works fine. However, when we get to the ARB_gpu_shader5
2088 * interpolation intrinsics, we need to reinterpolate the input
2089 * differently. If we used an intrinsic that just had an index it would
2090 * only give us the offset into the nir_inputs array. However, this is
2091 * useless because that value is post-interpolation and we need
2092 * pre-interpolation. In order to get the actual location of the bits
2093 * we get from the vertex fetching hardware, we need the variable.
2095 wm_prog_data
->pulls_bary
= true;
2097 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2098 const glsl_interp_qualifier interpolation
=
2099 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2101 switch (instr
->intrinsic
) {
2102 case nir_intrinsic_interp_var_at_centroid
:
2103 emit_pixel_interpolater_send(bld
,
2104 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2111 case nir_intrinsic_interp_var_at_sample
: {
2112 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
2115 unsigned msg_data
= const_sample
->i
[0] << 4;
2117 emit_pixel_interpolater_send(bld
,
2118 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2121 brw_imm_ud(msg_data
),
2124 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
2125 BRW_REGISTER_TYPE_UD
);
2127 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
2128 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2129 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2130 bld
.exec_all().group(1, 0)
2131 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2132 emit_pixel_interpolater_send(bld
,
2133 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2139 /* Make a loop that sends a message to the pixel interpolater
2140 * for the sample number in each live channel. If there are
2141 * multiple channels with the same sample number then these
2142 * will be handled simultaneously with a single interation of
2145 bld
.emit(BRW_OPCODE_DO
);
2147 /* Get the next live sample number into sample_id_reg */
2148 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2150 /* Set the flag register so that we can perform the send
2151 * message on all channels that have the same sample number
2153 bld
.CMP(bld
.null_reg_ud(),
2154 sample_src
, sample_id
,
2155 BRW_CONDITIONAL_EQ
);
2156 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2157 bld
.exec_all().group(1, 0)
2158 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2160 emit_pixel_interpolater_send(bld
,
2161 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2166 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
2168 /* Continue the loop if there are any live channels left */
2169 set_predicate_inv(BRW_PREDICATE_NORMAL
,
2171 bld
.emit(BRW_OPCODE_WHILE
));
2178 case nir_intrinsic_interp_var_at_offset
: {
2179 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2182 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
2183 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
2185 emit_pixel_interpolater_send(bld
,
2186 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
2189 brw_imm_ud(off_x
| (off_y
<< 4)),
2192 fs_reg src
= vgrf(glsl_type::ivec2_type
);
2193 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
2194 BRW_REGISTER_TYPE_F
);
2195 for (int i
= 0; i
< 2; i
++) {
2196 fs_reg temp
= vgrf(glsl_type::float_type
);
2197 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
2198 fs_reg itemp
= vgrf(glsl_type::int_type
);
2199 bld
.MOV(itemp
, temp
); /* float to int */
2201 /* Clamp the upper end of the range to +7/16.
2202 * ARB_gpu_shader5 requires that we support a maximum offset
2203 * of +0.5, which isn't representable in a S0.4 value -- if
2204 * we didn't clamp it, we'd end up with -8/16, which is the
2205 * opposite of what the shader author wanted.
2207 * This is legal due to ARB_gpu_shader5's quantization
2210 * "Not all values of <offset> may be supported; x and y
2211 * offsets may be rounded to fixed-point values with the
2212 * number of fraction bits given by the
2213 * implementation-dependent constant
2214 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2216 set_condmod(BRW_CONDITIONAL_L
,
2217 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2220 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2221 emit_pixel_interpolater_send(bld
,
2232 unreachable("Invalid intrinsic");
2235 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2236 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2237 src
.type
= dest
.type
;
2239 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2240 dest
= offset(dest
, bld
, 1);
2245 nir_emit_intrinsic(bld
, instr
);
2251 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2252 nir_intrinsic_instr
*instr
)
2254 assert(stage
== MESA_SHADER_COMPUTE
);
2255 struct brw_cs_prog_data
*cs_prog_data
=
2256 (struct brw_cs_prog_data
*) prog_data
;
2259 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2260 dest
= get_nir_dest(instr
->dest
);
2262 switch (instr
->intrinsic
) {
2263 case nir_intrinsic_barrier
:
2265 cs_prog_data
->uses_barrier
= true;
2268 case nir_intrinsic_load_local_invocation_id
:
2269 case nir_intrinsic_load_work_group_id
: {
2270 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2271 fs_reg val
= nir_system_values
[sv
];
2272 assert(val
.file
!= BAD_FILE
);
2273 dest
.type
= val
.type
;
2274 for (unsigned i
= 0; i
< 3; i
++)
2275 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2279 case nir_intrinsic_load_num_work_groups
: {
2280 const unsigned surface
=
2281 cs_prog_data
->binding_table
.work_groups_start
;
2283 cs_prog_data
->uses_num_work_groups
= true;
2285 fs_reg surf_index
= brw_imm_ud(surface
);
2286 brw_mark_surface_used(prog_data
, surface
);
2288 /* Read the 3 GLuint components of gl_NumWorkGroups */
2289 for (unsigned i
= 0; i
< 3; i
++) {
2290 fs_reg read_result
=
2291 emit_untyped_read(bld
, surf_index
,
2293 1 /* dims */, 1 /* size */,
2294 BRW_PREDICATE_NONE
);
2295 read_result
.type
= dest
.type
;
2296 bld
.MOV(dest
, read_result
);
2297 dest
= offset(dest
, bld
, 1);
2302 case nir_intrinsic_shared_atomic_add
:
2303 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
2305 case nir_intrinsic_shared_atomic_imin
:
2306 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
2308 case nir_intrinsic_shared_atomic_umin
:
2309 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
2311 case nir_intrinsic_shared_atomic_imax
:
2312 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
2314 case nir_intrinsic_shared_atomic_umax
:
2315 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
2317 case nir_intrinsic_shared_atomic_and
:
2318 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
2320 case nir_intrinsic_shared_atomic_or
:
2321 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
2323 case nir_intrinsic_shared_atomic_xor
:
2324 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
2326 case nir_intrinsic_shared_atomic_exchange
:
2327 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
2329 case nir_intrinsic_shared_atomic_comp_swap
:
2330 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2333 case nir_intrinsic_load_shared
: {
2334 assert(devinfo
->gen
>= 7);
2336 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2338 /* Get the offset to read from */
2340 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2342 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0]);
2344 offset_reg
= vgrf(glsl_type::uint_type
);
2346 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
2347 brw_imm_ud(instr
->const_index
[0]));
2350 /* Read the vector */
2351 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2353 instr
->num_components
,
2354 BRW_PREDICATE_NONE
);
2355 read_result
.type
= dest
.type
;
2356 for (int i
= 0; i
< instr
->num_components
; i
++)
2357 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2362 case nir_intrinsic_store_shared
: {
2363 assert(devinfo
->gen
>= 7);
2366 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2369 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2372 unsigned writemask
= instr
->const_index
[1];
2374 /* Combine groups of consecutive enabled channels in one write
2375 * message. We use ffs to find the first enabled channel and then ffs on
2376 * the bit-inverse, down-shifted writemask to determine the length of
2377 * the block of enabled bits.
2380 unsigned first_component
= ffs(writemask
) - 1;
2381 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2384 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2386 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0] +
2387 4 * first_component
);
2389 offset_reg
= vgrf(glsl_type::uint_type
);
2391 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
2392 brw_imm_ud(instr
->const_index
[0] + 4 * first_component
));
2395 emit_untyped_write(bld
, surf_index
, offset_reg
,
2396 offset(val_reg
, bld
, first_component
),
2397 1 /* dims */, length
,
2398 BRW_PREDICATE_NONE
);
2400 /* Clear the bits in the writemask that we just wrote, then try
2401 * again to see if more channels are left.
2403 writemask
&= (15 << (first_component
+ length
));
2410 nir_emit_intrinsic(bld
, instr
);
2416 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2419 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2420 dest
= get_nir_dest(instr
->dest
);
2422 switch (instr
->intrinsic
) {
2423 case nir_intrinsic_atomic_counter_inc
:
2424 case nir_intrinsic_atomic_counter_dec
:
2425 case nir_intrinsic_atomic_counter_read
: {
2426 using namespace surface_access
;
2428 /* Get the arguments of the atomic intrinsic. */
2429 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2430 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2431 instr
->const_index
[0]);
2434 /* Emit a surface read or atomic op. */
2435 switch (instr
->intrinsic
) {
2436 case nir_intrinsic_atomic_counter_read
:
2437 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2440 case nir_intrinsic_atomic_counter_inc
:
2441 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2442 fs_reg(), 1, 1, BRW_AOP_INC
);
2445 case nir_intrinsic_atomic_counter_dec
:
2446 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2447 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2451 unreachable("Unreachable");
2454 /* Assign the result. */
2455 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2457 /* Mark the surface as used. */
2458 brw_mark_surface_used(stage_prog_data
, surface
);
2462 case nir_intrinsic_image_load
:
2463 case nir_intrinsic_image_store
:
2464 case nir_intrinsic_image_atomic_add
:
2465 case nir_intrinsic_image_atomic_min
:
2466 case nir_intrinsic_image_atomic_max
:
2467 case nir_intrinsic_image_atomic_and
:
2468 case nir_intrinsic_image_atomic_or
:
2469 case nir_intrinsic_image_atomic_xor
:
2470 case nir_intrinsic_image_atomic_exchange
:
2471 case nir_intrinsic_image_atomic_comp_swap
: {
2472 using namespace image_access
;
2474 /* Get the referenced image variable and type. */
2475 const nir_variable
*var
= instr
->variables
[0]->var
;
2476 const glsl_type
*type
= var
->type
->without_array();
2477 const brw_reg_type base_type
= get_image_base_type(type
);
2479 /* Get some metadata from the image intrinsic. */
2480 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2481 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2482 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2483 const mesa_format format
=
2484 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
2485 _mesa_get_shader_image_format(var
->data
.image
.format
));
2487 /* Get the arguments of the image intrinsic. */
2488 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2489 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2490 BRW_REGISTER_TYPE_UD
);
2491 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2492 retype(get_nir_src(instr
->src
[2]), base_type
) :
2494 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2495 retype(get_nir_src(instr
->src
[3]), base_type
) :
2499 /* Emit an image load, store or atomic op. */
2500 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2501 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2503 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2504 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
2507 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2508 surf_dims
, arr_dims
, info
->dest_components
,
2509 get_image_atomic_op(instr
->intrinsic
, type
));
2511 /* Assign the result. */
2512 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2513 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2514 offset(tmp
, bld
, c
));
2518 case nir_intrinsic_memory_barrier_atomic_counter
:
2519 case nir_intrinsic_memory_barrier_buffer
:
2520 case nir_intrinsic_memory_barrier_image
:
2521 case nir_intrinsic_memory_barrier
: {
2522 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2523 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2528 case nir_intrinsic_group_memory_barrier
:
2529 case nir_intrinsic_memory_barrier_shared
:
2530 /* We treat these workgroup-level barriers as no-ops. This should be
2531 * safe at present and as long as:
2533 * - Memory access instructions are not subsequently reordered by the
2534 * compiler back-end.
2536 * - All threads from a given compute shader workgroup fit within a
2537 * single subslice and therefore talk to the same HDC shared unit
2538 * what supposedly guarantees ordering and coherency between threads
2539 * from the same workgroup. This may change in the future when we
2540 * start splitting workgroups across multiple subslices.
2542 * - The context is not in fault-and-stream mode, which could cause
2543 * memory transactions (including to SLM) prior to the barrier to be
2544 * replayed after the barrier if a pagefault occurs. This shouldn't
2545 * be a problem up to and including SKL because fault-and-stream is
2546 * not usable due to hardware issues, but that's likely to change in
2551 case nir_intrinsic_shader_clock
: {
2552 /* We cannot do anything if there is an event, so ignore it for now */
2553 fs_reg shader_clock
= get_timestamp(bld
);
2554 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2556 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2560 case nir_intrinsic_image_size
: {
2561 /* Get the referenced image variable and type. */
2562 const nir_variable
*var
= instr
->variables
[0]->var
;
2563 const glsl_type
*type
= var
->type
->without_array();
2565 /* Get the size of the image. */
2566 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2567 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
2569 /* For 1DArray image types, the array index is stored in the Z component.
2570 * Fix this by swizzling the Z component to the Y component.
2572 const bool is_1d_array_image
=
2573 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
2574 type
->sampler_array
;
2576 /* For CubeArray images, we should count the number of cubes instead
2577 * of the number of faces. Fix it by dividing the (Z component) by 6.
2579 const bool is_cube_array_image
=
2580 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2581 type
->sampler_array
;
2583 /* Copy all the components. */
2584 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2585 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
2586 if ((int)c
>= type
->coordinate_components()) {
2587 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2589 } else if (c
== 1 && is_1d_array_image
) {
2590 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2591 offset(size
, bld
, 2));
2592 } else if (c
== 2 && is_cube_array_image
) {
2593 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
2594 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2595 offset(size
, bld
, c
), brw_imm_d(6));
2597 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2598 offset(size
, bld
, c
));
2605 case nir_intrinsic_image_samples
:
2606 /* The driver does not support multi-sampled images. */
2607 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
2610 case nir_intrinsic_load_uniform
: {
2611 /* Offsets are in bytes but they should always be multiples of 4 */
2612 assert(instr
->const_index
[0] % 4 == 0);
2614 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
2616 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2618 /* Offsets are in bytes but they should always be multiples of 4 */
2619 assert(const_offset
->u
[0] % 4 == 0);
2620 src
.reg_offset
= const_offset
->u
[0] / 4;
2622 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2623 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2626 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
2627 BRW_REGISTER_TYPE_UD
);
2629 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
2630 * go past the end of the uniform. In order to keep the n'th
2631 * component from running past, we subtract off the size of all but
2632 * one component of the vector.
2634 assert(instr
->const_index
[1] >= instr
->num_components
* 4);
2635 unsigned read_size
= instr
->const_index
[1] -
2636 (instr
->num_components
- 1) * 4;
2638 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2639 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
2640 offset(dest
, bld
, j
), offset(src
, bld
, j
),
2641 indirect
, brw_imm_ud(read_size
));
2647 case nir_intrinsic_load_ubo
: {
2648 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
2652 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
2654 surf_index
= brw_imm_ud(index
);
2655 brw_mark_surface_used(prog_data
, index
);
2657 /* The block index is not a constant. Evaluate the index expression
2658 * per-channel and add the base UBO index; we have to select a value
2659 * from any live channel.
2661 surf_index
= vgrf(glsl_type::uint_type
);
2662 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2663 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
2664 surf_index
= bld
.emit_uniformize(surf_index
);
2666 /* Assume this may touch any UBO. It would be nice to provide
2667 * a tighter bound, but the array information is already lowered away.
2669 brw_mark_surface_used(prog_data
,
2670 stage_prog_data
->binding_table
.ubo_start
+
2671 nir
->info
.num_ubos
- 1);
2674 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2675 if (const_offset
== NULL
) {
2676 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
2677 BRW_REGISTER_TYPE_D
);
2679 for (int i
= 0; i
< instr
->num_components
; i
++)
2680 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
2681 base_offset
, i
* 4);
2683 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
2684 packed_consts
.type
= dest
.type
;
2686 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset
->u
[0] & ~15);
2687 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
2688 surf_index
, const_offset_reg
);
2690 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2691 packed_consts
.set_smear(const_offset
->u
[0] % 16 / 4 + i
);
2693 /* The std140 packing rules don't allow vectors to cross 16-byte
2694 * boundaries, and a reg is 32 bytes.
2696 assert(packed_consts
.subreg_offset
< 32);
2698 bld
.MOV(dest
, packed_consts
);
2699 dest
= offset(dest
, bld
, 1);
2705 case nir_intrinsic_load_ssbo
: {
2706 assert(devinfo
->gen
>= 7);
2708 nir_const_value
*const_uniform_block
=
2709 nir_src_as_const_value(instr
->src
[0]);
2712 if (const_uniform_block
) {
2713 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2714 const_uniform_block
->u
[0];
2715 surf_index
= brw_imm_ud(index
);
2716 brw_mark_surface_used(prog_data
, index
);
2718 surf_index
= vgrf(glsl_type::uint_type
);
2719 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2720 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2722 /* Assume this may touch any UBO. It would be nice to provide
2723 * a tighter bound, but the array information is already lowered away.
2725 brw_mark_surface_used(prog_data
,
2726 stage_prog_data
->binding_table
.ssbo_start
+
2727 nir
->info
.num_ssbos
- 1);
2731 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2733 offset_reg
= brw_imm_ud(const_offset
->u
[0]);
2735 offset_reg
= get_nir_src(instr
->src
[1]);
2738 /* Read the vector */
2739 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2741 instr
->num_components
,
2742 BRW_PREDICATE_NONE
);
2743 read_result
.type
= dest
.type
;
2744 for (int i
= 0; i
< instr
->num_components
; i
++)
2745 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2750 case nir_intrinsic_load_input
: {
2752 if (stage
== MESA_SHADER_VERTEX
) {
2753 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2755 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
2756 instr
->const_index
[0]);
2759 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2760 assert(const_offset
&& "Indirect input loads not allowed");
2761 src
= offset(src
, bld
, const_offset
->u
[0]);
2763 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2764 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2769 case nir_intrinsic_store_ssbo
: {
2770 assert(devinfo
->gen
>= 7);
2774 nir_const_value
*const_uniform_block
=
2775 nir_src_as_const_value(instr
->src
[1]);
2776 if (const_uniform_block
) {
2777 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2778 const_uniform_block
->u
[0];
2779 surf_index
= brw_imm_ud(index
);
2780 brw_mark_surface_used(prog_data
, index
);
2782 surf_index
= vgrf(glsl_type::uint_type
);
2783 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
2784 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2786 brw_mark_surface_used(prog_data
,
2787 stage_prog_data
->binding_table
.ssbo_start
+
2788 nir
->info
.num_ssbos
- 1);
2792 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2795 unsigned writemask
= instr
->const_index
[0];
2797 /* Combine groups of consecutive enabled channels in one write
2798 * message. We use ffs to find the first enabled channel and then ffs on
2799 * the bit-inverse, down-shifted writemask to determine the length of
2800 * the block of enabled bits.
2803 unsigned first_component
= ffs(writemask
) - 1;
2804 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2807 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
2809 offset_reg
= brw_imm_ud(const_offset
->u
[0] + 4 * first_component
);
2811 offset_reg
= vgrf(glsl_type::uint_type
);
2813 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
2814 brw_imm_ud(4 * first_component
));
2817 emit_untyped_write(bld
, surf_index
, offset_reg
,
2818 offset(val_reg
, bld
, first_component
),
2819 1 /* dims */, length
,
2820 BRW_PREDICATE_NONE
);
2822 /* Clear the bits in the writemask that we just wrote, then try
2823 * again to see if more channels are left.
2825 writemask
&= (15 << (first_component
+ length
));
2830 case nir_intrinsic_store_output
: {
2831 fs_reg src
= get_nir_src(instr
->src
[0]);
2832 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
2833 instr
->const_index
[0]);
2835 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2836 assert(const_offset
&& "Indirect output stores not allowed");
2837 new_dest
= offset(new_dest
, bld
, const_offset
->u
[0]);
2839 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2840 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
2845 case nir_intrinsic_ssbo_atomic_add
:
2846 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
2848 case nir_intrinsic_ssbo_atomic_imin
:
2849 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
2851 case nir_intrinsic_ssbo_atomic_umin
:
2852 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
2854 case nir_intrinsic_ssbo_atomic_imax
:
2855 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
2857 case nir_intrinsic_ssbo_atomic_umax
:
2858 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
2860 case nir_intrinsic_ssbo_atomic_and
:
2861 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
2863 case nir_intrinsic_ssbo_atomic_or
:
2864 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
2866 case nir_intrinsic_ssbo_atomic_xor
:
2867 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
2869 case nir_intrinsic_ssbo_atomic_exchange
:
2870 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
2872 case nir_intrinsic_ssbo_atomic_comp_swap
:
2873 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2876 case nir_intrinsic_get_buffer_size
: {
2877 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
2878 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
2879 int reg_width
= dispatch_width
/ 8;
2882 fs_reg source
= brw_imm_d(0);
2884 int mlen
= 1 * reg_width
;
2886 /* A resinfo's sampler message is used to get the buffer size.
2887 * The SIMD8's writeback message consists of four registers and
2888 * SIMD16's writeback message consists of 8 destination registers
2889 * (two per each component), although we are only interested on the
2890 * first component, where resinfo returns the buffer size for
2893 int regs_written
= 4 * mlen
;
2894 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
2895 BRW_REGISTER_TYPE_UD
);
2896 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
2897 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
2898 BRW_REGISTER_TYPE_UD
);
2899 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
2900 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
2901 src_payload
, brw_imm_ud(index
));
2902 inst
->header_size
= 0;
2904 inst
->regs_written
= regs_written
;
2906 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
2908 brw_mark_surface_used(prog_data
, index
);
2913 unreachable("unknown intrinsic");
2918 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
2919 int op
, nir_intrinsic_instr
*instr
)
2922 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2923 dest
= get_nir_dest(instr
->dest
);
2926 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
2927 if (const_surface
) {
2928 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
2929 const_surface
->u
[0];
2930 surface
= brw_imm_ud(surf_index
);
2931 brw_mark_surface_used(prog_data
, surf_index
);
2933 surface
= vgrf(glsl_type::uint_type
);
2934 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
2935 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2937 /* Assume this may touch any SSBO. This is the same we do for other
2938 * UBO/SSBO accesses with non-constant surface.
2940 brw_mark_surface_used(prog_data
,
2941 stage_prog_data
->binding_table
.ssbo_start
+
2942 nir
->info
.num_ssbos
- 1);
2945 fs_reg offset
= get_nir_src(instr
->src
[1]);
2946 fs_reg data1
= get_nir_src(instr
->src
[2]);
2948 if (op
== BRW_AOP_CMPWR
)
2949 data2
= get_nir_src(instr
->src
[3]);
2951 /* Emit the actual atomic operation operation */
2953 fs_reg atomic_result
=
2954 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2956 1 /* dims */, 1 /* rsize */,
2958 BRW_PREDICATE_NONE
);
2959 dest
.type
= atomic_result
.type
;
2960 bld
.MOV(dest
, atomic_result
);
2964 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
2965 int op
, nir_intrinsic_instr
*instr
)
2968 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2969 dest
= get_nir_dest(instr
->dest
);
2971 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
2972 fs_reg offset
= get_nir_src(instr
->src
[0]);
2973 fs_reg data1
= get_nir_src(instr
->src
[1]);
2975 if (op
== BRW_AOP_CMPWR
)
2976 data2
= get_nir_src(instr
->src
[2]);
2978 /* Emit the actual atomic operation operation */
2980 fs_reg atomic_result
=
2981 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2983 1 /* dims */, 1 /* rsize */,
2985 BRW_PREDICATE_NONE
);
2986 dest
.type
= atomic_result
.type
;
2987 bld
.MOV(dest
, atomic_result
);
2991 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
2993 unsigned texture
= instr
->texture_index
;
2994 unsigned sampler
= instr
->sampler_index
;
2995 fs_reg
texture_reg(brw_imm_ud(texture
));
2996 fs_reg
sampler_reg(brw_imm_ud(sampler
));
2998 int gather_component
= instr
->component
;
3000 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
3003 int lod_components
= 0;
3004 int UNUSED offset_components
= 0;
3006 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
3008 /* Our hardware requires a LOD for buffer textures */
3009 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
3012 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
3013 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
3014 switch (instr
->src
[i
].src_type
) {
3015 case nir_tex_src_bias
:
3016 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
3018 case nir_tex_src_comparitor
:
3019 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
3021 case nir_tex_src_coord
:
3022 switch (instr
->op
) {
3024 case nir_texop_txf_ms
:
3025 case nir_texop_samples_identical
:
3026 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
3029 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
3033 case nir_tex_src_ddx
:
3034 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
3035 lod_components
= nir_tex_instr_src_size(instr
, i
);
3037 case nir_tex_src_ddy
:
3038 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
3040 case nir_tex_src_lod
:
3041 switch (instr
->op
) {
3043 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
3046 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
3049 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
3053 case nir_tex_src_ms_index
:
3054 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
3056 case nir_tex_src_offset
:
3057 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
3058 if (instr
->is_array
)
3059 offset_components
= instr
->coord_components
- 1;
3061 offset_components
= instr
->coord_components
;
3063 case nir_tex_src_projector
:
3064 unreachable("should be lowered");
3066 case nir_tex_src_texture_offset
: {
3067 /* Figure out the highest possible texture index and mark it as used */
3068 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
3069 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
3070 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
3072 max_used
+= stage_prog_data
->binding_table
.texture_start
;
3074 brw_mark_surface_used(prog_data
, max_used
);
3076 /* Emit code to evaluate the actual indexing expression */
3077 texture_reg
= vgrf(glsl_type::uint_type
);
3078 bld
.ADD(texture_reg
, src
, brw_imm_ud(texture
));
3079 texture_reg
= bld
.emit_uniformize(texture_reg
);
3083 case nir_tex_src_sampler_offset
: {
3084 /* Emit code to evaluate the actual indexing expression */
3085 sampler_reg
= vgrf(glsl_type::uint_type
);
3086 bld
.ADD(sampler_reg
, src
, brw_imm_ud(sampler
));
3087 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
3092 unreachable("unknown texture source");
3096 if (instr
->op
== nir_texop_txf_ms
||
3097 instr
->op
== nir_texop_samples_identical
) {
3098 if (devinfo
->gen
>= 7 &&
3099 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
3100 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, texture_reg
);
3102 mcs
= brw_imm_ud(0u);
3106 for (unsigned i
= 0; i
< 3; i
++) {
3107 if (instr
->const_offset
[i
] != 0) {
3108 assert(offset_components
== 0);
3109 tex_offset
= brw_imm_ud(brw_texture_offset(instr
->const_offset
, 3));
3114 enum glsl_base_type dest_base_type
=
3115 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
3117 const glsl_type
*dest_type
=
3118 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
3121 ir_texture_opcode op
;
3122 switch (instr
->op
) {
3123 case nir_texop_lod
: op
= ir_lod
; break;
3124 case nir_texop_query_levels
: op
= ir_query_levels
; break;
3125 case nir_texop_tex
: op
= ir_tex
; break;
3126 case nir_texop_tg4
: op
= ir_tg4
; break;
3127 case nir_texop_txb
: op
= ir_txb
; break;
3128 case nir_texop_txd
: op
= ir_txd
; break;
3129 case nir_texop_txf
: op
= ir_txf
; break;
3130 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
3131 case nir_texop_txl
: op
= ir_txl
; break;
3132 case nir_texop_txs
: op
= ir_txs
; break;
3133 case nir_texop_texture_samples
: {
3134 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3135 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
3136 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
3137 texture_reg
, texture_reg
);
3139 inst
->header_size
= 1;
3140 inst
->base_mrf
= -1;
3143 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
3145 unreachable("unknown texture opcode");
3148 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
3149 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
3150 tex_offset
, mcs
, gather_component
,
3151 is_cube_array
, texture
, texture_reg
, sampler
, sampler_reg
);
3153 fs_reg dest
= get_nir_dest(instr
->dest
);
3154 dest
.type
= this->result
.type
;
3155 unsigned num_components
= nir_tex_instr_dest_size(instr
);
3156 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
3157 dest
, this->result
),
3158 (1 << num_components
) - 1);
3162 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
3164 switch (instr
->type
) {
3165 case nir_jump_break
:
3166 bld
.emit(BRW_OPCODE_BREAK
);
3168 case nir_jump_continue
:
3169 bld
.emit(BRW_OPCODE_CONTINUE
);
3171 case nir_jump_return
:
3173 unreachable("unknown jump");