2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "program/prog_to_nir.h"
34 fs_visitor::emit_nir_code()
36 nir_shader
*nir
= prog
->nir
;
38 /* emit the arrays used for inputs and outputs - load/store intrinsics will
39 * be converted to reads/writes of these arrays
42 if (nir
->num_inputs
> 0) {
43 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
44 nir_setup_inputs(nir
);
47 if (nir
->num_outputs
> 0) {
48 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
49 nir_setup_outputs(nir
);
52 if (nir
->num_uniforms
> 0) {
53 nir_setup_uniforms(nir
);
56 nir_emit_system_values(nir
);
58 /* get the main function and emit it */
59 nir_foreach_overload(nir
, overload
) {
60 assert(strcmp(overload
->function
->name
, "main") == 0);
61 assert(overload
->impl
);
62 nir_emit_impl(overload
->impl
);
67 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
69 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
70 enum brw_reg_type type
= brw_type_for_base_type(var
->type
);
71 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
75 case MESA_SHADER_VERTEX
: {
76 /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
77 * stored in nir_variable::location.
79 * However, NIR's load_input intrinsics use a different index - an
80 * offset into a single contiguous array containing all inputs.
81 * This index corresponds to the nir_variable::driver_location field.
83 * So, we need to copy from fs_reg(ATTR, var->location) to
84 * offset(nir_inputs, var->data.driver_location).
86 const glsl_type
*const t
= var
->type
->without_array();
87 const unsigned components
= t
->components();
88 const unsigned cols
= t
->matrix_columns
;
89 const unsigned elts
= t
->vector_elements
;
90 unsigned array_length
= var
->type
->is_array() ? var
->type
->length
: 1;
91 for (unsigned i
= 0; i
< array_length
; i
++) {
92 for (unsigned j
= 0; j
< cols
; j
++) {
93 for (unsigned k
= 0; k
< elts
; k
++) {
94 bld
.MOV(offset(retype(input
, type
), bld
,
95 components
* i
+ elts
* j
+ k
),
96 offset(fs_reg(ATTR
, var
->data
.location
+ i
, type
),
103 case MESA_SHADER_GEOMETRY
:
104 case MESA_SHADER_COMPUTE
:
105 case MESA_SHADER_TESS_CTRL
:
106 case MESA_SHADER_TESS_EVAL
:
107 unreachable("fs_visitor not used for these stages yet.");
109 case MESA_SHADER_FRAGMENT
:
110 if (var
->data
.location
== VARYING_SLOT_POS
) {
111 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
112 var
->data
.origin_upper_left
);
113 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
116 emit_general_interpolation(input
, var
->name
, var
->type
,
117 (glsl_interp_qualifier
) var
->data
.interpolation
,
118 var
->data
.location
, var
->data
.centroid
,
127 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
129 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
131 foreach_list_typed(nir_variable
, var
, node
, &shader
->outputs
) {
132 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
134 int vector_elements
=
135 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
136 : var
->type
->vector_elements
;
139 case MESA_SHADER_VERTEX
:
140 for (int i
= 0; i
< ALIGN(type_size(var
->type
), 4) / 4; i
++) {
141 int output
= var
->data
.location
+ i
;
142 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
143 this->output_components
[output
] = vector_elements
;
146 case MESA_SHADER_FRAGMENT
:
147 if (var
->data
.index
> 0) {
148 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
149 assert(var
->data
.index
== 1);
150 this->dual_src_output
= reg
;
151 this->do_dual_src
= true;
152 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
153 /* Writing gl_FragColor outputs to all color regions. */
154 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
155 this->outputs
[i
] = reg
;
156 this->output_components
[i
] = 4;
158 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
159 this->frag_depth
= reg
;
160 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
161 this->sample_mask
= reg
;
163 /* gl_FragData or a user-defined FS output */
164 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
165 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
167 /* General color output. */
168 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
169 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
170 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
171 this->output_components
[output
] = vector_elements
;
176 unreachable("unhandled shader stage");
182 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
184 uniforms
= shader
->num_uniforms
;
185 num_direct_uniforms
= shader
->num_direct_uniforms
;
187 /* We split the uniform register file in half. The first half is
188 * entirely direct uniforms. The second half is indirect.
190 param_size
[0] = num_direct_uniforms
;
191 if (shader
->num_uniforms
> num_direct_uniforms
)
192 param_size
[num_direct_uniforms
] = shader
->num_uniforms
- num_direct_uniforms
;
194 if (dispatch_width
!= 8)
198 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
199 /* UBO's and atomics don't take up space in the uniform file */
200 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
203 if (strncmp(var
->name
, "gl_", 3) == 0)
204 nir_setup_builtin_uniform(var
);
206 nir_setup_uniform(var
);
209 /* prog_to_nir doesn't create uniform variables; set param up directly. */
210 for (unsigned p
= 0; p
< prog
->Parameters
->NumParameters
; p
++) {
211 for (unsigned int i
= 0; i
< 4; i
++) {
212 stage_prog_data
->param
[4 * p
+ i
] =
213 &prog
->Parameters
->ParameterValues
[p
][i
];
220 fs_visitor::nir_setup_uniform(nir_variable
*var
)
222 int namelen
= strlen(var
->name
);
224 /* The data for our (non-builtin) uniforms is stored in a series of
225 * gl_uniform_driver_storage structs for each subcomponent that
226 * glGetUniformLocation() could name. We know it's been set up in the
227 * same order we'd walk the type, so walk the list of storage and find
228 * anything with our name, or the prefix of a component that starts with
231 unsigned index
= var
->data
.driver_location
;
232 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
233 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
235 if (storage
->builtin
)
238 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
239 (storage
->name
[namelen
] != 0 &&
240 storage
->name
[namelen
] != '.' &&
241 storage
->name
[namelen
] != '[')) {
245 unsigned slots
= storage
->type
->component_slots();
246 if (storage
->array_elements
)
247 slots
*= storage
->array_elements
;
249 for (unsigned i
= 0; i
< slots
; i
++) {
250 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
254 /* Make sure we actually initialized the right amount of stuff here. */
255 assert(var
->data
.driver_location
+ var
->type
->component_slots() == index
);
259 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
261 const nir_state_slot
*const slots
= var
->state_slots
;
262 assert(var
->state_slots
!= NULL
);
264 unsigned uniform_index
= var
->data
.driver_location
;
265 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
266 /* This state reference has already been setup by ir_to_mesa, but we'll
267 * get the same index back here.
269 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
270 (gl_state_index
*)slots
[i
].tokens
);
272 /* Add each of the unique swizzles of the element as a parameter.
273 * This'll end up matching the expected layout of the
274 * array/matrix/structure we're trying to fill in.
277 for (unsigned int j
= 0; j
< 4; j
++) {
278 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
279 if (swiz
== last_swiz
)
283 stage_prog_data
->param
[uniform_index
++] =
284 &prog
->Parameters
->ParameterValues
[index
][swiz
];
290 emit_system_values_block(nir_block
*block
, void *void_visitor
)
292 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
295 nir_foreach_instr(block
, instr
) {
296 if (instr
->type
!= nir_instr_type_intrinsic
)
299 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
300 switch (intrin
->intrinsic
) {
301 case nir_intrinsic_load_vertex_id
:
302 unreachable("should be lowered by lower_vertex_id().");
304 case nir_intrinsic_load_vertex_id_zero_base
:
305 assert(v
->stage
== MESA_SHADER_VERTEX
);
306 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
307 if (reg
->file
== BAD_FILE
)
308 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
311 case nir_intrinsic_load_base_vertex
:
312 assert(v
->stage
== MESA_SHADER_VERTEX
);
313 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
314 if (reg
->file
== BAD_FILE
)
315 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
318 case nir_intrinsic_load_instance_id
:
319 assert(v
->stage
== MESA_SHADER_VERTEX
);
320 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
321 if (reg
->file
== BAD_FILE
)
322 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
325 case nir_intrinsic_load_sample_pos
:
326 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
327 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
328 if (reg
->file
== BAD_FILE
)
329 *reg
= *v
->emit_samplepos_setup();
332 case nir_intrinsic_load_sample_id
:
333 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
334 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
335 if (reg
->file
== BAD_FILE
)
336 *reg
= *v
->emit_sampleid_setup();
339 case nir_intrinsic_load_sample_mask_in
:
340 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
341 assert(v
->devinfo
->gen
>= 7);
342 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
343 if (reg
->file
== BAD_FILE
)
344 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
345 BRW_REGISTER_TYPE_D
));
357 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
359 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
360 nir_foreach_overload(shader
, overload
) {
361 assert(strcmp(overload
->function
->name
, "main") == 0);
362 assert(overload
->impl
);
363 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
368 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
370 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
371 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
372 unsigned array_elems
=
373 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
374 unsigned size
= array_elems
* reg
->num_components
;
375 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
378 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
381 nir_emit_cf_list(&impl
->body
);
385 fs_visitor::nir_emit_cf_list(exec_list
*list
)
387 exec_list_validate(list
);
388 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
389 switch (node
->type
) {
391 nir_emit_if(nir_cf_node_as_if(node
));
394 case nir_cf_node_loop
:
395 nir_emit_loop(nir_cf_node_as_loop(node
));
398 case nir_cf_node_block
:
399 nir_emit_block(nir_cf_node_as_block(node
));
403 unreachable("Invalid CFG node block");
409 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
411 /* first, put the condition into f0 */
412 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
413 retype(get_nir_src(if_stmt
->condition
),
414 BRW_REGISTER_TYPE_D
));
415 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
417 bld
.IF(BRW_PREDICATE_NORMAL
);
419 nir_emit_cf_list(&if_stmt
->then_list
);
421 /* note: if the else is empty, dead CF elimination will remove it */
422 bld
.emit(BRW_OPCODE_ELSE
);
424 nir_emit_cf_list(&if_stmt
->else_list
);
426 bld
.emit(BRW_OPCODE_ENDIF
);
428 try_replace_with_sel();
432 fs_visitor::nir_emit_loop(nir_loop
*loop
)
434 bld
.emit(BRW_OPCODE_DO
);
436 nir_emit_cf_list(&loop
->body
);
438 bld
.emit(BRW_OPCODE_WHILE
);
442 fs_visitor::nir_emit_block(nir_block
*block
)
444 nir_foreach_instr(block
, instr
) {
445 nir_emit_instr(instr
);
450 fs_visitor::nir_emit_instr(nir_instr
*instr
)
452 const fs_builder abld
= bld
.annotate(NULL
, instr
);
454 switch (instr
->type
) {
455 case nir_instr_type_alu
:
456 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
459 case nir_instr_type_intrinsic
:
460 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
463 case nir_instr_type_tex
:
464 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
467 case nir_instr_type_load_const
:
468 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
471 case nir_instr_type_ssa_undef
:
472 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
475 case nir_instr_type_jump
:
476 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
480 unreachable("unknown instruction type");
485 brw_type_for_nir_type(nir_alu_type type
)
488 case nir_type_unsigned
:
489 return BRW_REGISTER_TYPE_UD
;
492 return BRW_REGISTER_TYPE_D
;
494 return BRW_REGISTER_TYPE_F
;
496 unreachable("unknown type");
499 return BRW_REGISTER_TYPE_F
;
503 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
504 const fs_reg
&result
)
506 if (!instr
->src
[0].src
.is_ssa
||
507 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
510 nir_intrinsic_instr
*src0
=
511 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
513 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
516 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
517 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
520 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
521 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
524 fs_reg tmp
= vgrf(glsl_type::int_type
);
526 if (devinfo
->gen
>= 6) {
527 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
528 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
530 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
532 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
533 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
535 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
537 * This negation looks like it's safe in practice, because bits 0:4 will
538 * surely be TRIANGLES
541 if (value1
->f
[0] == -1.0f
) {
545 tmp
.type
= BRW_REGISTER_TYPE_W
;
546 tmp
.subreg_offset
= 2;
549 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
550 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
552 tmp
.type
= BRW_REGISTER_TYPE_D
;
553 tmp
.subreg_offset
= 0;
556 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
557 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
559 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
561 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
562 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
564 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
566 * This negation looks like it's safe in practice, because bits 0:4 will
567 * surely be TRIANGLES
570 if (value1
->f
[0] == -1.0f
) {
574 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
576 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
582 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
584 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
587 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
588 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
591 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
592 op
[i
] = get_nir_src(instr
->src
[i
].src
);
593 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
594 op
[i
].abs
= instr
->src
[i
].abs
;
595 op
[i
].negate
= instr
->src
[i
].negate
;
598 /* We get a bunch of mov's out of the from_ssa pass and they may still
599 * be vectorized. We'll handle them as a special-case. We'll also
600 * handle vecN here because it's basically the same thing.
608 fs_reg temp
= result
;
609 bool need_extra_copy
= false;
610 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
611 if (!instr
->src
[i
].src
.is_ssa
&&
612 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
613 need_extra_copy
= true;
614 temp
= bld
.vgrf(result
.type
, 4);
619 for (unsigned i
= 0; i
< 4; i
++) {
620 if (!(instr
->dest
.write_mask
& (1 << i
)))
623 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
624 inst
= bld
.MOV(offset(temp
, bld
, i
),
625 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
627 inst
= bld
.MOV(offset(temp
, bld
, i
),
628 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
630 inst
->saturate
= instr
->dest
.saturate
;
633 /* In this case the source and destination registers were the same,
634 * so we need to insert an extra set of moves in order to deal with
637 if (need_extra_copy
) {
638 for (unsigned i
= 0; i
< 4; i
++) {
639 if (!(instr
->dest
.write_mask
& (1 << i
)))
642 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
651 /* At this point, we have dealt with any instruction that operates on
652 * more than a single channel. Therefore, we can just adjust the source
653 * and destination registers for that channel and emit the instruction.
655 unsigned channel
= 0;
656 if (nir_op_infos
[instr
->op
].output_size
== 0) {
657 /* Since NIR is doing the scalarizing for us, we should only ever see
658 * vectorized operations with a single channel.
660 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
661 channel
= ffs(instr
->dest
.write_mask
) - 1;
663 result
= offset(result
, bld
, channel
);
666 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
667 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
668 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
674 inst
= bld
.MOV(result
, op
[0]);
675 inst
->saturate
= instr
->dest
.saturate
;
680 bld
.MOV(result
, op
[0]);
684 /* AND(val, 0x80000000) gives the sign bit.
686 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
689 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
691 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
692 op
[0].type
= BRW_REGISTER_TYPE_UD
;
693 result
.type
= BRW_REGISTER_TYPE_UD
;
694 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
696 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
697 inst
->predicate
= BRW_PREDICATE_NORMAL
;
698 if (instr
->dest
.saturate
) {
699 inst
= bld
.MOV(result
, result
);
700 inst
->saturate
= true;
706 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
707 * -> non-negative val generates 0x00000000.
708 * Predicated OR sets 1 if val is positive.
710 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
711 bld
.ASR(result
, op
[0], fs_reg(31));
712 inst
= bld
.OR(result
, result
, fs_reg(1));
713 inst
->predicate
= BRW_PREDICATE_NORMAL
;
717 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
718 inst
->saturate
= instr
->dest
.saturate
;
722 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
723 inst
->saturate
= instr
->dest
.saturate
;
727 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
728 inst
->saturate
= instr
->dest
.saturate
;
732 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
733 inst
->saturate
= instr
->dest
.saturate
;
737 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
738 inst
->saturate
= instr
->dest
.saturate
;
742 if (fs_key
->high_quality_derivatives
) {
743 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
745 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
747 inst
->saturate
= instr
->dest
.saturate
;
749 case nir_op_fddx_fine
:
750 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
751 inst
->saturate
= instr
->dest
.saturate
;
753 case nir_op_fddx_coarse
:
754 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
755 inst
->saturate
= instr
->dest
.saturate
;
758 if (fs_key
->high_quality_derivatives
) {
759 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
760 fs_reg(fs_key
->render_to_fbo
));
762 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
763 fs_reg(fs_key
->render_to_fbo
));
765 inst
->saturate
= instr
->dest
.saturate
;
767 case nir_op_fddy_fine
:
768 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
769 fs_reg(fs_key
->render_to_fbo
));
770 inst
->saturate
= instr
->dest
.saturate
;
772 case nir_op_fddy_coarse
:
773 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
774 fs_reg(fs_key
->render_to_fbo
));
775 inst
->saturate
= instr
->dest
.saturate
;
780 inst
= bld
.ADD(result
, op
[0], op
[1]);
781 inst
->saturate
= instr
->dest
.saturate
;
785 inst
= bld
.MUL(result
, op
[0], op
[1]);
786 inst
->saturate
= instr
->dest
.saturate
;
790 bld
.MUL(result
, op
[0], op
[1]);
793 case nir_op_imul_high
:
794 case nir_op_umul_high
: {
795 if (devinfo
->gen
>= 7)
796 no16("SIMD16 explicit accumulator operands unsupported\n");
798 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
800 fs_inst
*mul
= bld
.MUL(acc
, op
[0], op
[1]);
801 bld
.MACH(result
, op
[0], op
[1]);
803 /* Until Gen8, integer multiplies read 32-bits from one source, and
804 * 16-bits from the other, and relying on the MACH instruction to
805 * generate the high bits of the result.
807 * On Gen8, the multiply instruction does a full 32x32-bit multiply,
808 * but in order to do a 64x64-bit multiply we have to simulate the
809 * previous behavior and then use a MACH instruction.
811 * FINISHME: Don't use source modifiers on src1.
813 if (devinfo
->gen
>= 8) {
814 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
815 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
816 if (mul
->src
[1].type
== BRW_REGISTER_TYPE_D
) {
817 mul
->src
[1].type
= BRW_REGISTER_TYPE_W
;
818 mul
->src
[1].stride
= 2;
820 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
821 mul
->src
[1].stride
= 2;
829 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
832 case nir_op_uadd_carry
:
833 unreachable("Should have been lowered by carry_to_arith().");
835 case nir_op_usub_borrow
:
836 unreachable("Should have been lowered by borrow_to_arith().");
839 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
845 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
851 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
856 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
861 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
865 if (devinfo
->gen
>= 8) {
866 resolve_source_modifiers(&op
[0]);
868 bld
.NOT(result
, op
[0]);
871 if (devinfo
->gen
>= 8) {
872 resolve_source_modifiers(&op
[0]);
873 resolve_source_modifiers(&op
[1]);
875 bld
.XOR(result
, op
[0], op
[1]);
878 if (devinfo
->gen
>= 8) {
879 resolve_source_modifiers(&op
[0]);
880 resolve_source_modifiers(&op
[1]);
882 bld
.OR(result
, op
[0], op
[1]);
885 if (devinfo
->gen
>= 8) {
886 resolve_source_modifiers(&op
[0]);
887 resolve_source_modifiers(&op
[1]);
889 bld
.AND(result
, op
[0], op
[1]);
901 case nir_op_ball_fequal2
:
902 case nir_op_ball_iequal2
:
903 case nir_op_ball_fequal3
:
904 case nir_op_ball_iequal3
:
905 case nir_op_ball_fequal4
:
906 case nir_op_ball_iequal4
:
907 case nir_op_bany_fnequal2
:
908 case nir_op_bany_inequal2
:
909 case nir_op_bany_fnequal3
:
910 case nir_op_bany_inequal3
:
911 case nir_op_bany_fnequal4
:
912 case nir_op_bany_inequal4
:
913 unreachable("Lowered by nir_lower_alu_reductions");
915 case nir_op_fnoise1_1
:
916 case nir_op_fnoise1_2
:
917 case nir_op_fnoise1_3
:
918 case nir_op_fnoise1_4
:
919 case nir_op_fnoise2_1
:
920 case nir_op_fnoise2_2
:
921 case nir_op_fnoise2_3
:
922 case nir_op_fnoise2_4
:
923 case nir_op_fnoise3_1
:
924 case nir_op_fnoise3_2
:
925 case nir_op_fnoise3_3
:
926 case nir_op_fnoise3_4
:
927 case nir_op_fnoise4_1
:
928 case nir_op_fnoise4_2
:
929 case nir_op_fnoise4_3
:
930 case nir_op_fnoise4_4
:
931 unreachable("not reached: should be handled by lower_noise");
934 unreachable("not reached: should be handled by ldexp_to_arith()");
937 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
938 inst
->saturate
= instr
->dest
.saturate
;
942 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
943 inst
->saturate
= instr
->dest
.saturate
;
948 bld
.MOV(result
, negate(op
[0]));
952 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
955 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
959 inst
= bld
.RNDZ(result
, op
[0]);
960 inst
->saturate
= instr
->dest
.saturate
;
964 op
[0].negate
= !op
[0].negate
;
965 fs_reg temp
= vgrf(glsl_type::float_type
);
966 bld
.RNDD(temp
, op
[0]);
968 inst
= bld
.MOV(result
, temp
);
969 inst
->saturate
= instr
->dest
.saturate
;
973 inst
= bld
.RNDD(result
, op
[0]);
974 inst
->saturate
= instr
->dest
.saturate
;
977 inst
= bld
.FRC(result
, op
[0]);
978 inst
->saturate
= instr
->dest
.saturate
;
980 case nir_op_fround_even
:
981 inst
= bld
.RNDE(result
, op
[0]);
982 inst
->saturate
= instr
->dest
.saturate
;
988 if (devinfo
->gen
>= 6) {
989 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
990 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
992 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
993 inst
= bld
.SEL(result
, op
[0], op
[1]);
994 inst
->predicate
= BRW_PREDICATE_NORMAL
;
996 inst
->saturate
= instr
->dest
.saturate
;
1002 if (devinfo
->gen
>= 6) {
1003 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1004 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1006 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
1007 inst
= bld
.SEL(result
, op
[0], op
[1]);
1008 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1010 inst
->saturate
= instr
->dest
.saturate
;
1013 case nir_op_pack_snorm_2x16
:
1014 case nir_op_pack_snorm_4x8
:
1015 case nir_op_pack_unorm_2x16
:
1016 case nir_op_pack_unorm_4x8
:
1017 case nir_op_unpack_snorm_2x16
:
1018 case nir_op_unpack_snorm_4x8
:
1019 case nir_op_unpack_unorm_2x16
:
1020 case nir_op_unpack_unorm_4x8
:
1021 case nir_op_unpack_half_2x16
:
1022 case nir_op_pack_half_2x16
:
1023 unreachable("not reached: should be handled by lower_packing_builtins");
1025 case nir_op_unpack_half_2x16_split_x
:
1026 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1027 inst
->saturate
= instr
->dest
.saturate
;
1029 case nir_op_unpack_half_2x16_split_y
:
1030 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1031 inst
->saturate
= instr
->dest
.saturate
;
1035 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1036 inst
->saturate
= instr
->dest
.saturate
;
1039 case nir_op_bitfield_reverse
:
1040 bld
.BFREV(result
, op
[0]);
1043 case nir_op_bit_count
:
1044 bld
.CBIT(result
, op
[0]);
1047 case nir_op_ufind_msb
:
1048 case nir_op_ifind_msb
: {
1049 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1051 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1052 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1053 * subtract the result from 31 to convert the MSB count into an LSB count.
1056 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
1057 fs_reg
neg_result(result
);
1058 neg_result
.negate
= true;
1059 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
1060 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1064 case nir_op_find_lsb
:
1065 bld
.FBL(result
, op
[0]);
1068 case nir_op_ubitfield_extract
:
1069 case nir_op_ibitfield_extract
:
1070 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1073 bld
.BFI1(result
, op
[0], op
[1]);
1076 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1079 case nir_op_bitfield_insert
:
1080 unreachable("not reached: should be handled by "
1081 "lower_instructions::bitfield_insert_to_bfm_bfi");
1084 bld
.SHL(result
, op
[0], op
[1]);
1087 bld
.ASR(result
, op
[0], op
[1]);
1090 bld
.SHR(result
, op
[0], op
[1]);
1093 case nir_op_pack_half_2x16_split
:
1094 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1098 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1099 inst
->saturate
= instr
->dest
.saturate
;
1103 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1104 inst
->saturate
= instr
->dest
.saturate
;
1108 if (optimize_frontfacing_ternary(instr
, result
))
1111 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
1112 inst
= bld
.SEL(result
, op
[1], op
[2]);
1113 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1117 unreachable("unhandled instruction");
1120 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1121 * to sign extend the low bit to 0/~0
1123 if (devinfo
->gen
<= 5 &&
1124 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1125 fs_reg masked
= vgrf(glsl_type::int_type
);
1126 bld
.AND(masked
, result
, fs_reg(1));
1127 masked
.negate
= true;
1128 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1133 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1134 nir_load_const_instr
*instr
)
1136 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1138 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1139 bld
.MOV(offset(reg
, bld
, i
), fs_reg(instr
->value
.i
[i
]));
1141 nir_ssa_values
[instr
->def
.index
] = reg
;
1145 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1147 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1148 instr
->def
.num_components
);
1152 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1153 unsigned base_offset
, nir_src
*indirect
)
1157 assert(!nir_reg
->is_global
);
1159 reg
= v
->nir_locals
[nir_reg
->index
];
1161 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1163 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1165 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1166 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1167 fs_reg(multiplier
));
1174 fs_visitor::get_nir_src(nir_src src
)
1178 reg
= nir_ssa_values
[src
.ssa
->index
];
1180 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1184 /* to avoid floating-point denorm flushing problems, set the type by
1185 * default to D - instructions that need floating point semantics will set
1186 * this to F if they need to
1188 return retype(reg
, BRW_REGISTER_TYPE_D
);
1192 fs_visitor::get_nir_dest(nir_dest dest
)
1195 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1196 dest
.ssa
.num_components
);
1197 return nir_ssa_values
[dest
.ssa
.index
];
1200 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1205 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1208 for (unsigned i
= 0; i
< 4; i
++) {
1209 if (!((wr_mask
>> i
) & 1))
1212 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1213 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1214 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1215 if (new_inst
->src
[j
].file
== GRF
)
1216 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1223 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1226 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1227 dest
= get_nir_dest(instr
->dest
);
1229 bool has_indirect
= false;
1231 switch (instr
->intrinsic
) {
1232 case nir_intrinsic_discard
:
1233 case nir_intrinsic_discard_if
: {
1234 /* We track our discarded pixels in f0.1. By predicating on it, we can
1235 * update just the flag bits that aren't yet discarded. If there's no
1236 * condition, we emit a CMP of g0 != g0, so all currently executing
1237 * channels will get turned off.
1240 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1241 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1242 fs_reg(0), BRW_CONDITIONAL_Z
);
1244 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1245 BRW_REGISTER_TYPE_UW
));
1246 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1248 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1249 cmp
->flag_subreg
= 1;
1251 if (devinfo
->gen
>= 6) {
1252 emit_discard_jump();
1257 case nir_intrinsic_atomic_counter_inc
:
1258 case nir_intrinsic_atomic_counter_dec
:
1259 case nir_intrinsic_atomic_counter_read
: {
1260 unsigned surf_index
= prog_data
->binding_table
.abo_start
+
1261 (unsigned) instr
->const_index
[0];
1262 fs_reg offset
= fs_reg(get_nir_src(instr
->src
[0]));
1264 switch (instr
->intrinsic
) {
1265 case nir_intrinsic_atomic_counter_inc
:
1266 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
1267 fs_reg(), fs_reg());
1269 case nir_intrinsic_atomic_counter_dec
:
1270 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
1271 fs_reg(), fs_reg());
1273 case nir_intrinsic_atomic_counter_read
:
1274 emit_untyped_surface_read(surf_index
, dest
, offset
);
1277 unreachable("Unreachable");
1280 /* Mark the surface as used. */
1281 brw_mark_surface_used(stage_prog_data
, surf_index
);
1285 case nir_intrinsic_load_front_face
:
1286 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1287 *emit_frontfacing_interpolation());
1290 case nir_intrinsic_load_vertex_id
:
1291 unreachable("should be lowered by lower_vertex_id()");
1293 case nir_intrinsic_load_vertex_id_zero_base
: {
1294 fs_reg vertex_id
= nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
1295 assert(vertex_id
.file
!= BAD_FILE
);
1296 dest
.type
= vertex_id
.type
;
1297 bld
.MOV(dest
, vertex_id
);
1301 case nir_intrinsic_load_base_vertex
: {
1302 fs_reg base_vertex
= nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
1303 assert(base_vertex
.file
!= BAD_FILE
);
1304 dest
.type
= base_vertex
.type
;
1305 bld
.MOV(dest
, base_vertex
);
1309 case nir_intrinsic_load_instance_id
: {
1310 fs_reg instance_id
= nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
1311 assert(instance_id
.file
!= BAD_FILE
);
1312 dest
.type
= instance_id
.type
;
1313 bld
.MOV(dest
, instance_id
);
1317 case nir_intrinsic_load_sample_mask_in
: {
1318 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1319 assert(sample_mask_in
.file
!= BAD_FILE
);
1320 dest
.type
= sample_mask_in
.type
;
1321 bld
.MOV(dest
, sample_mask_in
);
1325 case nir_intrinsic_load_sample_pos
: {
1326 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1327 assert(sample_pos
.file
!= BAD_FILE
);
1328 dest
.type
= sample_pos
.type
;
1329 bld
.MOV(dest
, sample_pos
);
1330 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1334 case nir_intrinsic_load_sample_id
: {
1335 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1336 assert(sample_id
.file
!= BAD_FILE
);
1337 dest
.type
= sample_id
.type
;
1338 bld
.MOV(dest
, sample_id
);
1342 case nir_intrinsic_load_uniform_indirect
:
1343 has_indirect
= true;
1345 case nir_intrinsic_load_uniform
: {
1346 unsigned index
= instr
->const_index
[0];
1349 if (index
< num_direct_uniforms
) {
1350 uniform_reg
= fs_reg(UNIFORM
, 0);
1352 uniform_reg
= fs_reg(UNIFORM
, num_direct_uniforms
);
1353 index
-= num_direct_uniforms
;
1356 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1357 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, index
);
1359 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1363 dest
= offset(dest
, bld
, 1);
1368 case nir_intrinsic_load_ubo_indirect
:
1369 has_indirect
= true;
1371 case nir_intrinsic_load_ubo
: {
1372 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1376 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1379 /* The block index is not a constant. Evaluate the index expression
1380 * per-channel and add the base UBO index; we have to select a value
1381 * from any live channel.
1383 surf_index
= vgrf(glsl_type::uint_type
);
1384 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1385 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1386 surf_index
= bld
.emit_uniformize(surf_index
);
1388 /* Assume this may touch any UBO. It would be nice to provide
1389 * a tighter bound, but the array information is already lowered away.
1391 brw_mark_surface_used(prog_data
,
1392 stage_prog_data
->binding_table
.ubo_start
+
1393 shader_prog
->NumUniformBlocks
- 1);
1397 /* Turn the byte offset into a dword offset. */
1398 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1399 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1400 BRW_REGISTER_TYPE_D
),
1403 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1404 for (int i
= 0; i
< instr
->num_components
; i
++)
1405 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
1406 base_offset
, vec4_offset
+ i
);
1408 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1409 packed_consts
.type
= dest
.type
;
1411 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1412 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1413 surf_index
, const_offset_reg
);
1415 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1416 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1418 /* The std140 packing rules don't allow vectors to cross 16-byte
1419 * boundaries, and a reg is 32 bytes.
1421 assert(packed_consts
.subreg_offset
< 32);
1423 bld
.MOV(dest
, packed_consts
);
1424 dest
= offset(dest
, bld
, 1);
1430 case nir_intrinsic_load_input_indirect
:
1431 has_indirect
= true;
1433 case nir_intrinsic_load_input
: {
1435 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1436 fs_reg src
= offset(retype(nir_inputs
, dest
.type
), bld
,
1437 instr
->const_index
[0] + index
);
1439 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1443 dest
= offset(dest
, bld
, 1);
1448 /* Handle ARB_gpu_shader5 interpolation intrinsics
1450 * It's worth a quick word of explanation as to why we handle the full
1451 * variable-based interpolation intrinsic rather than a lowered version
1452 * with like we do for other inputs. We have to do that because the way
1453 * we set up inputs doesn't allow us to use the already setup inputs for
1454 * interpolation. At the beginning of the shader, we go through all of
1455 * the input variables and do the initial interpolation and put it in
1456 * the nir_inputs array based on its location as determined in
1457 * nir_lower_io. If the input isn't used, dead code cleans up and
1458 * everything works fine. However, when we get to the ARB_gpu_shader5
1459 * interpolation intrinsics, we need to reinterpolate the input
1460 * differently. If we used an intrinsic that just had an index it would
1461 * only give us the offset into the nir_inputs array. However, this is
1462 * useless because that value is post-interpolation and we need
1463 * pre-interpolation. In order to get the actual location of the bits
1464 * we get from the vertex fetching hardware, we need the variable.
1466 case nir_intrinsic_interp_var_at_centroid
:
1467 case nir_intrinsic_interp_var_at_sample
:
1468 case nir_intrinsic_interp_var_at_offset
: {
1469 assert(stage
== MESA_SHADER_FRAGMENT
);
1471 ((struct brw_wm_prog_data
*) prog_data
)->pulls_bary
= true;
1473 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1475 /* For most messages, we need one reg of ignored data; the hardware
1476 * requires mlen==1 even when there is no payload. in the per-slot
1477 * offset case, we'll replace this with the proper source data.
1479 fs_reg src
= vgrf(glsl_type::float_type
);
1480 int mlen
= 1; /* one reg unless overriden */
1483 switch (instr
->intrinsic
) {
1484 case nir_intrinsic_interp_var_at_centroid
:
1485 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1486 dst_xy
, src
, fs_reg(0u));
1489 case nir_intrinsic_interp_var_at_sample
: {
1490 /* XXX: We should probably handle non-constant sample id's */
1491 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1492 assert(const_sample
);
1493 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1494 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_xy
, src
,
1499 case nir_intrinsic_interp_var_at_offset
: {
1500 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1503 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1504 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1506 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_xy
, src
,
1507 fs_reg(off_x
| (off_y
<< 4)));
1509 src
= vgrf(glsl_type::ivec2_type
);
1510 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1511 BRW_REGISTER_TYPE_F
);
1512 for (int i
= 0; i
< 2; i
++) {
1513 fs_reg temp
= vgrf(glsl_type::float_type
);
1514 bld
.MUL(temp
, offset(offset_src
, bld
, i
), fs_reg(16.0f
));
1515 fs_reg itemp
= vgrf(glsl_type::int_type
);
1516 bld
.MOV(itemp
, temp
); /* float to int */
1518 /* Clamp the upper end of the range to +7/16.
1519 * ARB_gpu_shader5 requires that we support a maximum offset
1520 * of +0.5, which isn't representable in a S0.4 value -- if
1521 * we didn't clamp it, we'd end up with -8/16, which is the
1522 * opposite of what the shader author wanted.
1524 * This is legal due to ARB_gpu_shader5's quantization
1527 * "Not all values of <offset> may be supported; x and y
1528 * offsets may be rounded to fixed-point values with the
1529 * number of fraction bits given by the
1530 * implementation-dependent constant
1531 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1533 set_condmod(BRW_CONDITIONAL_L
,
1534 bld
.SEL(offset(src
, bld
, i
), itemp
, fs_reg(7)));
1537 mlen
= 2 * dispatch_width
/ 8;
1538 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_xy
, src
,
1545 unreachable("Invalid intrinsic");
1549 /* 2 floats per slot returned */
1550 inst
->regs_written
= 2 * dispatch_width
/ 8;
1551 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1552 INTERP_QUALIFIER_NOPERSPECTIVE
;
1554 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1555 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1556 src
.type
= dest
.type
;
1558 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1559 dest
= offset(dest
, bld
, 1);
1564 case nir_intrinsic_store_output_indirect
:
1565 has_indirect
= true;
1567 case nir_intrinsic_store_output
: {
1568 fs_reg src
= get_nir_src(instr
->src
[0]);
1570 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1571 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
1572 instr
->const_index
[0] + index
);
1574 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1576 bld
.MOV(new_dest
, src
);
1577 src
= offset(src
, bld
, 1);
1582 case nir_intrinsic_barrier
:
1587 unreachable("unknown intrinsic");
1592 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1594 unsigned sampler
= instr
->sampler_index
;
1595 fs_reg
sampler_reg(sampler
);
1597 /* FINISHME: We're failing to recompile our programs when the sampler is
1598 * updated. This only matters for the texture rectangle scale parameters
1599 * (pre-gen6, or gen6+ with GL_CLAMP).
1601 int texunit
= prog
->SamplerUnits
[sampler
];
1603 int gather_component
= instr
->component
;
1605 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1607 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1610 int lod_components
= 0;
1611 int UNUSED offset_components
= 0;
1613 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1615 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1616 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1617 switch (instr
->src
[i
].src_type
) {
1618 case nir_tex_src_bias
:
1619 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1621 case nir_tex_src_comparitor
:
1622 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1624 case nir_tex_src_coord
:
1625 switch (instr
->op
) {
1627 case nir_texop_txf_ms
:
1628 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1631 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1635 case nir_tex_src_ddx
:
1636 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1637 lod_components
= nir_tex_instr_src_size(instr
, i
);
1639 case nir_tex_src_ddy
:
1640 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1642 case nir_tex_src_lod
:
1643 switch (instr
->op
) {
1645 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1648 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1651 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1655 case nir_tex_src_ms_index
:
1656 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1658 case nir_tex_src_offset
:
1659 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1660 if (instr
->is_array
)
1661 offset_components
= instr
->coord_components
- 1;
1663 offset_components
= instr
->coord_components
;
1665 case nir_tex_src_projector
:
1666 unreachable("should be lowered");
1668 case nir_tex_src_sampler_offset
: {
1669 /* Figure out the highest possible sampler index and mark it as used */
1670 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1671 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
1672 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1674 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1676 brw_mark_surface_used(prog_data
, max_used
);
1678 /* Emit code to evaluate the actual indexing expression */
1679 sampler_reg
= vgrf(glsl_type::uint_type
);
1680 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
1681 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
1686 unreachable("unknown texture source");
1690 if (instr
->op
== nir_texop_txf_ms
) {
1691 if (devinfo
->gen
>= 7 &&
1692 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1693 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1699 for (unsigned i
= 0; i
< 3; i
++) {
1700 if (instr
->const_offset
[i
] != 0) {
1701 assert(offset_components
== 0);
1702 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
1707 enum glsl_base_type dest_base_type
;
1708 switch (instr
->dest_type
) {
1709 case nir_type_float
:
1710 dest_base_type
= GLSL_TYPE_FLOAT
;
1713 dest_base_type
= GLSL_TYPE_INT
;
1715 case nir_type_unsigned
:
1716 dest_base_type
= GLSL_TYPE_UINT
;
1719 unreachable("bad type");
1722 const glsl_type
*dest_type
=
1723 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1726 ir_texture_opcode op
;
1727 switch (instr
->op
) {
1728 case nir_texop_lod
: op
= ir_lod
; break;
1729 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1730 case nir_texop_tex
: op
= ir_tex
; break;
1731 case nir_texop_tg4
: op
= ir_tg4
; break;
1732 case nir_texop_txb
: op
= ir_txb
; break;
1733 case nir_texop_txd
: op
= ir_txd
; break;
1734 case nir_texop_txf
: op
= ir_txf
; break;
1735 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1736 case nir_texop_txl
: op
= ir_txl
; break;
1737 case nir_texop_txs
: op
= ir_txs
; break;
1739 unreachable("unknown texture opcode");
1742 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1743 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1744 tex_offset
, mcs
, gather_component
,
1745 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1747 fs_reg dest
= get_nir_dest(instr
->dest
);
1748 dest
.type
= this->result
.type
;
1749 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1750 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
1751 dest
, this->result
),
1752 (1 << num_components
) - 1);
1756 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
1758 switch (instr
->type
) {
1759 case nir_jump_break
:
1760 bld
.emit(BRW_OPCODE_BREAK
);
1762 case nir_jump_continue
:
1763 bld
.emit(BRW_OPCODE_CONTINUE
);
1765 case nir_jump_return
:
1767 unreachable("unknown jump");