2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "main/shaderimage.h"
28 #include "program/prog_to_nir.h"
30 #include "brw_fs_surface_builder.h"
32 #include "brw_fs_surface_builder.h"
33 #include "brw_vec4_gs_visitor.h"
36 using namespace brw::surface_access
;
39 fs_visitor::emit_nir_code()
41 /* emit the arrays used for inputs and outputs - load/store intrinsics will
42 * be converted to reads/writes of these arrays
47 nir_emit_system_values();
49 /* get the main function and emit it */
50 nir_foreach_overload(nir
, overload
) {
51 assert(strcmp(overload
->function
->name
, "main") == 0);
52 assert(overload
->impl
);
53 nir_emit_impl(overload
->impl
);
58 fs_visitor::nir_setup_inputs()
60 if (stage
!= MESA_SHADER_FRAGMENT
)
63 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
65 nir_foreach_variable(var
, &nir
->inputs
) {
66 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
69 if (var
->data
.location
== VARYING_SLOT_POS
) {
70 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
71 var
->data
.origin_upper_left
);
72 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
75 emit_general_interpolation(input
, var
->name
, var
->type
,
76 (glsl_interp_qualifier
) var
->data
.interpolation
,
77 var
->data
.location
, var
->data
.centroid
,
84 fs_visitor::nir_setup_outputs()
86 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
88 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
90 nir_foreach_variable(var
, &nir
->outputs
) {
91 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
93 int vector_elements
= var
->type
->without_array()->vector_elements
;
96 case MESA_SHADER_VERTEX
:
97 for (unsigned int i
= 0; i
< ALIGN(type_size_scalar(var
->type
), 4) / 4; i
++) {
98 int output
= var
->data
.location
+ i
;
99 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
100 this->output_components
[output
] = vector_elements
;
103 case MESA_SHADER_FRAGMENT
:
104 if (var
->data
.index
> 0) {
105 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
106 assert(var
->data
.index
== 1);
107 this->dual_src_output
= reg
;
108 this->do_dual_src
= true;
109 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
110 /* Writing gl_FragColor outputs to all color regions. */
111 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
112 this->outputs
[i
] = reg
;
113 this->output_components
[i
] = 4;
115 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
116 this->frag_depth
= reg
;
117 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
118 this->frag_stencil
= reg
;
119 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
120 this->sample_mask
= reg
;
122 /* gl_FragData or a user-defined FS output */
123 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
124 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
126 /* General color output. */
127 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
128 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
129 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
130 this->output_components
[output
] = vector_elements
;
135 unreachable("unhandled shader stage");
141 fs_visitor::nir_setup_uniforms()
143 if (dispatch_width
!= 8)
146 uniforms
= nir
->num_uniforms
;
148 nir_foreach_variable(var
, &nir
->uniforms
) {
149 /* UBO's and atomics don't take up space in the uniform file */
150 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
153 if (type_size_scalar(var
->type
) > 0)
154 param_size
[var
->data
.driver_location
] = type_size_scalar(var
->type
);
159 emit_system_values_block(nir_block
*block
, void *void_visitor
)
161 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
164 nir_foreach_instr(block
, instr
) {
165 if (instr
->type
!= nir_instr_type_intrinsic
)
168 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
169 switch (intrin
->intrinsic
) {
170 case nir_intrinsic_load_vertex_id
:
171 unreachable("should be lowered by lower_vertex_id().");
173 case nir_intrinsic_load_vertex_id_zero_base
:
174 assert(v
->stage
== MESA_SHADER_VERTEX
);
175 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
176 if (reg
->file
== BAD_FILE
)
177 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
180 case nir_intrinsic_load_base_vertex
:
181 assert(v
->stage
== MESA_SHADER_VERTEX
);
182 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
183 if (reg
->file
== BAD_FILE
)
184 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
187 case nir_intrinsic_load_instance_id
:
188 assert(v
->stage
== MESA_SHADER_VERTEX
);
189 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
190 if (reg
->file
== BAD_FILE
)
191 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
194 case nir_intrinsic_load_invocation_id
:
195 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
196 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
197 if (reg
->file
== BAD_FILE
) {
198 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
199 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
200 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
201 abld
.SHR(iid
, g1
, fs_reg(27u));
206 case nir_intrinsic_load_sample_pos
:
207 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
208 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
209 if (reg
->file
== BAD_FILE
)
210 *reg
= *v
->emit_samplepos_setup();
213 case nir_intrinsic_load_sample_id
:
214 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
215 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
216 if (reg
->file
== BAD_FILE
)
217 *reg
= *v
->emit_sampleid_setup();
220 case nir_intrinsic_load_sample_mask_in
:
221 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
222 assert(v
->devinfo
->gen
>= 7);
223 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
224 if (reg
->file
== BAD_FILE
)
225 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
226 BRW_REGISTER_TYPE_D
));
229 case nir_intrinsic_load_local_invocation_id
:
230 assert(v
->stage
== MESA_SHADER_COMPUTE
);
231 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
232 if (reg
->file
== BAD_FILE
)
233 *reg
= *v
->emit_cs_local_invocation_id_setup();
236 case nir_intrinsic_load_work_group_id
:
237 assert(v
->stage
== MESA_SHADER_COMPUTE
);
238 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
239 if (reg
->file
== BAD_FILE
)
240 *reg
= *v
->emit_cs_work_group_id_setup();
252 fs_visitor::nir_emit_system_values()
254 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
255 nir_foreach_overload(nir
, overload
) {
256 assert(strcmp(overload
->function
->name
, "main") == 0);
257 assert(overload
->impl
);
258 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
263 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
265 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
266 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
267 unsigned array_elems
=
268 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
269 unsigned size
= array_elems
* reg
->num_components
;
270 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
273 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
276 nir_emit_cf_list(&impl
->body
);
280 fs_visitor::nir_emit_cf_list(exec_list
*list
)
282 exec_list_validate(list
);
283 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
284 switch (node
->type
) {
286 nir_emit_if(nir_cf_node_as_if(node
));
289 case nir_cf_node_loop
:
290 nir_emit_loop(nir_cf_node_as_loop(node
));
293 case nir_cf_node_block
:
294 nir_emit_block(nir_cf_node_as_block(node
));
298 unreachable("Invalid CFG node block");
304 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
306 /* first, put the condition into f0 */
307 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
308 retype(get_nir_src(if_stmt
->condition
),
309 BRW_REGISTER_TYPE_D
));
310 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
312 bld
.IF(BRW_PREDICATE_NORMAL
);
314 nir_emit_cf_list(&if_stmt
->then_list
);
316 /* note: if the else is empty, dead CF elimination will remove it */
317 bld
.emit(BRW_OPCODE_ELSE
);
319 nir_emit_cf_list(&if_stmt
->else_list
);
321 bld
.emit(BRW_OPCODE_ENDIF
);
325 fs_visitor::nir_emit_loop(nir_loop
*loop
)
327 bld
.emit(BRW_OPCODE_DO
);
329 nir_emit_cf_list(&loop
->body
);
331 bld
.emit(BRW_OPCODE_WHILE
);
335 fs_visitor::nir_emit_block(nir_block
*block
)
337 nir_foreach_instr(block
, instr
) {
338 nir_emit_instr(instr
);
343 fs_visitor::nir_emit_instr(nir_instr
*instr
)
345 const fs_builder abld
= bld
.annotate(NULL
, instr
);
347 switch (instr
->type
) {
348 case nir_instr_type_alu
:
349 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
352 case nir_instr_type_intrinsic
:
353 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
356 case nir_instr_type_tex
:
357 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
360 case nir_instr_type_load_const
:
361 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
364 case nir_instr_type_ssa_undef
:
365 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
368 case nir_instr_type_jump
:
369 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
373 unreachable("unknown instruction type");
378 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
379 const fs_reg
&result
)
381 if (!instr
->src
[0].src
.is_ssa
||
382 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
385 nir_intrinsic_instr
*src0
=
386 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
388 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
391 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
392 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
395 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
396 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
399 fs_reg tmp
= vgrf(glsl_type::int_type
);
401 if (devinfo
->gen
>= 6) {
402 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
403 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
405 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
407 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
408 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
410 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
412 * This negation looks like it's safe in practice, because bits 0:4 will
413 * surely be TRIANGLES
416 if (value1
->f
[0] == -1.0f
) {
420 tmp
.type
= BRW_REGISTER_TYPE_W
;
421 tmp
.subreg_offset
= 2;
424 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
425 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
427 tmp
.type
= BRW_REGISTER_TYPE_D
;
428 tmp
.subreg_offset
= 0;
431 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
432 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
434 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
436 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
437 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
439 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
441 * This negation looks like it's safe in practice, because bits 0:4 will
442 * surely be TRIANGLES
445 if (value1
->f
[0] == -1.0f
) {
449 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
451 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
457 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
459 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
462 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
463 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
466 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
467 op
[i
] = get_nir_src(instr
->src
[i
].src
);
468 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
469 op
[i
].abs
= instr
->src
[i
].abs
;
470 op
[i
].negate
= instr
->src
[i
].negate
;
473 /* We get a bunch of mov's out of the from_ssa pass and they may still
474 * be vectorized. We'll handle them as a special-case. We'll also
475 * handle vecN here because it's basically the same thing.
483 fs_reg temp
= result
;
484 bool need_extra_copy
= false;
485 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
486 if (!instr
->src
[i
].src
.is_ssa
&&
487 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
488 need_extra_copy
= true;
489 temp
= bld
.vgrf(result
.type
, 4);
494 for (unsigned i
= 0; i
< 4; i
++) {
495 if (!(instr
->dest
.write_mask
& (1 << i
)))
498 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
499 inst
= bld
.MOV(offset(temp
, bld
, i
),
500 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
502 inst
= bld
.MOV(offset(temp
, bld
, i
),
503 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
505 inst
->saturate
= instr
->dest
.saturate
;
508 /* In this case the source and destination registers were the same,
509 * so we need to insert an extra set of moves in order to deal with
512 if (need_extra_copy
) {
513 for (unsigned i
= 0; i
< 4; i
++) {
514 if (!(instr
->dest
.write_mask
& (1 << i
)))
517 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
526 /* At this point, we have dealt with any instruction that operates on
527 * more than a single channel. Therefore, we can just adjust the source
528 * and destination registers for that channel and emit the instruction.
530 unsigned channel
= 0;
531 if (nir_op_infos
[instr
->op
].output_size
== 0) {
532 /* Since NIR is doing the scalarizing for us, we should only ever see
533 * vectorized operations with a single channel.
535 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
536 channel
= ffs(instr
->dest
.write_mask
) - 1;
538 result
= offset(result
, bld
, channel
);
541 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
542 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
543 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
549 inst
= bld
.MOV(result
, op
[0]);
550 inst
->saturate
= instr
->dest
.saturate
;
555 bld
.MOV(result
, op
[0]);
559 /* AND(val, 0x80000000) gives the sign bit.
561 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
564 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
566 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
567 op
[0].type
= BRW_REGISTER_TYPE_UD
;
568 result
.type
= BRW_REGISTER_TYPE_UD
;
569 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
571 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
572 inst
->predicate
= BRW_PREDICATE_NORMAL
;
573 if (instr
->dest
.saturate
) {
574 inst
= bld
.MOV(result
, result
);
575 inst
->saturate
= true;
581 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
582 * -> non-negative val generates 0x00000000.
583 * Predicated OR sets 1 if val is positive.
585 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
586 bld
.ASR(result
, op
[0], fs_reg(31));
587 inst
= bld
.OR(result
, result
, fs_reg(1));
588 inst
->predicate
= BRW_PREDICATE_NORMAL
;
592 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
593 inst
->saturate
= instr
->dest
.saturate
;
597 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
598 inst
->saturate
= instr
->dest
.saturate
;
602 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
603 inst
->saturate
= instr
->dest
.saturate
;
607 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
608 inst
->saturate
= instr
->dest
.saturate
;
612 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
613 inst
->saturate
= instr
->dest
.saturate
;
617 if (fs_key
->high_quality_derivatives
) {
618 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
620 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
622 inst
->saturate
= instr
->dest
.saturate
;
624 case nir_op_fddx_fine
:
625 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
626 inst
->saturate
= instr
->dest
.saturate
;
628 case nir_op_fddx_coarse
:
629 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
630 inst
->saturate
= instr
->dest
.saturate
;
633 if (fs_key
->high_quality_derivatives
) {
634 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
635 fs_reg(fs_key
->render_to_fbo
));
637 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
638 fs_reg(fs_key
->render_to_fbo
));
640 inst
->saturate
= instr
->dest
.saturate
;
642 case nir_op_fddy_fine
:
643 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
644 fs_reg(fs_key
->render_to_fbo
));
645 inst
->saturate
= instr
->dest
.saturate
;
647 case nir_op_fddy_coarse
:
648 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
649 fs_reg(fs_key
->render_to_fbo
));
650 inst
->saturate
= instr
->dest
.saturate
;
655 inst
= bld
.ADD(result
, op
[0], op
[1]);
656 inst
->saturate
= instr
->dest
.saturate
;
660 inst
= bld
.MUL(result
, op
[0], op
[1]);
661 inst
->saturate
= instr
->dest
.saturate
;
665 bld
.MUL(result
, op
[0], op
[1]);
668 case nir_op_imul_high
:
669 case nir_op_umul_high
:
670 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
675 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
678 case nir_op_uadd_carry
:
679 unreachable("Should have been lowered by carry_to_arith().");
681 case nir_op_usub_borrow
:
682 unreachable("Should have been lowered by borrow_to_arith().");
685 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
691 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
697 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
702 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
707 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
711 if (devinfo
->gen
>= 8) {
712 op
[0] = resolve_source_modifiers(op
[0]);
714 bld
.NOT(result
, op
[0]);
717 if (devinfo
->gen
>= 8) {
718 op
[0] = resolve_source_modifiers(op
[0]);
719 op
[1] = resolve_source_modifiers(op
[1]);
721 bld
.XOR(result
, op
[0], op
[1]);
724 if (devinfo
->gen
>= 8) {
725 op
[0] = resolve_source_modifiers(op
[0]);
726 op
[1] = resolve_source_modifiers(op
[1]);
728 bld
.OR(result
, op
[0], op
[1]);
731 if (devinfo
->gen
>= 8) {
732 op
[0] = resolve_source_modifiers(op
[0]);
733 op
[1] = resolve_source_modifiers(op
[1]);
735 bld
.AND(result
, op
[0], op
[1]);
747 case nir_op_ball_fequal2
:
748 case nir_op_ball_iequal2
:
749 case nir_op_ball_fequal3
:
750 case nir_op_ball_iequal3
:
751 case nir_op_ball_fequal4
:
752 case nir_op_ball_iequal4
:
753 case nir_op_bany_fnequal2
:
754 case nir_op_bany_inequal2
:
755 case nir_op_bany_fnequal3
:
756 case nir_op_bany_inequal3
:
757 case nir_op_bany_fnequal4
:
758 case nir_op_bany_inequal4
:
759 unreachable("Lowered by nir_lower_alu_reductions");
761 case nir_op_fnoise1_1
:
762 case nir_op_fnoise1_2
:
763 case nir_op_fnoise1_3
:
764 case nir_op_fnoise1_4
:
765 case nir_op_fnoise2_1
:
766 case nir_op_fnoise2_2
:
767 case nir_op_fnoise2_3
:
768 case nir_op_fnoise2_4
:
769 case nir_op_fnoise3_1
:
770 case nir_op_fnoise3_2
:
771 case nir_op_fnoise3_3
:
772 case nir_op_fnoise3_4
:
773 case nir_op_fnoise4_1
:
774 case nir_op_fnoise4_2
:
775 case nir_op_fnoise4_3
:
776 case nir_op_fnoise4_4
:
777 unreachable("not reached: should be handled by lower_noise");
780 unreachable("not reached: should be handled by ldexp_to_arith()");
783 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
784 inst
->saturate
= instr
->dest
.saturate
;
788 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
789 inst
->saturate
= instr
->dest
.saturate
;
794 bld
.MOV(result
, negate(op
[0]));
798 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
801 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
805 inst
= bld
.RNDZ(result
, op
[0]);
806 inst
->saturate
= instr
->dest
.saturate
;
810 op
[0].negate
= !op
[0].negate
;
811 fs_reg temp
= vgrf(glsl_type::float_type
);
812 bld
.RNDD(temp
, op
[0]);
814 inst
= bld
.MOV(result
, temp
);
815 inst
->saturate
= instr
->dest
.saturate
;
819 inst
= bld
.RNDD(result
, op
[0]);
820 inst
->saturate
= instr
->dest
.saturate
;
823 inst
= bld
.FRC(result
, op
[0]);
824 inst
->saturate
= instr
->dest
.saturate
;
826 case nir_op_fround_even
:
827 inst
= bld
.RNDE(result
, op
[0]);
828 inst
->saturate
= instr
->dest
.saturate
;
834 if (devinfo
->gen
>= 6) {
835 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
836 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
838 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
839 inst
= bld
.SEL(result
, op
[0], op
[1]);
840 inst
->predicate
= BRW_PREDICATE_NORMAL
;
842 inst
->saturate
= instr
->dest
.saturate
;
848 if (devinfo
->gen
>= 6) {
849 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
850 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
852 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
853 inst
= bld
.SEL(result
, op
[0], op
[1]);
854 inst
->predicate
= BRW_PREDICATE_NORMAL
;
856 inst
->saturate
= instr
->dest
.saturate
;
859 case nir_op_pack_snorm_2x16
:
860 case nir_op_pack_snorm_4x8
:
861 case nir_op_pack_unorm_2x16
:
862 case nir_op_pack_unorm_4x8
:
863 case nir_op_unpack_snorm_2x16
:
864 case nir_op_unpack_snorm_4x8
:
865 case nir_op_unpack_unorm_2x16
:
866 case nir_op_unpack_unorm_4x8
:
867 case nir_op_unpack_half_2x16
:
868 case nir_op_pack_half_2x16
:
869 unreachable("not reached: should be handled by lower_packing_builtins");
871 case nir_op_unpack_half_2x16_split_x
:
872 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
873 inst
->saturate
= instr
->dest
.saturate
;
875 case nir_op_unpack_half_2x16_split_y
:
876 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
877 inst
->saturate
= instr
->dest
.saturate
;
881 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
882 inst
->saturate
= instr
->dest
.saturate
;
885 case nir_op_bitfield_reverse
:
886 bld
.BFREV(result
, op
[0]);
889 case nir_op_bit_count
:
890 bld
.CBIT(result
, op
[0]);
893 case nir_op_ufind_msb
:
894 case nir_op_ifind_msb
: {
895 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
897 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
898 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
899 * subtract the result from 31 to convert the MSB count into an LSB count.
902 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
903 fs_reg
neg_result(result
);
904 neg_result
.negate
= true;
905 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
906 inst
->predicate
= BRW_PREDICATE_NORMAL
;
910 case nir_op_find_lsb
:
911 bld
.FBL(result
, op
[0]);
914 case nir_op_ubitfield_extract
:
915 case nir_op_ibitfield_extract
:
916 bld
.BFE(result
, op
[2], op
[1], op
[0]);
919 bld
.BFI1(result
, op
[0], op
[1]);
922 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
925 case nir_op_bitfield_insert
:
926 unreachable("not reached: should be handled by "
927 "lower_instructions::bitfield_insert_to_bfm_bfi");
930 bld
.SHL(result
, op
[0], op
[1]);
933 bld
.ASR(result
, op
[0], op
[1]);
936 bld
.SHR(result
, op
[0], op
[1]);
939 case nir_op_pack_half_2x16_split
:
940 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
944 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
945 inst
->saturate
= instr
->dest
.saturate
;
949 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
950 inst
->saturate
= instr
->dest
.saturate
;
954 if (optimize_frontfacing_ternary(instr
, result
))
957 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
958 inst
= bld
.SEL(result
, op
[1], op
[2]);
959 inst
->predicate
= BRW_PREDICATE_NORMAL
;
963 unreachable("unhandled instruction");
966 /* If we need to do a boolean resolve, replace the result with -(x & 1)
967 * to sign extend the low bit to 0/~0
969 if (devinfo
->gen
<= 5 &&
970 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
971 fs_reg masked
= vgrf(glsl_type::int_type
);
972 bld
.AND(masked
, result
, fs_reg(1));
973 masked
.negate
= true;
974 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
979 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
980 nir_load_const_instr
*instr
)
982 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
984 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
985 bld
.MOV(offset(reg
, bld
, i
), fs_reg(instr
->value
.i
[i
]));
987 nir_ssa_values
[instr
->def
.index
] = reg
;
991 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
993 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
994 instr
->def
.num_components
);
998 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
999 unsigned base_offset
, nir_src
*indirect
)
1003 assert(!nir_reg
->is_global
);
1005 reg
= v
->nir_locals
[nir_reg
->index
];
1007 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1009 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1011 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1012 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1013 fs_reg(multiplier
));
1020 fs_visitor::get_nir_src(nir_src src
)
1024 reg
= nir_ssa_values
[src
.ssa
->index
];
1026 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1030 /* to avoid floating-point denorm flushing problems, set the type by
1031 * default to D - instructions that need floating point semantics will set
1032 * this to F if they need to
1034 return retype(reg
, BRW_REGISTER_TYPE_D
);
1038 fs_visitor::get_nir_dest(nir_dest dest
)
1041 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1042 dest
.ssa
.num_components
);
1043 return nir_ssa_values
[dest
.ssa
.index
];
1046 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1051 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1053 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
,
1054 BRW_REGISTER_TYPE_UD
);
1056 if (deref
->deref
.child
) {
1057 const nir_deref_array
*deref_array
=
1058 nir_deref_as_array(deref
->deref
.child
);
1059 assert(deref
->deref
.child
->deref_type
== nir_deref_type_array
&&
1060 deref_array
->deref
.child
== NULL
);
1061 const unsigned size
= glsl_get_length(deref
->var
->type
);
1062 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1064 image
= offset(image
, bld
, base
* BRW_IMAGE_PARAM_SIZE
);
1066 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1067 fs_reg
*tmp
= new(mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1069 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1070 /* IVB hangs when trying to access an invalid surface index with
1071 * the dataport. According to the spec "if the index used to
1072 * select an individual element is negative or greater than or
1073 * equal to the size of the array, the results of the operation
1074 * are undefined but may not lead to termination" -- which is one
1075 * of the possible outcomes of the hang. Clamp the index to
1076 * prevent access outside of the array bounds.
1078 bld
.emit_minmax(*tmp
, retype(get_nir_src(deref_array
->indirect
),
1079 BRW_REGISTER_TYPE_UD
),
1080 fs_reg(size
- base
- 1), BRW_CONDITIONAL_L
);
1082 bld
.MOV(*tmp
, get_nir_src(deref_array
->indirect
));
1085 bld
.MUL(*tmp
, *tmp
, fs_reg(BRW_IMAGE_PARAM_SIZE
));
1086 image
.reladdr
= tmp
;
1094 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1097 for (unsigned i
= 0; i
< 4; i
++) {
1098 if (!((wr_mask
>> i
) & 1))
1101 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1102 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1103 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1104 if (new_inst
->src
[j
].file
== GRF
)
1105 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1112 * Get the matching channel register datatype for an image intrinsic of the
1113 * specified GLSL image type.
1116 get_image_base_type(const glsl_type
*type
)
1118 switch ((glsl_base_type
)type
->sampler_type
) {
1119 case GLSL_TYPE_UINT
:
1120 return BRW_REGISTER_TYPE_UD
;
1122 return BRW_REGISTER_TYPE_D
;
1123 case GLSL_TYPE_FLOAT
:
1124 return BRW_REGISTER_TYPE_F
;
1126 unreachable("Not reached.");
1131 * Get the appropriate atomic op for an image atomic intrinsic.
1134 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1137 case nir_intrinsic_image_atomic_add
:
1139 case nir_intrinsic_image_atomic_min
:
1140 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1141 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1142 case nir_intrinsic_image_atomic_max
:
1143 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1144 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1145 case nir_intrinsic_image_atomic_and
:
1147 case nir_intrinsic_image_atomic_or
:
1149 case nir_intrinsic_image_atomic_xor
:
1151 case nir_intrinsic_image_atomic_exchange
:
1153 case nir_intrinsic_image_atomic_comp_swap
:
1154 return BRW_AOP_CMPWR
;
1156 unreachable("Not reachable.");
1161 emit_pixel_interpolater_send(const fs_builder
&bld
,
1166 glsl_interp_qualifier interpolation
)
1172 if (src
.file
== BAD_FILE
) {
1174 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1178 mlen
= 2 * bld
.dispatch_width() / 8;
1181 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1183 /* 2 floats per slot returned */
1184 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1185 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1191 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1194 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1195 dest
= get_nir_dest(instr
->dest
);
1197 bool has_indirect
= false;
1199 switch (instr
->intrinsic
) {
1200 case nir_intrinsic_discard
:
1201 case nir_intrinsic_discard_if
: {
1202 /* We track our discarded pixels in f0.1. By predicating on it, we can
1203 * update just the flag bits that aren't yet discarded. If there's no
1204 * condition, we emit a CMP of g0 != g0, so all currently executing
1205 * channels will get turned off.
1208 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1209 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1210 fs_reg(0), BRW_CONDITIONAL_Z
);
1212 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1213 BRW_REGISTER_TYPE_UW
));
1214 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1216 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1217 cmp
->flag_subreg
= 1;
1219 if (devinfo
->gen
>= 6) {
1220 emit_discard_jump();
1225 case nir_intrinsic_atomic_counter_inc
:
1226 case nir_intrinsic_atomic_counter_dec
:
1227 case nir_intrinsic_atomic_counter_read
: {
1228 using namespace surface_access
;
1230 /* Get the arguments of the atomic intrinsic. */
1231 const fs_reg offset
= get_nir_src(instr
->src
[0]);
1232 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
1233 instr
->const_index
[0]);
1236 /* Emit a surface read or atomic op. */
1237 switch (instr
->intrinsic
) {
1238 case nir_intrinsic_atomic_counter_read
:
1239 tmp
= emit_untyped_read(bld
, fs_reg(surface
), offset
, 1, 1);
1242 case nir_intrinsic_atomic_counter_inc
:
1243 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1244 fs_reg(), 1, 1, BRW_AOP_INC
);
1247 case nir_intrinsic_atomic_counter_dec
:
1248 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1249 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
1253 unreachable("Unreachable");
1256 /* Assign the result. */
1257 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
1259 /* Mark the surface as used. */
1260 brw_mark_surface_used(stage_prog_data
, surface
);
1264 case nir_intrinsic_image_load
:
1265 case nir_intrinsic_image_store
:
1266 case nir_intrinsic_image_atomic_add
:
1267 case nir_intrinsic_image_atomic_min
:
1268 case nir_intrinsic_image_atomic_max
:
1269 case nir_intrinsic_image_atomic_and
:
1270 case nir_intrinsic_image_atomic_or
:
1271 case nir_intrinsic_image_atomic_xor
:
1272 case nir_intrinsic_image_atomic_exchange
:
1273 case nir_intrinsic_image_atomic_comp_swap
: {
1274 using namespace image_access
;
1276 /* Get the referenced image variable and type. */
1277 const nir_variable
*var
= instr
->variables
[0]->var
;
1278 const glsl_type
*type
= var
->type
->without_array();
1279 const brw_reg_type base_type
= get_image_base_type(type
);
1281 /* Get some metadata from the image intrinsic. */
1282 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
1283 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
1284 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
1285 const mesa_format format
=
1286 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
1287 _mesa_get_shader_image_format(var
->data
.image
.format
));
1289 /* Get the arguments of the image intrinsic. */
1290 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
1291 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
1292 BRW_REGISTER_TYPE_UD
);
1293 const fs_reg src0
= (info
->num_srcs
>= 3 ?
1294 retype(get_nir_src(instr
->src
[2]), base_type
) :
1296 const fs_reg src1
= (info
->num_srcs
>= 4 ?
1297 retype(get_nir_src(instr
->src
[3]), base_type
) :
1301 /* Emit an image load, store or atomic op. */
1302 if (instr
->intrinsic
== nir_intrinsic_image_load
)
1303 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
1305 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
1306 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
1309 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
1310 surf_dims
, arr_dims
, info
->dest_components
,
1311 get_image_atomic_op(instr
->intrinsic
, type
));
1313 /* Assign the result. */
1314 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
1315 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
1316 offset(tmp
, bld
, c
));
1320 case nir_intrinsic_memory_barrier
: {
1321 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
1322 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
1327 case nir_intrinsic_image_size
: {
1328 /* Get the referenced image variable and type. */
1329 const nir_variable
*var
= instr
->variables
[0]->var
;
1330 const glsl_type
*type
= var
->type
->without_array();
1332 /* Get the size of the image. */
1333 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
1334 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
1336 /* For 1DArray image types, the array index is stored in the Z component.
1337 * Fix this by swizzling the Z component to the Y component.
1339 const bool is_1d_array_image
=
1340 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
1341 type
->sampler_array
;
1343 /* For CubeArray images, we should count the number of cubes instead
1344 * of the number of faces. Fix it by dividing the (Z component) by 6.
1346 const bool is_cube_array_image
=
1347 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1348 type
->sampler_array
;
1350 /* Copy all the components. */
1351 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
1352 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
1353 if ((int)c
>= type
->coordinate_components()) {
1354 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1356 } else if (c
== 1 && is_1d_array_image
) {
1357 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1358 offset(size
, bld
, 2));
1359 } else if (c
== 2 && is_cube_array_image
) {
1360 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
1361 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1362 offset(size
, bld
, c
), fs_reg(6));
1364 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1365 offset(size
, bld
, c
));
1372 case nir_intrinsic_image_samples
:
1373 /* The driver does not support multi-sampled images. */
1374 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), fs_reg(1));
1377 case nir_intrinsic_load_front_face
:
1378 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1379 *emit_frontfacing_interpolation());
1382 case nir_intrinsic_load_vertex_id
:
1383 unreachable("should be lowered by lower_vertex_id()");
1385 case nir_intrinsic_load_primitive_id
:
1386 assert(stage
== MESA_SHADER_GEOMETRY
);
1387 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
1388 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
1389 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
1392 case nir_intrinsic_load_vertex_id_zero_base
:
1393 case nir_intrinsic_load_base_vertex
:
1394 case nir_intrinsic_load_instance_id
:
1395 case nir_intrinsic_load_invocation_id
:
1396 case nir_intrinsic_load_sample_mask_in
:
1397 case nir_intrinsic_load_sample_id
: {
1398 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1399 fs_reg val
= nir_system_values
[sv
];
1400 assert(val
.file
!= BAD_FILE
);
1401 dest
.type
= val
.type
;
1406 case nir_intrinsic_load_sample_pos
: {
1407 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1408 assert(sample_pos
.file
!= BAD_FILE
);
1409 dest
.type
= sample_pos
.type
;
1410 bld
.MOV(dest
, sample_pos
);
1411 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1415 case nir_intrinsic_load_uniform_indirect
:
1416 has_indirect
= true;
1418 case nir_intrinsic_load_uniform
: {
1419 fs_reg
uniform_reg(UNIFORM
, instr
->const_index
[0]);
1420 uniform_reg
.reg_offset
= instr
->const_index
[1];
1422 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1423 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, j
);
1425 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1428 dest
= offset(dest
, bld
, 1);
1433 case nir_intrinsic_load_ubo_indirect
:
1434 has_indirect
= true;
1436 case nir_intrinsic_load_ubo
: {
1437 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1441 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1444 /* The block index is not a constant. Evaluate the index expression
1445 * per-channel and add the base UBO index; we have to select a value
1446 * from any live channel.
1448 surf_index
= vgrf(glsl_type::uint_type
);
1449 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1450 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1451 surf_index
= bld
.emit_uniformize(surf_index
);
1453 /* Assume this may touch any UBO. It would be nice to provide
1454 * a tighter bound, but the array information is already lowered away.
1456 brw_mark_surface_used(prog_data
,
1457 stage_prog_data
->binding_table
.ubo_start
+
1458 nir
->info
.num_ubos
- 1);
1462 /* Turn the byte offset into a dword offset. */
1463 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1464 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1465 BRW_REGISTER_TYPE_D
),
1468 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1469 for (int i
= 0; i
< instr
->num_components
; i
++)
1470 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
1471 base_offset
, vec4_offset
+ i
);
1473 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1474 packed_consts
.type
= dest
.type
;
1476 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1477 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1478 surf_index
, const_offset_reg
);
1480 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1481 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1483 /* The std140 packing rules don't allow vectors to cross 16-byte
1484 * boundaries, and a reg is 32 bytes.
1486 assert(packed_consts
.subreg_offset
< 32);
1488 bld
.MOV(dest
, packed_consts
);
1489 dest
= offset(dest
, bld
, 1);
1495 case nir_intrinsic_load_ssbo_indirect
:
1496 has_indirect
= true;
1498 case nir_intrinsic_load_ssbo
: {
1499 assert(devinfo
->gen
>= 7);
1501 nir_const_value
*const_uniform_block
=
1502 nir_src_as_const_value(instr
->src
[0]);
1505 if (const_uniform_block
) {
1506 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
1507 const_uniform_block
->u
[0];
1508 surf_index
= fs_reg(index
);
1509 brw_mark_surface_used(prog_data
, index
);
1511 surf_index
= vgrf(glsl_type::uint_type
);
1512 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1513 fs_reg(stage_prog_data
->binding_table
.ssbo_start
));
1514 surf_index
= bld
.emit_uniformize(surf_index
);
1516 /* Assume this may touch any UBO. It would be nice to provide
1517 * a tighter bound, but the array information is already lowered away.
1519 brw_mark_surface_used(prog_data
,
1520 stage_prog_data
->binding_table
.ssbo_start
+
1521 nir
->info
.num_ssbos
- 1);
1524 /* Get the offset to read from */
1525 fs_reg offset_reg
= vgrf(glsl_type::uint_type
);
1526 unsigned const_offset_bytes
= 0;
1528 bld
.MOV(offset_reg
, get_nir_src(instr
->src
[1]));
1530 const_offset_bytes
= instr
->const_index
[0];
1531 bld
.MOV(offset_reg
, fs_reg(const_offset_bytes
));
1534 /* Read the vector */
1535 for (int i
= 0; i
< instr
->num_components
; i
++) {
1536 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
1537 1 /* dims */, 1 /* size */,
1538 BRW_PREDICATE_NONE
);
1539 read_result
.type
= dest
.type
;
1540 bld
.MOV(dest
, read_result
);
1541 dest
= offset(dest
, bld
, 1);
1543 /* Vector components are stored contiguous in memory */
1544 if (i
< instr
->num_components
) {
1545 if (!has_indirect
) {
1546 const_offset_bytes
+= 4;
1547 bld
.MOV(offset_reg
, fs_reg(const_offset_bytes
));
1549 bld
.ADD(offset_reg
, offset_reg
, brw_imm_ud(4));
1557 case nir_intrinsic_load_input_indirect
:
1558 has_indirect
= true;
1560 case nir_intrinsic_load_input
: {
1562 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1564 if (stage
== MESA_SHADER_VERTEX
) {
1565 src
= offset(fs_reg(ATTR
, instr
->const_index
[0], dest
.type
), bld
, index
);
1567 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
1568 instr
->const_index
[0] + index
);
1571 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1575 dest
= offset(dest
, bld
, 1);
1580 /* Handle ARB_gpu_shader5 interpolation intrinsics
1582 * It's worth a quick word of explanation as to why we handle the full
1583 * variable-based interpolation intrinsic rather than a lowered version
1584 * with like we do for other inputs. We have to do that because the way
1585 * we set up inputs doesn't allow us to use the already setup inputs for
1586 * interpolation. At the beginning of the shader, we go through all of
1587 * the input variables and do the initial interpolation and put it in
1588 * the nir_inputs array based on its location as determined in
1589 * nir_lower_io. If the input isn't used, dead code cleans up and
1590 * everything works fine. However, when we get to the ARB_gpu_shader5
1591 * interpolation intrinsics, we need to reinterpolate the input
1592 * differently. If we used an intrinsic that just had an index it would
1593 * only give us the offset into the nir_inputs array. However, this is
1594 * useless because that value is post-interpolation and we need
1595 * pre-interpolation. In order to get the actual location of the bits
1596 * we get from the vertex fetching hardware, we need the variable.
1598 case nir_intrinsic_interp_var_at_centroid
:
1599 case nir_intrinsic_interp_var_at_sample
:
1600 case nir_intrinsic_interp_var_at_offset
: {
1601 assert(stage
== MESA_SHADER_FRAGMENT
);
1603 ((struct brw_wm_prog_data
*) prog_data
)->pulls_bary
= true;
1605 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1606 const glsl_interp_qualifier interpolation
=
1607 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
1609 switch (instr
->intrinsic
) {
1610 case nir_intrinsic_interp_var_at_centroid
:
1611 emit_pixel_interpolater_send(bld
,
1612 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1619 case nir_intrinsic_interp_var_at_sample
: {
1620 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1623 unsigned msg_data
= const_sample
->i
[0] << 4;
1625 emit_pixel_interpolater_send(bld
,
1626 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1632 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
1633 BRW_REGISTER_TYPE_UD
);
1635 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
1636 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1637 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1638 bld
.exec_all().group(1, 0).SHL(msg_data
, sample_id
, fs_reg(4u));
1639 emit_pixel_interpolater_send(bld
,
1640 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1646 /* Make a loop that sends a message to the pixel interpolater
1647 * for the sample number in each live channel. If there are
1648 * multiple channels with the same sample number then these
1649 * will be handled simultaneously with a single interation of
1652 bld
.emit(BRW_OPCODE_DO
);
1654 /* Get the next live sample number into sample_id_reg */
1655 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1657 /* Set the flag register so that we can perform the send
1658 * message on all channels that have the same sample number
1660 bld
.CMP(bld
.null_reg_ud(),
1661 sample_src
, sample_id
,
1662 BRW_CONDITIONAL_EQ
);
1663 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1664 bld
.exec_all().group(1, 0).SHL(msg_data
, sample_id
, fs_reg(4u));
1666 emit_pixel_interpolater_send(bld
,
1667 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1672 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
1674 /* Continue the loop if there are any live channels left */
1675 set_predicate_inv(BRW_PREDICATE_NORMAL
,
1677 bld
.emit(BRW_OPCODE_WHILE
));
1684 case nir_intrinsic_interp_var_at_offset
: {
1685 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1688 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1689 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1691 emit_pixel_interpolater_send(bld
,
1692 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
1695 fs_reg(off_x
| (off_y
<< 4)),
1698 fs_reg src
= vgrf(glsl_type::ivec2_type
);
1699 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1700 BRW_REGISTER_TYPE_F
);
1701 for (int i
= 0; i
< 2; i
++) {
1702 fs_reg temp
= vgrf(glsl_type::float_type
);
1703 bld
.MUL(temp
, offset(offset_src
, bld
, i
), fs_reg(16.0f
));
1704 fs_reg itemp
= vgrf(glsl_type::int_type
);
1705 bld
.MOV(itemp
, temp
); /* float to int */
1707 /* Clamp the upper end of the range to +7/16.
1708 * ARB_gpu_shader5 requires that we support a maximum offset
1709 * of +0.5, which isn't representable in a S0.4 value -- if
1710 * we didn't clamp it, we'd end up with -8/16, which is the
1711 * opposite of what the shader author wanted.
1713 * This is legal due to ARB_gpu_shader5's quantization
1716 * "Not all values of <offset> may be supported; x and y
1717 * offsets may be rounded to fixed-point values with the
1718 * number of fraction bits given by the
1719 * implementation-dependent constant
1720 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1722 set_condmod(BRW_CONDITIONAL_L
,
1723 bld
.SEL(offset(src
, bld
, i
), itemp
, fs_reg(7)));
1726 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
1727 emit_pixel_interpolater_send(bld
,
1738 unreachable("Invalid intrinsic");
1741 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1742 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1743 src
.type
= dest
.type
;
1745 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1746 dest
= offset(dest
, bld
, 1);
1751 case nir_intrinsic_store_ssbo_indirect
:
1752 has_indirect
= true;
1754 case nir_intrinsic_store_ssbo
: {
1755 assert(devinfo
->gen
>= 7);
1759 nir_const_value
*const_uniform_block
=
1760 nir_src_as_const_value(instr
->src
[1]);
1761 if (const_uniform_block
) {
1762 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
1763 const_uniform_block
->u
[0];
1764 surf_index
= fs_reg(index
);
1765 brw_mark_surface_used(prog_data
, index
);
1767 surf_index
= vgrf(glsl_type::uint_type
);
1768 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
1769 fs_reg(stage_prog_data
->binding_table
.ssbo_start
));
1770 surf_index
= bld
.emit_uniformize(surf_index
);
1772 brw_mark_surface_used(prog_data
,
1773 stage_prog_data
->binding_table
.ssbo_start
+
1774 nir
->info
.num_ssbos
- 1);
1778 fs_reg offset_reg
= vgrf(glsl_type::uint_type
);
1779 unsigned const_offset_bytes
= 0;
1781 bld
.MOV(offset_reg
, get_nir_src(instr
->src
[2]));
1783 const_offset_bytes
= instr
->const_index
[0];
1784 bld
.MOV(offset_reg
, fs_reg(const_offset_bytes
));
1788 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
1791 unsigned writemask
= instr
->const_index
[1];
1793 /* Write each component present in the writemask */
1794 unsigned skipped_channels
= 0;
1795 for (int i
= 0; i
< instr
->num_components
; i
++) {
1796 int component_mask
= 1 << i
;
1797 if (writemask
& component_mask
) {
1798 if (skipped_channels
) {
1799 if (!has_indirect
) {
1800 const_offset_bytes
+= 4 * skipped_channels
;
1801 bld
.MOV(offset_reg
, fs_reg(const_offset_bytes
));
1803 bld
.ADD(offset_reg
, offset_reg
,
1804 brw_imm_ud(4 * skipped_channels
));
1806 skipped_channels
= 0;
1809 emit_untyped_write(bld
, surf_index
, offset_reg
,
1810 offset(val_reg
, bld
, i
),
1811 1 /* dims */, 1 /* size */,
1812 BRW_PREDICATE_NONE
);
1820 case nir_intrinsic_store_output_indirect
:
1821 has_indirect
= true;
1823 case nir_intrinsic_store_output
: {
1824 fs_reg src
= get_nir_src(instr
->src
[0]);
1826 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1827 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
1828 instr
->const_index
[0] + index
);
1830 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1832 bld
.MOV(new_dest
, src
);
1833 src
= offset(src
, bld
, 1);
1838 case nir_intrinsic_barrier
:
1840 if (stage
== MESA_SHADER_COMPUTE
)
1841 ((struct brw_cs_prog_data
*) prog_data
)->uses_barrier
= true;
1844 case nir_intrinsic_load_local_invocation_id
:
1845 case nir_intrinsic_load_work_group_id
: {
1846 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1847 fs_reg val
= nir_system_values
[sv
];
1848 assert(val
.file
!= BAD_FILE
);
1849 dest
.type
= val
.type
;
1850 for (unsigned i
= 0; i
< 3; i
++)
1851 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
1855 case nir_intrinsic_ssbo_atomic_add
:
1856 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
1858 case nir_intrinsic_ssbo_atomic_imin
:
1859 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
1861 case nir_intrinsic_ssbo_atomic_umin
:
1862 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
1864 case nir_intrinsic_ssbo_atomic_imax
:
1865 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
1867 case nir_intrinsic_ssbo_atomic_umax
:
1868 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
1870 case nir_intrinsic_ssbo_atomic_and
:
1871 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
1873 case nir_intrinsic_ssbo_atomic_or
:
1874 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
1876 case nir_intrinsic_ssbo_atomic_xor
:
1877 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
1879 case nir_intrinsic_ssbo_atomic_exchange
:
1880 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
1882 case nir_intrinsic_ssbo_atomic_comp_swap
:
1883 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
1886 case nir_intrinsic_get_buffer_size
: {
1887 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
1888 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
1889 int reg_width
= dispatch_width
/ 8;
1892 fs_reg source
= fs_reg(0);
1894 int mlen
= 1 * reg_width
;
1895 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
1896 BRW_REGISTER_TYPE_UD
);
1897 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
1899 fs_reg surf_index
= fs_reg(prog_data
->binding_table
.ssbo_start
+ ssbo_index
);
1900 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, dest
,
1901 src_payload
, surf_index
);
1902 inst
->header_size
= 0;
1908 case nir_intrinsic_load_num_work_groups
: {
1909 assert(devinfo
->gen
>= 7);
1910 assert(stage
== MESA_SHADER_COMPUTE
);
1912 struct brw_cs_prog_data
*cs_prog_data
=
1913 (struct brw_cs_prog_data
*) prog_data
;
1914 const unsigned surface
=
1915 cs_prog_data
->binding_table
.work_groups_start
;
1917 cs_prog_data
->uses_num_work_groups
= true;
1919 fs_reg surf_index
= fs_reg(surface
);
1920 brw_mark_surface_used(prog_data
, surface
);
1922 /* Read the 3 GLuint components of gl_NumWorkGroups */
1923 for (unsigned i
= 0; i
< 3; i
++) {
1924 fs_reg read_result
=
1925 emit_untyped_read(bld
, surf_index
,
1927 1 /* dims */, 1 /* size */,
1928 BRW_PREDICATE_NONE
);
1929 read_result
.type
= dest
.type
;
1930 bld
.MOV(dest
, read_result
);
1931 dest
= offset(dest
, bld
, 1);
1937 unreachable("unknown intrinsic");
1942 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
1943 int op
, nir_intrinsic_instr
*instr
)
1946 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1947 dest
= get_nir_dest(instr
->dest
);
1950 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
1951 if (const_surface
) {
1952 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
1953 const_surface
->u
[0];
1954 surface
= fs_reg(surf_index
);
1955 brw_mark_surface_used(prog_data
, surf_index
);
1957 surface
= vgrf(glsl_type::uint_type
);
1958 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
1959 fs_reg(stage_prog_data
->binding_table
.ssbo_start
));
1961 /* Assume this may touch any SSBO. This is the same we do for other
1962 * UBO/SSBO accesses with non-constant surface.
1964 brw_mark_surface_used(prog_data
,
1965 stage_prog_data
->binding_table
.ssbo_start
+
1966 nir
->info
.num_ssbos
- 1);
1969 fs_reg offset
= get_nir_src(instr
->src
[1]);
1970 fs_reg data1
= get_nir_src(instr
->src
[2]);
1972 if (op
== BRW_AOP_CMPWR
)
1973 data2
= get_nir_src(instr
->src
[3]);
1975 /* Emit the actual atomic operation operation */
1977 fs_reg atomic_result
=
1978 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
1980 1 /* dims */, 1 /* rsize */,
1982 BRW_PREDICATE_NONE
);
1983 dest
.type
= atomic_result
.type
;
1984 bld
.MOV(dest
, atomic_result
);
1988 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1990 unsigned sampler
= instr
->sampler_index
;
1991 fs_reg
sampler_reg(sampler
);
1993 int gather_component
= instr
->component
;
1995 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1997 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
2000 int lod_components
= 0;
2001 int UNUSED offset_components
= 0;
2003 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
2005 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2006 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
2007 switch (instr
->src
[i
].src_type
) {
2008 case nir_tex_src_bias
:
2009 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2011 case nir_tex_src_comparitor
:
2012 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
2014 case nir_tex_src_coord
:
2015 switch (instr
->op
) {
2017 case nir_texop_txf_ms
:
2018 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
2021 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
2025 case nir_tex_src_ddx
:
2026 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2027 lod_components
= nir_tex_instr_src_size(instr
, i
);
2029 case nir_tex_src_ddy
:
2030 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
2032 case nir_tex_src_lod
:
2033 switch (instr
->op
) {
2035 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
2038 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
2041 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2045 case nir_tex_src_ms_index
:
2046 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
2048 case nir_tex_src_offset
:
2049 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
2050 if (instr
->is_array
)
2051 offset_components
= instr
->coord_components
- 1;
2053 offset_components
= instr
->coord_components
;
2055 case nir_tex_src_projector
:
2056 unreachable("should be lowered");
2058 case nir_tex_src_sampler_offset
: {
2059 /* Figure out the highest possible sampler index and mark it as used */
2060 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
2061 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
2062 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
2064 max_used
+= stage_prog_data
->binding_table
.texture_start
;
2066 brw_mark_surface_used(prog_data
, max_used
);
2068 /* Emit code to evaluate the actual indexing expression */
2069 sampler_reg
= vgrf(glsl_type::uint_type
);
2070 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
2071 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
2076 unreachable("unknown texture source");
2080 if (instr
->op
== nir_texop_txf_ms
) {
2081 if (devinfo
->gen
>= 7 &&
2082 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
2083 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
2089 for (unsigned i
= 0; i
< 3; i
++) {
2090 if (instr
->const_offset
[i
] != 0) {
2091 assert(offset_components
== 0);
2092 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
2097 enum glsl_base_type dest_base_type
=
2098 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
2100 const glsl_type
*dest_type
=
2101 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
2104 ir_texture_opcode op
;
2105 switch (instr
->op
) {
2106 case nir_texop_lod
: op
= ir_lod
; break;
2107 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2108 case nir_texop_tex
: op
= ir_tex
; break;
2109 case nir_texop_tg4
: op
= ir_tg4
; break;
2110 case nir_texop_txb
: op
= ir_txb
; break;
2111 case nir_texop_txd
: op
= ir_txd
; break;
2112 case nir_texop_txf
: op
= ir_txf
; break;
2113 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2114 case nir_texop_txl
: op
= ir_txl
; break;
2115 case nir_texop_txs
: op
= ir_txs
; break;
2116 case nir_texop_texture_samples
: {
2117 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
2118 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
2119 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
2122 inst
->header_size
= 1;
2123 inst
->base_mrf
= -1;
2127 unreachable("unknown texture opcode");
2130 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
2131 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
2132 tex_offset
, mcs
, gather_component
,
2133 is_cube_array
, is_rect
, sampler
, sampler_reg
);
2135 fs_reg dest
= get_nir_dest(instr
->dest
);
2136 dest
.type
= this->result
.type
;
2137 unsigned num_components
= nir_tex_instr_dest_size(instr
);
2138 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
2139 dest
, this->result
),
2140 (1 << num_components
) - 1);
2144 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
2146 switch (instr
->type
) {
2147 case nir_jump_break
:
2148 bld
.emit(BRW_OPCODE_BREAK
);
2150 case nir_jump_continue
:
2151 bld
.emit(BRW_OPCODE_CONTINUE
);
2153 case nir_jump_return
:
2155 unreachable("unknown jump");