2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "main/shaderimage.h"
28 #include "program/prog_to_nir.h"
30 #include "brw_fs_surface_builder.h"
32 #include "brw_fs_surface_builder.h"
35 using namespace brw::surface_access
;
38 fs_visitor::emit_nir_code()
40 /* emit the arrays used for inputs and outputs - load/store intrinsics will
41 * be converted to reads/writes of these arrays
46 nir_emit_system_values();
48 /* get the main function and emit it */
49 nir_foreach_overload(nir
, overload
) {
50 assert(strcmp(overload
->function
->name
, "main") == 0);
51 assert(overload
->impl
);
52 nir_emit_impl(overload
->impl
);
57 fs_visitor::nir_setup_inputs()
59 if (stage
!= MESA_SHADER_FRAGMENT
)
62 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
64 nir_foreach_variable(var
, &nir
->inputs
) {
65 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
68 if (var
->data
.location
== VARYING_SLOT_POS
) {
69 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
70 var
->data
.origin_upper_left
);
71 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
74 emit_general_interpolation(input
, var
->name
, var
->type
,
75 (glsl_interp_qualifier
) var
->data
.interpolation
,
76 var
->data
.location
, var
->data
.centroid
,
83 fs_visitor::nir_setup_outputs()
85 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
87 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
89 nir_foreach_variable(var
, &nir
->outputs
) {
90 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
93 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
94 : var
->type
->vector_elements
;
97 case MESA_SHADER_VERTEX
:
98 for (unsigned int i
= 0; i
< ALIGN(type_size_scalar(var
->type
), 4) / 4; i
++) {
99 int output
= var
->data
.location
+ i
;
100 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
101 this->output_components
[output
] = vector_elements
;
104 case MESA_SHADER_FRAGMENT
:
105 if (var
->data
.index
> 0) {
106 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
107 assert(var
->data
.index
== 1);
108 this->dual_src_output
= reg
;
109 this->do_dual_src
= true;
110 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
111 /* Writing gl_FragColor outputs to all color regions. */
112 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
113 this->outputs
[i
] = reg
;
114 this->output_components
[i
] = 4;
116 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
117 this->frag_depth
= reg
;
118 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
119 this->sample_mask
= reg
;
121 /* gl_FragData or a user-defined FS output */
122 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
123 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
125 /* General color output. */
126 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
127 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
128 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
129 this->output_components
[output
] = vector_elements
;
134 unreachable("unhandled shader stage");
140 fs_visitor::nir_setup_uniforms()
142 if (dispatch_width
!= 8)
145 uniforms
= nir
->num_uniforms
;
147 nir_foreach_variable(var
, &nir
->uniforms
) {
148 /* UBO's and atomics don't take up space in the uniform file */
149 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
152 if (type_size_scalar(var
->type
) > 0)
153 param_size
[var
->data
.driver_location
] = type_size_scalar(var
->type
);
158 emit_system_values_block(nir_block
*block
, void *void_visitor
)
160 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
163 nir_foreach_instr(block
, instr
) {
164 if (instr
->type
!= nir_instr_type_intrinsic
)
167 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
168 switch (intrin
->intrinsic
) {
169 case nir_intrinsic_load_vertex_id
:
170 unreachable("should be lowered by lower_vertex_id().");
172 case nir_intrinsic_load_vertex_id_zero_base
:
173 assert(v
->stage
== MESA_SHADER_VERTEX
);
174 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
175 if (reg
->file
== BAD_FILE
)
176 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
179 case nir_intrinsic_load_base_vertex
:
180 assert(v
->stage
== MESA_SHADER_VERTEX
);
181 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
182 if (reg
->file
== BAD_FILE
)
183 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
186 case nir_intrinsic_load_instance_id
:
187 assert(v
->stage
== MESA_SHADER_VERTEX
);
188 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
189 if (reg
->file
== BAD_FILE
)
190 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
193 case nir_intrinsic_load_sample_pos
:
194 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
195 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
196 if (reg
->file
== BAD_FILE
)
197 *reg
= *v
->emit_samplepos_setup();
200 case nir_intrinsic_load_sample_id
:
201 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
202 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
203 if (reg
->file
== BAD_FILE
)
204 *reg
= *v
->emit_sampleid_setup();
207 case nir_intrinsic_load_sample_mask_in
:
208 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
209 assert(v
->devinfo
->gen
>= 7);
210 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
211 if (reg
->file
== BAD_FILE
)
212 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
213 BRW_REGISTER_TYPE_D
));
216 case nir_intrinsic_load_local_invocation_id
:
217 assert(v
->stage
== MESA_SHADER_COMPUTE
);
218 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
219 if (reg
->file
== BAD_FILE
)
220 *reg
= *v
->emit_cs_local_invocation_id_setup();
223 case nir_intrinsic_load_work_group_id
:
224 assert(v
->stage
== MESA_SHADER_COMPUTE
);
225 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
226 if (reg
->file
== BAD_FILE
)
227 *reg
= *v
->emit_cs_work_group_id_setup();
239 fs_visitor::nir_emit_system_values()
241 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
242 nir_foreach_overload(nir
, overload
) {
243 assert(strcmp(overload
->function
->name
, "main") == 0);
244 assert(overload
->impl
);
245 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
250 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
252 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
253 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
254 unsigned array_elems
=
255 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
256 unsigned size
= array_elems
* reg
->num_components
;
257 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
260 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
263 nir_emit_cf_list(&impl
->body
);
267 fs_visitor::nir_emit_cf_list(exec_list
*list
)
269 exec_list_validate(list
);
270 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
271 switch (node
->type
) {
273 nir_emit_if(nir_cf_node_as_if(node
));
276 case nir_cf_node_loop
:
277 nir_emit_loop(nir_cf_node_as_loop(node
));
280 case nir_cf_node_block
:
281 nir_emit_block(nir_cf_node_as_block(node
));
285 unreachable("Invalid CFG node block");
291 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
293 /* first, put the condition into f0 */
294 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
295 retype(get_nir_src(if_stmt
->condition
),
296 BRW_REGISTER_TYPE_D
));
297 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
299 bld
.IF(BRW_PREDICATE_NORMAL
);
301 nir_emit_cf_list(&if_stmt
->then_list
);
303 /* note: if the else is empty, dead CF elimination will remove it */
304 bld
.emit(BRW_OPCODE_ELSE
);
306 nir_emit_cf_list(&if_stmt
->else_list
);
308 bld
.emit(BRW_OPCODE_ENDIF
);
312 fs_visitor::nir_emit_loop(nir_loop
*loop
)
314 bld
.emit(BRW_OPCODE_DO
);
316 nir_emit_cf_list(&loop
->body
);
318 bld
.emit(BRW_OPCODE_WHILE
);
322 fs_visitor::nir_emit_block(nir_block
*block
)
324 nir_foreach_instr(block
, instr
) {
325 nir_emit_instr(instr
);
330 fs_visitor::nir_emit_instr(nir_instr
*instr
)
332 const fs_builder abld
= bld
.annotate(NULL
, instr
);
334 switch (instr
->type
) {
335 case nir_instr_type_alu
:
336 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
339 case nir_instr_type_intrinsic
:
340 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
343 case nir_instr_type_tex
:
344 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
347 case nir_instr_type_load_const
:
348 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
351 case nir_instr_type_ssa_undef
:
352 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
355 case nir_instr_type_jump
:
356 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
360 unreachable("unknown instruction type");
365 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
366 const fs_reg
&result
)
368 if (!instr
->src
[0].src
.is_ssa
||
369 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
372 nir_intrinsic_instr
*src0
=
373 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
375 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
378 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
379 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
382 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
383 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
386 fs_reg tmp
= vgrf(glsl_type::int_type
);
388 if (devinfo
->gen
>= 6) {
389 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
390 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
392 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
394 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
395 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
397 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
399 * This negation looks like it's safe in practice, because bits 0:4 will
400 * surely be TRIANGLES
403 if (value1
->f
[0] == -1.0f
) {
407 tmp
.type
= BRW_REGISTER_TYPE_W
;
408 tmp
.subreg_offset
= 2;
411 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
412 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
414 tmp
.type
= BRW_REGISTER_TYPE_D
;
415 tmp
.subreg_offset
= 0;
418 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
419 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
421 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
423 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
424 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
426 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
428 * This negation looks like it's safe in practice, because bits 0:4 will
429 * surely be TRIANGLES
432 if (value1
->f
[0] == -1.0f
) {
436 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
438 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
444 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
446 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
449 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
450 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
453 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
454 op
[i
] = get_nir_src(instr
->src
[i
].src
);
455 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
456 op
[i
].abs
= instr
->src
[i
].abs
;
457 op
[i
].negate
= instr
->src
[i
].negate
;
460 /* We get a bunch of mov's out of the from_ssa pass and they may still
461 * be vectorized. We'll handle them as a special-case. We'll also
462 * handle vecN here because it's basically the same thing.
470 fs_reg temp
= result
;
471 bool need_extra_copy
= false;
472 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
473 if (!instr
->src
[i
].src
.is_ssa
&&
474 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
475 need_extra_copy
= true;
476 temp
= bld
.vgrf(result
.type
, 4);
481 for (unsigned i
= 0; i
< 4; i
++) {
482 if (!(instr
->dest
.write_mask
& (1 << i
)))
485 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
486 inst
= bld
.MOV(offset(temp
, bld
, i
),
487 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
489 inst
= bld
.MOV(offset(temp
, bld
, i
),
490 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
492 inst
->saturate
= instr
->dest
.saturate
;
495 /* In this case the source and destination registers were the same,
496 * so we need to insert an extra set of moves in order to deal with
499 if (need_extra_copy
) {
500 for (unsigned i
= 0; i
< 4; i
++) {
501 if (!(instr
->dest
.write_mask
& (1 << i
)))
504 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
513 /* At this point, we have dealt with any instruction that operates on
514 * more than a single channel. Therefore, we can just adjust the source
515 * and destination registers for that channel and emit the instruction.
517 unsigned channel
= 0;
518 if (nir_op_infos
[instr
->op
].output_size
== 0) {
519 /* Since NIR is doing the scalarizing for us, we should only ever see
520 * vectorized operations with a single channel.
522 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
523 channel
= ffs(instr
->dest
.write_mask
) - 1;
525 result
= offset(result
, bld
, channel
);
528 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
529 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
530 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
536 inst
= bld
.MOV(result
, op
[0]);
537 inst
->saturate
= instr
->dest
.saturate
;
542 bld
.MOV(result
, op
[0]);
546 /* AND(val, 0x80000000) gives the sign bit.
548 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
551 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
553 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
554 op
[0].type
= BRW_REGISTER_TYPE_UD
;
555 result
.type
= BRW_REGISTER_TYPE_UD
;
556 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
558 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
559 inst
->predicate
= BRW_PREDICATE_NORMAL
;
560 if (instr
->dest
.saturate
) {
561 inst
= bld
.MOV(result
, result
);
562 inst
->saturate
= true;
568 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
569 * -> non-negative val generates 0x00000000.
570 * Predicated OR sets 1 if val is positive.
572 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
573 bld
.ASR(result
, op
[0], fs_reg(31));
574 inst
= bld
.OR(result
, result
, fs_reg(1));
575 inst
->predicate
= BRW_PREDICATE_NORMAL
;
579 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
580 inst
->saturate
= instr
->dest
.saturate
;
584 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
585 inst
->saturate
= instr
->dest
.saturate
;
589 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
590 inst
->saturate
= instr
->dest
.saturate
;
594 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
595 inst
->saturate
= instr
->dest
.saturate
;
599 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
600 inst
->saturate
= instr
->dest
.saturate
;
604 if (fs_key
->high_quality_derivatives
) {
605 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
607 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
609 inst
->saturate
= instr
->dest
.saturate
;
611 case nir_op_fddx_fine
:
612 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
613 inst
->saturate
= instr
->dest
.saturate
;
615 case nir_op_fddx_coarse
:
616 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
617 inst
->saturate
= instr
->dest
.saturate
;
620 if (fs_key
->high_quality_derivatives
) {
621 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
622 fs_reg(fs_key
->render_to_fbo
));
624 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
625 fs_reg(fs_key
->render_to_fbo
));
627 inst
->saturate
= instr
->dest
.saturate
;
629 case nir_op_fddy_fine
:
630 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
631 fs_reg(fs_key
->render_to_fbo
));
632 inst
->saturate
= instr
->dest
.saturate
;
634 case nir_op_fddy_coarse
:
635 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
636 fs_reg(fs_key
->render_to_fbo
));
637 inst
->saturate
= instr
->dest
.saturate
;
642 inst
= bld
.ADD(result
, op
[0], op
[1]);
643 inst
->saturate
= instr
->dest
.saturate
;
647 inst
= bld
.MUL(result
, op
[0], op
[1]);
648 inst
->saturate
= instr
->dest
.saturate
;
652 bld
.MUL(result
, op
[0], op
[1]);
655 case nir_op_imul_high
:
656 case nir_op_umul_high
:
657 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
662 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
665 case nir_op_uadd_carry
:
666 unreachable("Should have been lowered by carry_to_arith().");
668 case nir_op_usub_borrow
:
669 unreachable("Should have been lowered by borrow_to_arith().");
672 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
678 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
684 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
689 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
694 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
698 if (devinfo
->gen
>= 8) {
699 op
[0] = resolve_source_modifiers(op
[0]);
701 bld
.NOT(result
, op
[0]);
704 if (devinfo
->gen
>= 8) {
705 op
[0] = resolve_source_modifiers(op
[0]);
706 op
[1] = resolve_source_modifiers(op
[1]);
708 bld
.XOR(result
, op
[0], op
[1]);
711 if (devinfo
->gen
>= 8) {
712 op
[0] = resolve_source_modifiers(op
[0]);
713 op
[1] = resolve_source_modifiers(op
[1]);
715 bld
.OR(result
, op
[0], op
[1]);
718 if (devinfo
->gen
>= 8) {
719 op
[0] = resolve_source_modifiers(op
[0]);
720 op
[1] = resolve_source_modifiers(op
[1]);
722 bld
.AND(result
, op
[0], op
[1]);
734 case nir_op_ball_fequal2
:
735 case nir_op_ball_iequal2
:
736 case nir_op_ball_fequal3
:
737 case nir_op_ball_iequal3
:
738 case nir_op_ball_fequal4
:
739 case nir_op_ball_iequal4
:
740 case nir_op_bany_fnequal2
:
741 case nir_op_bany_inequal2
:
742 case nir_op_bany_fnequal3
:
743 case nir_op_bany_inequal3
:
744 case nir_op_bany_fnequal4
:
745 case nir_op_bany_inequal4
:
746 unreachable("Lowered by nir_lower_alu_reductions");
748 case nir_op_fnoise1_1
:
749 case nir_op_fnoise1_2
:
750 case nir_op_fnoise1_3
:
751 case nir_op_fnoise1_4
:
752 case nir_op_fnoise2_1
:
753 case nir_op_fnoise2_2
:
754 case nir_op_fnoise2_3
:
755 case nir_op_fnoise2_4
:
756 case nir_op_fnoise3_1
:
757 case nir_op_fnoise3_2
:
758 case nir_op_fnoise3_3
:
759 case nir_op_fnoise3_4
:
760 case nir_op_fnoise4_1
:
761 case nir_op_fnoise4_2
:
762 case nir_op_fnoise4_3
:
763 case nir_op_fnoise4_4
:
764 unreachable("not reached: should be handled by lower_noise");
767 unreachable("not reached: should be handled by ldexp_to_arith()");
770 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
771 inst
->saturate
= instr
->dest
.saturate
;
775 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
776 inst
->saturate
= instr
->dest
.saturate
;
781 bld
.MOV(result
, negate(op
[0]));
785 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
788 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
792 inst
= bld
.RNDZ(result
, op
[0]);
793 inst
->saturate
= instr
->dest
.saturate
;
797 op
[0].negate
= !op
[0].negate
;
798 fs_reg temp
= vgrf(glsl_type::float_type
);
799 bld
.RNDD(temp
, op
[0]);
801 inst
= bld
.MOV(result
, temp
);
802 inst
->saturate
= instr
->dest
.saturate
;
806 inst
= bld
.RNDD(result
, op
[0]);
807 inst
->saturate
= instr
->dest
.saturate
;
810 inst
= bld
.FRC(result
, op
[0]);
811 inst
->saturate
= instr
->dest
.saturate
;
813 case nir_op_fround_even
:
814 inst
= bld
.RNDE(result
, op
[0]);
815 inst
->saturate
= instr
->dest
.saturate
;
821 if (devinfo
->gen
>= 6) {
822 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
823 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
825 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
826 inst
= bld
.SEL(result
, op
[0], op
[1]);
827 inst
->predicate
= BRW_PREDICATE_NORMAL
;
829 inst
->saturate
= instr
->dest
.saturate
;
835 if (devinfo
->gen
>= 6) {
836 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
837 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
839 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
840 inst
= bld
.SEL(result
, op
[0], op
[1]);
841 inst
->predicate
= BRW_PREDICATE_NORMAL
;
843 inst
->saturate
= instr
->dest
.saturate
;
846 case nir_op_pack_snorm_2x16
:
847 case nir_op_pack_snorm_4x8
:
848 case nir_op_pack_unorm_2x16
:
849 case nir_op_pack_unorm_4x8
:
850 case nir_op_unpack_snorm_2x16
:
851 case nir_op_unpack_snorm_4x8
:
852 case nir_op_unpack_unorm_2x16
:
853 case nir_op_unpack_unorm_4x8
:
854 case nir_op_unpack_half_2x16
:
855 case nir_op_pack_half_2x16
:
856 unreachable("not reached: should be handled by lower_packing_builtins");
858 case nir_op_unpack_half_2x16_split_x
:
859 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
860 inst
->saturate
= instr
->dest
.saturate
;
862 case nir_op_unpack_half_2x16_split_y
:
863 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
864 inst
->saturate
= instr
->dest
.saturate
;
868 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
869 inst
->saturate
= instr
->dest
.saturate
;
872 case nir_op_bitfield_reverse
:
873 bld
.BFREV(result
, op
[0]);
876 case nir_op_bit_count
:
877 bld
.CBIT(result
, op
[0]);
880 case nir_op_ufind_msb
:
881 case nir_op_ifind_msb
: {
882 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
884 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
885 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
886 * subtract the result from 31 to convert the MSB count into an LSB count.
889 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
890 fs_reg
neg_result(result
);
891 neg_result
.negate
= true;
892 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
893 inst
->predicate
= BRW_PREDICATE_NORMAL
;
897 case nir_op_find_lsb
:
898 bld
.FBL(result
, op
[0]);
901 case nir_op_ubitfield_extract
:
902 case nir_op_ibitfield_extract
:
903 bld
.BFE(result
, op
[2], op
[1], op
[0]);
906 bld
.BFI1(result
, op
[0], op
[1]);
909 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
912 case nir_op_bitfield_insert
:
913 unreachable("not reached: should be handled by "
914 "lower_instructions::bitfield_insert_to_bfm_bfi");
917 bld
.SHL(result
, op
[0], op
[1]);
920 bld
.ASR(result
, op
[0], op
[1]);
923 bld
.SHR(result
, op
[0], op
[1]);
926 case nir_op_pack_half_2x16_split
:
927 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
931 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
932 inst
->saturate
= instr
->dest
.saturate
;
936 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
937 inst
->saturate
= instr
->dest
.saturate
;
941 if (optimize_frontfacing_ternary(instr
, result
))
944 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
945 inst
= bld
.SEL(result
, op
[1], op
[2]);
946 inst
->predicate
= BRW_PREDICATE_NORMAL
;
950 unreachable("unhandled instruction");
953 /* If we need to do a boolean resolve, replace the result with -(x & 1)
954 * to sign extend the low bit to 0/~0
956 if (devinfo
->gen
<= 5 &&
957 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
958 fs_reg masked
= vgrf(glsl_type::int_type
);
959 bld
.AND(masked
, result
, fs_reg(1));
960 masked
.negate
= true;
961 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
966 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
967 nir_load_const_instr
*instr
)
969 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
971 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
972 bld
.MOV(offset(reg
, bld
, i
), fs_reg(instr
->value
.i
[i
]));
974 nir_ssa_values
[instr
->def
.index
] = reg
;
978 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
980 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
981 instr
->def
.num_components
);
985 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
986 unsigned base_offset
, nir_src
*indirect
)
990 assert(!nir_reg
->is_global
);
992 reg
= v
->nir_locals
[nir_reg
->index
];
994 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
996 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
998 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
999 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1000 fs_reg(multiplier
));
1007 fs_visitor::get_nir_src(nir_src src
)
1011 reg
= nir_ssa_values
[src
.ssa
->index
];
1013 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1017 /* to avoid floating-point denorm flushing problems, set the type by
1018 * default to D - instructions that need floating point semantics will set
1019 * this to F if they need to
1021 return retype(reg
, BRW_REGISTER_TYPE_D
);
1025 fs_visitor::get_nir_dest(nir_dest dest
)
1028 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1029 dest
.ssa
.num_components
);
1030 return nir_ssa_values
[dest
.ssa
.index
];
1033 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1038 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1040 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
,
1041 BRW_REGISTER_TYPE_UD
);
1043 if (deref
->deref
.child
) {
1044 const nir_deref_array
*deref_array
=
1045 nir_deref_as_array(deref
->deref
.child
);
1046 assert(deref
->deref
.child
->deref_type
== nir_deref_type_array
&&
1047 deref_array
->deref
.child
== NULL
);
1048 const unsigned size
= glsl_get_length(deref
->var
->type
);
1049 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1051 image
= offset(image
, bld
, base
* BRW_IMAGE_PARAM_SIZE
);
1053 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1054 fs_reg
*tmp
= new(mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1056 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1057 /* IVB hangs when trying to access an invalid surface index with
1058 * the dataport. According to the spec "if the index used to
1059 * select an individual element is negative or greater than or
1060 * equal to the size of the array, the results of the operation
1061 * are undefined but may not lead to termination" -- which is one
1062 * of the possible outcomes of the hang. Clamp the index to
1063 * prevent access outside of the array bounds.
1065 bld
.emit_minmax(*tmp
, retype(get_nir_src(deref_array
->indirect
),
1066 BRW_REGISTER_TYPE_UD
),
1067 fs_reg(size
- base
- 1), BRW_CONDITIONAL_L
);
1069 bld
.MOV(*tmp
, get_nir_src(deref_array
->indirect
));
1072 bld
.MUL(*tmp
, *tmp
, fs_reg(BRW_IMAGE_PARAM_SIZE
));
1073 image
.reladdr
= tmp
;
1081 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1084 for (unsigned i
= 0; i
< 4; i
++) {
1085 if (!((wr_mask
>> i
) & 1))
1088 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1089 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1090 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1091 if (new_inst
->src
[j
].file
== GRF
)
1092 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1099 * Get the matching channel register datatype for an image intrinsic of the
1100 * specified GLSL image type.
1103 get_image_base_type(const glsl_type
*type
)
1105 switch ((glsl_base_type
)type
->sampler_type
) {
1106 case GLSL_TYPE_UINT
:
1107 return BRW_REGISTER_TYPE_UD
;
1109 return BRW_REGISTER_TYPE_D
;
1110 case GLSL_TYPE_FLOAT
:
1111 return BRW_REGISTER_TYPE_F
;
1113 unreachable("Not reached.");
1118 * Get the appropriate atomic op for an image atomic intrinsic.
1121 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1124 case nir_intrinsic_image_atomic_add
:
1126 case nir_intrinsic_image_atomic_min
:
1127 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1128 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1129 case nir_intrinsic_image_atomic_max
:
1130 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1131 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1132 case nir_intrinsic_image_atomic_and
:
1134 case nir_intrinsic_image_atomic_or
:
1136 case nir_intrinsic_image_atomic_xor
:
1138 case nir_intrinsic_image_atomic_exchange
:
1140 case nir_intrinsic_image_atomic_comp_swap
:
1141 return BRW_AOP_CMPWR
;
1143 unreachable("Not reachable.");
1148 emit_pixel_interpolater_send(const fs_builder
&bld
,
1153 glsl_interp_qualifier interpolation
)
1159 if (src
.file
== BAD_FILE
) {
1161 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1165 mlen
= 2 * bld
.dispatch_width() / 8;
1168 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1170 /* 2 floats per slot returned */
1171 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1172 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1178 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1181 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1182 dest
= get_nir_dest(instr
->dest
);
1184 bool has_indirect
= false;
1186 switch (instr
->intrinsic
) {
1187 case nir_intrinsic_discard
:
1188 case nir_intrinsic_discard_if
: {
1189 /* We track our discarded pixels in f0.1. By predicating on it, we can
1190 * update just the flag bits that aren't yet discarded. If there's no
1191 * condition, we emit a CMP of g0 != g0, so all currently executing
1192 * channels will get turned off.
1195 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1196 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1197 fs_reg(0), BRW_CONDITIONAL_Z
);
1199 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1200 BRW_REGISTER_TYPE_UW
));
1201 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1203 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1204 cmp
->flag_subreg
= 1;
1206 if (devinfo
->gen
>= 6) {
1207 emit_discard_jump();
1212 case nir_intrinsic_atomic_counter_inc
:
1213 case nir_intrinsic_atomic_counter_dec
:
1214 case nir_intrinsic_atomic_counter_read
: {
1215 using namespace surface_access
;
1217 /* Get the arguments of the atomic intrinsic. */
1218 const fs_reg offset
= get_nir_src(instr
->src
[0]);
1219 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
1220 instr
->const_index
[0]);
1223 /* Emit a surface read or atomic op. */
1224 switch (instr
->intrinsic
) {
1225 case nir_intrinsic_atomic_counter_read
:
1226 tmp
= emit_untyped_read(bld
, fs_reg(surface
), offset
, 1, 1);
1229 case nir_intrinsic_atomic_counter_inc
:
1230 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1231 fs_reg(), 1, 1, BRW_AOP_INC
);
1234 case nir_intrinsic_atomic_counter_dec
:
1235 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1236 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
1240 unreachable("Unreachable");
1243 /* Assign the result. */
1244 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
1246 /* Mark the surface as used. */
1247 brw_mark_surface_used(stage_prog_data
, surface
);
1251 case nir_intrinsic_image_load
:
1252 case nir_intrinsic_image_store
:
1253 case nir_intrinsic_image_atomic_add
:
1254 case nir_intrinsic_image_atomic_min
:
1255 case nir_intrinsic_image_atomic_max
:
1256 case nir_intrinsic_image_atomic_and
:
1257 case nir_intrinsic_image_atomic_or
:
1258 case nir_intrinsic_image_atomic_xor
:
1259 case nir_intrinsic_image_atomic_exchange
:
1260 case nir_intrinsic_image_atomic_comp_swap
: {
1261 using namespace image_access
;
1263 /* Get the referenced image variable and type. */
1264 const nir_variable
*var
= instr
->variables
[0]->var
;
1265 const glsl_type
*type
= var
->type
->without_array();
1266 const brw_reg_type base_type
= get_image_base_type(type
);
1268 /* Get some metadata from the image intrinsic. */
1269 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
1270 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
1271 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
1272 const mesa_format format
=
1273 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
1274 _mesa_get_shader_image_format(var
->data
.image
.format
));
1276 /* Get the arguments of the image intrinsic. */
1277 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
1278 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
1279 BRW_REGISTER_TYPE_UD
);
1280 const fs_reg src0
= (info
->num_srcs
>= 3 ?
1281 retype(get_nir_src(instr
->src
[2]), base_type
) :
1283 const fs_reg src1
= (info
->num_srcs
>= 4 ?
1284 retype(get_nir_src(instr
->src
[3]), base_type
) :
1288 /* Emit an image load, store or atomic op. */
1289 if (instr
->intrinsic
== nir_intrinsic_image_load
)
1290 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
1292 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
1293 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
1296 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
1297 surf_dims
, arr_dims
, info
->dest_components
,
1298 get_image_atomic_op(instr
->intrinsic
, type
));
1300 /* Assign the result. */
1301 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
1302 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
1303 offset(tmp
, bld
, c
));
1307 case nir_intrinsic_memory_barrier
: {
1308 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
1309 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
1314 case nir_intrinsic_image_size
: {
1315 /* Get the referenced image variable and type. */
1316 const nir_variable
*var
= instr
->variables
[0]->var
;
1317 const glsl_type
*type
= var
->type
->without_array();
1319 /* Get the size of the image. */
1320 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
1321 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
1323 /* For 1DArray image types, the array index is stored in the Z component.
1324 * Fix this by swizzling the Z component to the Y component.
1326 const bool is_1d_array_image
=
1327 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
1328 type
->sampler_array
;
1330 /* For CubeArray images, we should count the number of cubes instead
1331 * of the number of faces. Fix it by dividing the (Z component) by 6.
1333 const bool is_cube_array_image
=
1334 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1335 type
->sampler_array
;
1337 /* Copy all the components. */
1338 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
1339 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
1340 if ((int)c
>= type
->coordinate_components()) {
1341 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1343 } else if (c
== 1 && is_1d_array_image
) {
1344 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1345 offset(size
, bld
, 2));
1346 } else if (c
== 2 && is_cube_array_image
) {
1347 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
1348 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1349 offset(size
, bld
, c
), fs_reg(6));
1351 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1352 offset(size
, bld
, c
));
1359 case nir_intrinsic_image_samples
:
1360 /* The driver does not support multi-sampled images. */
1361 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), fs_reg(1));
1364 case nir_intrinsic_load_front_face
:
1365 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1366 *emit_frontfacing_interpolation());
1369 case nir_intrinsic_load_vertex_id
:
1370 unreachable("should be lowered by lower_vertex_id()");
1372 case nir_intrinsic_load_vertex_id_zero_base
:
1373 case nir_intrinsic_load_base_vertex
:
1374 case nir_intrinsic_load_instance_id
:
1375 case nir_intrinsic_load_sample_mask_in
:
1376 case nir_intrinsic_load_sample_id
: {
1377 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1378 fs_reg val
= nir_system_values
[sv
];
1379 assert(val
.file
!= BAD_FILE
);
1380 dest
.type
= val
.type
;
1385 case nir_intrinsic_load_sample_pos
: {
1386 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1387 assert(sample_pos
.file
!= BAD_FILE
);
1388 dest
.type
= sample_pos
.type
;
1389 bld
.MOV(dest
, sample_pos
);
1390 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1394 case nir_intrinsic_load_uniform_indirect
:
1395 has_indirect
= true;
1397 case nir_intrinsic_load_uniform
: {
1398 fs_reg
uniform_reg(UNIFORM
, instr
->const_index
[0]);
1399 uniform_reg
.reg_offset
= instr
->const_index
[1];
1401 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1402 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, j
);
1404 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1407 dest
= offset(dest
, bld
, 1);
1412 case nir_intrinsic_load_ubo_indirect
:
1413 has_indirect
= true;
1415 case nir_intrinsic_load_ubo
: {
1416 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1420 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1423 /* The block index is not a constant. Evaluate the index expression
1424 * per-channel and add the base UBO index; we have to select a value
1425 * from any live channel.
1427 surf_index
= vgrf(glsl_type::uint_type
);
1428 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1429 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1430 surf_index
= bld
.emit_uniformize(surf_index
);
1432 /* Assume this may touch any UBO. It would be nice to provide
1433 * a tighter bound, but the array information is already lowered away.
1435 brw_mark_surface_used(prog_data
,
1436 stage_prog_data
->binding_table
.ubo_start
+
1437 nir
->info
.num_ssbos
- 1);
1441 /* Turn the byte offset into a dword offset. */
1442 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1443 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1444 BRW_REGISTER_TYPE_D
),
1447 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1448 for (int i
= 0; i
< instr
->num_components
; i
++)
1449 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
1450 base_offset
, vec4_offset
+ i
);
1452 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1453 packed_consts
.type
= dest
.type
;
1455 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1456 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1457 surf_index
, const_offset_reg
);
1459 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1460 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1462 /* The std140 packing rules don't allow vectors to cross 16-byte
1463 * boundaries, and a reg is 32 bytes.
1465 assert(packed_consts
.subreg_offset
< 32);
1467 bld
.MOV(dest
, packed_consts
);
1468 dest
= offset(dest
, bld
, 1);
1474 case nir_intrinsic_load_ssbo_indirect
:
1475 has_indirect
= true;
1477 case nir_intrinsic_load_ssbo
: {
1478 assert(devinfo
->gen
>= 7);
1480 nir_const_value
*const_uniform_block
=
1481 nir_src_as_const_value(instr
->src
[0]);
1484 if (const_uniform_block
) {
1485 unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
1486 const_uniform_block
->u
[0];
1487 surf_index
= fs_reg(index
);
1488 brw_mark_surface_used(prog_data
, index
);
1490 surf_index
= vgrf(glsl_type::uint_type
);
1491 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1492 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1493 surf_index
= bld
.emit_uniformize(surf_index
);
1495 /* Assume this may touch any UBO. It would be nice to provide
1496 * a tighter bound, but the array information is already lowered away.
1498 brw_mark_surface_used(prog_data
,
1499 stage_prog_data
->binding_table
.ubo_start
+
1500 nir
->info
.num_ssbos
- 1);
1503 /* Get the offset to read from */
1504 fs_reg offset_reg
= vgrf(glsl_type::uint_type
);
1505 unsigned const_offset_bytes
= 0;
1507 bld
.MOV(offset_reg
, get_nir_src(instr
->src
[1]));
1509 const_offset_bytes
= instr
->const_index
[0];
1510 bld
.MOV(offset_reg
, fs_reg(const_offset_bytes
));
1513 /* Read the vector */
1514 for (int i
= 0; i
< instr
->num_components
; i
++) {
1515 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
1516 1 /* dims */, 1 /* size */,
1517 BRW_PREDICATE_NONE
);
1518 read_result
.type
= dest
.type
;
1519 bld
.MOV(dest
, read_result
);
1520 dest
= offset(dest
, bld
, 1);
1522 /* Vector components are stored contiguous in memory */
1523 if (i
< instr
->num_components
) {
1524 if (!has_indirect
) {
1525 const_offset_bytes
+= 4;
1526 bld
.MOV(offset_reg
, fs_reg(const_offset_bytes
));
1528 bld
.ADD(offset_reg
, offset_reg
, brw_imm_ud(4));
1536 case nir_intrinsic_load_input_indirect
:
1537 has_indirect
= true;
1539 case nir_intrinsic_load_input
: {
1541 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1543 if (stage
== MESA_SHADER_VERTEX
) {
1544 src
= offset(fs_reg(ATTR
, instr
->const_index
[0], dest
.type
), bld
, index
);
1546 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
1547 instr
->const_index
[0] + index
);
1550 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1554 dest
= offset(dest
, bld
, 1);
1559 /* Handle ARB_gpu_shader5 interpolation intrinsics
1561 * It's worth a quick word of explanation as to why we handle the full
1562 * variable-based interpolation intrinsic rather than a lowered version
1563 * with like we do for other inputs. We have to do that because the way
1564 * we set up inputs doesn't allow us to use the already setup inputs for
1565 * interpolation. At the beginning of the shader, we go through all of
1566 * the input variables and do the initial interpolation and put it in
1567 * the nir_inputs array based on its location as determined in
1568 * nir_lower_io. If the input isn't used, dead code cleans up and
1569 * everything works fine. However, when we get to the ARB_gpu_shader5
1570 * interpolation intrinsics, we need to reinterpolate the input
1571 * differently. If we used an intrinsic that just had an index it would
1572 * only give us the offset into the nir_inputs array. However, this is
1573 * useless because that value is post-interpolation and we need
1574 * pre-interpolation. In order to get the actual location of the bits
1575 * we get from the vertex fetching hardware, we need the variable.
1577 case nir_intrinsic_interp_var_at_centroid
:
1578 case nir_intrinsic_interp_var_at_sample
:
1579 case nir_intrinsic_interp_var_at_offset
: {
1580 assert(stage
== MESA_SHADER_FRAGMENT
);
1582 ((struct brw_wm_prog_data
*) prog_data
)->pulls_bary
= true;
1584 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1585 const glsl_interp_qualifier interpolation
=
1586 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
1588 switch (instr
->intrinsic
) {
1589 case nir_intrinsic_interp_var_at_centroid
:
1590 emit_pixel_interpolater_send(bld
,
1591 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1598 case nir_intrinsic_interp_var_at_sample
: {
1599 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1602 unsigned msg_data
= const_sample
->i
[0] << 4;
1604 emit_pixel_interpolater_send(bld
,
1605 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1611 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
1612 BRW_REGISTER_TYPE_UD
);
1614 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
1615 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1616 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1617 bld
.exec_all().group(1, 0).SHL(msg_data
, sample_id
, fs_reg(4u));
1618 emit_pixel_interpolater_send(bld
,
1619 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1625 /* Make a loop that sends a message to the pixel interpolater
1626 * for the sample number in each live channel. If there are
1627 * multiple channels with the same sample number then these
1628 * will be handled simultaneously with a single interation of
1631 bld
.emit(BRW_OPCODE_DO
);
1633 /* Get the next live sample number into sample_id_reg */
1634 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1636 /* Set the flag register so that we can perform the send
1637 * message on all channels that have the same sample number
1639 bld
.CMP(bld
.null_reg_ud(),
1640 sample_src
, sample_id
,
1641 BRW_CONDITIONAL_EQ
);
1642 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1643 bld
.exec_all().group(1, 0).SHL(msg_data
, sample_id
, fs_reg(4u));
1645 emit_pixel_interpolater_send(bld
,
1646 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1651 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
1653 /* Continue the loop if there are any live channels left */
1654 set_predicate_inv(BRW_PREDICATE_NORMAL
,
1656 bld
.emit(BRW_OPCODE_WHILE
));
1663 case nir_intrinsic_interp_var_at_offset
: {
1664 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1667 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1668 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1670 emit_pixel_interpolater_send(bld
,
1671 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
1674 fs_reg(off_x
| (off_y
<< 4)),
1677 fs_reg src
= vgrf(glsl_type::ivec2_type
);
1678 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1679 BRW_REGISTER_TYPE_F
);
1680 for (int i
= 0; i
< 2; i
++) {
1681 fs_reg temp
= vgrf(glsl_type::float_type
);
1682 bld
.MUL(temp
, offset(offset_src
, bld
, i
), fs_reg(16.0f
));
1683 fs_reg itemp
= vgrf(glsl_type::int_type
);
1684 bld
.MOV(itemp
, temp
); /* float to int */
1686 /* Clamp the upper end of the range to +7/16.
1687 * ARB_gpu_shader5 requires that we support a maximum offset
1688 * of +0.5, which isn't representable in a S0.4 value -- if
1689 * we didn't clamp it, we'd end up with -8/16, which is the
1690 * opposite of what the shader author wanted.
1692 * This is legal due to ARB_gpu_shader5's quantization
1695 * "Not all values of <offset> may be supported; x and y
1696 * offsets may be rounded to fixed-point values with the
1697 * number of fraction bits given by the
1698 * implementation-dependent constant
1699 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1701 set_condmod(BRW_CONDITIONAL_L
,
1702 bld
.SEL(offset(src
, bld
, i
), itemp
, fs_reg(7)));
1705 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
1706 emit_pixel_interpolater_send(bld
,
1717 unreachable("Invalid intrinsic");
1720 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1721 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1722 src
.type
= dest
.type
;
1724 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1725 dest
= offset(dest
, bld
, 1);
1730 case nir_intrinsic_store_ssbo_indirect
:
1731 has_indirect
= true;
1733 case nir_intrinsic_store_ssbo
: {
1734 assert(devinfo
->gen
>= 7);
1738 nir_const_value
*const_uniform_block
=
1739 nir_src_as_const_value(instr
->src
[1]);
1740 if (const_uniform_block
) {
1741 unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
1742 const_uniform_block
->u
[0];
1743 surf_index
= fs_reg(index
);
1744 brw_mark_surface_used(prog_data
, index
);
1746 surf_index
= vgrf(glsl_type::uint_type
);
1747 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
1748 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1749 surf_index
= bld
.emit_uniformize(surf_index
);
1751 brw_mark_surface_used(prog_data
,
1752 stage_prog_data
->binding_table
.ubo_start
+
1753 nir
->info
.num_ssbos
- 1);
1757 fs_reg offset_reg
= vgrf(glsl_type::uint_type
);
1758 unsigned const_offset_bytes
= 0;
1760 bld
.MOV(offset_reg
, get_nir_src(instr
->src
[2]));
1762 const_offset_bytes
= instr
->const_index
[0];
1763 bld
.MOV(offset_reg
, fs_reg(const_offset_bytes
));
1767 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
1770 unsigned writemask
= instr
->const_index
[1];
1772 /* Write each component present in the writemask */
1773 unsigned skipped_channels
= 0;
1774 for (int i
= 0; i
< instr
->num_components
; i
++) {
1775 int component_mask
= 1 << i
;
1776 if (writemask
& component_mask
) {
1777 if (skipped_channels
) {
1778 if (!has_indirect
) {
1779 const_offset_bytes
+= 4 * skipped_channels
;
1780 bld
.MOV(offset_reg
, fs_reg(const_offset_bytes
));
1782 bld
.ADD(offset_reg
, offset_reg
,
1783 brw_imm_ud(4 * skipped_channels
));
1785 skipped_channels
= 0;
1788 emit_untyped_write(bld
, surf_index
, offset_reg
,
1789 offset(val_reg
, bld
, i
),
1790 1 /* dims */, 1 /* size */,
1791 BRW_PREDICATE_NONE
);
1799 case nir_intrinsic_store_output_indirect
:
1800 has_indirect
= true;
1802 case nir_intrinsic_store_output
: {
1803 fs_reg src
= get_nir_src(instr
->src
[0]);
1805 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1806 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
1807 instr
->const_index
[0] + index
);
1809 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1811 bld
.MOV(new_dest
, src
);
1812 src
= offset(src
, bld
, 1);
1817 case nir_intrinsic_barrier
:
1819 if (stage
== MESA_SHADER_COMPUTE
)
1820 ((struct brw_cs_prog_data
*) prog_data
)->uses_barrier
= true;
1823 case nir_intrinsic_load_local_invocation_id
:
1824 case nir_intrinsic_load_work_group_id
: {
1825 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1826 fs_reg val
= nir_system_values
[sv
];
1827 assert(val
.file
!= BAD_FILE
);
1828 dest
.type
= val
.type
;
1829 for (unsigned i
= 0; i
< 3; i
++)
1830 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
1834 case nir_intrinsic_ssbo_atomic_add
:
1835 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
1837 case nir_intrinsic_ssbo_atomic_min
:
1838 if (dest
.type
== BRW_REGISTER_TYPE_D
)
1839 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
1841 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
1843 case nir_intrinsic_ssbo_atomic_max
:
1844 if (dest
.type
== BRW_REGISTER_TYPE_D
)
1845 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
1847 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
1849 case nir_intrinsic_ssbo_atomic_and
:
1850 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
1852 case nir_intrinsic_ssbo_atomic_or
:
1853 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
1855 case nir_intrinsic_ssbo_atomic_xor
:
1856 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
1858 case nir_intrinsic_ssbo_atomic_exchange
:
1859 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
1861 case nir_intrinsic_ssbo_atomic_comp_swap
:
1862 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
1865 case nir_intrinsic_get_buffer_size
: {
1866 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
1867 unsigned ubo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
1868 int reg_width
= dispatch_width
/ 8;
1871 fs_reg source
= fs_reg(0);
1873 int mlen
= 1 * reg_width
;
1874 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
1875 BRW_REGISTER_TYPE_UD
);
1876 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
1878 fs_reg surf_index
= fs_reg(prog_data
->binding_table
.ubo_start
+ ubo_index
);
1879 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, dest
,
1880 src_payload
, surf_index
);
1881 inst
->header_size
= 0;
1887 case nir_intrinsic_load_num_work_groups
: {
1888 assert(devinfo
->gen
>= 7);
1889 assert(stage
== MESA_SHADER_COMPUTE
);
1891 struct brw_cs_prog_data
*cs_prog_data
=
1892 (struct brw_cs_prog_data
*) prog_data
;
1893 const unsigned surface
=
1894 cs_prog_data
->binding_table
.work_groups_start
;
1896 cs_prog_data
->uses_num_work_groups
= true;
1898 fs_reg surf_index
= fs_reg(surface
);
1899 brw_mark_surface_used(prog_data
, surface
);
1901 /* Read the 3 GLuint components of gl_NumWorkGroups */
1902 for (unsigned i
= 0; i
< 3; i
++) {
1903 fs_reg read_result
=
1904 emit_untyped_read(bld
, surf_index
,
1906 1 /* dims */, 1 /* size */,
1907 BRW_PREDICATE_NONE
);
1908 read_result
.type
= dest
.type
;
1909 bld
.MOV(dest
, read_result
);
1910 dest
= offset(dest
, bld
, 1);
1916 unreachable("unknown intrinsic");
1921 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
1922 int op
, nir_intrinsic_instr
*instr
)
1925 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1926 dest
= get_nir_dest(instr
->dest
);
1929 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
1930 if (const_surface
) {
1931 unsigned surf_index
= stage_prog_data
->binding_table
.ubo_start
+
1932 const_surface
->u
[0];
1933 surface
= fs_reg(surf_index
);
1934 brw_mark_surface_used(prog_data
, surf_index
);
1936 surface
= vgrf(glsl_type::uint_type
);
1937 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
1938 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1940 /* Assume this may touch any UBO. This is the same we do for other
1941 * UBO/SSBO accesses with non-constant surface.
1943 brw_mark_surface_used(prog_data
,
1944 stage_prog_data
->binding_table
.ubo_start
+
1945 nir
->info
.num_ssbos
- 1);
1948 fs_reg offset
= get_nir_src(instr
->src
[1]);
1949 fs_reg data1
= get_nir_src(instr
->src
[2]);
1951 if (op
== BRW_AOP_CMPWR
)
1952 data2
= get_nir_src(instr
->src
[3]);
1954 /* Emit the actual atomic operation operation */
1956 fs_reg atomic_result
=
1957 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
1959 1 /* dims */, 1 /* rsize */,
1961 BRW_PREDICATE_NONE
);
1962 dest
.type
= atomic_result
.type
;
1963 bld
.MOV(dest
, atomic_result
);
1967 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1969 unsigned sampler
= instr
->sampler_index
;
1970 fs_reg
sampler_reg(sampler
);
1972 int gather_component
= instr
->component
;
1974 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1976 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1979 int lod_components
= 0;
1980 int UNUSED offset_components
= 0;
1982 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1984 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1985 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1986 switch (instr
->src
[i
].src_type
) {
1987 case nir_tex_src_bias
:
1988 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1990 case nir_tex_src_comparitor
:
1991 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1993 case nir_tex_src_coord
:
1994 switch (instr
->op
) {
1996 case nir_texop_txf_ms
:
1997 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
2000 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
2004 case nir_tex_src_ddx
:
2005 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2006 lod_components
= nir_tex_instr_src_size(instr
, i
);
2008 case nir_tex_src_ddy
:
2009 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
2011 case nir_tex_src_lod
:
2012 switch (instr
->op
) {
2014 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
2017 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
2020 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2024 case nir_tex_src_ms_index
:
2025 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
2027 case nir_tex_src_offset
:
2028 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
2029 if (instr
->is_array
)
2030 offset_components
= instr
->coord_components
- 1;
2032 offset_components
= instr
->coord_components
;
2034 case nir_tex_src_projector
:
2035 unreachable("should be lowered");
2037 case nir_tex_src_sampler_offset
: {
2038 /* Figure out the highest possible sampler index and mark it as used */
2039 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
2040 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
2041 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
2043 max_used
+= stage_prog_data
->binding_table
.texture_start
;
2045 brw_mark_surface_used(prog_data
, max_used
);
2047 /* Emit code to evaluate the actual indexing expression */
2048 sampler_reg
= vgrf(glsl_type::uint_type
);
2049 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
2050 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
2055 unreachable("unknown texture source");
2059 if (instr
->op
== nir_texop_txf_ms
) {
2060 if (devinfo
->gen
>= 7 &&
2061 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
2062 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
2068 for (unsigned i
= 0; i
< 3; i
++) {
2069 if (instr
->const_offset
[i
] != 0) {
2070 assert(offset_components
== 0);
2071 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
2076 enum glsl_base_type dest_base_type
=
2077 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
2079 const glsl_type
*dest_type
=
2080 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
2083 ir_texture_opcode op
;
2084 switch (instr
->op
) {
2085 case nir_texop_lod
: op
= ir_lod
; break;
2086 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2087 case nir_texop_tex
: op
= ir_tex
; break;
2088 case nir_texop_tg4
: op
= ir_tg4
; break;
2089 case nir_texop_txb
: op
= ir_txb
; break;
2090 case nir_texop_txd
: op
= ir_txd
; break;
2091 case nir_texop_txf
: op
= ir_txf
; break;
2092 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2093 case nir_texop_txl
: op
= ir_txl
; break;
2094 case nir_texop_txs
: op
= ir_txs
; break;
2095 case nir_texop_texture_samples
: {
2096 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
2097 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
2098 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
2101 inst
->header_size
= 1;
2102 inst
->base_mrf
= -1;
2106 unreachable("unknown texture opcode");
2109 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
2110 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
2111 tex_offset
, mcs
, gather_component
,
2112 is_cube_array
, is_rect
, sampler
, sampler_reg
);
2114 fs_reg dest
= get_nir_dest(instr
->dest
);
2115 dest
.type
= this->result
.type
;
2116 unsigned num_components
= nir_tex_instr_dest_size(instr
);
2117 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
2118 dest
, this->result
),
2119 (1 << num_components
) - 1);
2123 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
2125 switch (instr
->type
) {
2126 case nir_jump_break
:
2127 bld
.emit(BRW_OPCODE_BREAK
);
2129 case nir_jump_continue
:
2130 bld
.emit(BRW_OPCODE_CONTINUE
);
2132 case nir_jump_return
:
2134 unreachable("unknown jump");