2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
25 #include "main/shaderimage.h"
27 #include "brw_fs_surface_builder.h"
29 #include "brw_program.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
43 nir_emit_system_values();
45 /* get the main function and emit it */
46 nir_foreach_function(nir
, function
) {
47 assert(strcmp(function
->name
, "main") == 0);
48 assert(function
->impl
);
49 nir_emit_impl(function
->impl
);
54 fs_visitor::nir_setup_inputs()
56 if (stage
!= MESA_SHADER_FRAGMENT
)
59 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
61 nir_foreach_variable(var
, &nir
->inputs
) {
62 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
65 if (var
->data
.location
== VARYING_SLOT_POS
) {
66 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
67 var
->data
.origin_upper_left
);
68 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
70 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
71 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
72 reg
.type
= BRW_REGISTER_TYPE_D
;
73 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
74 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
75 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
76 reg
.type
= BRW_REGISTER_TYPE_D
;
77 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
79 int location
= var
->data
.location
;
80 emit_general_interpolation(&input
, var
->name
, var
->type
,
81 (glsl_interp_qualifier
) var
->data
.interpolation
,
82 &location
, var
->data
.centroid
,
89 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
90 const glsl_type
*type
,
93 if (type
->is_array() || type
->is_matrix()) {
94 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
95 const unsigned length
= glsl_get_length(type
);
97 for (unsigned i
= 0; i
< length
; i
++) {
98 nir_setup_single_output_varying(reg
, elem_type
, location
);
100 } else if (type
->is_record()) {
101 for (unsigned i
= 0; i
< type
->length
; i
++) {
102 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
103 nir_setup_single_output_varying(reg
, field_type
, location
);
106 assert(type
->is_scalar() || type
->is_vector());
107 this->outputs
[*location
] = *reg
;
108 this->output_components
[*location
] = type
->vector_elements
;
109 *reg
= offset(*reg
, bld
, 4);
115 fs_visitor::nir_setup_outputs()
117 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
119 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
121 nir_foreach_variable(var
, &nir
->outputs
) {
122 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
125 case MESA_SHADER_VERTEX
:
126 case MESA_SHADER_TESS_EVAL
:
127 case MESA_SHADER_GEOMETRY
: {
128 unsigned location
= var
->data
.location
;
129 nir_setup_single_output_varying(®
, var
->type
, &location
);
132 case MESA_SHADER_FRAGMENT
:
133 if (key
->force_dual_color_blend
&&
134 var
->data
.location
== FRAG_RESULT_DATA1
) {
135 this->dual_src_output
= reg
;
136 this->do_dual_src
= true;
137 } else if (var
->data
.index
> 0) {
138 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
139 assert(var
->data
.index
== 1);
140 this->dual_src_output
= reg
;
141 this->do_dual_src
= true;
142 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
143 /* Writing gl_FragColor outputs to all color regions. */
144 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
145 this->outputs
[i
] = reg
;
146 this->output_components
[i
] = 4;
148 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
149 this->frag_depth
= reg
;
150 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
151 this->frag_stencil
= reg
;
152 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
153 this->sample_mask
= reg
;
155 int vector_elements
= var
->type
->without_array()->vector_elements
;
157 /* gl_FragData or a user-defined FS output */
158 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
159 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
161 /* General color output. */
162 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
163 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
164 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
165 this->output_components
[output
] = vector_elements
;
170 unreachable("unhandled shader stage");
176 fs_visitor::nir_setup_uniforms()
178 if (dispatch_width
!= 8)
181 uniforms
= nir
->num_uniforms
/ 4;
185 emit_system_values_block(nir_block
*block
, void *void_visitor
)
187 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
190 nir_foreach_instr(block
, instr
) {
191 if (instr
->type
!= nir_instr_type_intrinsic
)
194 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
195 switch (intrin
->intrinsic
) {
196 case nir_intrinsic_load_vertex_id
:
197 unreachable("should be lowered by lower_vertex_id().");
199 case nir_intrinsic_load_vertex_id_zero_base
:
200 assert(v
->stage
== MESA_SHADER_VERTEX
);
201 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
202 if (reg
->file
== BAD_FILE
)
203 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
206 case nir_intrinsic_load_base_vertex
:
207 assert(v
->stage
== MESA_SHADER_VERTEX
);
208 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
209 if (reg
->file
== BAD_FILE
)
210 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
213 case nir_intrinsic_load_instance_id
:
214 assert(v
->stage
== MESA_SHADER_VERTEX
);
215 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
216 if (reg
->file
== BAD_FILE
)
217 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
220 case nir_intrinsic_load_base_instance
:
221 assert(v
->stage
== MESA_SHADER_VERTEX
);
222 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
223 if (reg
->file
== BAD_FILE
)
224 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
227 case nir_intrinsic_load_draw_id
:
228 assert(v
->stage
== MESA_SHADER_VERTEX
);
229 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
230 if (reg
->file
== BAD_FILE
)
231 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
234 case nir_intrinsic_load_invocation_id
:
235 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
236 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
237 if (reg
->file
== BAD_FILE
) {
238 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
239 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
240 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
241 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
246 case nir_intrinsic_load_sample_pos
:
247 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
248 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
249 if (reg
->file
== BAD_FILE
)
250 *reg
= *v
->emit_samplepos_setup();
253 case nir_intrinsic_load_sample_id
:
254 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
255 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
256 if (reg
->file
== BAD_FILE
)
257 *reg
= *v
->emit_sampleid_setup();
260 case nir_intrinsic_load_sample_mask_in
:
261 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
262 assert(v
->devinfo
->gen
>= 7);
263 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
264 if (reg
->file
== BAD_FILE
)
265 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
266 BRW_REGISTER_TYPE_D
));
269 case nir_intrinsic_load_local_invocation_id
:
270 assert(v
->stage
== MESA_SHADER_COMPUTE
);
271 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
272 if (reg
->file
== BAD_FILE
)
273 *reg
= *v
->emit_cs_local_invocation_id_setup();
276 case nir_intrinsic_load_work_group_id
:
277 assert(v
->stage
== MESA_SHADER_COMPUTE
);
278 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
279 if (reg
->file
== BAD_FILE
)
280 *reg
= *v
->emit_cs_work_group_id_setup();
283 case nir_intrinsic_load_helper_invocation
:
284 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
285 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
286 if (reg
->file
== BAD_FILE
) {
287 const fs_builder abld
=
288 v
->bld
.annotate("gl_HelperInvocation", NULL
);
290 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
291 * pixel mask is in g1.7 of the thread payload.
293 * We move the per-channel pixel enable bit to the low bit of each
294 * channel by shifting the byte containing the pixel mask by the
295 * vector immediate 0x76543210UV.
297 * The region of <1,8,0> reads only 1 byte (the pixel masks for
298 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
299 * masks for 2 and 3) in SIMD16.
301 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
303 stride(byte_offset(retype(brw_vec1_grf(1, 0),
304 BRW_REGISTER_TYPE_UB
), 28),
306 brw_imm_uv(0x76543210));
308 /* A set bit in the pixel mask means the channel is enabled, but
309 * that is the opposite of gl_HelperInvocation so we need to invert
312 * The negate source-modifier bit of logical instructions on Gen8+
313 * performs 1's complement negation, so we can use that instead of
316 fs_reg inverted
= negate(shifted
);
317 if (v
->devinfo
->gen
< 8) {
318 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
319 abld
.NOT(inverted
, shifted
);
322 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
323 * with 1 and negating.
325 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
326 abld
.AND(anded
, inverted
, brw_imm_uw(1));
328 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
329 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
343 fs_visitor::nir_emit_system_values()
345 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
346 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
347 nir_system_values
[i
] = fs_reg();
350 nir_foreach_function(nir
, function
) {
351 assert(strcmp(function
->name
, "main") == 0);
352 assert(function
->impl
);
353 nir_foreach_block(function
->impl
, emit_system_values_block
, this);
358 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
360 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
361 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
362 nir_locals
[i
] = fs_reg();
365 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
366 unsigned array_elems
=
367 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
368 unsigned size
= array_elems
* reg
->num_components
;
369 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
372 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
375 nir_emit_cf_list(&impl
->body
);
379 fs_visitor::nir_emit_cf_list(exec_list
*list
)
381 exec_list_validate(list
);
382 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
383 switch (node
->type
) {
385 nir_emit_if(nir_cf_node_as_if(node
));
388 case nir_cf_node_loop
:
389 nir_emit_loop(nir_cf_node_as_loop(node
));
392 case nir_cf_node_block
:
393 nir_emit_block(nir_cf_node_as_block(node
));
397 unreachable("Invalid CFG node block");
403 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
405 /* first, put the condition into f0 */
406 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
407 retype(get_nir_src(if_stmt
->condition
),
408 BRW_REGISTER_TYPE_D
));
409 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
411 bld
.IF(BRW_PREDICATE_NORMAL
);
413 nir_emit_cf_list(&if_stmt
->then_list
);
415 /* note: if the else is empty, dead CF elimination will remove it */
416 bld
.emit(BRW_OPCODE_ELSE
);
418 nir_emit_cf_list(&if_stmt
->else_list
);
420 bld
.emit(BRW_OPCODE_ENDIF
);
424 fs_visitor::nir_emit_loop(nir_loop
*loop
)
426 bld
.emit(BRW_OPCODE_DO
);
428 nir_emit_cf_list(&loop
->body
);
430 bld
.emit(BRW_OPCODE_WHILE
);
434 fs_visitor::nir_emit_block(nir_block
*block
)
436 nir_foreach_instr(block
, instr
) {
437 nir_emit_instr(instr
);
442 fs_visitor::nir_emit_instr(nir_instr
*instr
)
444 const fs_builder abld
= bld
.annotate(NULL
, instr
);
446 switch (instr
->type
) {
447 case nir_instr_type_alu
:
448 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
451 case nir_instr_type_intrinsic
:
453 case MESA_SHADER_VERTEX
:
454 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
456 case MESA_SHADER_TESS_EVAL
:
457 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
459 case MESA_SHADER_GEOMETRY
:
460 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
462 case MESA_SHADER_FRAGMENT
:
463 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 case MESA_SHADER_COMPUTE
:
466 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
469 unreachable("unsupported shader stage");
473 case nir_instr_type_tex
:
474 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
477 case nir_instr_type_load_const
:
478 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
481 case nir_instr_type_ssa_undef
:
482 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
485 case nir_instr_type_jump
:
486 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
490 unreachable("unknown instruction type");
495 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
499 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
500 const fs_reg
&result
)
502 if (!instr
->src
[0].src
.is_ssa
||
503 !instr
->src
[0].src
.ssa
->parent_instr
)
506 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
509 nir_alu_instr
*src0
=
510 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
512 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
513 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
516 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
517 assert(element
!= NULL
);
519 enum opcode extract_op
;
520 if (src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
) {
521 assert(element
->u32
[0] <= 1);
522 extract_op
= SHADER_OPCODE_EXTRACT_WORD
;
524 assert(element
->u32
[0] <= 3);
525 extract_op
= SHADER_OPCODE_EXTRACT_BYTE
;
528 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
529 op0
.type
= brw_type_for_nir_type(nir_op_infos
[src0
->op
].input_types
[0]);
530 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
532 set_saturate(instr
->dest
.saturate
,
533 bld
.emit(extract_op
, result
, op0
, brw_imm_ud(element
->u32
[0])));
538 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
539 const fs_reg
&result
)
541 if (!instr
->src
[0].src
.is_ssa
||
542 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
545 nir_intrinsic_instr
*src0
=
546 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
548 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
551 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
552 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
555 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
556 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
559 fs_reg tmp
= vgrf(glsl_type::int_type
);
561 if (devinfo
->gen
>= 6) {
562 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
563 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
565 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
567 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
568 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
570 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
572 * This negation looks like it's safe in practice, because bits 0:4 will
573 * surely be TRIANGLES
576 if (value1
->f32
[0] == -1.0f
) {
580 tmp
.type
= BRW_REGISTER_TYPE_W
;
581 tmp
.subreg_offset
= 2;
584 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
586 tmp
.type
= BRW_REGISTER_TYPE_D
;
587 tmp
.subreg_offset
= 0;
590 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
591 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
593 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
595 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
596 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
598 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
600 * This negation looks like it's safe in practice, because bits 0:4 will
601 * surely be TRIANGLES
604 if (value1
->f32
[0] == -1.0f
) {
608 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
610 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
616 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
618 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
621 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
622 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
625 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
626 op
[i
] = get_nir_src(instr
->src
[i
].src
);
627 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
628 op
[i
].abs
= instr
->src
[i
].abs
;
629 op
[i
].negate
= instr
->src
[i
].negate
;
632 /* We get a bunch of mov's out of the from_ssa pass and they may still
633 * be vectorized. We'll handle them as a special-case. We'll also
634 * handle vecN here because it's basically the same thing.
642 fs_reg temp
= result
;
643 bool need_extra_copy
= false;
644 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
645 if (!instr
->src
[i
].src
.is_ssa
&&
646 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
647 need_extra_copy
= true;
648 temp
= bld
.vgrf(result
.type
, 4);
653 for (unsigned i
= 0; i
< 4; i
++) {
654 if (!(instr
->dest
.write_mask
& (1 << i
)))
657 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
658 inst
= bld
.MOV(offset(temp
, bld
, i
),
659 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
661 inst
= bld
.MOV(offset(temp
, bld
, i
),
662 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
664 inst
->saturate
= instr
->dest
.saturate
;
667 /* In this case the source and destination registers were the same,
668 * so we need to insert an extra set of moves in order to deal with
671 if (need_extra_copy
) {
672 for (unsigned i
= 0; i
< 4; i
++) {
673 if (!(instr
->dest
.write_mask
& (1 << i
)))
676 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
685 /* At this point, we have dealt with any instruction that operates on
686 * more than a single channel. Therefore, we can just adjust the source
687 * and destination registers for that channel and emit the instruction.
689 unsigned channel
= 0;
690 if (nir_op_infos
[instr
->op
].output_size
== 0) {
691 /* Since NIR is doing the scalarizing for us, we should only ever see
692 * vectorized operations with a single channel.
694 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
695 channel
= ffs(instr
->dest
.write_mask
) - 1;
697 result
= offset(result
, bld
, channel
);
700 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
701 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
702 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
708 if (optimize_extract_to_float(instr
, result
))
711 inst
= bld
.MOV(result
, op
[0]);
712 inst
->saturate
= instr
->dest
.saturate
;
717 bld
.MOV(result
, op
[0]);
721 /* AND(val, 0x80000000) gives the sign bit.
723 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
726 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
728 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
729 op
[0].type
= BRW_REGISTER_TYPE_UD
;
730 result
.type
= BRW_REGISTER_TYPE_UD
;
731 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
733 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
734 inst
->predicate
= BRW_PREDICATE_NORMAL
;
735 if (instr
->dest
.saturate
) {
736 inst
= bld
.MOV(result
, result
);
737 inst
->saturate
= true;
743 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
744 * -> non-negative val generates 0x00000000.
745 * Predicated OR sets 1 if val is positive.
747 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
748 bld
.ASR(result
, op
[0], brw_imm_d(31));
749 inst
= bld
.OR(result
, result
, brw_imm_d(1));
750 inst
->predicate
= BRW_PREDICATE_NORMAL
;
754 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
755 inst
->saturate
= instr
->dest
.saturate
;
759 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
760 inst
->saturate
= instr
->dest
.saturate
;
764 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
765 inst
->saturate
= instr
->dest
.saturate
;
769 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
770 inst
= bld
.emit(SHADER_OPCODE_SIN
, tmp
, op
[0]);
771 if (instr
->dest
.saturate
) {
773 inst
->saturate
= true;
775 bld
.MUL(result
, tmp
, brw_imm_f(0.99997));
781 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
782 inst
= bld
.emit(SHADER_OPCODE_COS
, tmp
, op
[0]);
783 if (instr
->dest
.saturate
) {
785 inst
->saturate
= true;
787 bld
.MUL(result
, tmp
, brw_imm_f(0.99997));
793 if (fs_key
->high_quality_derivatives
) {
794 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
796 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
798 inst
->saturate
= instr
->dest
.saturate
;
800 case nir_op_fddx_fine
:
801 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
802 inst
->saturate
= instr
->dest
.saturate
;
804 case nir_op_fddx_coarse
:
805 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
806 inst
->saturate
= instr
->dest
.saturate
;
809 if (fs_key
->high_quality_derivatives
) {
810 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
811 brw_imm_d(fs_key
->render_to_fbo
));
813 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
814 brw_imm_d(fs_key
->render_to_fbo
));
816 inst
->saturate
= instr
->dest
.saturate
;
818 case nir_op_fddy_fine
:
819 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
820 brw_imm_d(fs_key
->render_to_fbo
));
821 inst
->saturate
= instr
->dest
.saturate
;
823 case nir_op_fddy_coarse
:
824 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
825 brw_imm_d(fs_key
->render_to_fbo
));
826 inst
->saturate
= instr
->dest
.saturate
;
831 inst
= bld
.ADD(result
, op
[0], op
[1]);
832 inst
->saturate
= instr
->dest
.saturate
;
836 inst
= bld
.MUL(result
, op
[0], op
[1]);
837 inst
->saturate
= instr
->dest
.saturate
;
841 bld
.MUL(result
, op
[0], op
[1]);
844 case nir_op_imul_high
:
845 case nir_op_umul_high
:
846 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
851 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
854 case nir_op_uadd_carry
:
855 unreachable("Should have been lowered by carry_to_arith().");
857 case nir_op_usub_borrow
:
858 unreachable("Should have been lowered by borrow_to_arith().");
862 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
863 * appears that our hardware just does the right thing for signed
866 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
870 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
871 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
873 /* Math instructions don't support conditional mod */
874 inst
= bld
.MOV(bld
.null_reg_d(), result
);
875 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
877 /* Now, we need to determine if signs of the sources are different.
878 * When we XOR the sources, the top bit is 0 if they are the same and 1
879 * if they are different. We can then use a conditional modifier to
880 * turn that into a predicate. This leads us to an XOR.l instruction.
882 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
883 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
884 inst
->predicate
= BRW_PREDICATE_NORMAL
;
885 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
887 /* If the result of the initial remainder operation is non-zero and the
888 * two sources have different signs, add in a copy of op[1] to get the
889 * final integer modulus value.
891 inst
= bld
.ADD(result
, result
, op
[1]);
892 inst
->predicate
= BRW_PREDICATE_NORMAL
;
899 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
905 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
910 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
915 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
919 if (devinfo
->gen
>= 8) {
920 op
[0] = resolve_source_modifiers(op
[0]);
922 bld
.NOT(result
, op
[0]);
925 if (devinfo
->gen
>= 8) {
926 op
[0] = resolve_source_modifiers(op
[0]);
927 op
[1] = resolve_source_modifiers(op
[1]);
929 bld
.XOR(result
, op
[0], op
[1]);
932 if (devinfo
->gen
>= 8) {
933 op
[0] = resolve_source_modifiers(op
[0]);
934 op
[1] = resolve_source_modifiers(op
[1]);
936 bld
.OR(result
, op
[0], op
[1]);
939 if (devinfo
->gen
>= 8) {
940 op
[0] = resolve_source_modifiers(op
[0]);
941 op
[1] = resolve_source_modifiers(op
[1]);
943 bld
.AND(result
, op
[0], op
[1]);
949 case nir_op_ball_fequal2
:
950 case nir_op_ball_iequal2
:
951 case nir_op_ball_fequal3
:
952 case nir_op_ball_iequal3
:
953 case nir_op_ball_fequal4
:
954 case nir_op_ball_iequal4
:
955 case nir_op_bany_fnequal2
:
956 case nir_op_bany_inequal2
:
957 case nir_op_bany_fnequal3
:
958 case nir_op_bany_inequal3
:
959 case nir_op_bany_fnequal4
:
960 case nir_op_bany_inequal4
:
961 unreachable("Lowered by nir_lower_alu_reductions");
963 case nir_op_fnoise1_1
:
964 case nir_op_fnoise1_2
:
965 case nir_op_fnoise1_3
:
966 case nir_op_fnoise1_4
:
967 case nir_op_fnoise2_1
:
968 case nir_op_fnoise2_2
:
969 case nir_op_fnoise2_3
:
970 case nir_op_fnoise2_4
:
971 case nir_op_fnoise3_1
:
972 case nir_op_fnoise3_2
:
973 case nir_op_fnoise3_3
:
974 case nir_op_fnoise3_4
:
975 case nir_op_fnoise4_1
:
976 case nir_op_fnoise4_2
:
977 case nir_op_fnoise4_3
:
978 case nir_op_fnoise4_4
:
979 unreachable("not reached: should be handled by lower_noise");
982 unreachable("not reached: should be handled by ldexp_to_arith()");
985 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
986 inst
->saturate
= instr
->dest
.saturate
;
990 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
991 inst
->saturate
= instr
->dest
.saturate
;
996 bld
.MOV(result
, negate(op
[0]));
1000 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1003 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1007 inst
= bld
.RNDZ(result
, op
[0]);
1008 inst
->saturate
= instr
->dest
.saturate
;
1011 case nir_op_fceil
: {
1012 op
[0].negate
= !op
[0].negate
;
1013 fs_reg temp
= vgrf(glsl_type::float_type
);
1014 bld
.RNDD(temp
, op
[0]);
1016 inst
= bld
.MOV(result
, temp
);
1017 inst
->saturate
= instr
->dest
.saturate
;
1021 inst
= bld
.RNDD(result
, op
[0]);
1022 inst
->saturate
= instr
->dest
.saturate
;
1025 inst
= bld
.FRC(result
, op
[0]);
1026 inst
->saturate
= instr
->dest
.saturate
;
1028 case nir_op_fround_even
:
1029 inst
= bld
.RNDE(result
, op
[0]);
1030 inst
->saturate
= instr
->dest
.saturate
;
1033 case nir_op_fquantize2f16
: {
1034 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1035 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1036 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1038 /* The destination stride must be at least as big as the source stride. */
1039 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1042 /* Check for denormal */
1043 fs_reg abs_src0
= op
[0];
1044 abs_src0
.abs
= true;
1045 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1047 /* Get the appropriately signed zero */
1048 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1049 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1050 brw_imm_ud(0x80000000));
1051 /* Do the actual F32 -> F16 -> F32 conversion */
1052 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1053 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1054 /* Select that or zero based on normal status */
1055 inst
= bld
.SEL(result
, zero
, tmp32
);
1056 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1057 inst
->saturate
= instr
->dest
.saturate
;
1064 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1065 inst
->saturate
= instr
->dest
.saturate
;
1071 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1072 inst
->saturate
= instr
->dest
.saturate
;
1075 case nir_op_pack_snorm_2x16
:
1076 case nir_op_pack_snorm_4x8
:
1077 case nir_op_pack_unorm_2x16
:
1078 case nir_op_pack_unorm_4x8
:
1079 case nir_op_unpack_snorm_2x16
:
1080 case nir_op_unpack_snorm_4x8
:
1081 case nir_op_unpack_unorm_2x16
:
1082 case nir_op_unpack_unorm_4x8
:
1083 case nir_op_unpack_half_2x16
:
1084 case nir_op_pack_half_2x16
:
1085 unreachable("not reached: should be handled by lower_packing_builtins");
1087 case nir_op_unpack_half_2x16_split_x
:
1088 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1089 inst
->saturate
= instr
->dest
.saturate
;
1091 case nir_op_unpack_half_2x16_split_y
:
1092 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1093 inst
->saturate
= instr
->dest
.saturate
;
1097 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1098 inst
->saturate
= instr
->dest
.saturate
;
1101 case nir_op_bitfield_reverse
:
1102 bld
.BFREV(result
, op
[0]);
1105 case nir_op_bit_count
:
1106 bld
.CBIT(result
, op
[0]);
1109 case nir_op_ufind_msb
:
1110 case nir_op_ifind_msb
: {
1111 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1113 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1114 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1115 * subtract the result from 31 to convert the MSB count into an LSB count.
1117 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1119 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1120 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1121 inst
->src
[0].negate
= true;
1125 case nir_op_find_lsb
:
1126 bld
.FBL(result
, op
[0]);
1129 case nir_op_ubitfield_extract
:
1130 case nir_op_ibitfield_extract
:
1131 unreachable("should have been lowered");
1134 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1137 bld
.BFI1(result
, op
[0], op
[1]);
1140 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1143 case nir_op_bitfield_insert
:
1144 unreachable("not reached: should have been lowered");
1147 bld
.SHL(result
, op
[0], op
[1]);
1150 bld
.ASR(result
, op
[0], op
[1]);
1153 bld
.SHR(result
, op
[0], op
[1]);
1156 case nir_op_pack_half_2x16_split
:
1157 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1161 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1162 inst
->saturate
= instr
->dest
.saturate
;
1166 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1167 inst
->saturate
= instr
->dest
.saturate
;
1171 if (optimize_frontfacing_ternary(instr
, result
))
1174 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1175 inst
= bld
.SEL(result
, op
[1], op
[2]);
1176 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1179 case nir_op_extract_u8
:
1180 case nir_op_extract_i8
: {
1181 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1182 bld
.emit(SHADER_OPCODE_EXTRACT_BYTE
,
1183 result
, op
[0], brw_imm_ud(byte
->u32
[0]));
1187 case nir_op_extract_u16
:
1188 case nir_op_extract_i16
: {
1189 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1190 bld
.emit(SHADER_OPCODE_EXTRACT_WORD
,
1191 result
, op
[0], brw_imm_ud(word
->u32
[0]));
1196 unreachable("unhandled instruction");
1199 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1200 * to sign extend the low bit to 0/~0
1202 if (devinfo
->gen
<= 5 &&
1203 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1204 fs_reg masked
= vgrf(glsl_type::int_type
);
1205 bld
.AND(masked
, result
, brw_imm_d(1));
1206 masked
.negate
= true;
1207 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1212 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1213 nir_load_const_instr
*instr
)
1215 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1217 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1218 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1220 nir_ssa_values
[instr
->def
.index
] = reg
;
1224 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1226 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1227 instr
->def
.num_components
);
1231 fs_visitor::get_nir_src(nir_src src
)
1235 reg
= nir_ssa_values
[src
.ssa
->index
];
1237 /* We don't handle indirects on locals */
1238 assert(src
.reg
.indirect
== NULL
);
1239 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1240 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1243 /* to avoid floating-point denorm flushing problems, set the type by
1244 * default to D - instructions that need floating point semantics will set
1245 * this to F if they need to
1247 return retype(reg
, BRW_REGISTER_TYPE_D
);
1251 fs_visitor::get_nir_dest(nir_dest dest
)
1254 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1255 dest
.ssa
.num_components
);
1256 return nir_ssa_values
[dest
.ssa
.index
];
1258 /* We don't handle indirects on locals */
1259 assert(dest
.reg
.indirect
== NULL
);
1260 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1261 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1266 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1268 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1269 BRW_REGISTER_TYPE_UD
);
1271 unsigned indirect_max
= 0;
1273 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1274 tail
= tail
->child
) {
1275 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1276 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1277 const unsigned size
= glsl_get_length(tail
->type
);
1278 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1279 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1280 image
= offset(image
, bld
, base
* element_size
);
1282 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1283 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1285 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1286 /* IVB hangs when trying to access an invalid surface index with
1287 * the dataport. According to the spec "if the index used to
1288 * select an individual element is negative or greater than or
1289 * equal to the size of the array, the results of the operation
1290 * are undefined but may not lead to termination" -- which is one
1291 * of the possible outcomes of the hang. Clamp the index to
1292 * prevent access outside of the array bounds.
1294 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1295 BRW_REGISTER_TYPE_UD
),
1296 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1298 bld
.MOV(tmp
, get_nir_src(deref_array
->indirect
));
1301 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1303 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1304 if (indirect
.file
== BAD_FILE
) {
1307 bld
.ADD(indirect
, indirect
, tmp
);
1312 if (indirect
.file
== BAD_FILE
) {
1315 /* Emit a pile of MOVs to load the uniform into a temporary. The
1316 * dead-code elimination pass will get rid of what we don't use.
1318 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1319 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1320 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1321 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1322 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1329 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1332 for (unsigned i
= 0; i
< 4; i
++) {
1333 if (!((wr_mask
>> i
) & 1))
1336 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1337 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1338 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1339 if (new_inst
->src
[j
].file
== VGRF
)
1340 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1347 * Get the matching channel register datatype for an image intrinsic of the
1348 * specified GLSL image type.
1351 get_image_base_type(const glsl_type
*type
)
1353 switch ((glsl_base_type
)type
->sampled_type
) {
1354 case GLSL_TYPE_UINT
:
1355 return BRW_REGISTER_TYPE_UD
;
1357 return BRW_REGISTER_TYPE_D
;
1358 case GLSL_TYPE_FLOAT
:
1359 return BRW_REGISTER_TYPE_F
;
1361 unreachable("Not reached.");
1366 * Get the appropriate atomic op for an image atomic intrinsic.
1369 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1372 case nir_intrinsic_image_atomic_add
:
1374 case nir_intrinsic_image_atomic_min
:
1375 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1376 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1377 case nir_intrinsic_image_atomic_max
:
1378 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1379 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1380 case nir_intrinsic_image_atomic_and
:
1382 case nir_intrinsic_image_atomic_or
:
1384 case nir_intrinsic_image_atomic_xor
:
1386 case nir_intrinsic_image_atomic_exchange
:
1388 case nir_intrinsic_image_atomic_comp_swap
:
1389 return BRW_AOP_CMPWR
;
1391 unreachable("Not reachable.");
1396 emit_pixel_interpolater_send(const fs_builder
&bld
,
1401 glsl_interp_qualifier interpolation
)
1407 if (src
.file
== BAD_FILE
) {
1409 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1413 mlen
= 2 * bld
.dispatch_width() / 8;
1416 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1418 /* 2 floats per slot returned */
1419 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1420 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1426 * Computes 1 << x, given a D/UD register containing some value x.
1429 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1431 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1433 fs_reg result
= bld
.vgrf(x
.type
, 1);
1434 fs_reg one
= bld
.vgrf(x
.type
, 1);
1436 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1437 bld
.SHL(result
, one
, x
);
1442 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1444 assert(stage
== MESA_SHADER_GEOMETRY
);
1446 struct brw_gs_prog_data
*gs_prog_data
=
1447 (struct brw_gs_prog_data
*) prog_data
;
1449 /* We can only do EndPrimitive() functionality when the control data
1450 * consists of cut bits. Fortunately, the only time it isn't is when the
1451 * output type is points, in which case EndPrimitive() is a no-op.
1453 if (gs_prog_data
->control_data_format
!=
1454 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1458 /* Cut bits use one bit per vertex. */
1459 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1461 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1462 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1464 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1465 * vertex n, 0 otherwise. So all we need to do here is mark bit
1466 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1467 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1468 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1470 * Note that if EndPrimitive() is called before emitting any vertices, this
1471 * will cause us to set bit 31 of the control_data_bits register to 1.
1472 * That's fine because:
1474 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1475 * output, so the hardware will ignore cut bit 31.
1477 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1478 * last vertex, so setting cut bit 31 has no effect (since the primitive
1479 * is automatically ended when the GS terminates).
1481 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1482 * control_data_bits register to 0 when the first vertex is emitted.
1485 const fs_builder abld
= bld
.annotate("end primitive");
1487 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1488 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1489 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1490 fs_reg mask
= intexp2(abld
, prev_count
);
1491 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1492 * attention to the lower 5 bits of its second source argument, so on this
1493 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1494 * ((vertex_count - 1) % 32).
1496 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1500 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1502 assert(stage
== MESA_SHADER_GEOMETRY
);
1503 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1505 struct brw_gs_prog_data
*gs_prog_data
=
1506 (struct brw_gs_prog_data
*) prog_data
;
1508 const fs_builder abld
= bld
.annotate("emit control data bits");
1509 const fs_builder fwa_bld
= bld
.exec_all();
1511 /* We use a single UD register to accumulate control data bits (32 bits
1512 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1515 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1516 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1517 * use the Channel Mask phase to enable/disable which DWord within that
1518 * group to write. (Remember, different SIMD8 channels may have emitted
1519 * different numbers of vertices, so we may need per-slot offsets.)
1521 * Channel masking presents an annoying problem: we may have to replicate
1522 * the data up to 4 times:
1524 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1526 * To avoid penalizing shaders that emit a small number of vertices, we
1527 * can avoid these sometimes: if the size of the control data header is
1528 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1529 * land in the same 128-bit group, so we can skip per-slot offsets.
1531 * Similarly, if the control data header is <= 32 bits, there is only one
1532 * DWord, so we can skip channel masks.
1534 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1536 fs_reg channel_mask
, per_slot_offset
;
1538 if (gs_compile
->control_data_header_size_bits
> 32) {
1539 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1540 channel_mask
= vgrf(glsl_type::uint_type
);
1543 if (gs_compile
->control_data_header_size_bits
> 128) {
1544 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1545 per_slot_offset
= vgrf(glsl_type::uint_type
);
1548 /* Figure out which DWord we're trying to write to using the formula:
1550 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1552 * Since bits_per_vertex is a power of two, and is known at compile
1553 * time, this can be optimized to:
1555 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1557 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1558 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1559 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1560 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1561 unsigned log2_bits_per_vertex
=
1562 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1563 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1565 if (per_slot_offset
.file
!= BAD_FILE
) {
1566 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1567 * the appropriate OWord within the control data header.
1569 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1572 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1573 * write to the appropriate DWORD within the OWORD.
1575 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1576 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1577 channel_mask
= intexp2(fwa_bld
, channel
);
1578 /* Then the channel masks need to be in bits 23:16. */
1579 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1582 /* Store the control data bits in the message payload and send it. */
1584 if (channel_mask
.file
!= BAD_FILE
)
1585 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1586 if (per_slot_offset
.file
!= BAD_FILE
)
1589 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1590 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1592 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1593 if (per_slot_offset
.file
!= BAD_FILE
)
1594 sources
[i
++] = per_slot_offset
;
1595 if (channel_mask
.file
!= BAD_FILE
)
1596 sources
[i
++] = channel_mask
;
1598 sources
[i
++] = this->control_data_bits
;
1601 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1602 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1604 /* We need to increment Global Offset by 256-bits to make room for
1605 * Broadwell's extra "Vertex Count" payload at the beginning of the
1606 * URB entry. Since this is an OWord message, Global Offset is counted
1607 * in 128-bit units, so we must set it to 2.
1609 if (gs_prog_data
->static_vertex_count
== -1)
1614 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1617 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1619 /* Note: we are calling this *before* increasing vertex_count, so
1620 * this->vertex_count == vertex_count - 1 in the formula above.
1623 /* Stream mode uses 2 bits per vertex */
1624 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1626 /* Must be a valid stream */
1627 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1629 /* Control data bits are initialized to 0 so we don't have to set any
1630 * bits when sending vertices to stream 0.
1635 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1637 /* reg::sid = stream_id */
1638 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1639 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1641 /* reg:shift_count = 2 * (vertex_count - 1) */
1642 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1643 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1645 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1646 * attention to the lower 5 bits of its second source argument, so on this
1647 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1648 * stream_id << ((2 * (vertex_count - 1)) % 32).
1650 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1651 abld
.SHL(mask
, sid
, shift_count
);
1652 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1656 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1659 assert(stage
== MESA_SHADER_GEOMETRY
);
1661 struct brw_gs_prog_data
*gs_prog_data
=
1662 (struct brw_gs_prog_data
*) prog_data
;
1664 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1665 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1667 /* Haswell and later hardware ignores the "Render Stream Select" bits
1668 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1669 * and instead sends all primitives down the pipeline for rasterization.
1670 * If the SOL stage is enabled, "Render Stream Select" is honored and
1671 * primitives bound to non-zero streams are discarded after stream output.
1673 * Since the only purpose of primives sent to non-zero streams is to
1674 * be recorded by transform feedback, we can simply discard all geometry
1675 * bound to these streams when transform feedback is disabled.
1677 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1680 /* If we're outputting 32 control data bits or less, then we can wait
1681 * until the shader is over to output them all. Otherwise we need to
1682 * output them as we go. Now is the time to do it, since we're about to
1683 * output the vertex_count'th vertex, so it's guaranteed that the
1684 * control data bits associated with the (vertex_count - 1)th vertex are
1687 if (gs_compile
->control_data_header_size_bits
> 32) {
1688 const fs_builder abld
=
1689 bld
.annotate("emit vertex: emit control data bits");
1691 /* Only emit control data bits if we've finished accumulating a batch
1692 * of 32 bits. This is the case when:
1694 * (vertex_count * bits_per_vertex) % 32 == 0
1696 * (in other words, when the last 5 bits of vertex_count *
1697 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1698 * integer n (which is always the case, since bits_per_vertex is
1699 * always 1 or 2), this is equivalent to requiring that the last 5-n
1700 * bits of vertex_count are 0:
1702 * vertex_count & (2^(5-n) - 1) == 0
1704 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1707 * vertex_count & (32 / bits_per_vertex - 1) == 0
1709 * TODO: If vertex_count is an immediate, we could do some of this math
1710 * at compile time...
1713 abld
.AND(bld
.null_reg_d(), vertex_count
,
1714 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1715 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1717 abld
.IF(BRW_PREDICATE_NORMAL
);
1718 /* If vertex_count is 0, then no control data bits have been
1719 * accumulated yet, so we can skip emitting them.
1721 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1722 BRW_CONDITIONAL_NEQ
);
1723 abld
.IF(BRW_PREDICATE_NORMAL
);
1724 emit_gs_control_data_bits(vertex_count
);
1725 abld
.emit(BRW_OPCODE_ENDIF
);
1727 /* Reset control_data_bits to 0 so we can start accumulating a new
1730 * Note: in the case where vertex_count == 0, this neutralizes the
1731 * effect of any call to EndPrimitive() that the shader may have
1732 * made before outputting its first vertex.
1734 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1735 inst
->force_writemask_all
= true;
1736 abld
.emit(BRW_OPCODE_ENDIF
);
1739 emit_urb_writes(vertex_count
);
1741 /* In stream mode we have to set control data bits for all vertices
1742 * unless we have disabled control data bits completely (which we do
1743 * do for GL_POINTS outputs that don't use streams).
1745 if (gs_compile
->control_data_header_size_bits
> 0 &&
1746 gs_prog_data
->control_data_format
==
1747 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1748 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1753 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1754 const nir_src
&vertex_src
,
1755 unsigned base_offset
,
1756 const nir_src
&offset_src
,
1757 unsigned num_components
)
1759 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1761 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1762 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1763 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1765 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1766 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1767 * gl_PointSize is available as a GS input, however, so it must be that.
1769 const bool is_point_size
= (base_offset
== 0);
1771 if (offset_const
!= NULL
&& vertex_const
!= NULL
&&
1772 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
1773 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
1774 vertex_const
->u32
[0] * push_reg_count
;
1775 /* This input was pushed into registers. */
1776 if (is_point_size
) {
1777 /* gl_PointSize comes in .w */
1778 assert(imm_offset
== 0);
1779 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1781 for (unsigned i
= 0; i
< num_components
; i
++) {
1782 bld
.MOV(offset(dst
, bld
, i
),
1783 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1787 /* Resort to the pull model. Ensure the VUE handles are provided. */
1788 gs_prog_data
->base
.include_vue_handles
= true;
1790 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1794 /* The vertex index is constant; just select the proper URB handle. */
1796 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
1797 BRW_REGISTER_TYPE_UD
);
1799 /* The vertex index is non-constant. We need to use indirect
1800 * addressing to fetch the proper URB handle.
1802 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1803 * indicating that channel <n> should read the handle from
1804 * DWord <n>. We convert that to bytes by multiplying by 4.
1806 * Next, we convert the vertex index to bytes by multiplying
1807 * by 32 (shifting by 5), and add the two together. This is
1808 * the final indirect byte offset.
1810 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1811 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1812 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1813 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1814 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1816 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1817 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1818 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1819 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1820 /* Convert vertex_index to bytes (multiply by 32) */
1821 bld
.SHL(vertex_offset_bytes
,
1822 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1824 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1826 /* Use first_icp_handle as the base offset. There is one register
1827 * of URB handles per vertex, so inform the register allocator that
1828 * we might read up to nir->info.gs.vertices_in registers.
1830 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1831 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1832 fs_reg(icp_offset_bytes
),
1833 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1838 /* Constant indexing - use global offset. */
1839 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1840 inst
->offset
= base_offset
+ offset_const
->u32
[0];
1841 inst
->base_mrf
= -1;
1843 inst
->regs_written
= num_components
;
1845 /* Indirect indexing - use per-slot offsets as well. */
1846 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
1847 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1848 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1850 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1851 inst
->offset
= base_offset
;
1852 inst
->base_mrf
= -1;
1854 inst
->regs_written
= num_components
;
1857 if (is_point_size
) {
1858 /* Read the whole VUE header (because of alignment) and read .w. */
1859 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1861 inst
->regs_written
= 4;
1862 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1868 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
1870 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
1871 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
1874 /* The only constant offset we should find is 0. brw_nir.c's
1875 * add_const_offset_to_base() will fold other constant offsets
1876 * into instr->const_index[0].
1878 assert(const_value
->u32
[0] == 0);
1882 return get_nir_src(*offset_src
);
1886 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1887 nir_intrinsic_instr
*instr
)
1889 assert(stage
== MESA_SHADER_VERTEX
);
1892 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1893 dest
= get_nir_dest(instr
->dest
);
1895 switch (instr
->intrinsic
) {
1896 case nir_intrinsic_load_vertex_id
:
1897 unreachable("should be lowered by lower_vertex_id()");
1899 case nir_intrinsic_load_vertex_id_zero_base
:
1900 case nir_intrinsic_load_base_vertex
:
1901 case nir_intrinsic_load_instance_id
:
1902 case nir_intrinsic_load_base_instance
:
1903 case nir_intrinsic_load_draw_id
: {
1904 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1905 fs_reg val
= nir_system_values
[sv
];
1906 assert(val
.file
!= BAD_FILE
);
1907 dest
.type
= val
.type
;
1913 nir_emit_intrinsic(bld
, instr
);
1919 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
1920 nir_intrinsic_instr
*instr
)
1922 assert(stage
== MESA_SHADER_TESS_EVAL
);
1923 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
1926 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1927 dest
= get_nir_dest(instr
->dest
);
1929 switch (instr
->intrinsic
) {
1930 case nir_intrinsic_load_primitive_id
:
1931 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
1933 case nir_intrinsic_load_tess_coord
:
1934 /* gl_TessCoord is part of the payload in g1-3 */
1935 for (unsigned i
= 0; i
< 3; i
++) {
1936 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
1940 case nir_intrinsic_load_tess_level_outer
:
1941 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
1942 * appears as a push-model input. So, we can simply use the ATTR file
1943 * rather than issuing URB read messages. The data is stored in the
1944 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
1947 switch (tes_prog_data
->domain
) {
1948 case BRW_TESS_DOMAIN_QUAD
:
1949 for (unsigned i
= 0; i
< 4; i
++)
1950 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1952 case BRW_TESS_DOMAIN_TRI
:
1953 for (unsigned i
= 0; i
< 3; i
++)
1954 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1956 case BRW_TESS_DOMAIN_ISOLINE
:
1957 for (unsigned i
= 0; i
< 2; i
++)
1958 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1963 case nir_intrinsic_load_tess_level_inner
:
1964 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
1965 * appears as a push-model input. So, we can simply use the ATTR file
1966 * rather than issuing URB read messages.
1968 switch (tes_prog_data
->domain
) {
1969 case BRW_TESS_DOMAIN_QUAD
:
1970 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
1971 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
1973 case BRW_TESS_DOMAIN_TRI
:
1974 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
1976 case BRW_TESS_DOMAIN_ISOLINE
:
1977 /* ignore - value is undefined */
1982 case nir_intrinsic_load_input
:
1983 case nir_intrinsic_load_per_vertex_input
: {
1984 fs_reg indirect_offset
= get_indirect_offset(instr
);
1985 unsigned imm_offset
= instr
->const_index
[0];
1988 if (indirect_offset
.file
== BAD_FILE
) {
1989 /* Arbitrarily only push up to 32 vec4 slots worth of data,
1990 * which is 16 registers (since each holds 2 vec4 slots).
1992 const unsigned max_push_slots
= 32;
1993 if (imm_offset
< max_push_slots
) {
1994 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
1995 for (int i
= 0; i
< instr
->num_components
; i
++) {
1996 bld
.MOV(offset(dest
, bld
, i
),
1997 component(src
, 4 * (imm_offset
% 2) + i
));
1999 tes_prog_data
->base
.urb_read_length
=
2000 MAX2(tes_prog_data
->base
.urb_read_length
,
2001 DIV_ROUND_UP(imm_offset
+ 1, 2));
2003 /* Replicate the patch handle to all enabled channels */
2004 const fs_reg srcs
[] = {
2005 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2007 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2008 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2010 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
2012 inst
->offset
= imm_offset
;
2013 inst
->base_mrf
= -1;
2014 inst
->regs_written
= instr
->num_components
;
2017 /* Indirect indexing - use per-slot offsets as well. */
2018 const fs_reg srcs
[] = {
2019 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2022 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2023 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2025 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
2027 inst
->offset
= imm_offset
;
2028 inst
->base_mrf
= -1;
2029 inst
->regs_written
= instr
->num_components
;
2034 nir_emit_intrinsic(bld
, instr
);
2040 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2041 nir_intrinsic_instr
*instr
)
2043 assert(stage
== MESA_SHADER_GEOMETRY
);
2044 fs_reg indirect_offset
;
2047 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2048 dest
= get_nir_dest(instr
->dest
);
2050 switch (instr
->intrinsic
) {
2051 case nir_intrinsic_load_primitive_id
:
2052 assert(stage
== MESA_SHADER_GEOMETRY
);
2053 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
2054 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2055 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2058 case nir_intrinsic_load_input
:
2059 unreachable("load_input intrinsics are invalid for the GS stage");
2061 case nir_intrinsic_load_per_vertex_input
:
2062 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2063 instr
->src
[1], instr
->num_components
);
2066 case nir_intrinsic_emit_vertex_with_counter
:
2067 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2070 case nir_intrinsic_end_primitive_with_counter
:
2071 emit_gs_end_primitive(instr
->src
[0]);
2074 case nir_intrinsic_set_vertex_count
:
2075 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2078 case nir_intrinsic_load_invocation_id
: {
2079 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2080 assert(val
.file
!= BAD_FILE
);
2081 dest
.type
= val
.type
;
2087 nir_emit_intrinsic(bld
, instr
);
2093 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
2094 nir_intrinsic_instr
*instr
)
2096 assert(stage
== MESA_SHADER_FRAGMENT
);
2097 struct brw_wm_prog_data
*wm_prog_data
=
2098 (struct brw_wm_prog_data
*) prog_data
;
2101 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2102 dest
= get_nir_dest(instr
->dest
);
2104 switch (instr
->intrinsic
) {
2105 case nir_intrinsic_load_front_face
:
2106 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
2107 *emit_frontfacing_interpolation());
2110 case nir_intrinsic_load_sample_pos
: {
2111 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
2112 assert(sample_pos
.file
!= BAD_FILE
);
2113 dest
.type
= sample_pos
.type
;
2114 bld
.MOV(dest
, sample_pos
);
2115 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
2119 case nir_intrinsic_load_helper_invocation
:
2120 case nir_intrinsic_load_sample_mask_in
:
2121 case nir_intrinsic_load_sample_id
: {
2122 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2123 fs_reg val
= nir_system_values
[sv
];
2124 assert(val
.file
!= BAD_FILE
);
2125 dest
.type
= val
.type
;
2130 case nir_intrinsic_discard
:
2131 case nir_intrinsic_discard_if
: {
2132 /* We track our discarded pixels in f0.1. By predicating on it, we can
2133 * update just the flag bits that aren't yet discarded. If there's no
2134 * condition, we emit a CMP of g0 != g0, so all currently executing
2135 * channels will get turned off.
2138 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
2139 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
2140 brw_imm_d(0), BRW_CONDITIONAL_Z
);
2142 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2143 BRW_REGISTER_TYPE_UW
));
2144 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
2146 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2147 cmp
->flag_subreg
= 1;
2149 if (devinfo
->gen
>= 6) {
2150 emit_discard_jump();
2155 case nir_intrinsic_interp_var_at_centroid
:
2156 case nir_intrinsic_interp_var_at_sample
:
2157 case nir_intrinsic_interp_var_at_offset
: {
2158 /* Handle ARB_gpu_shader5 interpolation intrinsics
2160 * It's worth a quick word of explanation as to why we handle the full
2161 * variable-based interpolation intrinsic rather than a lowered version
2162 * with like we do for other inputs. We have to do that because the way
2163 * we set up inputs doesn't allow us to use the already setup inputs for
2164 * interpolation. At the beginning of the shader, we go through all of
2165 * the input variables and do the initial interpolation and put it in
2166 * the nir_inputs array based on its location as determined in
2167 * nir_lower_io. If the input isn't used, dead code cleans up and
2168 * everything works fine. However, when we get to the ARB_gpu_shader5
2169 * interpolation intrinsics, we need to reinterpolate the input
2170 * differently. If we used an intrinsic that just had an index it would
2171 * only give us the offset into the nir_inputs array. However, this is
2172 * useless because that value is post-interpolation and we need
2173 * pre-interpolation. In order to get the actual location of the bits
2174 * we get from the vertex fetching hardware, we need the variable.
2176 wm_prog_data
->pulls_bary
= true;
2178 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2179 const glsl_interp_qualifier interpolation
=
2180 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2182 switch (instr
->intrinsic
) {
2183 case nir_intrinsic_interp_var_at_centroid
:
2184 emit_pixel_interpolater_send(bld
,
2185 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2192 case nir_intrinsic_interp_var_at_sample
: {
2193 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
2196 unsigned msg_data
= const_sample
->i32
[0] << 4;
2198 emit_pixel_interpolater_send(bld
,
2199 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2202 brw_imm_ud(msg_data
),
2205 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
2206 BRW_REGISTER_TYPE_UD
);
2208 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
2209 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2210 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2211 bld
.exec_all().group(1, 0)
2212 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2213 emit_pixel_interpolater_send(bld
,
2214 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2220 /* Make a loop that sends a message to the pixel interpolater
2221 * for the sample number in each live channel. If there are
2222 * multiple channels with the same sample number then these
2223 * will be handled simultaneously with a single interation of
2226 bld
.emit(BRW_OPCODE_DO
);
2228 /* Get the next live sample number into sample_id_reg */
2229 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2231 /* Set the flag register so that we can perform the send
2232 * message on all channels that have the same sample number
2234 bld
.CMP(bld
.null_reg_ud(),
2235 sample_src
, sample_id
,
2236 BRW_CONDITIONAL_EQ
);
2237 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2238 bld
.exec_all().group(1, 0)
2239 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2241 emit_pixel_interpolater_send(bld
,
2242 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2247 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
2249 /* Continue the loop if there are any live channels left */
2250 set_predicate_inv(BRW_PREDICATE_NORMAL
,
2252 bld
.emit(BRW_OPCODE_WHILE
));
2259 case nir_intrinsic_interp_var_at_offset
: {
2260 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2263 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
2264 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
2266 emit_pixel_interpolater_send(bld
,
2267 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
2270 brw_imm_ud(off_x
| (off_y
<< 4)),
2273 fs_reg src
= vgrf(glsl_type::ivec2_type
);
2274 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
2275 BRW_REGISTER_TYPE_F
);
2276 for (int i
= 0; i
< 2; i
++) {
2277 fs_reg temp
= vgrf(glsl_type::float_type
);
2278 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
2279 fs_reg itemp
= vgrf(glsl_type::int_type
);
2280 bld
.MOV(itemp
, temp
); /* float to int */
2282 /* Clamp the upper end of the range to +7/16.
2283 * ARB_gpu_shader5 requires that we support a maximum offset
2284 * of +0.5, which isn't representable in a S0.4 value -- if
2285 * we didn't clamp it, we'd end up with -8/16, which is the
2286 * opposite of what the shader author wanted.
2288 * This is legal due to ARB_gpu_shader5's quantization
2291 * "Not all values of <offset> may be supported; x and y
2292 * offsets may be rounded to fixed-point values with the
2293 * number of fraction bits given by the
2294 * implementation-dependent constant
2295 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2297 set_condmod(BRW_CONDITIONAL_L
,
2298 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2301 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2302 emit_pixel_interpolater_send(bld
,
2313 unreachable("Invalid intrinsic");
2316 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2317 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2318 src
.type
= dest
.type
;
2320 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2321 dest
= offset(dest
, bld
, 1);
2326 nir_emit_intrinsic(bld
, instr
);
2332 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2333 nir_intrinsic_instr
*instr
)
2335 assert(stage
== MESA_SHADER_COMPUTE
);
2336 struct brw_cs_prog_data
*cs_prog_data
=
2337 (struct brw_cs_prog_data
*) prog_data
;
2340 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2341 dest
= get_nir_dest(instr
->dest
);
2343 switch (instr
->intrinsic
) {
2344 case nir_intrinsic_barrier
:
2346 cs_prog_data
->uses_barrier
= true;
2349 case nir_intrinsic_load_local_invocation_id
:
2350 case nir_intrinsic_load_work_group_id
: {
2351 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2352 fs_reg val
= nir_system_values
[sv
];
2353 assert(val
.file
!= BAD_FILE
);
2354 dest
.type
= val
.type
;
2355 for (unsigned i
= 0; i
< 3; i
++)
2356 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2360 case nir_intrinsic_load_num_work_groups
: {
2361 const unsigned surface
=
2362 cs_prog_data
->binding_table
.work_groups_start
;
2364 cs_prog_data
->uses_num_work_groups
= true;
2366 fs_reg surf_index
= brw_imm_ud(surface
);
2367 brw_mark_surface_used(prog_data
, surface
);
2369 /* Read the 3 GLuint components of gl_NumWorkGroups */
2370 for (unsigned i
= 0; i
< 3; i
++) {
2371 fs_reg read_result
=
2372 emit_untyped_read(bld
, surf_index
,
2374 1 /* dims */, 1 /* size */,
2375 BRW_PREDICATE_NONE
);
2376 read_result
.type
= dest
.type
;
2377 bld
.MOV(dest
, read_result
);
2378 dest
= offset(dest
, bld
, 1);
2383 case nir_intrinsic_shared_atomic_add
:
2384 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
2386 case nir_intrinsic_shared_atomic_imin
:
2387 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
2389 case nir_intrinsic_shared_atomic_umin
:
2390 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
2392 case nir_intrinsic_shared_atomic_imax
:
2393 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
2395 case nir_intrinsic_shared_atomic_umax
:
2396 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
2398 case nir_intrinsic_shared_atomic_and
:
2399 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
2401 case nir_intrinsic_shared_atomic_or
:
2402 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
2404 case nir_intrinsic_shared_atomic_xor
:
2405 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
2407 case nir_intrinsic_shared_atomic_exchange
:
2408 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
2410 case nir_intrinsic_shared_atomic_comp_swap
:
2411 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2414 case nir_intrinsic_load_shared
: {
2415 assert(devinfo
->gen
>= 7);
2417 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2419 /* Get the offset to read from */
2421 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2423 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
2425 offset_reg
= vgrf(glsl_type::uint_type
);
2427 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
2428 brw_imm_ud(instr
->const_index
[0]));
2431 /* Read the vector */
2432 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2434 instr
->num_components
,
2435 BRW_PREDICATE_NONE
);
2436 read_result
.type
= dest
.type
;
2437 for (int i
= 0; i
< instr
->num_components
; i
++)
2438 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2443 case nir_intrinsic_store_shared
: {
2444 assert(devinfo
->gen
>= 7);
2447 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2450 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2453 unsigned writemask
= instr
->const_index
[1];
2455 /* Combine groups of consecutive enabled channels in one write
2456 * message. We use ffs to find the first enabled channel and then ffs on
2457 * the bit-inverse, down-shifted writemask to determine the length of
2458 * the block of enabled bits.
2461 unsigned first_component
= ffs(writemask
) - 1;
2462 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2465 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2467 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
2468 4 * first_component
);
2470 offset_reg
= vgrf(glsl_type::uint_type
);
2472 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
2473 brw_imm_ud(instr
->const_index
[0] + 4 * first_component
));
2476 emit_untyped_write(bld
, surf_index
, offset_reg
,
2477 offset(val_reg
, bld
, first_component
),
2478 1 /* dims */, length
,
2479 BRW_PREDICATE_NONE
);
2481 /* Clear the bits in the writemask that we just wrote, then try
2482 * again to see if more channels are left.
2484 writemask
&= (15 << (first_component
+ length
));
2491 nir_emit_intrinsic(bld
, instr
);
2497 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2500 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2501 dest
= get_nir_dest(instr
->dest
);
2503 switch (instr
->intrinsic
) {
2504 case nir_intrinsic_atomic_counter_inc
:
2505 case nir_intrinsic_atomic_counter_dec
:
2506 case nir_intrinsic_atomic_counter_read
: {
2507 /* Get the arguments of the atomic intrinsic. */
2508 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2509 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2510 instr
->const_index
[0]);
2513 /* Emit a surface read or atomic op. */
2514 switch (instr
->intrinsic
) {
2515 case nir_intrinsic_atomic_counter_read
:
2516 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2519 case nir_intrinsic_atomic_counter_inc
:
2520 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2521 fs_reg(), 1, 1, BRW_AOP_INC
);
2524 case nir_intrinsic_atomic_counter_dec
:
2525 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2526 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2530 unreachable("Unreachable");
2533 /* Assign the result. */
2534 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2536 /* Mark the surface as used. */
2537 brw_mark_surface_used(stage_prog_data
, surface
);
2541 case nir_intrinsic_image_load
:
2542 case nir_intrinsic_image_store
:
2543 case nir_intrinsic_image_atomic_add
:
2544 case nir_intrinsic_image_atomic_min
:
2545 case nir_intrinsic_image_atomic_max
:
2546 case nir_intrinsic_image_atomic_and
:
2547 case nir_intrinsic_image_atomic_or
:
2548 case nir_intrinsic_image_atomic_xor
:
2549 case nir_intrinsic_image_atomic_exchange
:
2550 case nir_intrinsic_image_atomic_comp_swap
: {
2551 using namespace image_access
;
2553 /* Get the referenced image variable and type. */
2554 const nir_variable
*var
= instr
->variables
[0]->var
;
2555 const glsl_type
*type
= var
->type
->without_array();
2556 const brw_reg_type base_type
= get_image_base_type(type
);
2558 /* Get some metadata from the image intrinsic. */
2559 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2560 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2561 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2562 const mesa_format format
=
2563 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
2564 _mesa_get_shader_image_format(var
->data
.image
.format
));
2566 /* Get the arguments of the image intrinsic. */
2567 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2568 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2569 BRW_REGISTER_TYPE_UD
);
2570 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2571 retype(get_nir_src(instr
->src
[2]), base_type
) :
2573 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2574 retype(get_nir_src(instr
->src
[3]), base_type
) :
2578 /* Emit an image load, store or atomic op. */
2579 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2580 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2582 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2583 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
2586 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2587 surf_dims
, arr_dims
, info
->dest_components
,
2588 get_image_atomic_op(instr
->intrinsic
, type
));
2590 /* Assign the result. */
2591 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2592 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2593 offset(tmp
, bld
, c
));
2597 case nir_intrinsic_memory_barrier_atomic_counter
:
2598 case nir_intrinsic_memory_barrier_buffer
:
2599 case nir_intrinsic_memory_barrier_image
:
2600 case nir_intrinsic_memory_barrier
: {
2601 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2602 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2607 case nir_intrinsic_group_memory_barrier
:
2608 case nir_intrinsic_memory_barrier_shared
:
2609 /* We treat these workgroup-level barriers as no-ops. This should be
2610 * safe at present and as long as:
2612 * - Memory access instructions are not subsequently reordered by the
2613 * compiler back-end.
2615 * - All threads from a given compute shader workgroup fit within a
2616 * single subslice and therefore talk to the same HDC shared unit
2617 * what supposedly guarantees ordering and coherency between threads
2618 * from the same workgroup. This may change in the future when we
2619 * start splitting workgroups across multiple subslices.
2621 * - The context is not in fault-and-stream mode, which could cause
2622 * memory transactions (including to SLM) prior to the barrier to be
2623 * replayed after the barrier if a pagefault occurs. This shouldn't
2624 * be a problem up to and including SKL because fault-and-stream is
2625 * not usable due to hardware issues, but that's likely to change in
2630 case nir_intrinsic_shader_clock
: {
2631 /* We cannot do anything if there is an event, so ignore it for now */
2632 fs_reg shader_clock
= get_timestamp(bld
);
2633 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2635 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2639 case nir_intrinsic_image_size
: {
2640 /* Get the referenced image variable and type. */
2641 const nir_variable
*var
= instr
->variables
[0]->var
;
2642 const glsl_type
*type
= var
->type
->without_array();
2644 /* Get the size of the image. */
2645 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2646 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
2648 /* For 1DArray image types, the array index is stored in the Z component.
2649 * Fix this by swizzling the Z component to the Y component.
2651 const bool is_1d_array_image
=
2652 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
2653 type
->sampler_array
;
2655 /* For CubeArray images, we should count the number of cubes instead
2656 * of the number of faces. Fix it by dividing the (Z component) by 6.
2658 const bool is_cube_array_image
=
2659 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2660 type
->sampler_array
;
2662 /* Copy all the components. */
2663 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2664 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
2665 if ((int)c
>= type
->coordinate_components()) {
2666 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2668 } else if (c
== 1 && is_1d_array_image
) {
2669 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2670 offset(size
, bld
, 2));
2671 } else if (c
== 2 && is_cube_array_image
) {
2672 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
2673 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2674 offset(size
, bld
, c
), brw_imm_d(6));
2676 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2677 offset(size
, bld
, c
));
2684 case nir_intrinsic_image_samples
:
2685 /* The driver does not support multi-sampled images. */
2686 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
2689 case nir_intrinsic_load_uniform
: {
2690 /* Offsets are in bytes but they should always be multiples of 4 */
2691 assert(instr
->const_index
[0] % 4 == 0);
2693 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
2695 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2697 /* Offsets are in bytes but they should always be multiples of 4 */
2698 assert(const_offset
->u32
[0] % 4 == 0);
2699 src
.reg_offset
= const_offset
->u32
[0] / 4;
2701 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2702 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2705 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
2706 BRW_REGISTER_TYPE_UD
);
2708 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
2709 * go past the end of the uniform. In order to keep the n'th
2710 * component from running past, we subtract off the size of all but
2711 * one component of the vector.
2713 assert(instr
->const_index
[1] >= instr
->num_components
* 4);
2714 unsigned read_size
= instr
->const_index
[1] -
2715 (instr
->num_components
- 1) * 4;
2717 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2718 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
2719 offset(dest
, bld
, j
), offset(src
, bld
, j
),
2720 indirect
, brw_imm_ud(read_size
));
2726 case nir_intrinsic_load_ubo
: {
2727 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
2731 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
2732 const_index
->u32
[0];
2733 surf_index
= brw_imm_ud(index
);
2734 brw_mark_surface_used(prog_data
, index
);
2736 /* The block index is not a constant. Evaluate the index expression
2737 * per-channel and add the base UBO index; we have to select a value
2738 * from any live channel.
2740 surf_index
= vgrf(glsl_type::uint_type
);
2741 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2742 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
2743 surf_index
= bld
.emit_uniformize(surf_index
);
2745 /* Assume this may touch any UBO. It would be nice to provide
2746 * a tighter bound, but the array information is already lowered away.
2748 brw_mark_surface_used(prog_data
,
2749 stage_prog_data
->binding_table
.ubo_start
+
2750 nir
->info
.num_ubos
- 1);
2753 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2754 if (const_offset
== NULL
) {
2755 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
2756 BRW_REGISTER_TYPE_D
);
2758 for (int i
= 0; i
< instr
->num_components
; i
++)
2759 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
2760 base_offset
, i
* 4);
2762 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
2763 packed_consts
.type
= dest
.type
;
2765 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
2766 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
2767 surf_index
, const_offset_reg
);
2769 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2770 packed_consts
.set_smear(const_offset
->u32
[0] % 16 / 4 + i
);
2772 /* The std140 packing rules don't allow vectors to cross 16-byte
2773 * boundaries, and a reg is 32 bytes.
2775 assert(packed_consts
.subreg_offset
< 32);
2777 bld
.MOV(dest
, packed_consts
);
2778 dest
= offset(dest
, bld
, 1);
2784 case nir_intrinsic_load_ssbo
: {
2785 assert(devinfo
->gen
>= 7);
2787 nir_const_value
*const_uniform_block
=
2788 nir_src_as_const_value(instr
->src
[0]);
2791 if (const_uniform_block
) {
2792 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2793 const_uniform_block
->u32
[0];
2794 surf_index
= brw_imm_ud(index
);
2795 brw_mark_surface_used(prog_data
, index
);
2797 surf_index
= vgrf(glsl_type::uint_type
);
2798 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2799 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2801 /* Assume this may touch any UBO. It would be nice to provide
2802 * a tighter bound, but the array information is already lowered away.
2804 brw_mark_surface_used(prog_data
,
2805 stage_prog_data
->binding_table
.ssbo_start
+
2806 nir
->info
.num_ssbos
- 1);
2810 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2812 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
2814 offset_reg
= get_nir_src(instr
->src
[1]);
2817 /* Read the vector */
2818 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2820 instr
->num_components
,
2821 BRW_PREDICATE_NONE
);
2822 read_result
.type
= dest
.type
;
2823 for (int i
= 0; i
< instr
->num_components
; i
++)
2824 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2829 case nir_intrinsic_load_input
: {
2831 if (stage
== MESA_SHADER_VERTEX
) {
2832 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2834 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
2835 instr
->const_index
[0]);
2838 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2839 assert(const_offset
&& "Indirect input loads not allowed");
2840 src
= offset(src
, bld
, const_offset
->u32
[0]);
2842 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2843 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2848 case nir_intrinsic_store_ssbo
: {
2849 assert(devinfo
->gen
>= 7);
2853 nir_const_value
*const_uniform_block
=
2854 nir_src_as_const_value(instr
->src
[1]);
2855 if (const_uniform_block
) {
2856 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2857 const_uniform_block
->u32
[0];
2858 surf_index
= brw_imm_ud(index
);
2859 brw_mark_surface_used(prog_data
, index
);
2861 surf_index
= vgrf(glsl_type::uint_type
);
2862 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
2863 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2865 brw_mark_surface_used(prog_data
,
2866 stage_prog_data
->binding_table
.ssbo_start
+
2867 nir
->info
.num_ssbos
- 1);
2871 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2874 unsigned writemask
= instr
->const_index
[0];
2876 /* Combine groups of consecutive enabled channels in one write
2877 * message. We use ffs to find the first enabled channel and then ffs on
2878 * the bit-inverse, down-shifted writemask to determine the length of
2879 * the block of enabled bits.
2882 unsigned first_component
= ffs(writemask
) - 1;
2883 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2886 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
2888 offset_reg
= brw_imm_ud(const_offset
->u32
[0] + 4 * first_component
);
2890 offset_reg
= vgrf(glsl_type::uint_type
);
2892 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
2893 brw_imm_ud(4 * first_component
));
2896 emit_untyped_write(bld
, surf_index
, offset_reg
,
2897 offset(val_reg
, bld
, first_component
),
2898 1 /* dims */, length
,
2899 BRW_PREDICATE_NONE
);
2901 /* Clear the bits in the writemask that we just wrote, then try
2902 * again to see if more channels are left.
2904 writemask
&= (15 << (first_component
+ length
));
2909 case nir_intrinsic_store_output
: {
2910 fs_reg src
= get_nir_src(instr
->src
[0]);
2911 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
2912 instr
->const_index
[0]);
2914 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2915 assert(const_offset
&& "Indirect output stores not allowed");
2916 new_dest
= offset(new_dest
, bld
, const_offset
->u32
[0]);
2918 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2919 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
2924 case nir_intrinsic_ssbo_atomic_add
:
2925 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
2927 case nir_intrinsic_ssbo_atomic_imin
:
2928 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
2930 case nir_intrinsic_ssbo_atomic_umin
:
2931 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
2933 case nir_intrinsic_ssbo_atomic_imax
:
2934 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
2936 case nir_intrinsic_ssbo_atomic_umax
:
2937 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
2939 case nir_intrinsic_ssbo_atomic_and
:
2940 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
2942 case nir_intrinsic_ssbo_atomic_or
:
2943 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
2945 case nir_intrinsic_ssbo_atomic_xor
:
2946 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
2948 case nir_intrinsic_ssbo_atomic_exchange
:
2949 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
2951 case nir_intrinsic_ssbo_atomic_comp_swap
:
2952 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2955 case nir_intrinsic_get_buffer_size
: {
2956 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
2957 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
2958 int reg_width
= dispatch_width
/ 8;
2961 fs_reg source
= brw_imm_d(0);
2963 int mlen
= 1 * reg_width
;
2965 /* A resinfo's sampler message is used to get the buffer size.
2966 * The SIMD8's writeback message consists of four registers and
2967 * SIMD16's writeback message consists of 8 destination registers
2968 * (two per each component), although we are only interested on the
2969 * first component, where resinfo returns the buffer size for
2972 int regs_written
= 4 * mlen
;
2973 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
2974 BRW_REGISTER_TYPE_UD
);
2975 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
2976 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
2977 BRW_REGISTER_TYPE_UD
);
2978 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
2979 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
2980 src_payload
, brw_imm_ud(index
));
2981 inst
->header_size
= 0;
2983 inst
->regs_written
= regs_written
;
2985 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
2987 brw_mark_surface_used(prog_data
, index
);
2992 unreachable("unknown intrinsic");
2997 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
2998 int op
, nir_intrinsic_instr
*instr
)
3001 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3002 dest
= get_nir_dest(instr
->dest
);
3005 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
3006 if (const_surface
) {
3007 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
3008 const_surface
->u32
[0];
3009 surface
= brw_imm_ud(surf_index
);
3010 brw_mark_surface_used(prog_data
, surf_index
);
3012 surface
= vgrf(glsl_type::uint_type
);
3013 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
3014 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3016 /* Assume this may touch any SSBO. This is the same we do for other
3017 * UBO/SSBO accesses with non-constant surface.
3019 brw_mark_surface_used(prog_data
,
3020 stage_prog_data
->binding_table
.ssbo_start
+
3021 nir
->info
.num_ssbos
- 1);
3024 fs_reg offset
= get_nir_src(instr
->src
[1]);
3025 fs_reg data1
= get_nir_src(instr
->src
[2]);
3027 if (op
== BRW_AOP_CMPWR
)
3028 data2
= get_nir_src(instr
->src
[3]);
3030 /* Emit the actual atomic operation operation */
3032 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3034 1 /* dims */, 1 /* rsize */,
3036 BRW_PREDICATE_NONE
);
3037 dest
.type
= atomic_result
.type
;
3038 bld
.MOV(dest
, atomic_result
);
3042 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
3043 int op
, nir_intrinsic_instr
*instr
)
3046 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3047 dest
= get_nir_dest(instr
->dest
);
3049 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
3050 fs_reg offset
= get_nir_src(instr
->src
[0]);
3051 fs_reg data1
= get_nir_src(instr
->src
[1]);
3053 if (op
== BRW_AOP_CMPWR
)
3054 data2
= get_nir_src(instr
->src
[2]);
3056 /* Emit the actual atomic operation operation */
3058 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3060 1 /* dims */, 1 /* rsize */,
3062 BRW_PREDICATE_NONE
);
3063 dest
.type
= atomic_result
.type
;
3064 bld
.MOV(dest
, atomic_result
);
3068 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
3070 unsigned texture
= instr
->texture_index
;
3071 unsigned sampler
= instr
->sampler_index
;
3072 fs_reg
texture_reg(brw_imm_ud(texture
));
3073 fs_reg
sampler_reg(brw_imm_ud(sampler
));
3075 int gather_component
= instr
->component
;
3077 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
3080 int lod_components
= 0;
3082 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
3084 /* Our hardware requires a LOD for buffer textures */
3085 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
3088 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
3089 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
3090 switch (instr
->src
[i
].src_type
) {
3091 case nir_tex_src_bias
:
3092 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
3094 case nir_tex_src_comparitor
:
3095 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
3097 case nir_tex_src_coord
:
3098 switch (instr
->op
) {
3100 case nir_texop_txf_ms
:
3101 case nir_texop_samples_identical
:
3102 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
3105 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
3109 case nir_tex_src_ddx
:
3110 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
3111 lod_components
= nir_tex_instr_src_size(instr
, i
);
3113 case nir_tex_src_ddy
:
3114 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
3116 case nir_tex_src_lod
:
3117 switch (instr
->op
) {
3119 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
3122 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
3125 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
3129 case nir_tex_src_ms_index
:
3130 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
3133 case nir_tex_src_offset
: {
3134 nir_const_value
*const_offset
=
3135 nir_src_as_const_value(instr
->src
[i
].src
);
3137 tex_offset
= brw_imm_ud(brw_texture_offset(const_offset
->i32
, 3));
3139 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
3144 case nir_tex_src_projector
:
3145 unreachable("should be lowered");
3147 case nir_tex_src_texture_offset
: {
3148 /* Figure out the highest possible texture index and mark it as used */
3149 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
3150 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
3151 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
3153 max_used
+= stage_prog_data
->binding_table
.texture_start
;
3155 brw_mark_surface_used(prog_data
, max_used
);
3157 /* Emit code to evaluate the actual indexing expression */
3158 texture_reg
= vgrf(glsl_type::uint_type
);
3159 bld
.ADD(texture_reg
, src
, brw_imm_ud(texture
));
3160 texture_reg
= bld
.emit_uniformize(texture_reg
);
3164 case nir_tex_src_sampler_offset
: {
3165 /* Emit code to evaluate the actual indexing expression */
3166 sampler_reg
= vgrf(glsl_type::uint_type
);
3167 bld
.ADD(sampler_reg
, src
, brw_imm_ud(sampler
));
3168 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
3173 unreachable("unknown texture source");
3177 if (instr
->op
== nir_texop_txf_ms
||
3178 instr
->op
== nir_texop_samples_identical
) {
3179 if (devinfo
->gen
>= 7 &&
3180 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
3181 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, texture_reg
);
3183 mcs
= brw_imm_ud(0u);
3187 enum glsl_base_type dest_base_type
=
3188 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
3190 const glsl_type
*dest_type
=
3191 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
3194 ir_texture_opcode op
;
3195 switch (instr
->op
) {
3196 case nir_texop_lod
: op
= ir_lod
; break;
3197 case nir_texop_query_levels
: op
= ir_query_levels
; break;
3198 case nir_texop_tex
: op
= ir_tex
; break;
3199 case nir_texop_tg4
: op
= ir_tg4
; break;
3200 case nir_texop_txb
: op
= ir_txb
; break;
3201 case nir_texop_txd
: op
= ir_txd
; break;
3202 case nir_texop_txf
: op
= ir_txf
; break;
3203 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
3204 case nir_texop_txl
: op
= ir_txl
; break;
3205 case nir_texop_txs
: op
= ir_txs
; break;
3206 case nir_texop_texture_samples
: {
3207 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3208 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
3209 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
3210 texture_reg
, texture_reg
);
3212 inst
->header_size
= 1;
3213 inst
->base_mrf
= -1;
3216 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
3218 unreachable("unknown texture opcode");
3221 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
3222 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
3223 tex_offset
, mcs
, gather_component
, is_cube_array
,
3224 texture
, texture_reg
, sampler
, sampler_reg
);
3226 fs_reg dest
= get_nir_dest(instr
->dest
);
3227 dest
.type
= this->result
.type
;
3228 unsigned num_components
= nir_tex_instr_dest_size(instr
);
3229 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
3230 dest
, this->result
),
3231 (1 << num_components
) - 1);
3235 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
3237 switch (instr
->type
) {
3238 case nir_jump_break
:
3239 bld
.emit(BRW_OPCODE_BREAK
);
3241 case nir_jump_continue
:
3242 bld
.emit(BRW_OPCODE_CONTINUE
);
3244 case nir_jump_return
:
3246 unreachable("unknown jump");