2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
41 nir_emit_system_values();
43 /* get the main function and emit it */
44 nir_foreach_function(function
, nir
) {
45 assert(strcmp(function
->name
, "main") == 0);
46 assert(function
->impl
);
47 nir_emit_impl(function
->impl
);
52 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
53 const glsl_type
*type
,
56 if (type
->is_array() || type
->is_matrix()) {
57 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
58 const unsigned length
= glsl_get_length(type
);
60 for (unsigned i
= 0; i
< length
; i
++) {
61 nir_setup_single_output_varying(reg
, elem_type
, location
);
63 } else if (type
->is_record()) {
64 for (unsigned i
= 0; i
< type
->length
; i
++) {
65 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
66 nir_setup_single_output_varying(reg
, field_type
, location
);
69 assert(type
->is_scalar() || type
->is_vector());
70 unsigned num_elements
= type
->vector_elements
;
71 if (type
->is_double())
73 for (unsigned count
= 0; count
< num_elements
; count
+= 4) {
74 this->outputs
[*location
] = *reg
;
75 this->output_components
[*location
] = MIN2(4, num_elements
- count
);
76 *reg
= offset(*reg
, bld
, this->output_components
[*location
]);
83 fs_visitor::nir_setup_outputs()
85 if (stage
== MESA_SHADER_TESS_CTRL
)
88 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
90 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
92 nir_foreach_variable(var
, &nir
->outputs
) {
93 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
96 case MESA_SHADER_VERTEX
:
97 case MESA_SHADER_TESS_EVAL
:
98 case MESA_SHADER_GEOMETRY
: {
99 unsigned location
= var
->data
.location
;
100 nir_setup_single_output_varying(®
, var
->type
, &location
);
103 case MESA_SHADER_FRAGMENT
:
104 if (key
->force_dual_color_blend
&&
105 var
->data
.location
== FRAG_RESULT_DATA1
) {
106 this->dual_src_output
= reg
;
107 this->do_dual_src
= true;
108 } else if (var
->data
.index
> 0) {
109 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
110 assert(var
->data
.index
== 1);
111 this->dual_src_output
= reg
;
112 this->do_dual_src
= true;
113 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
114 /* Writing gl_FragColor outputs to all color regions. */
115 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
116 this->outputs
[i
] = reg
;
117 this->output_components
[i
] = 4;
119 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
120 this->frag_depth
= reg
;
121 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
122 this->frag_stencil
= reg
;
123 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
124 this->sample_mask
= reg
;
126 int vector_elements
= var
->type
->without_array()->vector_elements
;
128 /* gl_FragData or a user-defined FS output */
129 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
130 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
132 /* General color output. */
133 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
134 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
135 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
136 this->output_components
[output
] = vector_elements
;
141 unreachable("unhandled shader stage");
147 fs_visitor::nir_setup_uniforms()
149 if (dispatch_width
!= min_dispatch_width
)
152 uniforms
= nir
->num_uniforms
/ 4;
156 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
160 nir_foreach_instr(instr
, block
) {
161 if (instr
->type
!= nir_instr_type_intrinsic
)
164 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
165 switch (intrin
->intrinsic
) {
166 case nir_intrinsic_load_vertex_id
:
167 unreachable("should be lowered by lower_vertex_id().");
169 case nir_intrinsic_load_vertex_id_zero_base
:
170 assert(v
->stage
== MESA_SHADER_VERTEX
);
171 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
172 if (reg
->file
== BAD_FILE
)
173 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
176 case nir_intrinsic_load_base_vertex
:
177 assert(v
->stage
== MESA_SHADER_VERTEX
);
178 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
179 if (reg
->file
== BAD_FILE
)
180 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
183 case nir_intrinsic_load_instance_id
:
184 assert(v
->stage
== MESA_SHADER_VERTEX
);
185 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
186 if (reg
->file
== BAD_FILE
)
187 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
190 case nir_intrinsic_load_base_instance
:
191 assert(v
->stage
== MESA_SHADER_VERTEX
);
192 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
193 if (reg
->file
== BAD_FILE
)
194 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
197 case nir_intrinsic_load_draw_id
:
198 assert(v
->stage
== MESA_SHADER_VERTEX
);
199 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
200 if (reg
->file
== BAD_FILE
)
201 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
204 case nir_intrinsic_load_invocation_id
:
205 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
207 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
208 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
209 if (reg
->file
== BAD_FILE
) {
210 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
211 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
212 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
213 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
218 case nir_intrinsic_load_sample_pos
:
219 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
220 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
221 if (reg
->file
== BAD_FILE
)
222 *reg
= *v
->emit_samplepos_setup();
225 case nir_intrinsic_load_sample_id
:
226 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
227 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
228 if (reg
->file
== BAD_FILE
)
229 *reg
= *v
->emit_sampleid_setup();
232 case nir_intrinsic_load_sample_mask_in
:
233 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
234 assert(v
->devinfo
->gen
>= 7);
235 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
236 if (reg
->file
== BAD_FILE
)
237 *reg
= *v
->emit_samplemaskin_setup();
240 case nir_intrinsic_load_work_group_id
:
241 assert(v
->stage
== MESA_SHADER_COMPUTE
);
242 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
243 if (reg
->file
== BAD_FILE
)
244 *reg
= *v
->emit_cs_work_group_id_setup();
247 case nir_intrinsic_load_helper_invocation
:
248 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
249 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
250 if (reg
->file
== BAD_FILE
) {
251 const fs_builder abld
=
252 v
->bld
.annotate("gl_HelperInvocation", NULL
);
254 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
255 * pixel mask is in g1.7 of the thread payload.
257 * We move the per-channel pixel enable bit to the low bit of each
258 * channel by shifting the byte containing the pixel mask by the
259 * vector immediate 0x76543210UV.
261 * The region of <1,8,0> reads only 1 byte (the pixel masks for
262 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
263 * masks for 2 and 3) in SIMD16.
265 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
267 stride(byte_offset(retype(brw_vec1_grf(1, 0),
268 BRW_REGISTER_TYPE_UB
), 28),
270 brw_imm_v(0x76543210));
272 /* A set bit in the pixel mask means the channel is enabled, but
273 * that is the opposite of gl_HelperInvocation so we need to invert
276 * The negate source-modifier bit of logical instructions on Gen8+
277 * performs 1's complement negation, so we can use that instead of
280 fs_reg inverted
= negate(shifted
);
281 if (v
->devinfo
->gen
< 8) {
282 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
283 abld
.NOT(inverted
, shifted
);
286 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
287 * with 1 and negating.
289 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
290 abld
.AND(anded
, inverted
, brw_imm_uw(1));
292 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
293 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
307 fs_visitor::nir_emit_system_values()
309 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
310 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
311 nir_system_values
[i
] = fs_reg();
314 nir_foreach_function(function
, nir
) {
315 assert(strcmp(function
->name
, "main") == 0);
316 assert(function
->impl
);
317 nir_foreach_block(block
, function
->impl
) {
318 emit_system_values_block(block
, this);
324 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
326 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
327 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
328 nir_locals
[i
] = fs_reg();
331 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
332 unsigned array_elems
=
333 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
334 unsigned size
= array_elems
* reg
->num_components
;
335 const brw_reg_type reg_type
=
336 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
337 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
340 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
343 nir_emit_cf_list(&impl
->body
);
347 fs_visitor::nir_emit_cf_list(exec_list
*list
)
349 exec_list_validate(list
);
350 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
351 switch (node
->type
) {
353 nir_emit_if(nir_cf_node_as_if(node
));
356 case nir_cf_node_loop
:
357 nir_emit_loop(nir_cf_node_as_loop(node
));
360 case nir_cf_node_block
:
361 nir_emit_block(nir_cf_node_as_block(node
));
365 unreachable("Invalid CFG node block");
371 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
373 /* first, put the condition into f0 */
374 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
375 retype(get_nir_src(if_stmt
->condition
),
376 BRW_REGISTER_TYPE_D
));
377 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
379 bld
.IF(BRW_PREDICATE_NORMAL
);
381 nir_emit_cf_list(&if_stmt
->then_list
);
383 /* note: if the else is empty, dead CF elimination will remove it */
384 bld
.emit(BRW_OPCODE_ELSE
);
386 nir_emit_cf_list(&if_stmt
->else_list
);
388 bld
.emit(BRW_OPCODE_ENDIF
);
392 fs_visitor::nir_emit_loop(nir_loop
*loop
)
394 bld
.emit(BRW_OPCODE_DO
);
396 nir_emit_cf_list(&loop
->body
);
398 bld
.emit(BRW_OPCODE_WHILE
);
402 fs_visitor::nir_emit_block(nir_block
*block
)
404 nir_foreach_instr(instr
, block
) {
405 nir_emit_instr(instr
);
410 fs_visitor::nir_emit_instr(nir_instr
*instr
)
412 const fs_builder abld
= bld
.annotate(NULL
, instr
);
414 switch (instr
->type
) {
415 case nir_instr_type_alu
:
416 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
419 case nir_instr_type_intrinsic
:
421 case MESA_SHADER_VERTEX
:
422 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
424 case MESA_SHADER_TESS_CTRL
:
425 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
427 case MESA_SHADER_TESS_EVAL
:
428 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
430 case MESA_SHADER_GEOMETRY
:
431 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
433 case MESA_SHADER_FRAGMENT
:
434 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
436 case MESA_SHADER_COMPUTE
:
437 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
440 unreachable("unsupported shader stage");
444 case nir_instr_type_tex
:
445 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
448 case nir_instr_type_load_const
:
449 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
452 case nir_instr_type_ssa_undef
:
453 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
456 case nir_instr_type_jump
:
457 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
461 unreachable("unknown instruction type");
466 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
470 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
471 const fs_reg
&result
)
473 if (!instr
->src
[0].src
.is_ssa
||
474 !instr
->src
[0].src
.ssa
->parent_instr
)
477 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
480 nir_alu_instr
*src0
=
481 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
483 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
484 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
487 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
488 assert(element
!= NULL
);
490 /* Element type to extract.*/
491 const brw_reg_type type
= brw_int_type(
492 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
493 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
495 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
496 op0
.type
= brw_type_for_nir_type(
497 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
498 nir_src_bit_size(src0
->src
[0].src
)));
499 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
501 set_saturate(instr
->dest
.saturate
,
502 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
507 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
508 const fs_reg
&result
)
510 if (!instr
->src
[0].src
.is_ssa
||
511 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
514 nir_intrinsic_instr
*src0
=
515 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
517 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
520 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
521 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
524 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
525 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
528 fs_reg tmp
= vgrf(glsl_type::int_type
);
530 if (devinfo
->gen
>= 6) {
531 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
532 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
534 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
536 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
537 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
539 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
541 * This negation looks like it's safe in practice, because bits 0:4 will
542 * surely be TRIANGLES
545 if (value1
->f32
[0] == -1.0f
) {
549 tmp
.type
= BRW_REGISTER_TYPE_W
;
550 tmp
.subreg_offset
= 2;
553 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
555 tmp
.type
= BRW_REGISTER_TYPE_D
;
556 tmp
.subreg_offset
= 0;
559 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
560 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
562 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
564 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
565 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
567 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
569 * This negation looks like it's safe in practice, because bits 0:4 will
570 * surely be TRIANGLES
573 if (value1
->f32
[0] == -1.0f
) {
577 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
579 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
585 emit_find_msb_using_lzd(const fs_builder
&bld
,
586 const fs_reg
&result
,
594 /* LZD of an absolute value source almost always does the right
595 * thing. There are two problem values:
597 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
598 * 0. However, findMSB(int(0x80000000)) == 30.
600 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
601 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
603 * For a value of zero or negative one, -1 will be returned.
605 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
606 * findMSB(-(1<<x)) should return x-1.
608 * For all negative number cases, including 0x80000000 and
609 * 0xffffffff, the correct value is obtained from LZD if instead of
610 * negating the (already negative) value the logical-not is used. A
611 * conditonal logical-not can be achieved in two instructions.
613 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
615 bld
.ASR(temp
, src
, brw_imm_d(31));
616 bld
.XOR(temp
, temp
, src
);
619 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
620 retype(temp
, BRW_REGISTER_TYPE_UD
));
622 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
623 * from the LSB side. Subtract the result from 31 to convert the MSB
624 * count into an LSB count. If no bits are set, LZD will return 32.
625 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
627 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
628 inst
->src
[0].negate
= true;
632 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
634 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
637 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
638 result
.type
= brw_type_for_nir_type(
639 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
640 nir_dest_bit_size(instr
->dest
.dest
)));
643 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
644 op
[i
] = get_nir_src(instr
->src
[i
].src
);
645 op
[i
].type
= brw_type_for_nir_type(
646 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
647 nir_src_bit_size(instr
->src
[i
].src
)));
648 op
[i
].abs
= instr
->src
[i
].abs
;
649 op
[i
].negate
= instr
->src
[i
].negate
;
652 /* We get a bunch of mov's out of the from_ssa pass and they may still
653 * be vectorized. We'll handle them as a special-case. We'll also
654 * handle vecN here because it's basically the same thing.
662 fs_reg temp
= result
;
663 bool need_extra_copy
= false;
664 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
665 if (!instr
->src
[i
].src
.is_ssa
&&
666 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
667 need_extra_copy
= true;
668 temp
= bld
.vgrf(result
.type
, 4);
673 for (unsigned i
= 0; i
< 4; i
++) {
674 if (!(instr
->dest
.write_mask
& (1 << i
)))
677 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
678 inst
= bld
.MOV(offset(temp
, bld
, i
),
679 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
681 inst
= bld
.MOV(offset(temp
, bld
, i
),
682 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
684 inst
->saturate
= instr
->dest
.saturate
;
687 /* In this case the source and destination registers were the same,
688 * so we need to insert an extra set of moves in order to deal with
691 if (need_extra_copy
) {
692 for (unsigned i
= 0; i
< 4; i
++) {
693 if (!(instr
->dest
.write_mask
& (1 << i
)))
696 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
705 /* At this point, we have dealt with any instruction that operates on
706 * more than a single channel. Therefore, we can just adjust the source
707 * and destination registers for that channel and emit the instruction.
709 unsigned channel
= 0;
710 if (nir_op_infos
[instr
->op
].output_size
== 0) {
711 /* Since NIR is doing the scalarizing for us, we should only ever see
712 * vectorized operations with a single channel.
714 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
715 channel
= ffs(instr
->dest
.write_mask
) - 1;
717 result
= offset(result
, bld
, channel
);
720 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
721 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
722 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
728 if (optimize_extract_to_float(instr
, result
))
730 inst
= bld
.MOV(result
, op
[0]);
731 inst
->saturate
= instr
->dest
.saturate
;
737 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
739 * "When source or destination is 64b (...), regioning in Align1
740 * must follow these rules:
742 * 1. Source and destination horizontal stride must be aligned to
746 * This means that 32-bit to 64-bit conversions need to have the 32-bit
747 * data elements aligned to 64-bit. This restriction does not apply to
750 if (devinfo
->is_cherryview
|| devinfo
->is_broxton
) {
751 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
752 tmp
= subscript(tmp
, op
[0].type
, 0);
753 inst
= bld
.MOV(tmp
, op
[0]);
754 inst
= bld
.MOV(result
, tmp
);
755 inst
->saturate
= instr
->dest
.saturate
;
762 inst
= bld
.MOV(result
, op
[0]);
763 inst
->saturate
= instr
->dest
.saturate
;
768 bld
.MOV(result
, op
[0]);
772 if (type_sz(op
[0].type
) < 8) {
773 /* AND(val, 0x80000000) gives the sign bit.
775 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
778 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
780 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
781 op
[0].type
= BRW_REGISTER_TYPE_UD
;
782 result
.type
= BRW_REGISTER_TYPE_UD
;
783 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
785 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
786 inst
->predicate
= BRW_PREDICATE_NORMAL
;
787 if (instr
->dest
.saturate
) {
788 inst
= bld
.MOV(result
, result
);
789 inst
->saturate
= true;
792 /* For doubles we do the same but we need to consider:
794 * - 2-src instructions can't operate with 64-bit immediates
795 * - The sign is encoded in the high 32-bit of each DF
796 * - CMP with DF requires special handling in SIMD16
797 * - We need to produce a DF result.
800 /* 2-src instructions can't have 64-bit immediates, so put 0.0 in
801 * a register and compare with that.
803 fs_reg tmp
= vgrf(glsl_type::double_type
);
804 bld
.MOV(tmp
, setup_imm_df(bld
, 0.0));
806 /* A direct DF CMP using the flag register (null dst) won't work in
807 * SIMD16 because the CMP will be split in two by lower_simd_width,
808 * resulting in two CMP instructions with the same dst (NULL),
809 * leading to dead code elimination of the first one. In SIMD8,
810 * however, there is no need to split the CMP and we can save some
813 fs_reg dst_tmp
= vgrf(glsl_type::double_type
);
814 bld
.CMP(dst_tmp
, op
[0], tmp
, BRW_CONDITIONAL_NZ
);
816 /* In SIMD16 we want to avoid using a NULL dst register with DF CMP,
817 * so we store the result of the comparison in a vgrf instead and
818 * then we generate a UD comparison from that that won't have to
819 * be split by lower_simd_width. This is what NIR does to handle
820 * double comparisons in the general case.
822 if (bld
.dispatch_width() == 16 ) {
823 fs_reg dst_tmp_ud
= retype(dst_tmp
, BRW_REGISTER_TYPE_UD
);
824 bld
.MOV(dst_tmp_ud
, subscript(dst_tmp
, BRW_REGISTER_TYPE_UD
, 0));
825 bld
.CMP(bld
.null_reg_ud(),
826 dst_tmp_ud
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
829 /* Get the high 32-bit of each double component where the sign is */
830 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
831 bld
.MOV(result_int
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
833 /* Get the sign bit */
834 bld
.AND(result_int
, result_int
, brw_imm_ud(0x80000000u
));
836 /* Add 1.0 to the sign, predicated to skip the case of op[0] == 0.0 */
837 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
838 inst
->predicate
= BRW_PREDICATE_NORMAL
;
840 /* Convert from 32-bit float to 64-bit double */
841 result
.type
= BRW_REGISTER_TYPE_DF
;
842 inst
= bld
.MOV(result
, retype(result_int
, BRW_REGISTER_TYPE_F
));
844 if (instr
->dest
.saturate
) {
845 inst
= bld
.MOV(result
, result
);
846 inst
->saturate
= true;
853 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
854 * -> non-negative val generates 0x00000000.
855 * Predicated OR sets 1 if val is positive.
857 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
858 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
859 bld
.ASR(result
, op
[0], brw_imm_d(31));
860 inst
= bld
.OR(result
, result
, brw_imm_d(1));
861 inst
->predicate
= BRW_PREDICATE_NORMAL
;
865 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
866 inst
->saturate
= instr
->dest
.saturate
;
870 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
871 inst
->saturate
= instr
->dest
.saturate
;
875 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
876 inst
->saturate
= instr
->dest
.saturate
;
880 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
881 inst
->saturate
= instr
->dest
.saturate
;
885 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
886 inst
->saturate
= instr
->dest
.saturate
;
890 if (fs_key
->high_quality_derivatives
) {
891 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
893 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
895 inst
->saturate
= instr
->dest
.saturate
;
897 case nir_op_fddx_fine
:
898 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
899 inst
->saturate
= instr
->dest
.saturate
;
901 case nir_op_fddx_coarse
:
902 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
903 inst
->saturate
= instr
->dest
.saturate
;
906 if (fs_key
->high_quality_derivatives
) {
907 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
909 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
911 inst
->saturate
= instr
->dest
.saturate
;
913 case nir_op_fddy_fine
:
914 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
915 inst
->saturate
= instr
->dest
.saturate
;
917 case nir_op_fddy_coarse
:
918 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
919 inst
->saturate
= instr
->dest
.saturate
;
923 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
925 inst
= bld
.ADD(result
, op
[0], op
[1]);
926 inst
->saturate
= instr
->dest
.saturate
;
930 inst
= bld
.MUL(result
, op
[0], op
[1]);
931 inst
->saturate
= instr
->dest
.saturate
;
935 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
936 bld
.MUL(result
, op
[0], op
[1]);
939 case nir_op_imul_high
:
940 case nir_op_umul_high
:
941 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
942 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
947 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
948 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
951 case nir_op_uadd_carry
:
952 unreachable("Should have been lowered by carry_to_arith().");
954 case nir_op_usub_borrow
:
955 unreachable("Should have been lowered by borrow_to_arith().");
959 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
960 * appears that our hardware just does the right thing for signed
963 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
964 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
968 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
969 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
971 /* Math instructions don't support conditional mod */
972 inst
= bld
.MOV(bld
.null_reg_d(), result
);
973 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
975 /* Now, we need to determine if signs of the sources are different.
976 * When we XOR the sources, the top bit is 0 if they are the same and 1
977 * if they are different. We can then use a conditional modifier to
978 * turn that into a predicate. This leads us to an XOR.l instruction.
980 * Technically, according to the PRM, you're not allowed to use .l on a
981 * XOR instruction. However, emperical experiments and Curro's reading
982 * of the simulator source both indicate that it's safe.
984 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
985 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
986 inst
->predicate
= BRW_PREDICATE_NORMAL
;
987 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
989 /* If the result of the initial remainder operation is non-zero and the
990 * two sources have different signs, add in a copy of op[1] to get the
991 * final integer modulus value.
993 inst
= bld
.ADD(result
, result
, op
[1]);
994 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1002 fs_reg dest
= result
;
1003 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1004 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
1006 brw_conditional_mod cond
;
1007 switch (instr
->op
) {
1009 cond
= BRW_CONDITIONAL_L
;
1012 cond
= BRW_CONDITIONAL_GE
;
1015 cond
= BRW_CONDITIONAL_Z
;
1018 cond
= BRW_CONDITIONAL_NZ
;
1021 unreachable("bad opcode");
1023 bld
.CMP(dest
, op
[0], op
[1], cond
);
1024 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1025 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1032 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1033 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1038 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1039 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1043 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1044 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
1048 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1049 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
1053 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1054 if (devinfo
->gen
>= 8) {
1055 op
[0] = resolve_source_modifiers(op
[0]);
1057 bld
.NOT(result
, op
[0]);
1060 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1061 if (devinfo
->gen
>= 8) {
1062 op
[0] = resolve_source_modifiers(op
[0]);
1063 op
[1] = resolve_source_modifiers(op
[1]);
1065 bld
.XOR(result
, op
[0], op
[1]);
1068 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1069 if (devinfo
->gen
>= 8) {
1070 op
[0] = resolve_source_modifiers(op
[0]);
1071 op
[1] = resolve_source_modifiers(op
[1]);
1073 bld
.OR(result
, op
[0], op
[1]);
1076 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1077 if (devinfo
->gen
>= 8) {
1078 op
[0] = resolve_source_modifiers(op
[0]);
1079 op
[1] = resolve_source_modifiers(op
[1]);
1081 bld
.AND(result
, op
[0], op
[1]);
1087 case nir_op_ball_fequal2
:
1088 case nir_op_ball_iequal2
:
1089 case nir_op_ball_fequal3
:
1090 case nir_op_ball_iequal3
:
1091 case nir_op_ball_fequal4
:
1092 case nir_op_ball_iequal4
:
1093 case nir_op_bany_fnequal2
:
1094 case nir_op_bany_inequal2
:
1095 case nir_op_bany_fnequal3
:
1096 case nir_op_bany_inequal3
:
1097 case nir_op_bany_fnequal4
:
1098 case nir_op_bany_inequal4
:
1099 unreachable("Lowered by nir_lower_alu_reductions");
1101 case nir_op_fnoise1_1
:
1102 case nir_op_fnoise1_2
:
1103 case nir_op_fnoise1_3
:
1104 case nir_op_fnoise1_4
:
1105 case nir_op_fnoise2_1
:
1106 case nir_op_fnoise2_2
:
1107 case nir_op_fnoise2_3
:
1108 case nir_op_fnoise2_4
:
1109 case nir_op_fnoise3_1
:
1110 case nir_op_fnoise3_2
:
1111 case nir_op_fnoise3_3
:
1112 case nir_op_fnoise3_4
:
1113 case nir_op_fnoise4_1
:
1114 case nir_op_fnoise4_2
:
1115 case nir_op_fnoise4_3
:
1116 case nir_op_fnoise4_4
:
1117 unreachable("not reached: should be handled by lower_noise");
1120 unreachable("not reached: should be handled by ldexp_to_arith()");
1123 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1124 inst
->saturate
= instr
->dest
.saturate
;
1128 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1129 inst
->saturate
= instr
->dest
.saturate
;
1134 bld
.MOV(result
, negate(op
[0]));
1138 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1141 /* two-argument instructions can't take 64-bit immediates */
1142 fs_reg zero
= vgrf(glsl_type::double_type
);
1143 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1144 /* A SIMD16 execution needs to be split in two instructions, so use
1145 * a vgrf instead of the flag register as dst so instruction splitting
1148 fs_reg tmp
= vgrf(glsl_type::double_type
);
1149 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1150 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1154 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1158 inst
= bld
.RNDZ(result
, op
[0]);
1159 inst
->saturate
= instr
->dest
.saturate
;
1162 case nir_op_fceil
: {
1163 op
[0].negate
= !op
[0].negate
;
1164 fs_reg temp
= vgrf(glsl_type::float_type
);
1165 bld
.RNDD(temp
, op
[0]);
1167 inst
= bld
.MOV(result
, temp
);
1168 inst
->saturate
= instr
->dest
.saturate
;
1172 inst
= bld
.RNDD(result
, op
[0]);
1173 inst
->saturate
= instr
->dest
.saturate
;
1176 inst
= bld
.FRC(result
, op
[0]);
1177 inst
->saturate
= instr
->dest
.saturate
;
1179 case nir_op_fround_even
:
1180 inst
= bld
.RNDE(result
, op
[0]);
1181 inst
->saturate
= instr
->dest
.saturate
;
1184 case nir_op_fquantize2f16
: {
1185 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1186 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1187 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1189 /* The destination stride must be at least as big as the source stride. */
1190 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1193 /* Check for denormal */
1194 fs_reg abs_src0
= op
[0];
1195 abs_src0
.abs
= true;
1196 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1198 /* Get the appropriately signed zero */
1199 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1200 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1201 brw_imm_ud(0x80000000));
1202 /* Do the actual F32 -> F16 -> F32 conversion */
1203 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1204 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1205 /* Select that or zero based on normal status */
1206 inst
= bld
.SEL(result
, zero
, tmp32
);
1207 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1208 inst
->saturate
= instr
->dest
.saturate
;
1214 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1216 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1217 inst
->saturate
= instr
->dest
.saturate
;
1222 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1224 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1225 inst
->saturate
= instr
->dest
.saturate
;
1228 case nir_op_pack_snorm_2x16
:
1229 case nir_op_pack_snorm_4x8
:
1230 case nir_op_pack_unorm_2x16
:
1231 case nir_op_pack_unorm_4x8
:
1232 case nir_op_unpack_snorm_2x16
:
1233 case nir_op_unpack_snorm_4x8
:
1234 case nir_op_unpack_unorm_2x16
:
1235 case nir_op_unpack_unorm_4x8
:
1236 case nir_op_unpack_half_2x16
:
1237 case nir_op_pack_half_2x16
:
1238 unreachable("not reached: should be handled by lower_packing_builtins");
1240 case nir_op_unpack_half_2x16_split_x
:
1241 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1242 inst
->saturate
= instr
->dest
.saturate
;
1244 case nir_op_unpack_half_2x16_split_y
:
1245 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1246 inst
->saturate
= instr
->dest
.saturate
;
1249 case nir_op_pack_double_2x32_split
:
1250 /* Optimize the common case where we are re-packing a double with
1251 * the result of a previous double unpack. In this case we can take the
1252 * 32-bit value to use in the re-pack from the original double and bypass
1253 * the unpack operation.
1255 for (int i
= 0; i
< 2; i
++) {
1256 if (instr
->src
[i
].src
.is_ssa
)
1259 const nir_instr
*parent_instr
= instr
->src
[i
].src
.ssa
->parent_instr
;
1260 if (parent_instr
->type
== nir_instr_type_alu
)
1263 const nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1264 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_x
||
1265 alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1268 if (!alu_parent
->src
[0].src
.is_ssa
)
1271 op
[i
] = get_nir_src(alu_parent
->src
[0].src
);
1272 op
[i
] = offset(retype(op
[i
], BRW_REGISTER_TYPE_DF
), bld
,
1273 alu_parent
->src
[0].swizzle
[channel
]);
1274 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1275 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 1);
1277 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 0);
1279 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1282 case nir_op_unpack_double_2x32_split_x
:
1283 case nir_op_unpack_double_2x32_split_y
: {
1284 /* Optimize the common case where we are unpacking from a double we have
1285 * previously packed. In this case we can just bypass the pack operation
1286 * and source directly from its arguments.
1288 unsigned index
= (instr
->op
== nir_op_unpack_double_2x32_split_x
) ? 0 : 1;
1289 if (instr
->src
[0].src
.is_ssa
) {
1290 nir_instr
*parent_instr
= instr
->src
[0].src
.ssa
->parent_instr
;
1291 if (parent_instr
->type
== nir_instr_type_alu
) {
1292 nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1293 if (alu_parent
->op
== nir_op_pack_double_2x32_split
&&
1294 alu_parent
->src
[index
].src
.is_ssa
) {
1295 op
[0] = retype(get_nir_src(alu_parent
->src
[index
].src
),
1296 BRW_REGISTER_TYPE_UD
);
1298 offset(op
[0], bld
, alu_parent
->src
[index
].swizzle
[channel
]);
1299 bld
.MOV(result
, op
[0]);
1305 if (instr
->op
== nir_op_unpack_double_2x32_split_x
)
1306 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1308 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1313 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1314 inst
->saturate
= instr
->dest
.saturate
;
1317 case nir_op_bitfield_reverse
:
1318 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1319 bld
.BFREV(result
, op
[0]);
1322 case nir_op_bit_count
:
1323 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1324 bld
.CBIT(result
, op
[0]);
1327 case nir_op_ufind_msb
: {
1328 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1329 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1333 case nir_op_ifind_msb
: {
1334 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1336 if (devinfo
->gen
< 7) {
1337 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1339 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1341 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1342 * count from the LSB side. If FBH didn't return an error
1343 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1344 * count into an LSB count.
1346 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1348 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1349 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1350 inst
->src
[0].negate
= true;
1355 case nir_op_find_lsb
:
1356 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1358 if (devinfo
->gen
< 7) {
1359 fs_reg temp
= vgrf(glsl_type::int_type
);
1361 /* (x & -x) generates a value that consists of only the LSB of x.
1362 * For all powers of 2, findMSB(y) == findLSB(y).
1364 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1365 fs_reg negated_src
= src
;
1367 /* One must be negated, and the other must be non-negated. It
1368 * doesn't matter which is which.
1370 negated_src
.negate
= true;
1373 bld
.AND(temp
, src
, negated_src
);
1374 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1376 bld
.FBL(result
, op
[0]);
1380 case nir_op_ubitfield_extract
:
1381 case nir_op_ibitfield_extract
:
1382 unreachable("should have been lowered");
1385 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1386 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1389 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1390 bld
.BFI1(result
, op
[0], op
[1]);
1393 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1394 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1397 case nir_op_bitfield_insert
:
1398 unreachable("not reached: should have been lowered");
1401 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1402 bld
.SHL(result
, op
[0], op
[1]);
1405 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1406 bld
.ASR(result
, op
[0], op
[1]);
1409 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1410 bld
.SHR(result
, op
[0], op
[1]);
1413 case nir_op_pack_half_2x16_split
:
1414 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1418 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1419 inst
->saturate
= instr
->dest
.saturate
;
1423 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1424 inst
->saturate
= instr
->dest
.saturate
;
1428 if (optimize_frontfacing_ternary(instr
, result
))
1431 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1432 inst
= bld
.SEL(result
, op
[1], op
[2]);
1433 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1436 case nir_op_extract_u8
:
1437 case nir_op_extract_i8
: {
1438 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1439 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1440 assert(byte
!= NULL
);
1441 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1445 case nir_op_extract_u16
:
1446 case nir_op_extract_i16
: {
1447 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1448 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1449 assert(word
!= NULL
);
1450 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1455 unreachable("unhandled instruction");
1458 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1459 * to sign extend the low bit to 0/~0
1461 if (devinfo
->gen
<= 5 &&
1462 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1463 fs_reg masked
= vgrf(glsl_type::int_type
);
1464 bld
.AND(masked
, result
, brw_imm_d(1));
1465 masked
.negate
= true;
1466 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1471 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1472 nir_load_const_instr
*instr
)
1474 const brw_reg_type reg_type
=
1475 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1476 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1478 switch (instr
->def
.bit_size
) {
1480 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1481 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1485 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1486 bld
.MOV(offset(reg
, bld
, i
),
1487 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1491 unreachable("Invalid bit size");
1494 nir_ssa_values
[instr
->def
.index
] = reg
;
1498 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1500 const brw_reg_type reg_type
=
1501 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1502 nir_ssa_values
[instr
->def
.index
] =
1503 bld
.vgrf(reg_type
, instr
->def
.num_components
);
1507 fs_visitor::get_nir_src(const nir_src
&src
)
1511 reg
= nir_ssa_values
[src
.ssa
->index
];
1513 /* We don't handle indirects on locals */
1514 assert(src
.reg
.indirect
== NULL
);
1515 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1516 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1519 /* to avoid floating-point denorm flushing problems, set the type by
1520 * default to D - instructions that need floating point semantics will set
1521 * this to F if they need to
1523 return retype(reg
, BRW_REGISTER_TYPE_D
);
1527 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1530 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1532 nir_const_value
*val
= nir_src_as_const_value(src
);
1533 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1537 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1540 const brw_reg_type reg_type
=
1541 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1542 nir_ssa_values
[dest
.ssa
.index
] =
1543 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1544 return nir_ssa_values
[dest
.ssa
.index
];
1546 /* We don't handle indirects on locals */
1547 assert(dest
.reg
.indirect
== NULL
);
1548 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1549 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1554 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1556 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1557 BRW_REGISTER_TYPE_UD
);
1559 unsigned indirect_max
= 0;
1561 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1562 tail
= tail
->child
) {
1563 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1564 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1565 const unsigned size
= glsl_get_length(tail
->type
);
1566 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1567 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1568 image
= offset(image
, bld
, base
* element_size
);
1570 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1571 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1573 /* Accessing an invalid surface index with the dataport can result
1574 * in a hang. According to the spec "if the index used to
1575 * select an individual element is negative or greater than or
1576 * equal to the size of the array, the results of the operation
1577 * are undefined but may not lead to termination" -- which is one
1578 * of the possible outcomes of the hang. Clamp the index to
1579 * prevent access outside of the array bounds.
1581 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1582 BRW_REGISTER_TYPE_UD
),
1583 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1585 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1587 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1588 if (indirect
.file
== BAD_FILE
) {
1591 bld
.ADD(indirect
, indirect
, tmp
);
1596 if (indirect
.file
== BAD_FILE
) {
1599 /* Emit a pile of MOVs to load the uniform into a temporary. The
1600 * dead-code elimination pass will get rid of what we don't use.
1602 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1603 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1604 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1605 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1606 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1613 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1616 for (unsigned i
= 0; i
< 4; i
++) {
1617 if (!((wr_mask
>> i
) & 1))
1620 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1621 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1622 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1623 if (new_inst
->src
[j
].file
== VGRF
)
1624 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1631 * Get the matching channel register datatype for an image intrinsic of the
1632 * specified GLSL image type.
1635 get_image_base_type(const glsl_type
*type
)
1637 switch ((glsl_base_type
)type
->sampled_type
) {
1638 case GLSL_TYPE_UINT
:
1639 return BRW_REGISTER_TYPE_UD
;
1641 return BRW_REGISTER_TYPE_D
;
1642 case GLSL_TYPE_FLOAT
:
1643 return BRW_REGISTER_TYPE_F
;
1645 unreachable("Not reached.");
1650 * Get the appropriate atomic op for an image atomic intrinsic.
1653 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1656 case nir_intrinsic_image_atomic_add
:
1658 case nir_intrinsic_image_atomic_min
:
1659 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1660 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1661 case nir_intrinsic_image_atomic_max
:
1662 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1663 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1664 case nir_intrinsic_image_atomic_and
:
1666 case nir_intrinsic_image_atomic_or
:
1668 case nir_intrinsic_image_atomic_xor
:
1670 case nir_intrinsic_image_atomic_exchange
:
1672 case nir_intrinsic_image_atomic_comp_swap
:
1673 return BRW_AOP_CMPWR
;
1675 unreachable("Not reachable.");
1680 emit_pixel_interpolater_send(const fs_builder
&bld
,
1685 glsl_interp_mode interpolation
)
1687 struct brw_wm_prog_data
*wm_prog_data
=
1688 (struct brw_wm_prog_data
*) bld
.shader
->stage_prog_data
;
1693 if (src
.file
== BAD_FILE
) {
1695 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1699 mlen
= 2 * bld
.dispatch_width() / 8;
1702 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1704 /* 2 floats per slot returned */
1705 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1706 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1708 wm_prog_data
->pulls_bary
= true;
1714 * Computes 1 << x, given a D/UD register containing some value x.
1717 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1719 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1721 fs_reg result
= bld
.vgrf(x
.type
, 1);
1722 fs_reg one
= bld
.vgrf(x
.type
, 1);
1724 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1725 bld
.SHL(result
, one
, x
);
1730 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1732 assert(stage
== MESA_SHADER_GEOMETRY
);
1734 struct brw_gs_prog_data
*gs_prog_data
=
1735 (struct brw_gs_prog_data
*) prog_data
;
1737 if (gs_compile
->control_data_header_size_bits
== 0)
1740 /* We can only do EndPrimitive() functionality when the control data
1741 * consists of cut bits. Fortunately, the only time it isn't is when the
1742 * output type is points, in which case EndPrimitive() is a no-op.
1744 if (gs_prog_data
->control_data_format
!=
1745 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1749 /* Cut bits use one bit per vertex. */
1750 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1752 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1753 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1755 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1756 * vertex n, 0 otherwise. So all we need to do here is mark bit
1757 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1758 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1759 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1761 * Note that if EndPrimitive() is called before emitting any vertices, this
1762 * will cause us to set bit 31 of the control_data_bits register to 1.
1763 * That's fine because:
1765 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1766 * output, so the hardware will ignore cut bit 31.
1768 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1769 * last vertex, so setting cut bit 31 has no effect (since the primitive
1770 * is automatically ended when the GS terminates).
1772 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1773 * control_data_bits register to 0 when the first vertex is emitted.
1776 const fs_builder abld
= bld
.annotate("end primitive");
1778 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1779 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1780 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1781 fs_reg mask
= intexp2(abld
, prev_count
);
1782 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1783 * attention to the lower 5 bits of its second source argument, so on this
1784 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1785 * ((vertex_count - 1) % 32).
1787 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1791 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1793 assert(stage
== MESA_SHADER_GEOMETRY
);
1794 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1796 struct brw_gs_prog_data
*gs_prog_data
=
1797 (struct brw_gs_prog_data
*) prog_data
;
1799 const fs_builder abld
= bld
.annotate("emit control data bits");
1800 const fs_builder fwa_bld
= bld
.exec_all();
1802 /* We use a single UD register to accumulate control data bits (32 bits
1803 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1806 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1807 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1808 * use the Channel Mask phase to enable/disable which DWord within that
1809 * group to write. (Remember, different SIMD8 channels may have emitted
1810 * different numbers of vertices, so we may need per-slot offsets.)
1812 * Channel masking presents an annoying problem: we may have to replicate
1813 * the data up to 4 times:
1815 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1817 * To avoid penalizing shaders that emit a small number of vertices, we
1818 * can avoid these sometimes: if the size of the control data header is
1819 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1820 * land in the same 128-bit group, so we can skip per-slot offsets.
1822 * Similarly, if the control data header is <= 32 bits, there is only one
1823 * DWord, so we can skip channel masks.
1825 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1827 fs_reg channel_mask
, per_slot_offset
;
1829 if (gs_compile
->control_data_header_size_bits
> 32) {
1830 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1831 channel_mask
= vgrf(glsl_type::uint_type
);
1834 if (gs_compile
->control_data_header_size_bits
> 128) {
1835 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1836 per_slot_offset
= vgrf(glsl_type::uint_type
);
1839 /* Figure out which DWord we're trying to write to using the formula:
1841 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1843 * Since bits_per_vertex is a power of two, and is known at compile
1844 * time, this can be optimized to:
1846 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1848 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1849 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1850 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1851 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1852 unsigned log2_bits_per_vertex
=
1853 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1854 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1856 if (per_slot_offset
.file
!= BAD_FILE
) {
1857 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1858 * the appropriate OWord within the control data header.
1860 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1863 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1864 * write to the appropriate DWORD within the OWORD.
1866 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1867 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1868 channel_mask
= intexp2(fwa_bld
, channel
);
1869 /* Then the channel masks need to be in bits 23:16. */
1870 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1873 /* Store the control data bits in the message payload and send it. */
1875 if (channel_mask
.file
!= BAD_FILE
)
1876 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1877 if (per_slot_offset
.file
!= BAD_FILE
)
1880 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1881 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1883 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1884 if (per_slot_offset
.file
!= BAD_FILE
)
1885 sources
[i
++] = per_slot_offset
;
1886 if (channel_mask
.file
!= BAD_FILE
)
1887 sources
[i
++] = channel_mask
;
1889 sources
[i
++] = this->control_data_bits
;
1892 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1893 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1895 /* We need to increment Global Offset by 256-bits to make room for
1896 * Broadwell's extra "Vertex Count" payload at the beginning of the
1897 * URB entry. Since this is an OWord message, Global Offset is counted
1898 * in 128-bit units, so we must set it to 2.
1900 if (gs_prog_data
->static_vertex_count
== -1)
1905 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1908 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1910 /* Note: we are calling this *before* increasing vertex_count, so
1911 * this->vertex_count == vertex_count - 1 in the formula above.
1914 /* Stream mode uses 2 bits per vertex */
1915 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1917 /* Must be a valid stream */
1918 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1920 /* Control data bits are initialized to 0 so we don't have to set any
1921 * bits when sending vertices to stream 0.
1926 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1928 /* reg::sid = stream_id */
1929 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1930 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1932 /* reg:shift_count = 2 * (vertex_count - 1) */
1933 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1934 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1936 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1937 * attention to the lower 5 bits of its second source argument, so on this
1938 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1939 * stream_id << ((2 * (vertex_count - 1)) % 32).
1941 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1942 abld
.SHL(mask
, sid
, shift_count
);
1943 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1947 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1950 assert(stage
== MESA_SHADER_GEOMETRY
);
1952 struct brw_gs_prog_data
*gs_prog_data
=
1953 (struct brw_gs_prog_data
*) prog_data
;
1955 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1956 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1958 /* Haswell and later hardware ignores the "Render Stream Select" bits
1959 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1960 * and instead sends all primitives down the pipeline for rasterization.
1961 * If the SOL stage is enabled, "Render Stream Select" is honored and
1962 * primitives bound to non-zero streams are discarded after stream output.
1964 * Since the only purpose of primives sent to non-zero streams is to
1965 * be recorded by transform feedback, we can simply discard all geometry
1966 * bound to these streams when transform feedback is disabled.
1968 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1971 /* If we're outputting 32 control data bits or less, then we can wait
1972 * until the shader is over to output them all. Otherwise we need to
1973 * output them as we go. Now is the time to do it, since we're about to
1974 * output the vertex_count'th vertex, so it's guaranteed that the
1975 * control data bits associated with the (vertex_count - 1)th vertex are
1978 if (gs_compile
->control_data_header_size_bits
> 32) {
1979 const fs_builder abld
=
1980 bld
.annotate("emit vertex: emit control data bits");
1982 /* Only emit control data bits if we've finished accumulating a batch
1983 * of 32 bits. This is the case when:
1985 * (vertex_count * bits_per_vertex) % 32 == 0
1987 * (in other words, when the last 5 bits of vertex_count *
1988 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1989 * integer n (which is always the case, since bits_per_vertex is
1990 * always 1 or 2), this is equivalent to requiring that the last 5-n
1991 * bits of vertex_count are 0:
1993 * vertex_count & (2^(5-n) - 1) == 0
1995 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1998 * vertex_count & (32 / bits_per_vertex - 1) == 0
2000 * TODO: If vertex_count is an immediate, we could do some of this math
2001 * at compile time...
2004 abld
.AND(bld
.null_reg_d(), vertex_count
,
2005 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2006 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2008 abld
.IF(BRW_PREDICATE_NORMAL
);
2009 /* If vertex_count is 0, then no control data bits have been
2010 * accumulated yet, so we can skip emitting them.
2012 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2013 BRW_CONDITIONAL_NEQ
);
2014 abld
.IF(BRW_PREDICATE_NORMAL
);
2015 emit_gs_control_data_bits(vertex_count
);
2016 abld
.emit(BRW_OPCODE_ENDIF
);
2018 /* Reset control_data_bits to 0 so we can start accumulating a new
2021 * Note: in the case where vertex_count == 0, this neutralizes the
2022 * effect of any call to EndPrimitive() that the shader may have
2023 * made before outputting its first vertex.
2025 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2026 inst
->force_writemask_all
= true;
2027 abld
.emit(BRW_OPCODE_ENDIF
);
2030 emit_urb_writes(vertex_count
);
2032 /* In stream mode we have to set control data bits for all vertices
2033 * unless we have disabled control data bits completely (which we do
2034 * do for GL_POINTS outputs that don't use streams).
2036 if (gs_compile
->control_data_header_size_bits
> 0 &&
2037 gs_prog_data
->control_data_format
==
2038 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2039 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2044 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2045 const nir_src
&vertex_src
,
2046 unsigned base_offset
,
2047 const nir_src
&offset_src
,
2048 unsigned num_components
,
2049 unsigned first_component
)
2051 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
2053 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2054 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2055 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2057 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
2058 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
2059 * gl_PointSize is available as a GS input, however, so it must be that.
2061 const bool is_point_size
= (base_offset
== 0);
2063 /* TODO: figure out push input layout for invocations == 1 */
2064 if (gs_prog_data
->invocations
== 1 &&
2065 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2066 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2067 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2068 vertex_const
->u32
[0] * push_reg_count
;
2069 /* This input was pushed into registers. */
2070 if (is_point_size
) {
2071 /* gl_PointSize comes in .w */
2072 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
2074 for (unsigned i
= 0; i
< num_components
; i
++) {
2075 bld
.MOV(offset(dst
, bld
, i
),
2076 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
2082 /* Resort to the pull model. Ensure the VUE handles are provided. */
2083 gs_prog_data
->base
.include_vue_handles
= true;
2085 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2086 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2088 if (gs_prog_data
->invocations
== 1) {
2090 /* The vertex index is constant; just select the proper URB handle. */
2092 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2093 BRW_REGISTER_TYPE_UD
);
2095 /* The vertex index is non-constant. We need to use indirect
2096 * addressing to fetch the proper URB handle.
2098 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2099 * indicating that channel <n> should read the handle from
2100 * DWord <n>. We convert that to bytes by multiplying by 4.
2102 * Next, we convert the vertex index to bytes by multiplying
2103 * by 32 (shifting by 5), and add the two together. This is
2104 * the final indirect byte offset.
2106 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
2107 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2108 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2109 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2111 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2112 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2113 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2114 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2115 /* Convert vertex_index to bytes (multiply by 32) */
2116 bld
.SHL(vertex_offset_bytes
,
2117 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2119 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2121 /* Use first_icp_handle as the base offset. There is one register
2122 * of URB handles per vertex, so inform the register allocator that
2123 * we might read up to nir->info.gs.vertices_in registers.
2125 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2126 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2127 fs_reg(icp_offset_bytes
),
2128 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2131 assert(gs_prog_data
->invocations
> 1);
2134 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2136 retype(brw_vec1_grf(first_icp_handle
+
2137 vertex_const
->i32
[0] / 8,
2138 vertex_const
->i32
[0] % 8),
2139 BRW_REGISTER_TYPE_UD
));
2141 /* The vertex index is non-constant. We need to use indirect
2142 * addressing to fetch the proper URB handle.
2145 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2147 /* Convert vertex_index to bytes (multiply by 4) */
2148 bld
.SHL(icp_offset_bytes
,
2149 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2152 /* Use first_icp_handle as the base offset. There is one DWord
2153 * of URB handles per vertex, so inform the register allocator that
2154 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2156 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2157 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2158 fs_reg(icp_offset_bytes
),
2159 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2166 fs_reg tmp_dst
= dst
;
2167 fs_reg indirect_offset
= get_nir_src(offset_src
);
2168 unsigned num_iterations
= 1;
2169 unsigned orig_num_components
= num_components
;
2171 if (type_sz(dst
.type
) == 8) {
2172 if (num_components
> 2) {
2176 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2178 first_component
= first_component
/ 2;
2181 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2183 /* Constant indexing - use global offset. */
2184 if (first_component
!= 0) {
2185 unsigned read_components
= num_components
+ first_component
;
2186 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2187 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2188 inst
->regs_written
= read_components
* type_sz(tmp_dst
.type
) / 4;
2189 for (unsigned i
= 0; i
< num_components
; i
++) {
2190 bld
.MOV(offset(tmp_dst
, bld
, i
),
2191 offset(tmp
, bld
, i
+ first_component
));
2194 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2196 inst
->regs_written
= num_components
* type_sz(tmp_dst
.type
) / 4;
2198 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2201 /* Indirect indexing - use per-slot offsets as well. */
2202 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2203 unsigned read_components
= num_components
+ first_component
;
2204 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2205 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2206 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2207 if (first_component
!= 0) {
2208 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2210 inst
->regs_written
= read_components
* type_sz(tmp_dst
.type
) / 4;
2211 for (unsigned i
= 0; i
< num_components
; i
++) {
2212 bld
.MOV(offset(tmp_dst
, bld
, i
),
2213 offset(tmp
, bld
, i
+ first_component
));
2216 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2218 inst
->regs_written
= num_components
* type_sz(tmp_dst
.type
) / 4;
2220 inst
->offset
= base_offset
;
2224 if (type_sz(dst
.type
) == 8) {
2225 shuffle_32bit_load_result_to_64bit_data(
2226 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2228 for (unsigned c
= 0; c
< num_components
; c
++)
2229 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2232 if (num_iterations
> 1) {
2233 num_components
= orig_num_components
- 2;
2237 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2238 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2239 indirect_offset
= new_indirect
;
2244 if (is_point_size
) {
2245 /* Read the whole VUE header (because of alignment) and read .w. */
2246 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
2248 inst
->regs_written
= 4;
2249 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2254 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2256 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2257 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2260 /* The only constant offset we should find is 0. brw_nir.c's
2261 * add_const_offset_to_base() will fold other constant offsets
2262 * into instr->const_index[0].
2264 assert(const_value
->u32
[0] == 0);
2268 return get_nir_src(*offset_src
);
2272 do_untyped_vector_read(const fs_builder
&bld
,
2274 const fs_reg surf_index
,
2275 const fs_reg offset_reg
,
2276 unsigned num_components
)
2278 if (type_sz(dest
.type
) == 4) {
2279 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2282 BRW_PREDICATE_NONE
);
2283 read_result
.type
= dest
.type
;
2284 for (unsigned i
= 0; i
< num_components
; i
++)
2285 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2286 } else if (type_sz(dest
.type
) == 8) {
2287 /* Reading a dvec, so we need to:
2289 * 1. Multiply num_components by 2, to account for the fact that we
2290 * need to read 64-bit components.
2291 * 2. Shuffle the result of the load to form valid 64-bit elements
2292 * 3. Emit a second load (for components z/w) if needed.
2294 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2295 bld
.MOV(read_offset
, offset_reg
);
2297 int iters
= num_components
<= 2 ? 1 : 2;
2299 /* Load the dvec, the first iteration loads components x/y, the second
2300 * iteration, if needed, loads components z/w
2302 for (int it
= 0; it
< iters
; it
++) {
2303 /* Compute number of components to read in this iteration */
2304 int iter_components
= MIN2(2, num_components
);
2305 num_components
-= iter_components
;
2307 /* Read. Since this message reads 32-bit components, we need to
2308 * read twice as many components.
2310 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2312 iter_components
* 2,
2313 BRW_PREDICATE_NONE
);
2315 /* Shuffle the 32-bit load result into valid 64-bit data */
2316 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2317 shuffle_32bit_load_result_to_64bit_data(
2318 bld
, packed_result
, read_result
, iter_components
);
2320 /* Move each component to its destination */
2321 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2322 for (int c
= 0; c
< iter_components
; c
++) {
2323 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2324 offset(packed_result
, bld
, c
));
2327 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2330 unreachable("Unsupported type");
2335 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2336 nir_intrinsic_instr
*instr
)
2338 assert(stage
== MESA_SHADER_VERTEX
);
2341 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2342 dest
= get_nir_dest(instr
->dest
);
2344 switch (instr
->intrinsic
) {
2345 case nir_intrinsic_load_vertex_id
:
2346 unreachable("should be lowered by lower_vertex_id()");
2348 case nir_intrinsic_load_vertex_id_zero_base
:
2349 case nir_intrinsic_load_base_vertex
:
2350 case nir_intrinsic_load_instance_id
:
2351 case nir_intrinsic_load_base_instance
:
2352 case nir_intrinsic_load_draw_id
: {
2353 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2354 fs_reg val
= nir_system_values
[sv
];
2355 assert(val
.file
!= BAD_FILE
);
2356 dest
.type
= val
.type
;
2361 case nir_intrinsic_load_input
: {
2362 fs_reg src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2363 unsigned num_components
= instr
->num_components
;
2364 enum brw_reg_type type
= dest
.type
;
2366 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2367 assert(const_offset
&& "Indirect input loads not allowed");
2368 src
= offset(src
, bld
, const_offset
->u32
[0]);
2370 for (unsigned j
= 0; j
< num_components
; j
++) {
2371 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2374 if (type
== BRW_REGISTER_TYPE_DF
) {
2375 /* Once the double vector is read, set again its original register
2376 * type to continue with normal execution.
2378 src
= retype(src
, type
);
2379 dest
= retype(dest
, type
);
2382 if (type_sz(src
.type
) == 8) {
2383 shuffle_32bit_load_result_to_64bit_data(bld
,
2385 retype(dest
, BRW_REGISTER_TYPE_F
),
2386 instr
->num_components
);
2392 nir_emit_intrinsic(bld
, instr
);
2398 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2399 nir_intrinsic_instr
*instr
)
2401 assert(stage
== MESA_SHADER_TESS_CTRL
);
2402 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2403 struct brw_tcs_prog_data
*tcs_prog_data
=
2404 (struct brw_tcs_prog_data
*) prog_data
;
2407 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2408 dst
= get_nir_dest(instr
->dest
);
2410 switch (instr
->intrinsic
) {
2411 case nir_intrinsic_load_primitive_id
:
2412 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2414 case nir_intrinsic_load_invocation_id
:
2415 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2417 case nir_intrinsic_load_patch_vertices_in
:
2418 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2419 brw_imm_d(tcs_key
->input_vertices
));
2422 case nir_intrinsic_barrier
: {
2423 if (tcs_prog_data
->instances
== 1)
2426 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2427 fs_reg m0_2
= byte_offset(m0
, 2 * sizeof(uint32_t));
2429 const fs_builder fwa_bld
= bld
.exec_all();
2431 /* Zero the message header */
2432 fwa_bld
.MOV(m0
, brw_imm_ud(0u));
2434 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2435 fwa_bld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2436 brw_imm_ud(INTEL_MASK(16, 13)));
2438 /* Shift it up to bits 27:24. */
2439 fwa_bld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2441 /* Set the Barrier Count and the enable bit */
2442 fwa_bld
.OR(m0_2
, m0_2
,
2443 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2445 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2449 case nir_intrinsic_load_input
:
2450 unreachable("nir_lower_io should never give us these.");
2453 case nir_intrinsic_load_per_vertex_input
: {
2454 fs_reg indirect_offset
= get_indirect_offset(instr
);
2455 unsigned imm_offset
= instr
->const_index
[0];
2457 const nir_src
&vertex_src
= instr
->src
[0];
2458 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2465 /* Emit a MOV to resolve <0,1,0> regioning. */
2466 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2468 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2469 vertex_const
->i32
[0] & 7),
2470 BRW_REGISTER_TYPE_UD
));
2471 } else if (tcs_prog_data
->instances
== 1 &&
2472 vertex_src
.is_ssa
&&
2473 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2474 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2475 /* For the common case of only 1 instance, an array index of
2476 * gl_InvocationID means reading g1. Skip all the indirect work.
2478 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2480 /* The vertex index is non-constant. We need to use indirect
2481 * addressing to fetch the proper URB handle.
2483 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2485 /* Each ICP handle is a single DWord (4 bytes) */
2486 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2487 bld
.SHL(vertex_offset_bytes
,
2488 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2491 /* Start at g1. We might read up to 4 registers. */
2492 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2493 fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes
,
2494 brw_imm_ud(4 * REG_SIZE
));
2497 /* We can only read two double components with each URB read, so
2498 * we send two read messages in that case, each one loading up to
2499 * two double components.
2501 unsigned num_iterations
= 1;
2502 unsigned num_components
= instr
->num_components
;
2503 unsigned first_component
= nir_intrinsic_component(instr
);
2504 fs_reg orig_dst
= dst
;
2505 if (type_sz(dst
.type
) == 8) {
2506 first_component
= first_component
/ 2;
2507 if (instr
->num_components
> 2) {
2512 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2516 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2517 if (indirect_offset
.file
== BAD_FILE
) {
2518 /* Constant indexing - use global offset. */
2519 if (first_component
!= 0) {
2520 unsigned read_components
= num_components
+ first_component
;
2521 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2522 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2523 for (unsigned i
= 0; i
< num_components
; i
++) {
2524 bld
.MOV(offset(dst
, bld
, i
),
2525 offset(tmp
, bld
, i
+ first_component
));
2528 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2530 inst
->offset
= imm_offset
;
2533 /* Indirect indexing - use per-slot offsets as well. */
2534 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2535 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2536 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2537 if (first_component
!= 0) {
2538 unsigned read_components
= num_components
+ first_component
;
2539 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2540 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2542 for (unsigned i
= 0; i
< num_components
; i
++) {
2543 bld
.MOV(offset(dst
, bld
, i
),
2544 offset(tmp
, bld
, i
+ first_component
));
2547 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2550 inst
->offset
= imm_offset
;
2553 inst
->regs_written
=
2554 ((num_components
+ first_component
) * type_sz(dst
.type
) / 4);
2556 /* If we are reading 64-bit data using 32-bit read messages we need
2557 * build proper 64-bit data elements by shuffling the low and high
2558 * 32-bit components around like we do for other things like UBOs
2561 if (type_sz(dst
.type
) == 8) {
2562 shuffle_32bit_load_result_to_64bit_data(
2563 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2565 for (unsigned c
= 0; c
< num_components
; c
++) {
2566 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2567 offset(dst
, bld
, c
));
2571 /* Copy the temporary to the destination to deal with writemasking.
2573 * Also attempt to deal with gl_PointSize being in the .w component.
2575 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2576 assert(type_sz(dst
.type
) < 8);
2577 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2578 inst
->regs_written
= 4;
2579 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2582 /* If we are loading double data and we need a second read message
2583 * adjust the write offset
2585 if (num_iterations
> 1) {
2586 num_components
= instr
->num_components
- 2;
2593 case nir_intrinsic_load_output
:
2594 case nir_intrinsic_load_per_vertex_output
: {
2595 fs_reg indirect_offset
= get_indirect_offset(instr
);
2596 unsigned imm_offset
= instr
->const_index
[0];
2599 if (indirect_offset
.file
== BAD_FILE
) {
2600 /* Replicate the patch handle to all enabled channels */
2601 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2602 bld
.MOV(patch_handle
,
2603 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2605 if (imm_offset
== 0) {
2606 /* This is a read of gl_TessLevelInner[], which lives in the
2607 * Patch URB header. The layout depends on the domain.
2609 dst
.type
= BRW_REGISTER_TYPE_F
;
2610 switch (tcs_key
->tes_primitive_mode
) {
2612 /* DWords 3-2 (reversed) */
2613 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2615 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2618 inst
->regs_written
= 4;
2620 /* dst.xy = tmp.wz */
2621 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2622 bld
.MOV(offset(dst
, bld
, 1), offset(tmp
, bld
, 2));
2626 /* DWord 4; hardcode offset = 1 and regs_written = 1 */
2627 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2630 inst
->regs_written
= 1;
2633 /* All channels are undefined. */
2636 unreachable("Bogus tessellation domain");
2638 } else if (imm_offset
== 1) {
2639 /* This is a read of gl_TessLevelOuter[], which lives in the
2640 * Patch URB header. The layout depends on the domain.
2642 dst
.type
= BRW_REGISTER_TYPE_F
;
2644 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2645 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2648 inst
->regs_written
= 4;
2650 /* Reswizzle: WZYX */
2652 offset(tmp
, bld
, 3),
2653 offset(tmp
, bld
, 2),
2654 offset(tmp
, bld
, 1),
2655 offset(tmp
, bld
, 0),
2658 unsigned num_components
;
2659 switch (tcs_key
->tes_primitive_mode
) {
2667 /* Isolines are not reversed; swizzle .zw -> .xy */
2668 srcs
[0] = offset(tmp
, bld
, 2);
2669 srcs
[1] = offset(tmp
, bld
, 3);
2673 unreachable("Bogus tessellation domain");
2675 bld
.LOAD_PAYLOAD(dst
, srcs
, num_components
, 0);
2677 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2678 inst
->offset
= imm_offset
;
2680 inst
->regs_written
= instr
->num_components
;
2683 /* Indirect indexing - use per-slot offsets as well. */
2684 const fs_reg srcs
[] = {
2685 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2688 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2689 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2691 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2692 inst
->offset
= imm_offset
;
2694 inst
->regs_written
= instr
->num_components
;
2699 case nir_intrinsic_store_output
:
2700 case nir_intrinsic_store_per_vertex_output
: {
2701 fs_reg value
= get_nir_src(instr
->src
[0]);
2702 bool is_64bit
= (instr
->src
[0].is_ssa
?
2703 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2704 fs_reg indirect_offset
= get_indirect_offset(instr
);
2705 unsigned imm_offset
= instr
->const_index
[0];
2706 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2707 unsigned mask
= instr
->const_index
[1];
2708 unsigned header_regs
= 0;
2710 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2712 if (indirect_offset
.file
!= BAD_FILE
) {
2713 srcs
[header_regs
++] = indirect_offset
;
2714 } else if (!is_passthrough_shader
) {
2715 if (imm_offset
== 0) {
2716 value
.type
= BRW_REGISTER_TYPE_F
;
2718 mask
&= (1 << tesslevel_inner_components(tcs_key
->tes_primitive_mode
)) - 1;
2720 /* This is a write to gl_TessLevelInner[], which lives in the
2721 * Patch URB header. The layout depends on the domain.
2723 switch (tcs_key
->tes_primitive_mode
) {
2725 /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
2726 * We use an XXYX swizzle to reverse put .xy in the .wz
2727 * channels, and use a .zw writemask.
2729 mask
= writemask_for_backwards_vector(mask
);
2730 swiz
= BRW_SWIZZLE4(0, 0, 1, 0);
2733 /* gl_TessLevelInner[].x lives at DWord 4, so we set the
2734 * writemask to X and bump the URB offset by 1.
2739 /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
2742 unreachable("Bogus tessellation domain");
2744 } else if (imm_offset
== 1) {
2745 /* This is a write to gl_TessLevelOuter[] which lives in the
2746 * Patch URB Header at DWords 4-7. However, it's reversed, so
2747 * instead of .xyzw we have .wzyx.
2749 value
.type
= BRW_REGISTER_TYPE_F
;
2751 mask
&= (1 << tesslevel_outer_components(tcs_key
->tes_primitive_mode
)) - 1;
2753 if (tcs_key
->tes_primitive_mode
== GL_ISOLINES
) {
2754 /* Isolines .xy should be stored in .zw, in order. */
2755 swiz
= BRW_SWIZZLE4(0, 0, 0, 1);
2758 /* Other domains are reversed; store .wzyx instead of .xyzw */
2759 swiz
= BRW_SWIZZLE_WZYX
;
2760 mask
= writemask_for_backwards_vector(mask
);
2768 unsigned num_components
= _mesa_fls(mask
);
2771 /* We can only pack two 64-bit components in a single message, so send
2772 * 2 messages if we have more components
2774 unsigned num_iterations
= 1;
2775 unsigned iter_components
= num_components
;
2776 unsigned first_component
= nir_intrinsic_component(instr
);
2778 first_component
= first_component
/ 2;
2779 if (instr
->num_components
> 2) {
2781 iter_components
= 2;
2785 /* 64-bit data needs to me shuffled before we can write it to the URB.
2786 * We will use this temporary to shuffle the components in each
2790 fs_reg(VGRF
, alloc
.allocate(2 * iter_components
), value
.type
);
2792 mask
= mask
<< first_component
;
2794 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2795 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2796 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2797 opcode
= indirect_offset
.file
!= BAD_FILE
?
2798 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2799 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2800 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2801 /* Expand the 64-bit mask to 32-bit channels. We only handle
2802 * two channels in each iteration, so we only care about X/Y.
2804 unsigned mask32
= 0;
2805 if (mask
& WRITEMASK_X
)
2806 mask32
|= WRITEMASK_XY
;
2807 if (mask
& WRITEMASK_Y
)
2808 mask32
|= WRITEMASK_ZW
;
2810 /* If the mask does not include any of the channels X or Y there
2811 * is nothing to do in this iteration. Move on to the next couple
2812 * of 64-bit channels.
2820 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2821 opcode
= indirect_offset
.file
!= BAD_FILE
?
2822 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2823 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2825 opcode
= indirect_offset
.file
!= BAD_FILE
?
2826 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2827 SHADER_OPCODE_URB_WRITE_SIMD8
;
2830 for (unsigned i
= 0; i
< iter_components
; i
++) {
2831 if (!(mask
& (1 << (i
+ first_component
))))
2835 srcs
[header_regs
+ i
+ first_component
] =
2836 offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2838 /* We need to shuffle the 64-bit data to match the layout
2839 * expected by our 32-bit URB write messages. We use a temporary
2842 unsigned channel
= BRW_GET_SWZ(swiz
, iter
* 2 + i
);
2843 shuffle_64bit_data_for_32bit_write(bld
,
2844 retype(offset(tmp
, bld
, 2 * i
), BRW_REGISTER_TYPE_F
),
2845 retype(offset(value
, bld
, 2 * channel
), BRW_REGISTER_TYPE_DF
),
2848 /* Now copy the data to the destination */
2849 fs_reg dest
= fs_reg(VGRF
, alloc
.allocate(2), value
.type
);
2850 unsigned idx
= 2 * i
;
2851 bld
.MOV(dest
, offset(tmp
, bld
, idx
));
2852 bld
.MOV(offset(dest
, bld
, 1), offset(tmp
, bld
, idx
+ 1));
2853 srcs
[header_regs
+ idx
+ first_component
* 2] = dest
;
2854 srcs
[header_regs
+ idx
+ 1 + first_component
* 2] =
2855 offset(dest
, bld
, 1);
2860 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2861 (is_64bit
? 2 * first_component
: first_component
);
2863 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2864 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2866 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2867 inst
->offset
= imm_offset
;
2870 /* If this is a 64-bit attribute, select the next two 64-bit channels
2871 * to be handled in the next iteration.
2882 nir_emit_intrinsic(bld
, instr
);
2888 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2889 nir_intrinsic_instr
*instr
)
2891 assert(stage
== MESA_SHADER_TESS_EVAL
);
2892 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
2895 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2896 dest
= get_nir_dest(instr
->dest
);
2898 switch (instr
->intrinsic
) {
2899 case nir_intrinsic_load_primitive_id
:
2900 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2902 case nir_intrinsic_load_tess_coord
:
2903 /* gl_TessCoord is part of the payload in g1-3 */
2904 for (unsigned i
= 0; i
< 3; i
++) {
2905 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2909 case nir_intrinsic_load_tess_level_outer
:
2910 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
2911 * appears as a push-model input. So, we can simply use the ATTR file
2912 * rather than issuing URB read messages. The data is stored in the
2913 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
2916 switch (tes_prog_data
->domain
) {
2917 case BRW_TESS_DOMAIN_QUAD
:
2918 for (unsigned i
= 0; i
< 4; i
++)
2919 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2921 case BRW_TESS_DOMAIN_TRI
:
2922 for (unsigned i
= 0; i
< 3; i
++)
2923 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2925 case BRW_TESS_DOMAIN_ISOLINE
:
2926 for (unsigned i
= 0; i
< 2; i
++)
2927 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 6 + i
));
2932 case nir_intrinsic_load_tess_level_inner
:
2933 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
2934 * appears as a push-model input. So, we can simply use the ATTR file
2935 * rather than issuing URB read messages.
2937 switch (tes_prog_data
->domain
) {
2938 case BRW_TESS_DOMAIN_QUAD
:
2939 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
2940 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
2942 case BRW_TESS_DOMAIN_TRI
:
2943 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
2945 case BRW_TESS_DOMAIN_ISOLINE
:
2946 /* ignore - value is undefined */
2951 case nir_intrinsic_load_input
:
2952 case nir_intrinsic_load_per_vertex_input
: {
2953 fs_reg indirect_offset
= get_indirect_offset(instr
);
2954 unsigned imm_offset
= instr
->const_index
[0];
2955 unsigned first_component
= nir_intrinsic_component(instr
);
2957 if (type_sz(dest
.type
) == 8) {
2958 first_component
= first_component
/ 2;
2962 if (indirect_offset
.file
== BAD_FILE
) {
2963 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2964 * which is 16 registers (since each holds 2 vec4 slots).
2966 const unsigned max_push_slots
= 32;
2967 if (imm_offset
< max_push_slots
) {
2968 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2969 for (int i
= 0; i
< instr
->num_components
; i
++) {
2970 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2971 i
+ first_component
;
2972 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2974 tes_prog_data
->base
.urb_read_length
=
2975 MAX2(tes_prog_data
->base
.urb_read_length
,
2976 DIV_ROUND_UP(imm_offset
+ 1, 2));
2978 /* Replicate the patch handle to all enabled channels */
2979 const fs_reg srcs
[] = {
2980 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2982 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2983 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2985 if (first_component
!= 0) {
2986 unsigned read_components
=
2987 instr
->num_components
+ first_component
;
2988 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2989 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2991 inst
->regs_written
= read_components
;
2992 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2993 bld
.MOV(offset(dest
, bld
, i
),
2994 offset(tmp
, bld
, i
+ first_component
));
2997 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2999 inst
->regs_written
= instr
->num_components
;
3002 inst
->offset
= imm_offset
;
3005 /* Indirect indexing - use per-slot offsets as well. */
3007 /* We can only read two double components with each URB read, so
3008 * we send two read messages in that case, each one loading up to
3009 * two double components.
3011 unsigned num_iterations
= 1;
3012 unsigned num_components
= instr
->num_components
;
3013 fs_reg orig_dest
= dest
;
3014 if (type_sz(dest
.type
) == 8) {
3015 if (instr
->num_components
> 2) {
3019 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
3023 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
3024 const fs_reg srcs
[] = {
3025 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3028 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3029 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3031 if (first_component
!= 0) {
3032 unsigned read_components
=
3033 num_components
+ first_component
;
3034 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3035 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3037 for (unsigned i
= 0; i
< num_components
; i
++) {
3038 bld
.MOV(offset(dest
, bld
, i
),
3039 offset(tmp
, bld
, i
+ first_component
));
3042 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3046 inst
->offset
= imm_offset
;
3047 inst
->regs_written
=
3048 ((num_components
+ first_component
) * type_sz(dest
.type
) / 4);
3050 /* If we are reading 64-bit data using 32-bit read messages we need
3051 * build proper 64-bit data elements by shuffling the low and high
3052 * 32-bit components around like we do for other things like UBOs
3055 if (type_sz(dest
.type
) == 8) {
3056 shuffle_32bit_load_result_to_64bit_data(
3057 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
3059 for (unsigned c
= 0; c
< num_components
; c
++) {
3060 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
3061 offset(dest
, bld
, c
));
3065 /* If we are loading double data and we need a second read message
3068 if (num_iterations
> 1) {
3069 num_components
= instr
->num_components
- 2;
3077 nir_emit_intrinsic(bld
, instr
);
3083 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3084 nir_intrinsic_instr
*instr
)
3086 assert(stage
== MESA_SHADER_GEOMETRY
);
3087 fs_reg indirect_offset
;
3090 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3091 dest
= get_nir_dest(instr
->dest
);
3093 switch (instr
->intrinsic
) {
3094 case nir_intrinsic_load_primitive_id
:
3095 assert(stage
== MESA_SHADER_GEOMETRY
);
3096 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
3097 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3098 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3101 case nir_intrinsic_load_input
:
3102 unreachable("load_input intrinsics are invalid for the GS stage");
3104 case nir_intrinsic_load_per_vertex_input
:
3105 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3106 instr
->src
[1], instr
->num_components
,
3107 nir_intrinsic_component(instr
));
3110 case nir_intrinsic_emit_vertex_with_counter
:
3111 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3114 case nir_intrinsic_end_primitive_with_counter
:
3115 emit_gs_end_primitive(instr
->src
[0]);
3118 case nir_intrinsic_set_vertex_count
:
3119 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3122 case nir_intrinsic_load_invocation_id
: {
3123 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3124 assert(val
.file
!= BAD_FILE
);
3125 dest
.type
= val
.type
;
3131 nir_emit_intrinsic(bld
, instr
);
3137 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3138 nir_intrinsic_instr
*instr
)
3140 assert(stage
== MESA_SHADER_FRAGMENT
);
3143 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3144 dest
= get_nir_dest(instr
->dest
);
3146 switch (instr
->intrinsic
) {
3147 case nir_intrinsic_load_front_face
:
3148 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3149 *emit_frontfacing_interpolation());
3152 case nir_intrinsic_load_sample_pos
: {
3153 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3154 assert(sample_pos
.file
!= BAD_FILE
);
3155 dest
.type
= sample_pos
.type
;
3156 bld
.MOV(dest
, sample_pos
);
3157 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3161 case nir_intrinsic_load_helper_invocation
:
3162 case nir_intrinsic_load_sample_mask_in
:
3163 case nir_intrinsic_load_sample_id
: {
3164 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3165 fs_reg val
= nir_system_values
[sv
];
3166 assert(val
.file
!= BAD_FILE
);
3167 dest
.type
= val
.type
;
3172 case nir_intrinsic_discard
:
3173 case nir_intrinsic_discard_if
: {
3174 /* We track our discarded pixels in f0.1. By predicating on it, we can
3175 * update just the flag bits that aren't yet discarded. If there's no
3176 * condition, we emit a CMP of g0 != g0, so all currently executing
3177 * channels will get turned off.
3180 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3181 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3182 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3184 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3185 BRW_REGISTER_TYPE_UW
));
3186 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3188 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3189 cmp
->flag_subreg
= 1;
3191 if (devinfo
->gen
>= 6) {
3192 emit_discard_jump();
3197 case nir_intrinsic_load_input
: {
3198 /* load_input is only used for flat inputs */
3199 unsigned base
= nir_intrinsic_base(instr
);
3200 unsigned component
= nir_intrinsic_component(instr
);
3201 unsigned num_components
= instr
->num_components
;
3202 enum brw_reg_type type
= dest
.type
;
3204 /* Special case fields in the VUE header */
3205 if (base
== VARYING_SLOT_LAYER
)
3207 else if (base
== VARYING_SLOT_VIEWPORT
)
3210 if (nir_dest_bit_size(instr
->dest
) == 64) {
3211 /* const_index is in 32-bit type size units that could not be aligned
3212 * with DF. We need to read the double vector as if it was a float
3213 * vector of twice the number of components to fetch the right data.
3215 type
= BRW_REGISTER_TYPE_F
;
3216 num_components
*= 2;
3219 for (unsigned int i
= 0; i
< num_components
; i
++) {
3220 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3221 interp
= suboffset(interp
, 3);
3222 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3223 retype(fs_reg(interp
), type
));
3226 if (nir_dest_bit_size(instr
->dest
) == 64) {
3227 shuffle_32bit_load_result_to_64bit_data(bld
,
3230 instr
->num_components
);
3235 case nir_intrinsic_load_barycentric_pixel
:
3236 case nir_intrinsic_load_barycentric_centroid
:
3237 case nir_intrinsic_load_barycentric_sample
:
3238 /* Do nothing - load_interpolated_input handling will handle it later. */
3241 case nir_intrinsic_load_barycentric_at_sample
: {
3242 const glsl_interp_mode interpolation
=
3243 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3245 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3248 unsigned msg_data
= const_sample
->i32
[0] << 4;
3250 emit_pixel_interpolater_send(bld
,
3251 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3254 brw_imm_ud(msg_data
),
3257 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3258 BRW_REGISTER_TYPE_UD
);
3260 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3261 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3262 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3263 bld
.exec_all().group(1, 0)
3264 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3265 emit_pixel_interpolater_send(bld
,
3266 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3272 /* Make a loop that sends a message to the pixel interpolater
3273 * for the sample number in each live channel. If there are
3274 * multiple channels with the same sample number then these
3275 * will be handled simultaneously with a single interation of
3278 bld
.emit(BRW_OPCODE_DO
);
3280 /* Get the next live sample number into sample_id_reg */
3281 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3283 /* Set the flag register so that we can perform the send
3284 * message on all channels that have the same sample number
3286 bld
.CMP(bld
.null_reg_ud(),
3287 sample_src
, sample_id
,
3288 BRW_CONDITIONAL_EQ
);
3289 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3290 bld
.exec_all().group(1, 0)
3291 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3293 emit_pixel_interpolater_send(bld
,
3294 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3299 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3301 /* Continue the loop if there are any live channels left */
3302 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3304 bld
.emit(BRW_OPCODE_WHILE
));
3310 case nir_intrinsic_load_barycentric_at_offset
: {
3311 const glsl_interp_mode interpolation
=
3312 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3314 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3317 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3318 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3320 emit_pixel_interpolater_send(bld
,
3321 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3324 brw_imm_ud(off_x
| (off_y
<< 4)),
3327 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3328 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3329 BRW_REGISTER_TYPE_F
);
3330 for (int i
= 0; i
< 2; i
++) {
3331 fs_reg temp
= vgrf(glsl_type::float_type
);
3332 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3333 fs_reg itemp
= vgrf(glsl_type::int_type
);
3335 bld
.MOV(itemp
, temp
);
3337 /* Clamp the upper end of the range to +7/16.
3338 * ARB_gpu_shader5 requires that we support a maximum offset
3339 * of +0.5, which isn't representable in a S0.4 value -- if
3340 * we didn't clamp it, we'd end up with -8/16, which is the
3341 * opposite of what the shader author wanted.
3343 * This is legal due to ARB_gpu_shader5's quantization
3346 * "Not all values of <offset> may be supported; x and y
3347 * offsets may be rounded to fixed-point values with the
3348 * number of fraction bits given by the
3349 * implementation-dependent constant
3350 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3352 set_condmod(BRW_CONDITIONAL_L
,
3353 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3356 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3357 emit_pixel_interpolater_send(bld
,
3367 case nir_intrinsic_load_interpolated_input
: {
3368 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3369 emit_fragcoord_interpolation(dest
);
3373 assert(instr
->src
[0].ssa
&&
3374 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3375 nir_intrinsic_instr
*bary_intrinsic
=
3376 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3377 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3378 enum glsl_interp_mode interp_mode
=
3379 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3382 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3383 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3384 /* Use the result of the PI message */
3385 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3387 /* Use the delta_xy values computed from the payload */
3388 enum brw_barycentric_mode bary
=
3389 brw_barycentric_mode(interp_mode
, bary_intrin
);
3391 dst_xy
= this->delta_xy
[bary
];
3394 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3396 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3397 nir_intrinsic_component(instr
) + i
));
3398 interp
.type
= BRW_REGISTER_TYPE_F
;
3399 dest
.type
= BRW_REGISTER_TYPE_F
;
3401 if (devinfo
->needs_unlit_centroid_workaround
&&
3402 bary_intrin
== nir_intrinsic_load_barycentric_centroid
) {
3404 /* Get the pixel/sample mask into f0 so that we know which
3405 * pixels are lit. Then, for each channel that is unlit,
3406 * replace the centroid data with non-centroid data.
3408 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
3410 fs_reg dest_i
= offset(dest
, bld
, i
);
3411 fs_reg dst_xy_pixel
=
3412 delta_xy
[brw_barycentric_mode(interp_mode
,
3413 nir_intrinsic_load_barycentric_pixel
)];
3416 inst
= bld
.emit(FS_OPCODE_LINTERP
, dest_i
, dst_xy_pixel
, interp
);
3417 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3418 inst
->predicate_inverse
= true;
3419 inst
->no_dd_clear
= true;
3421 inst
= bld
.emit(FS_OPCODE_LINTERP
, dest_i
, dst_xy
, interp
);
3422 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3423 inst
->predicate_inverse
= false;
3424 inst
->no_dd_check
= true;
3425 } else if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3426 fs_reg tmp
= vgrf(glsl_type::float_type
);
3427 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3428 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3430 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3437 nir_emit_intrinsic(bld
, instr
);
3443 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3444 nir_intrinsic_instr
*instr
)
3446 assert(stage
== MESA_SHADER_COMPUTE
);
3447 struct brw_cs_prog_data
*cs_prog_data
=
3448 (struct brw_cs_prog_data
*) prog_data
;
3451 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3452 dest
= get_nir_dest(instr
->dest
);
3454 switch (instr
->intrinsic
) {
3455 case nir_intrinsic_barrier
:
3457 cs_prog_data
->uses_barrier
= true;
3460 case nir_intrinsic_load_local_invocation_id
:
3461 case nir_intrinsic_load_work_group_id
: {
3462 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3463 fs_reg val
= nir_system_values
[sv
];
3464 assert(val
.file
!= BAD_FILE
);
3465 dest
.type
= val
.type
;
3466 for (unsigned i
= 0; i
< 3; i
++)
3467 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3471 case nir_intrinsic_load_num_work_groups
: {
3472 const unsigned surface
=
3473 cs_prog_data
->binding_table
.work_groups_start
;
3475 cs_prog_data
->uses_num_work_groups
= true;
3477 fs_reg surf_index
= brw_imm_ud(surface
);
3478 brw_mark_surface_used(prog_data
, surface
);
3480 /* Read the 3 GLuint components of gl_NumWorkGroups */
3481 for (unsigned i
= 0; i
< 3; i
++) {
3482 fs_reg read_result
=
3483 emit_untyped_read(bld
, surf_index
,
3485 1 /* dims */, 1 /* size */,
3486 BRW_PREDICATE_NONE
);
3487 read_result
.type
= dest
.type
;
3488 bld
.MOV(dest
, read_result
);
3489 dest
= offset(dest
, bld
, 1);
3494 case nir_intrinsic_shared_atomic_add
:
3495 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3497 case nir_intrinsic_shared_atomic_imin
:
3498 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3500 case nir_intrinsic_shared_atomic_umin
:
3501 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3503 case nir_intrinsic_shared_atomic_imax
:
3504 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3506 case nir_intrinsic_shared_atomic_umax
:
3507 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3509 case nir_intrinsic_shared_atomic_and
:
3510 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3512 case nir_intrinsic_shared_atomic_or
:
3513 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3515 case nir_intrinsic_shared_atomic_xor
:
3516 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3518 case nir_intrinsic_shared_atomic_exchange
:
3519 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3521 case nir_intrinsic_shared_atomic_comp_swap
:
3522 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3525 case nir_intrinsic_load_shared
: {
3526 assert(devinfo
->gen
>= 7);
3528 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3530 /* Get the offset to read from */
3532 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3534 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3536 offset_reg
= vgrf(glsl_type::uint_type
);
3538 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3539 brw_imm_ud(instr
->const_index
[0]));
3542 /* Read the vector */
3543 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3544 instr
->num_components
);
3548 case nir_intrinsic_store_shared
: {
3549 assert(devinfo
->gen
>= 7);
3552 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3555 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3558 unsigned writemask
= instr
->const_index
[1];
3560 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3561 * since the untyped writes below operate in units of 32-bits, which
3562 * means that we need to write twice as many components each time.
3563 * Also, we have to suffle 64-bit data to be in the appropriate layout
3564 * expected by our 32-bit write messages.
3566 unsigned type_size
= 4;
3567 unsigned bit_size
= instr
->src
[0].is_ssa
?
3568 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3569 if (bit_size
== 64) {
3572 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3573 shuffle_64bit_data_for_32bit_write(
3575 retype(tmp
, BRW_REGISTER_TYPE_F
),
3576 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3577 instr
->num_components
);
3581 unsigned type_slots
= type_size
/ 4;
3583 /* Combine groups of consecutive enabled channels in one write
3584 * message. We use ffs to find the first enabled channel and then ffs on
3585 * the bit-inverse, down-shifted writemask to determine the length of
3586 * the block of enabled bits.
3589 unsigned first_component
= ffs(writemask
) - 1;
3590 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3592 /* We can't write more than 2 64-bit components at once. Limit the
3593 * length of the write to what we can do and let the next iteration
3597 length
= MIN2(2, length
);
3600 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3602 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3603 type_size
* first_component
);
3605 offset_reg
= vgrf(glsl_type::uint_type
);
3607 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3608 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3611 emit_untyped_write(bld
, surf_index
, offset_reg
,
3612 offset(val_reg
, bld
, first_component
* type_slots
),
3613 1 /* dims */, length
* type_slots
,
3614 BRW_PREDICATE_NONE
);
3616 /* Clear the bits in the writemask that we just wrote, then try
3617 * again to see if more channels are left.
3619 writemask
&= (15 << (first_component
+ length
));
3626 nir_emit_intrinsic(bld
, instr
);
3632 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3635 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3636 dest
= get_nir_dest(instr
->dest
);
3638 switch (instr
->intrinsic
) {
3639 case nir_intrinsic_atomic_counter_inc
:
3640 case nir_intrinsic_atomic_counter_dec
:
3641 case nir_intrinsic_atomic_counter_read
: {
3642 if (stage
== MESA_SHADER_FRAGMENT
&&
3643 instr
->intrinsic
!= nir_intrinsic_atomic_counter_read
)
3644 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
3646 /* Get the arguments of the atomic intrinsic. */
3647 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3648 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3649 instr
->const_index
[0]);
3652 /* Emit a surface read or atomic op. */
3653 switch (instr
->intrinsic
) {
3654 case nir_intrinsic_atomic_counter_read
:
3655 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3658 case nir_intrinsic_atomic_counter_inc
:
3659 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
3660 fs_reg(), 1, 1, BRW_AOP_INC
);
3663 case nir_intrinsic_atomic_counter_dec
:
3664 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
3665 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
3669 unreachable("Unreachable");
3672 /* Assign the result. */
3673 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3675 /* Mark the surface as used. */
3676 brw_mark_surface_used(stage_prog_data
, surface
);
3680 case nir_intrinsic_image_load
:
3681 case nir_intrinsic_image_store
:
3682 case nir_intrinsic_image_atomic_add
:
3683 case nir_intrinsic_image_atomic_min
:
3684 case nir_intrinsic_image_atomic_max
:
3685 case nir_intrinsic_image_atomic_and
:
3686 case nir_intrinsic_image_atomic_or
:
3687 case nir_intrinsic_image_atomic_xor
:
3688 case nir_intrinsic_image_atomic_exchange
:
3689 case nir_intrinsic_image_atomic_comp_swap
: {
3690 using namespace image_access
;
3692 if (stage
== MESA_SHADER_FRAGMENT
&&
3693 instr
->intrinsic
!= nir_intrinsic_image_load
)
3694 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
3696 /* Get the referenced image variable and type. */
3697 const nir_variable
*var
= instr
->variables
[0]->var
;
3698 const glsl_type
*type
= var
->type
->without_array();
3699 const brw_reg_type base_type
= get_image_base_type(type
);
3701 /* Get some metadata from the image intrinsic. */
3702 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3703 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3704 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3705 const unsigned format
= var
->data
.image
.format
;
3707 /* Get the arguments of the image intrinsic. */
3708 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3709 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3710 BRW_REGISTER_TYPE_UD
);
3711 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3712 retype(get_nir_src(instr
->src
[2]), base_type
) :
3714 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3715 retype(get_nir_src(instr
->src
[3]), base_type
) :
3719 /* Emit an image load, store or atomic op. */
3720 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3721 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3723 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3724 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3725 var
->data
.image
.write_only
? GL_NONE
: format
);
3728 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3729 surf_dims
, arr_dims
, info
->dest_components
,
3730 get_image_atomic_op(instr
->intrinsic
, type
));
3732 /* Assign the result. */
3733 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3734 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3735 offset(tmp
, bld
, c
));
3739 case nir_intrinsic_memory_barrier_atomic_counter
:
3740 case nir_intrinsic_memory_barrier_buffer
:
3741 case nir_intrinsic_memory_barrier_image
:
3742 case nir_intrinsic_memory_barrier
: {
3743 const fs_builder ubld
= bld
.group(8, 0);
3744 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3745 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3750 case nir_intrinsic_group_memory_barrier
:
3751 case nir_intrinsic_memory_barrier_shared
:
3752 /* We treat these workgroup-level barriers as no-ops. This should be
3753 * safe at present and as long as:
3755 * - Memory access instructions are not subsequently reordered by the
3756 * compiler back-end.
3758 * - All threads from a given compute shader workgroup fit within a
3759 * single subslice and therefore talk to the same HDC shared unit
3760 * what supposedly guarantees ordering and coherency between threads
3761 * from the same workgroup. This may change in the future when we
3762 * start splitting workgroups across multiple subslices.
3764 * - The context is not in fault-and-stream mode, which could cause
3765 * memory transactions (including to SLM) prior to the barrier to be
3766 * replayed after the barrier if a pagefault occurs. This shouldn't
3767 * be a problem up to and including SKL because fault-and-stream is
3768 * not usable due to hardware issues, but that's likely to change in
3773 case nir_intrinsic_shader_clock
: {
3774 /* We cannot do anything if there is an event, so ignore it for now */
3775 fs_reg shader_clock
= get_timestamp(bld
);
3776 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
3778 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3782 case nir_intrinsic_image_size
: {
3783 /* Get the referenced image variable and type. */
3784 const nir_variable
*var
= instr
->variables
[0]->var
;
3785 const glsl_type
*type
= var
->type
->without_array();
3787 /* Get the size of the image. */
3788 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3789 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3791 /* For 1DArray image types, the array index is stored in the Z component.
3792 * Fix this by swizzling the Z component to the Y component.
3794 const bool is_1d_array_image
=
3795 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3796 type
->sampler_array
;
3798 /* For CubeArray images, we should count the number of cubes instead
3799 * of the number of faces. Fix it by dividing the (Z component) by 6.
3801 const bool is_cube_array_image
=
3802 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3803 type
->sampler_array
;
3805 /* Copy all the components. */
3806 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3807 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
3808 if ((int)c
>= type
->coordinate_components()) {
3809 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3811 } else if (c
== 1 && is_1d_array_image
) {
3812 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3813 offset(size
, bld
, 2));
3814 } else if (c
== 2 && is_cube_array_image
) {
3815 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3816 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3817 offset(size
, bld
, c
), brw_imm_d(6));
3819 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3820 offset(size
, bld
, c
));
3827 case nir_intrinsic_image_samples
:
3828 /* The driver does not support multi-sampled images. */
3829 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3832 case nir_intrinsic_load_uniform
: {
3833 /* Offsets are in bytes but they should always be multiples of 4 */
3834 assert(instr
->const_index
[0] % 4 == 0);
3836 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3838 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3840 /* Offsets are in bytes but they should always be multiples of 4 */
3841 assert(const_offset
->u32
[0] % 4 == 0);
3842 src
.reg_offset
= const_offset
->u32
[0] / 4;
3844 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3845 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3848 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3849 BRW_REGISTER_TYPE_UD
);
3851 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3852 * go past the end of the uniform. In order to keep the n'th
3853 * component from running past, we subtract off the size of all but
3854 * one component of the vector.
3856 assert(instr
->const_index
[1] >=
3857 instr
->num_components
* (int) type_sz(dest
.type
));
3858 unsigned read_size
= instr
->const_index
[1] -
3859 (instr
->num_components
- 1) * type_sz(dest
.type
);
3861 fs_reg indirect_chv_high_32bit
;
3862 bool is_chv_bxt_64bit
=
3863 (devinfo
->is_cherryview
|| devinfo
->is_broxton
) &&
3864 type_sz(dest
.type
) == 8;
3865 if (is_chv_bxt_64bit
) {
3866 indirect_chv_high_32bit
= vgrf(glsl_type::uint_type
);
3867 /* Calculate indirect address to read high 32 bits */
3868 bld
.ADD(indirect_chv_high_32bit
, indirect
, brw_imm_ud(4));
3871 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3872 if (!is_chv_bxt_64bit
) {
3873 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3874 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3875 indirect
, brw_imm_ud(read_size
));
3877 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3878 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, 0),
3879 offset(src
, bld
, j
),
3880 indirect
, brw_imm_ud(read_size
));
3882 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3883 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, 1),
3884 offset(src
, bld
, j
),
3885 indirect_chv_high_32bit
, brw_imm_ud(read_size
));
3892 case nir_intrinsic_load_ubo
: {
3893 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3897 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3898 const_index
->u32
[0];
3899 surf_index
= brw_imm_ud(index
);
3900 brw_mark_surface_used(prog_data
, index
);
3902 /* The block index is not a constant. Evaluate the index expression
3903 * per-channel and add the base UBO index; we have to select a value
3904 * from any live channel.
3906 surf_index
= vgrf(glsl_type::uint_type
);
3907 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3908 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3909 surf_index
= bld
.emit_uniformize(surf_index
);
3911 /* Assume this may touch any UBO. It would be nice to provide
3912 * a tighter bound, but the array information is already lowered away.
3914 brw_mark_surface_used(prog_data
,
3915 stage_prog_data
->binding_table
.ubo_start
+
3916 nir
->info
.num_ubos
- 1);
3919 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3920 if (const_offset
== NULL
) {
3921 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3922 BRW_REGISTER_TYPE_UD
);
3924 for (int i
= 0; i
< instr
->num_components
; i
++)
3925 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3926 base_offset
, i
* type_sz(dest
.type
));
3928 /* Even if we are loading doubles, a pull constant load will load
3929 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3930 * need to load a full dvec4 we will have to emit 2 loads. This is
3931 * similar to demote_pull_constants(), except that in that case we
3932 * see individual accesses to each component of the vector and then
3933 * we let CSE deal with duplicate loads. Here we see a vector access
3934 * and we have to split it if necessary.
3936 const unsigned type_size
= type_sz(dest
.type
);
3937 const fs_reg packed_consts
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
3938 for (unsigned c
= 0; c
< instr
->num_components
;) {
3939 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
3941 /* Number of usable components in the next 16B-aligned load */
3942 const unsigned count
= MIN2(instr
->num_components
- c
,
3943 (16 - base
% 16) / type_size
);
3946 .emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3947 packed_consts
, surf_index
, brw_imm_ud(base
& ~15));
3949 const fs_reg consts
=
3950 retype(byte_offset(packed_consts
, base
& 15), dest
.type
);
3952 for (unsigned d
= 0; d
< count
; d
++)
3953 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3961 case nir_intrinsic_load_ssbo
: {
3962 assert(devinfo
->gen
>= 7);
3964 nir_const_value
*const_uniform_block
=
3965 nir_src_as_const_value(instr
->src
[0]);
3968 if (const_uniform_block
) {
3969 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3970 const_uniform_block
->u32
[0];
3971 surf_index
= brw_imm_ud(index
);
3972 brw_mark_surface_used(prog_data
, index
);
3974 surf_index
= vgrf(glsl_type::uint_type
);
3975 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3976 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3978 /* Assume this may touch any UBO. It would be nice to provide
3979 * a tighter bound, but the array information is already lowered away.
3981 brw_mark_surface_used(prog_data
,
3982 stage_prog_data
->binding_table
.ssbo_start
+
3983 nir
->info
.num_ssbos
- 1);
3987 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3989 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3991 offset_reg
= get_nir_src(instr
->src
[1]);
3994 /* Read the vector */
3995 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3996 instr
->num_components
);
4001 case nir_intrinsic_store_ssbo
: {
4002 assert(devinfo
->gen
>= 7);
4004 if (stage
== MESA_SHADER_FRAGMENT
)
4005 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
4009 nir_const_value
*const_uniform_block
=
4010 nir_src_as_const_value(instr
->src
[1]);
4011 if (const_uniform_block
) {
4012 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4013 const_uniform_block
->u32
[0];
4014 surf_index
= brw_imm_ud(index
);
4015 brw_mark_surface_used(prog_data
, index
);
4017 surf_index
= vgrf(glsl_type::uint_type
);
4018 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4019 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4021 brw_mark_surface_used(prog_data
,
4022 stage_prog_data
->binding_table
.ssbo_start
+
4023 nir
->info
.num_ssbos
- 1);
4027 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4030 unsigned writemask
= instr
->const_index
[0];
4032 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4033 * since the untyped writes below operate in units of 32-bits, which
4034 * means that we need to write twice as many components each time.
4035 * Also, we have to suffle 64-bit data to be in the appropriate layout
4036 * expected by our 32-bit write messages.
4038 unsigned type_size
= 4;
4039 unsigned bit_size
= instr
->src
[0].is_ssa
?
4040 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
4041 if (bit_size
== 64) {
4044 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
4045 shuffle_64bit_data_for_32bit_write(bld
,
4046 retype(tmp
, BRW_REGISTER_TYPE_F
),
4047 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
4048 instr
->num_components
);
4052 unsigned type_slots
= type_size
/ 4;
4054 /* Combine groups of consecutive enabled channels in one write
4055 * message. We use ffs to find the first enabled channel and then ffs on
4056 * the bit-inverse, down-shifted writemask to determine the length of
4057 * the block of enabled bits.
4060 unsigned first_component
= ffs(writemask
) - 1;
4061 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
4063 /* We can't write more than 2 64-bit components at once. Limit the
4064 * length of the write to what we can do and let the next iteration
4068 length
= MIN2(2, length
);
4071 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4073 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4074 type_size
* first_component
);
4076 offset_reg
= vgrf(glsl_type::uint_type
);
4078 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4079 brw_imm_ud(type_size
* first_component
));
4083 emit_untyped_write(bld
, surf_index
, offset_reg
,
4084 offset(val_reg
, bld
, first_component
* type_slots
),
4085 1 /* dims */, length
* type_slots
,
4086 BRW_PREDICATE_NONE
);
4088 /* Clear the bits in the writemask that we just wrote, then try
4089 * again to see if more channels are left.
4091 writemask
&= (15 << (first_component
+ length
));
4096 case nir_intrinsic_store_output
: {
4097 fs_reg src
= get_nir_src(instr
->src
[0]);
4098 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
4099 instr
->const_index
[0]);
4101 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4102 assert(const_offset
&& "Indirect output stores not allowed");
4103 new_dest
= offset(new_dest
, bld
, const_offset
->u32
[0]);
4105 unsigned num_components
= instr
->num_components
;
4106 unsigned bit_size
= instr
->src
[0].is_ssa
?
4107 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
4108 if (bit_size
== 64) {
4110 fs_reg(VGRF
, alloc
.allocate(2 * num_components
),
4111 BRW_REGISTER_TYPE_F
);
4112 shuffle_64bit_data_for_32bit_write(
4113 bld
, tmp
, retype(src
, BRW_REGISTER_TYPE_DF
), num_components
);
4114 src
= retype(tmp
, src
.type
);
4115 num_components
*= 2;
4118 for (unsigned j
= 0; j
< num_components
; j
++) {
4119 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
4124 case nir_intrinsic_ssbo_atomic_add
:
4125 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4127 case nir_intrinsic_ssbo_atomic_imin
:
4128 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4130 case nir_intrinsic_ssbo_atomic_umin
:
4131 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4133 case nir_intrinsic_ssbo_atomic_imax
:
4134 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4136 case nir_intrinsic_ssbo_atomic_umax
:
4137 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4139 case nir_intrinsic_ssbo_atomic_and
:
4140 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4142 case nir_intrinsic_ssbo_atomic_or
:
4143 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4145 case nir_intrinsic_ssbo_atomic_xor
:
4146 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4148 case nir_intrinsic_ssbo_atomic_exchange
:
4149 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4151 case nir_intrinsic_ssbo_atomic_comp_swap
:
4152 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4155 case nir_intrinsic_get_buffer_size
: {
4156 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4157 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4159 /* A resinfo's sampler message is used to get the buffer size. The
4160 * SIMD8's writeback message consists of four registers and SIMD16's
4161 * writeback message consists of 8 destination registers (two per each
4162 * component). Because we are only interested on the first channel of
4163 * the first returned component, where resinfo returns the buffer size
4164 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4165 * the dispatch width.
4167 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4168 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4169 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4172 ubld
.MOV(src_payload
, brw_imm_d(0));
4174 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4175 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4176 src_payload
, brw_imm_ud(index
));
4177 inst
->header_size
= 0;
4179 inst
->regs_written
= 4;
4181 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4182 brw_mark_surface_used(prog_data
, index
);
4186 case nir_intrinsic_load_channel_num
: {
4187 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
4188 dest
= retype(dest
, BRW_REGISTER_TYPE_UD
);
4189 const fs_builder allbld8
= bld
.group(8, 0).exec_all();
4190 allbld8
.MOV(tmp
, brw_imm_v(0x76543210));
4191 if (dispatch_width
> 8)
4192 allbld8
.ADD(byte_offset(tmp
, 16), tmp
, brw_imm_uw(8u));
4193 if (dispatch_width
> 16) {
4194 const fs_builder allbld16
= bld
.group(16, 0).exec_all();
4195 allbld16
.ADD(byte_offset(tmp
, 32), tmp
, brw_imm_uw(16u));
4202 unreachable("unknown intrinsic");
4207 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4208 int op
, nir_intrinsic_instr
*instr
)
4210 if (stage
== MESA_SHADER_FRAGMENT
)
4211 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
4214 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4215 dest
= get_nir_dest(instr
->dest
);
4218 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4219 if (const_surface
) {
4220 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4221 const_surface
->u32
[0];
4222 surface
= brw_imm_ud(surf_index
);
4223 brw_mark_surface_used(prog_data
, surf_index
);
4225 surface
= vgrf(glsl_type::uint_type
);
4226 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4227 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4229 /* Assume this may touch any SSBO. This is the same we do for other
4230 * UBO/SSBO accesses with non-constant surface.
4232 brw_mark_surface_used(prog_data
,
4233 stage_prog_data
->binding_table
.ssbo_start
+
4234 nir
->info
.num_ssbos
- 1);
4237 fs_reg offset
= get_nir_src(instr
->src
[1]);
4238 fs_reg data1
= get_nir_src(instr
->src
[2]);
4240 if (op
== BRW_AOP_CMPWR
)
4241 data2
= get_nir_src(instr
->src
[3]);
4243 /* Emit the actual atomic operation operation */
4245 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4247 1 /* dims */, 1 /* rsize */,
4249 BRW_PREDICATE_NONE
);
4250 dest
.type
= atomic_result
.type
;
4251 bld
.MOV(dest
, atomic_result
);
4255 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4256 int op
, nir_intrinsic_instr
*instr
)
4259 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4260 dest
= get_nir_dest(instr
->dest
);
4262 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4263 fs_reg offset
= get_nir_src(instr
->src
[0]);
4264 fs_reg data1
= get_nir_src(instr
->src
[1]);
4266 if (op
== BRW_AOP_CMPWR
)
4267 data2
= get_nir_src(instr
->src
[2]);
4269 /* Emit the actual atomic operation operation */
4271 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4273 1 /* dims */, 1 /* rsize */,
4275 BRW_PREDICATE_NONE
);
4276 dest
.type
= atomic_result
.type
;
4277 bld
.MOV(dest
, atomic_result
);
4281 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4283 unsigned texture
= instr
->texture_index
;
4284 unsigned sampler
= instr
->sampler_index
;
4286 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4288 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4289 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4291 int lod_components
= 0;
4293 /* The hardware requires a LOD for buffer textures */
4294 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4295 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4297 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4298 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4299 switch (instr
->src
[i
].src_type
) {
4300 case nir_tex_src_bias
:
4301 srcs
[TEX_LOGICAL_SRC_LOD
] =
4302 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4304 case nir_tex_src_comparitor
:
4305 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4307 case nir_tex_src_coord
:
4308 switch (instr
->op
) {
4310 case nir_texop_txf_ms
:
4311 case nir_texop_txf_ms_mcs
:
4312 case nir_texop_samples_identical
:
4313 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4316 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4320 case nir_tex_src_ddx
:
4321 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4322 lod_components
= nir_tex_instr_src_size(instr
, i
);
4324 case nir_tex_src_ddy
:
4325 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4327 case nir_tex_src_lod
:
4328 switch (instr
->op
) {
4330 srcs
[TEX_LOGICAL_SRC_LOD
] =
4331 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4334 srcs
[TEX_LOGICAL_SRC_LOD
] =
4335 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4338 srcs
[TEX_LOGICAL_SRC_LOD
] =
4339 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4343 case nir_tex_src_ms_index
:
4344 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4347 case nir_tex_src_offset
: {
4348 nir_const_value
*const_offset
=
4349 nir_src_as_const_value(instr
->src
[i
].src
);
4351 unsigned header_bits
= brw_texture_offset(const_offset
->i32
, 3);
4352 if (header_bits
!= 0)
4353 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] = brw_imm_ud(header_bits
);
4355 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] =
4356 retype(src
, BRW_REGISTER_TYPE_D
);
4361 case nir_tex_src_projector
:
4362 unreachable("should be lowered");
4364 case nir_tex_src_texture_offset
: {
4365 /* Figure out the highest possible texture index and mark it as used */
4366 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4367 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4368 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4370 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4372 brw_mark_surface_used(prog_data
, max_used
);
4374 /* Emit code to evaluate the actual indexing expression */
4375 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4376 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4377 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4381 case nir_tex_src_sampler_offset
: {
4382 /* Emit code to evaluate the actual indexing expression */
4383 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4384 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4385 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4389 case nir_tex_src_ms_mcs
:
4390 assert(instr
->op
== nir_texop_txf_ms
);
4391 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4394 case nir_tex_src_plane
: {
4395 nir_const_value
*const_plane
=
4396 nir_src_as_const_value(instr
->src
[i
].src
);
4397 const uint32_t plane
= const_plane
->u32
[0];
4398 const uint32_t texture_index
=
4399 instr
->texture_index
+
4400 stage_prog_data
->binding_table
.plane_start
[plane
] -
4401 stage_prog_data
->binding_table
.texture_start
;
4403 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4408 unreachable("unknown texture source");
4412 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4413 (instr
->op
== nir_texop_txf_ms
||
4414 instr
->op
== nir_texop_samples_identical
)) {
4415 if (devinfo
->gen
>= 7 &&
4416 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4417 srcs
[TEX_LOGICAL_SRC_MCS
] =
4418 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4419 instr
->coord_components
,
4420 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4422 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4426 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4427 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4429 if (instr
->op
== nir_texop_query_levels
) {
4430 /* textureQueryLevels() is implemented in terms of TXS so we need to
4431 * pass a valid LOD argument.
4433 assert(srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
);
4434 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
4438 switch (instr
->op
) {
4440 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
4443 opcode
= FS_OPCODE_TXB_LOGICAL
;
4446 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4449 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4452 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4454 case nir_texop_txf_ms
:
4455 if ((key_tex
->msaa_16
& (1 << sampler
)))
4456 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4458 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4460 case nir_texop_txf_ms_mcs
:
4461 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4463 case nir_texop_query_levels
:
4465 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4468 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4471 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= BAD_FILE
&&
4472 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= IMM
)
4473 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4475 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4477 case nir_texop_texture_samples
:
4478 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4480 case nir_texop_samples_identical
: {
4481 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4483 /* If mcs is an immediate value, it means there is no MCS. In that case
4484 * just return false.
4486 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4487 bld
.MOV(dst
, brw_imm_ud(0u));
4488 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4489 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4490 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4491 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4492 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4494 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4495 BRW_CONDITIONAL_EQ
);
4500 unreachable("unknown texture opcode");
4503 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(instr
->dest_type
), 4);
4504 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4506 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4507 if (devinfo
->gen
>= 9 &&
4508 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4509 unsigned write_mask
= instr
->dest
.is_ssa
?
4510 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4511 (1 << dest_size
) - 1;
4512 assert(write_mask
!= 0); /* dead code should have been eliminated */
4513 inst
->regs_written
= _mesa_fls(write_mask
) * dispatch_width
/ 8;
4515 inst
->regs_written
= 4 * dispatch_width
/ 8;
4518 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4519 inst
->shadow_compare
= true;
4521 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
== IMM
)
4522 inst
->offset
= srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].ud
;
4524 if (instr
->op
== nir_texop_tg4
) {
4525 if (instr
->component
== 1 &&
4526 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4527 /* gather4 sampler is broken for green channel on RG32F --
4528 * we must ask for blue instead.
4530 inst
->offset
|= 2 << 16;
4532 inst
->offset
|= instr
->component
<< 16;
4535 if (devinfo
->gen
== 6)
4536 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4540 for (unsigned i
= 0; i
< dest_size
; i
++)
4541 nir_dest
[i
] = offset(dst
, bld
, i
);
4543 if (instr
->op
== nir_texop_query_levels
) {
4544 /* # levels is in .w */
4545 nir_dest
[0] = offset(dst
, bld
, 3);
4546 } else if (instr
->op
== nir_texop_txs
&&
4547 dest_size
>= 3 && devinfo
->gen
< 7) {
4548 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4549 fs_reg depth
= offset(dst
, bld
, 2);
4550 nir_dest
[2] = vgrf(glsl_type::int_type
);
4551 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4554 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4558 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4560 switch (instr
->type
) {
4561 case nir_jump_break
:
4562 bld
.emit(BRW_OPCODE_BREAK
);
4564 case nir_jump_continue
:
4565 bld
.emit(BRW_OPCODE_CONTINUE
);
4567 case nir_jump_return
:
4569 unreachable("unknown jump");
4574 * This helper takes the result of a load operation that reads 32-bit elements
4582 * and shuffles the data to get this:
4589 * Which is exactly what we want if the load is reading 64-bit components
4590 * like doubles, where x represents the low 32-bit of the x double component
4591 * and y represents the high 32-bit of the x double component (likewise with
4592 * z and w for double component y). The parameter @components represents
4593 * the number of 64-bit components present in @src. This would typically be
4594 * 2 at most, since we can only fit 2 double elements in the result of a
4597 * Notice that @dst and @src can be the same register.
4600 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4603 uint32_t components
)
4605 assert(type_sz(src
.type
) == 4);
4606 assert(type_sz(dst
.type
) == 8);
4608 /* A temporary that we will use to shuffle the 32-bit data of each
4609 * component in the vector into valid 64-bit data. We can't write directly
4610 * to dst because dst can be (and would usually be) the same as src
4611 * and in that case the first MOV in the loop below would overwrite the
4612 * data read in the second MOV.
4614 fs_reg tmp
= bld
.vgrf(dst
.type
);
4616 for (unsigned i
= 0; i
< components
; i
++) {
4617 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4619 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4620 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4622 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4627 * This helper does the inverse operation of
4628 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4630 * We need to do this when we are going to use untyped write messsages that
4631 * operate with 32-bit components in order to arrange our 64-bit data to be
4632 * in the expected layout.
4634 * Notice that callers of this function, unlike in the case of the inverse
4635 * operation, would typically need to call this with dst and src being
4636 * different registers, since they would otherwise corrupt the original
4637 * 64-bit data they are about to write. Because of this the function checks
4638 * that the src and dst regions involved in the operation do not overlap.
4641 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4644 uint32_t components
)
4646 assert(type_sz(src
.type
) == 8);
4647 assert(type_sz(dst
.type
) == 4);
4649 assert(!src
.in_range(dst
, 2 * components
* bld
.dispatch_width() / 8));
4651 for (unsigned i
= 0; i
< components
; i
++) {
4652 const fs_reg component_i
= offset(src
, bld
, i
);
4653 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4654 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4659 setup_imm_df(const fs_builder
&bld
, double v
)
4661 const struct brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4662 assert(devinfo
->gen
>= 7);
4664 if (devinfo
->gen
>= 8)
4665 return brw_imm_df(v
);
4667 /* gen7.5 does not support DF immediates straighforward but the DIM
4668 * instruction allows to set the 64-bit immediate value.
4670 if (devinfo
->is_haswell
) {
4671 const fs_builder ubld
= bld
.exec_all();
4672 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4673 ubld
.DIM(dst
, brw_imm_df(v
));
4674 return component(dst
, 0);
4677 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4678 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4679 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4681 * Alternatively, we could also produce a normal VGRF (without stride 0)
4682 * by writing to all the channels in the VGRF, however, that would hit the
4683 * gen7 bug where we have to split writes that span more than 1 register
4684 * into instructions with a width of 4 (otherwise the write to the second
4685 * register written runs into an execmask hardware bug) which isn't very
4698 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4699 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4700 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4701 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4703 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);