2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "program/prog_to_nir.h"
29 #include "brw_fs_surface_builder.h"
35 fs_visitor::emit_nir_code()
37 nir_shader
*nir
= prog
->nir
;
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
43 if (nir
->num_inputs
> 0) {
44 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
45 nir_setup_inputs(nir
);
48 if (nir
->num_outputs
> 0) {
49 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
50 nir_setup_outputs(nir
);
53 if (nir
->num_uniforms
> 0) {
54 nir_setup_uniforms(nir
);
57 nir_emit_system_values(nir
);
59 /* get the main function and emit it */
60 nir_foreach_overload(nir
, overload
) {
61 assert(strcmp(overload
->function
->name
, "main") == 0);
62 assert(overload
->impl
);
63 nir_emit_impl(overload
->impl
);
68 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
70 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
71 enum brw_reg_type type
= brw_type_for_base_type(var
->type
);
72 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
76 case MESA_SHADER_VERTEX
: {
77 /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
78 * stored in nir_variable::location.
80 * However, NIR's load_input intrinsics use a different index - an
81 * offset into a single contiguous array containing all inputs.
82 * This index corresponds to the nir_variable::driver_location field.
84 * So, we need to copy from fs_reg(ATTR, var->location) to
85 * offset(nir_inputs, var->data.driver_location).
87 const glsl_type
*const t
= var
->type
->without_array();
88 const unsigned components
= t
->components();
89 const unsigned cols
= t
->matrix_columns
;
90 const unsigned elts
= t
->vector_elements
;
91 unsigned array_length
= var
->type
->is_array() ? var
->type
->length
: 1;
92 for (unsigned i
= 0; i
< array_length
; i
++) {
93 for (unsigned j
= 0; j
< cols
; j
++) {
94 for (unsigned k
= 0; k
< elts
; k
++) {
95 bld
.MOV(offset(retype(input
, type
), bld
,
96 components
* i
+ elts
* j
+ k
),
97 offset(fs_reg(ATTR
, var
->data
.location
+ i
, type
),
104 case MESA_SHADER_GEOMETRY
:
105 case MESA_SHADER_COMPUTE
:
106 case MESA_SHADER_TESS_CTRL
:
107 case MESA_SHADER_TESS_EVAL
:
108 unreachable("fs_visitor not used for these stages yet.");
110 case MESA_SHADER_FRAGMENT
:
111 if (var
->data
.location
== VARYING_SLOT_POS
) {
112 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
113 var
->data
.origin_upper_left
);
114 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
117 emit_general_interpolation(input
, var
->name
, var
->type
,
118 (glsl_interp_qualifier
) var
->data
.interpolation
,
119 var
->data
.location
, var
->data
.centroid
,
128 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
130 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
132 foreach_list_typed(nir_variable
, var
, node
, &shader
->outputs
) {
133 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
135 int vector_elements
=
136 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
137 : var
->type
->vector_elements
;
140 case MESA_SHADER_VERTEX
:
141 for (int i
= 0; i
< ALIGN(type_size(var
->type
), 4) / 4; i
++) {
142 int output
= var
->data
.location
+ i
;
143 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
144 this->output_components
[output
] = vector_elements
;
147 case MESA_SHADER_FRAGMENT
:
148 if (var
->data
.index
> 0) {
149 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
150 assert(var
->data
.index
== 1);
151 this->dual_src_output
= reg
;
152 this->do_dual_src
= true;
153 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
154 /* Writing gl_FragColor outputs to all color regions. */
155 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
156 this->outputs
[i
] = reg
;
157 this->output_components
[i
] = 4;
159 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
160 this->frag_depth
= reg
;
161 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
162 this->sample_mask
= reg
;
164 /* gl_FragData or a user-defined FS output */
165 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
166 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
168 /* General color output. */
169 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
170 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
171 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
172 this->output_components
[output
] = vector_elements
;
177 unreachable("unhandled shader stage");
183 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
185 num_direct_uniforms
= shader
->num_direct_uniforms
;
187 if (dispatch_width
!= 8)
190 /* We split the uniform register file in half. The first half is
191 * entirely direct uniforms. The second half is indirect.
193 param_size
[0] = num_direct_uniforms
;
194 if (shader
->num_uniforms
> num_direct_uniforms
)
195 param_size
[num_direct_uniforms
] = shader
->num_uniforms
- num_direct_uniforms
;
197 uniforms
= shader
->num_uniforms
;
200 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
201 /* UBO's and atomics don't take up space in the uniform file */
202 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
205 if (strncmp(var
->name
, "gl_", 3) == 0)
206 nir_setup_builtin_uniform(var
);
208 nir_setup_uniform(var
);
211 /* prog_to_nir doesn't create uniform variables; set param up directly. */
212 for (unsigned p
= 0; p
< prog
->Parameters
->NumParameters
; p
++) {
213 for (unsigned int i
= 0; i
< 4; i
++) {
214 stage_prog_data
->param
[4 * p
+ i
] =
215 &prog
->Parameters
->ParameterValues
[p
][i
];
222 fs_visitor::nir_setup_uniform(nir_variable
*var
)
224 int namelen
= strlen(var
->name
);
226 /* The data for our (non-builtin) uniforms is stored in a series of
227 * gl_uniform_driver_storage structs for each subcomponent that
228 * glGetUniformLocation() could name. We know it's been set up in the
229 * same order we'd walk the type, so walk the list of storage and find
230 * anything with our name, or the prefix of a component that starts with
233 unsigned index
= var
->data
.driver_location
;
234 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
235 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
237 if (storage
->builtin
)
240 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
241 (storage
->name
[namelen
] != 0 &&
242 storage
->name
[namelen
] != '.' &&
243 storage
->name
[namelen
] != '[')) {
247 unsigned slots
= storage
->type
->component_slots();
248 if (storage
->array_elements
)
249 slots
*= storage
->array_elements
;
251 for (unsigned i
= 0; i
< slots
; i
++) {
252 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
256 /* Make sure we actually initialized the right amount of stuff here. */
257 assert(var
->data
.driver_location
+ var
->type
->component_slots() == index
);
261 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
263 const nir_state_slot
*const slots
= var
->state_slots
;
264 assert(var
->state_slots
!= NULL
);
266 unsigned uniform_index
= var
->data
.driver_location
;
267 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
268 /* This state reference has already been setup by ir_to_mesa, but we'll
269 * get the same index back here.
271 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
272 (gl_state_index
*)slots
[i
].tokens
);
274 /* Add each of the unique swizzles of the element as a parameter.
275 * This'll end up matching the expected layout of the
276 * array/matrix/structure we're trying to fill in.
279 for (unsigned int j
= 0; j
< 4; j
++) {
280 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
281 if (swiz
== last_swiz
)
285 stage_prog_data
->param
[uniform_index
++] =
286 &prog
->Parameters
->ParameterValues
[index
][swiz
];
292 emit_system_values_block(nir_block
*block
, void *void_visitor
)
294 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
297 nir_foreach_instr(block
, instr
) {
298 if (instr
->type
!= nir_instr_type_intrinsic
)
301 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
302 switch (intrin
->intrinsic
) {
303 case nir_intrinsic_load_vertex_id
:
304 unreachable("should be lowered by lower_vertex_id().");
306 case nir_intrinsic_load_vertex_id_zero_base
:
307 assert(v
->stage
== MESA_SHADER_VERTEX
);
308 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
309 if (reg
->file
== BAD_FILE
)
310 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
313 case nir_intrinsic_load_base_vertex
:
314 assert(v
->stage
== MESA_SHADER_VERTEX
);
315 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
316 if (reg
->file
== BAD_FILE
)
317 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
320 case nir_intrinsic_load_instance_id
:
321 assert(v
->stage
== MESA_SHADER_VERTEX
);
322 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
323 if (reg
->file
== BAD_FILE
)
324 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
327 case nir_intrinsic_load_sample_pos
:
328 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
329 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
330 if (reg
->file
== BAD_FILE
)
331 *reg
= *v
->emit_samplepos_setup();
334 case nir_intrinsic_load_sample_id
:
335 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
336 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
337 if (reg
->file
== BAD_FILE
)
338 *reg
= *v
->emit_sampleid_setup();
341 case nir_intrinsic_load_sample_mask_in
:
342 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
343 assert(v
->devinfo
->gen
>= 7);
344 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
345 if (reg
->file
== BAD_FILE
)
346 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
347 BRW_REGISTER_TYPE_D
));
359 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
361 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
362 nir_foreach_overload(shader
, overload
) {
363 assert(strcmp(overload
->function
->name
, "main") == 0);
364 assert(overload
->impl
);
365 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
370 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
372 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
373 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
374 unsigned array_elems
=
375 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
376 unsigned size
= array_elems
* reg
->num_components
;
377 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
380 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
383 nir_emit_cf_list(&impl
->body
);
387 fs_visitor::nir_emit_cf_list(exec_list
*list
)
389 exec_list_validate(list
);
390 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
391 switch (node
->type
) {
393 nir_emit_if(nir_cf_node_as_if(node
));
396 case nir_cf_node_loop
:
397 nir_emit_loop(nir_cf_node_as_loop(node
));
400 case nir_cf_node_block
:
401 nir_emit_block(nir_cf_node_as_block(node
));
405 unreachable("Invalid CFG node block");
411 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
413 /* first, put the condition into f0 */
414 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
415 retype(get_nir_src(if_stmt
->condition
),
416 BRW_REGISTER_TYPE_D
));
417 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
419 bld
.IF(BRW_PREDICATE_NORMAL
);
421 nir_emit_cf_list(&if_stmt
->then_list
);
423 /* note: if the else is empty, dead CF elimination will remove it */
424 bld
.emit(BRW_OPCODE_ELSE
);
426 nir_emit_cf_list(&if_stmt
->else_list
);
428 bld
.emit(BRW_OPCODE_ENDIF
);
430 try_replace_with_sel();
434 fs_visitor::nir_emit_loop(nir_loop
*loop
)
436 bld
.emit(BRW_OPCODE_DO
);
438 nir_emit_cf_list(&loop
->body
);
440 bld
.emit(BRW_OPCODE_WHILE
);
444 fs_visitor::nir_emit_block(nir_block
*block
)
446 nir_foreach_instr(block
, instr
) {
447 nir_emit_instr(instr
);
452 fs_visitor::nir_emit_instr(nir_instr
*instr
)
454 const fs_builder abld
= bld
.annotate(NULL
, instr
);
456 switch (instr
->type
) {
457 case nir_instr_type_alu
:
458 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
461 case nir_instr_type_intrinsic
:
462 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 case nir_instr_type_tex
:
466 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
469 case nir_instr_type_load_const
:
470 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
473 case nir_instr_type_ssa_undef
:
474 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
477 case nir_instr_type_jump
:
478 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
482 unreachable("unknown instruction type");
487 brw_type_for_nir_type(nir_alu_type type
)
490 case nir_type_unsigned
:
491 return BRW_REGISTER_TYPE_UD
;
494 return BRW_REGISTER_TYPE_D
;
496 return BRW_REGISTER_TYPE_F
;
498 unreachable("unknown type");
501 return BRW_REGISTER_TYPE_F
;
505 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
506 const fs_reg
&result
)
508 if (!instr
->src
[0].src
.is_ssa
||
509 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
512 nir_intrinsic_instr
*src0
=
513 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
515 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
518 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
519 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
522 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
523 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
526 fs_reg tmp
= vgrf(glsl_type::int_type
);
528 if (devinfo
->gen
>= 6) {
529 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
530 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
532 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
534 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
535 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
537 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
539 * This negation looks like it's safe in practice, because bits 0:4 will
540 * surely be TRIANGLES
543 if (value1
->f
[0] == -1.0f
) {
547 tmp
.type
= BRW_REGISTER_TYPE_W
;
548 tmp
.subreg_offset
= 2;
551 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
552 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
554 tmp
.type
= BRW_REGISTER_TYPE_D
;
555 tmp
.subreg_offset
= 0;
558 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
559 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
561 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
563 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
564 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
566 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
568 * This negation looks like it's safe in practice, because bits 0:4 will
569 * surely be TRIANGLES
572 if (value1
->f
[0] == -1.0f
) {
576 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
578 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
584 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
586 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
589 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
590 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
593 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
594 op
[i
] = get_nir_src(instr
->src
[i
].src
);
595 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
596 op
[i
].abs
= instr
->src
[i
].abs
;
597 op
[i
].negate
= instr
->src
[i
].negate
;
600 /* We get a bunch of mov's out of the from_ssa pass and they may still
601 * be vectorized. We'll handle them as a special-case. We'll also
602 * handle vecN here because it's basically the same thing.
610 fs_reg temp
= result
;
611 bool need_extra_copy
= false;
612 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
613 if (!instr
->src
[i
].src
.is_ssa
&&
614 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
615 need_extra_copy
= true;
616 temp
= bld
.vgrf(result
.type
, 4);
621 for (unsigned i
= 0; i
< 4; i
++) {
622 if (!(instr
->dest
.write_mask
& (1 << i
)))
625 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
626 inst
= bld
.MOV(offset(temp
, bld
, i
),
627 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
629 inst
= bld
.MOV(offset(temp
, bld
, i
),
630 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
632 inst
->saturate
= instr
->dest
.saturate
;
635 /* In this case the source and destination registers were the same,
636 * so we need to insert an extra set of moves in order to deal with
639 if (need_extra_copy
) {
640 for (unsigned i
= 0; i
< 4; i
++) {
641 if (!(instr
->dest
.write_mask
& (1 << i
)))
644 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
653 /* At this point, we have dealt with any instruction that operates on
654 * more than a single channel. Therefore, we can just adjust the source
655 * and destination registers for that channel and emit the instruction.
657 unsigned channel
= 0;
658 if (nir_op_infos
[instr
->op
].output_size
== 0) {
659 /* Since NIR is doing the scalarizing for us, we should only ever see
660 * vectorized operations with a single channel.
662 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
663 channel
= ffs(instr
->dest
.write_mask
) - 1;
665 result
= offset(result
, bld
, channel
);
668 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
669 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
670 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
676 inst
= bld
.MOV(result
, op
[0]);
677 inst
->saturate
= instr
->dest
.saturate
;
682 bld
.MOV(result
, op
[0]);
686 /* AND(val, 0x80000000) gives the sign bit.
688 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
691 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
693 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
694 op
[0].type
= BRW_REGISTER_TYPE_UD
;
695 result
.type
= BRW_REGISTER_TYPE_UD
;
696 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
698 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
699 inst
->predicate
= BRW_PREDICATE_NORMAL
;
700 if (instr
->dest
.saturate
) {
701 inst
= bld
.MOV(result
, result
);
702 inst
->saturate
= true;
708 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
709 * -> non-negative val generates 0x00000000.
710 * Predicated OR sets 1 if val is positive.
712 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
713 bld
.ASR(result
, op
[0], fs_reg(31));
714 inst
= bld
.OR(result
, result
, fs_reg(1));
715 inst
->predicate
= BRW_PREDICATE_NORMAL
;
719 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
720 inst
->saturate
= instr
->dest
.saturate
;
724 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
725 inst
->saturate
= instr
->dest
.saturate
;
729 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
730 inst
->saturate
= instr
->dest
.saturate
;
734 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
735 inst
->saturate
= instr
->dest
.saturate
;
739 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
740 inst
->saturate
= instr
->dest
.saturate
;
744 if (fs_key
->high_quality_derivatives
) {
745 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
747 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
749 inst
->saturate
= instr
->dest
.saturate
;
751 case nir_op_fddx_fine
:
752 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
753 inst
->saturate
= instr
->dest
.saturate
;
755 case nir_op_fddx_coarse
:
756 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
757 inst
->saturate
= instr
->dest
.saturate
;
760 if (fs_key
->high_quality_derivatives
) {
761 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
762 fs_reg(fs_key
->render_to_fbo
));
764 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
765 fs_reg(fs_key
->render_to_fbo
));
767 inst
->saturate
= instr
->dest
.saturate
;
769 case nir_op_fddy_fine
:
770 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
771 fs_reg(fs_key
->render_to_fbo
));
772 inst
->saturate
= instr
->dest
.saturate
;
774 case nir_op_fddy_coarse
:
775 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
776 fs_reg(fs_key
->render_to_fbo
));
777 inst
->saturate
= instr
->dest
.saturate
;
782 inst
= bld
.ADD(result
, op
[0], op
[1]);
783 inst
->saturate
= instr
->dest
.saturate
;
787 inst
= bld
.MUL(result
, op
[0], op
[1]);
788 inst
->saturate
= instr
->dest
.saturate
;
792 bld
.MUL(result
, op
[0], op
[1]);
795 case nir_op_imul_high
:
796 case nir_op_umul_high
: {
797 if (devinfo
->gen
>= 7)
798 no16("SIMD16 explicit accumulator operands unsupported\n");
800 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
802 fs_inst
*mul
= bld
.MUL(acc
, op
[0], op
[1]);
803 bld
.MACH(result
, op
[0], op
[1]);
805 /* Until Gen8, integer multiplies read 32-bits from one source, and
806 * 16-bits from the other, and relying on the MACH instruction to
807 * generate the high bits of the result.
809 * On Gen8, the multiply instruction does a full 32x32-bit multiply,
810 * but in order to do a 64x64-bit multiply we have to simulate the
811 * previous behavior and then use a MACH instruction.
813 * FINISHME: Don't use source modifiers on src1.
815 if (devinfo
->gen
>= 8) {
816 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
817 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
818 if (mul
->src
[1].type
== BRW_REGISTER_TYPE_D
) {
819 mul
->src
[1].type
= BRW_REGISTER_TYPE_W
;
820 mul
->src
[1].stride
= 2;
822 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
823 mul
->src
[1].stride
= 2;
831 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
834 case nir_op_uadd_carry
:
835 unreachable("Should have been lowered by carry_to_arith().");
837 case nir_op_usub_borrow
:
838 unreachable("Should have been lowered by borrow_to_arith().");
841 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
847 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
853 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
858 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
863 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
867 if (devinfo
->gen
>= 8) {
868 resolve_source_modifiers(&op
[0]);
870 bld
.NOT(result
, op
[0]);
873 if (devinfo
->gen
>= 8) {
874 resolve_source_modifiers(&op
[0]);
875 resolve_source_modifiers(&op
[1]);
877 bld
.XOR(result
, op
[0], op
[1]);
880 if (devinfo
->gen
>= 8) {
881 resolve_source_modifiers(&op
[0]);
882 resolve_source_modifiers(&op
[1]);
884 bld
.OR(result
, op
[0], op
[1]);
887 if (devinfo
->gen
>= 8) {
888 resolve_source_modifiers(&op
[0]);
889 resolve_source_modifiers(&op
[1]);
891 bld
.AND(result
, op
[0], op
[1]);
903 case nir_op_ball_fequal2
:
904 case nir_op_ball_iequal2
:
905 case nir_op_ball_fequal3
:
906 case nir_op_ball_iequal3
:
907 case nir_op_ball_fequal4
:
908 case nir_op_ball_iequal4
:
909 case nir_op_bany_fnequal2
:
910 case nir_op_bany_inequal2
:
911 case nir_op_bany_fnequal3
:
912 case nir_op_bany_inequal3
:
913 case nir_op_bany_fnequal4
:
914 case nir_op_bany_inequal4
:
915 unreachable("Lowered by nir_lower_alu_reductions");
917 case nir_op_fnoise1_1
:
918 case nir_op_fnoise1_2
:
919 case nir_op_fnoise1_3
:
920 case nir_op_fnoise1_4
:
921 case nir_op_fnoise2_1
:
922 case nir_op_fnoise2_2
:
923 case nir_op_fnoise2_3
:
924 case nir_op_fnoise2_4
:
925 case nir_op_fnoise3_1
:
926 case nir_op_fnoise3_2
:
927 case nir_op_fnoise3_3
:
928 case nir_op_fnoise3_4
:
929 case nir_op_fnoise4_1
:
930 case nir_op_fnoise4_2
:
931 case nir_op_fnoise4_3
:
932 case nir_op_fnoise4_4
:
933 unreachable("not reached: should be handled by lower_noise");
936 unreachable("not reached: should be handled by ldexp_to_arith()");
939 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
940 inst
->saturate
= instr
->dest
.saturate
;
944 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
945 inst
->saturate
= instr
->dest
.saturate
;
950 bld
.MOV(result
, negate(op
[0]));
954 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
957 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
961 inst
= bld
.RNDZ(result
, op
[0]);
962 inst
->saturate
= instr
->dest
.saturate
;
966 op
[0].negate
= !op
[0].negate
;
967 fs_reg temp
= vgrf(glsl_type::float_type
);
968 bld
.RNDD(temp
, op
[0]);
970 inst
= bld
.MOV(result
, temp
);
971 inst
->saturate
= instr
->dest
.saturate
;
975 inst
= bld
.RNDD(result
, op
[0]);
976 inst
->saturate
= instr
->dest
.saturate
;
979 inst
= bld
.FRC(result
, op
[0]);
980 inst
->saturate
= instr
->dest
.saturate
;
982 case nir_op_fround_even
:
983 inst
= bld
.RNDE(result
, op
[0]);
984 inst
->saturate
= instr
->dest
.saturate
;
990 if (devinfo
->gen
>= 6) {
991 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
992 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
994 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
995 inst
= bld
.SEL(result
, op
[0], op
[1]);
996 inst
->predicate
= BRW_PREDICATE_NORMAL
;
998 inst
->saturate
= instr
->dest
.saturate
;
1004 if (devinfo
->gen
>= 6) {
1005 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1006 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1008 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
1009 inst
= bld
.SEL(result
, op
[0], op
[1]);
1010 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1012 inst
->saturate
= instr
->dest
.saturate
;
1015 case nir_op_pack_snorm_2x16
:
1016 case nir_op_pack_snorm_4x8
:
1017 case nir_op_pack_unorm_2x16
:
1018 case nir_op_pack_unorm_4x8
:
1019 case nir_op_unpack_snorm_2x16
:
1020 case nir_op_unpack_snorm_4x8
:
1021 case nir_op_unpack_unorm_2x16
:
1022 case nir_op_unpack_unorm_4x8
:
1023 case nir_op_unpack_half_2x16
:
1024 case nir_op_pack_half_2x16
:
1025 unreachable("not reached: should be handled by lower_packing_builtins");
1027 case nir_op_unpack_half_2x16_split_x
:
1028 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1029 inst
->saturate
= instr
->dest
.saturate
;
1031 case nir_op_unpack_half_2x16_split_y
:
1032 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1033 inst
->saturate
= instr
->dest
.saturate
;
1037 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1038 inst
->saturate
= instr
->dest
.saturate
;
1041 case nir_op_bitfield_reverse
:
1042 bld
.BFREV(result
, op
[0]);
1045 case nir_op_bit_count
:
1046 bld
.CBIT(result
, op
[0]);
1049 case nir_op_ufind_msb
:
1050 case nir_op_ifind_msb
: {
1051 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1053 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1054 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1055 * subtract the result from 31 to convert the MSB count into an LSB count.
1058 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
1059 fs_reg
neg_result(result
);
1060 neg_result
.negate
= true;
1061 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
1062 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1066 case nir_op_find_lsb
:
1067 bld
.FBL(result
, op
[0]);
1070 case nir_op_ubitfield_extract
:
1071 case nir_op_ibitfield_extract
:
1072 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1075 bld
.BFI1(result
, op
[0], op
[1]);
1078 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1081 case nir_op_bitfield_insert
:
1082 unreachable("not reached: should be handled by "
1083 "lower_instructions::bitfield_insert_to_bfm_bfi");
1086 bld
.SHL(result
, op
[0], op
[1]);
1089 bld
.ASR(result
, op
[0], op
[1]);
1092 bld
.SHR(result
, op
[0], op
[1]);
1095 case nir_op_pack_half_2x16_split
:
1096 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1100 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1101 inst
->saturate
= instr
->dest
.saturate
;
1105 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1106 inst
->saturate
= instr
->dest
.saturate
;
1110 if (optimize_frontfacing_ternary(instr
, result
))
1113 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
1114 inst
= bld
.SEL(result
, op
[1], op
[2]);
1115 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1119 unreachable("unhandled instruction");
1122 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1123 * to sign extend the low bit to 0/~0
1125 if (devinfo
->gen
<= 5 &&
1126 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1127 fs_reg masked
= vgrf(glsl_type::int_type
);
1128 bld
.AND(masked
, result
, fs_reg(1));
1129 masked
.negate
= true;
1130 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1135 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1136 nir_load_const_instr
*instr
)
1138 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1140 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1141 bld
.MOV(offset(reg
, bld
, i
), fs_reg(instr
->value
.i
[i
]));
1143 nir_ssa_values
[instr
->def
.index
] = reg
;
1147 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1149 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1150 instr
->def
.num_components
);
1154 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1155 unsigned base_offset
, nir_src
*indirect
)
1159 assert(!nir_reg
->is_global
);
1161 reg
= v
->nir_locals
[nir_reg
->index
];
1163 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1165 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1167 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1168 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1169 fs_reg(multiplier
));
1176 fs_visitor::get_nir_src(nir_src src
)
1180 reg
= nir_ssa_values
[src
.ssa
->index
];
1182 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1186 /* to avoid floating-point denorm flushing problems, set the type by
1187 * default to D - instructions that need floating point semantics will set
1188 * this to F if they need to
1190 return retype(reg
, BRW_REGISTER_TYPE_D
);
1194 fs_visitor::get_nir_dest(nir_dest dest
)
1197 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1198 dest
.ssa
.num_components
);
1199 return nir_ssa_values
[dest
.ssa
.index
];
1202 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1207 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1210 for (unsigned i
= 0; i
< 4; i
++) {
1211 if (!((wr_mask
>> i
) & 1))
1214 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1215 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1216 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1217 if (new_inst
->src
[j
].file
== GRF
)
1218 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1225 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1228 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1229 dest
= get_nir_dest(instr
->dest
);
1231 bool has_indirect
= false;
1233 switch (instr
->intrinsic
) {
1234 case nir_intrinsic_discard
:
1235 case nir_intrinsic_discard_if
: {
1236 /* We track our discarded pixels in f0.1. By predicating on it, we can
1237 * update just the flag bits that aren't yet discarded. If there's no
1238 * condition, we emit a CMP of g0 != g0, so all currently executing
1239 * channels will get turned off.
1242 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1243 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1244 fs_reg(0), BRW_CONDITIONAL_Z
);
1246 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1247 BRW_REGISTER_TYPE_UW
));
1248 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1250 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1251 cmp
->flag_subreg
= 1;
1253 if (devinfo
->gen
>= 6) {
1254 emit_discard_jump();
1259 case nir_intrinsic_atomic_counter_inc
:
1260 case nir_intrinsic_atomic_counter_dec
:
1261 case nir_intrinsic_atomic_counter_read
: {
1262 using namespace surface_access
;
1264 /* Get the arguments of the atomic intrinsic. */
1265 const fs_reg offset
= get_nir_src(instr
->src
[0]);
1266 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
1267 instr
->const_index
[0]);
1270 /* Emit a surface read or atomic op. */
1271 switch (instr
->intrinsic
) {
1272 case nir_intrinsic_atomic_counter_read
:
1273 tmp
= emit_untyped_read(bld
, fs_reg(surface
), offset
, 1, 1);
1276 case nir_intrinsic_atomic_counter_inc
:
1277 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1278 fs_reg(), 1, 1, BRW_AOP_INC
);
1281 case nir_intrinsic_atomic_counter_dec
:
1282 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1283 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
1287 unreachable("Unreachable");
1290 /* Assign the result. */
1291 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
1293 /* Mark the surface as used. */
1294 brw_mark_surface_used(stage_prog_data
, surface
);
1298 case nir_intrinsic_load_front_face
:
1299 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1300 *emit_frontfacing_interpolation());
1303 case nir_intrinsic_load_vertex_id
:
1304 unreachable("should be lowered by lower_vertex_id()");
1306 case nir_intrinsic_load_vertex_id_zero_base
: {
1307 fs_reg vertex_id
= nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
1308 assert(vertex_id
.file
!= BAD_FILE
);
1309 dest
.type
= vertex_id
.type
;
1310 bld
.MOV(dest
, vertex_id
);
1314 case nir_intrinsic_load_base_vertex
: {
1315 fs_reg base_vertex
= nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
1316 assert(base_vertex
.file
!= BAD_FILE
);
1317 dest
.type
= base_vertex
.type
;
1318 bld
.MOV(dest
, base_vertex
);
1322 case nir_intrinsic_load_instance_id
: {
1323 fs_reg instance_id
= nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
1324 assert(instance_id
.file
!= BAD_FILE
);
1325 dest
.type
= instance_id
.type
;
1326 bld
.MOV(dest
, instance_id
);
1330 case nir_intrinsic_load_sample_mask_in
: {
1331 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1332 assert(sample_mask_in
.file
!= BAD_FILE
);
1333 dest
.type
= sample_mask_in
.type
;
1334 bld
.MOV(dest
, sample_mask_in
);
1338 case nir_intrinsic_load_sample_pos
: {
1339 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1340 assert(sample_pos
.file
!= BAD_FILE
);
1341 dest
.type
= sample_pos
.type
;
1342 bld
.MOV(dest
, sample_pos
);
1343 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1347 case nir_intrinsic_load_sample_id
: {
1348 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1349 assert(sample_id
.file
!= BAD_FILE
);
1350 dest
.type
= sample_id
.type
;
1351 bld
.MOV(dest
, sample_id
);
1355 case nir_intrinsic_load_uniform_indirect
:
1356 has_indirect
= true;
1358 case nir_intrinsic_load_uniform
: {
1359 unsigned index
= instr
->const_index
[0];
1362 if (index
< num_direct_uniforms
) {
1363 uniform_reg
= fs_reg(UNIFORM
, 0);
1365 uniform_reg
= fs_reg(UNIFORM
, num_direct_uniforms
);
1366 index
-= num_direct_uniforms
;
1369 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1370 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, index
);
1372 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1376 dest
= offset(dest
, bld
, 1);
1381 case nir_intrinsic_load_ubo_indirect
:
1382 has_indirect
= true;
1384 case nir_intrinsic_load_ubo
: {
1385 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1389 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1392 /* The block index is not a constant. Evaluate the index expression
1393 * per-channel and add the base UBO index; we have to select a value
1394 * from any live channel.
1396 surf_index
= vgrf(glsl_type::uint_type
);
1397 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1398 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1399 surf_index
= bld
.emit_uniformize(surf_index
);
1401 /* Assume this may touch any UBO. It would be nice to provide
1402 * a tighter bound, but the array information is already lowered away.
1404 brw_mark_surface_used(prog_data
,
1405 stage_prog_data
->binding_table
.ubo_start
+
1406 shader_prog
->NumUniformBlocks
- 1);
1410 /* Turn the byte offset into a dword offset. */
1411 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1412 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1413 BRW_REGISTER_TYPE_D
),
1416 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1417 for (int i
= 0; i
< instr
->num_components
; i
++)
1418 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
1419 base_offset
, vec4_offset
+ i
);
1421 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1422 packed_consts
.type
= dest
.type
;
1424 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1425 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1426 surf_index
, const_offset_reg
);
1428 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1429 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1431 /* The std140 packing rules don't allow vectors to cross 16-byte
1432 * boundaries, and a reg is 32 bytes.
1434 assert(packed_consts
.subreg_offset
< 32);
1436 bld
.MOV(dest
, packed_consts
);
1437 dest
= offset(dest
, bld
, 1);
1443 case nir_intrinsic_load_input_indirect
:
1444 has_indirect
= true;
1446 case nir_intrinsic_load_input
: {
1448 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1449 fs_reg src
= offset(retype(nir_inputs
, dest
.type
), bld
,
1450 instr
->const_index
[0] + index
);
1452 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1456 dest
= offset(dest
, bld
, 1);
1461 /* Handle ARB_gpu_shader5 interpolation intrinsics
1463 * It's worth a quick word of explanation as to why we handle the full
1464 * variable-based interpolation intrinsic rather than a lowered version
1465 * with like we do for other inputs. We have to do that because the way
1466 * we set up inputs doesn't allow us to use the already setup inputs for
1467 * interpolation. At the beginning of the shader, we go through all of
1468 * the input variables and do the initial interpolation and put it in
1469 * the nir_inputs array based on its location as determined in
1470 * nir_lower_io. If the input isn't used, dead code cleans up and
1471 * everything works fine. However, when we get to the ARB_gpu_shader5
1472 * interpolation intrinsics, we need to reinterpolate the input
1473 * differently. If we used an intrinsic that just had an index it would
1474 * only give us the offset into the nir_inputs array. However, this is
1475 * useless because that value is post-interpolation and we need
1476 * pre-interpolation. In order to get the actual location of the bits
1477 * we get from the vertex fetching hardware, we need the variable.
1479 case nir_intrinsic_interp_var_at_centroid
:
1480 case nir_intrinsic_interp_var_at_sample
:
1481 case nir_intrinsic_interp_var_at_offset
: {
1482 assert(stage
== MESA_SHADER_FRAGMENT
);
1484 ((struct brw_wm_prog_data
*) prog_data
)->pulls_bary
= true;
1486 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1488 /* For most messages, we need one reg of ignored data; the hardware
1489 * requires mlen==1 even when there is no payload. in the per-slot
1490 * offset case, we'll replace this with the proper source data.
1492 fs_reg src
= vgrf(glsl_type::float_type
);
1493 int mlen
= 1; /* one reg unless overriden */
1496 switch (instr
->intrinsic
) {
1497 case nir_intrinsic_interp_var_at_centroid
:
1498 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1499 dst_xy
, src
, fs_reg(0u));
1502 case nir_intrinsic_interp_var_at_sample
: {
1503 /* XXX: We should probably handle non-constant sample id's */
1504 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1505 assert(const_sample
);
1506 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1507 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_xy
, src
,
1512 case nir_intrinsic_interp_var_at_offset
: {
1513 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1516 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1517 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1519 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_xy
, src
,
1520 fs_reg(off_x
| (off_y
<< 4)));
1522 src
= vgrf(glsl_type::ivec2_type
);
1523 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1524 BRW_REGISTER_TYPE_F
);
1525 for (int i
= 0; i
< 2; i
++) {
1526 fs_reg temp
= vgrf(glsl_type::float_type
);
1527 bld
.MUL(temp
, offset(offset_src
, bld
, i
), fs_reg(16.0f
));
1528 fs_reg itemp
= vgrf(glsl_type::int_type
);
1529 bld
.MOV(itemp
, temp
); /* float to int */
1531 /* Clamp the upper end of the range to +7/16.
1532 * ARB_gpu_shader5 requires that we support a maximum offset
1533 * of +0.5, which isn't representable in a S0.4 value -- if
1534 * we didn't clamp it, we'd end up with -8/16, which is the
1535 * opposite of what the shader author wanted.
1537 * This is legal due to ARB_gpu_shader5's quantization
1540 * "Not all values of <offset> may be supported; x and y
1541 * offsets may be rounded to fixed-point values with the
1542 * number of fraction bits given by the
1543 * implementation-dependent constant
1544 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1546 set_condmod(BRW_CONDITIONAL_L
,
1547 bld
.SEL(offset(src
, bld
, i
), itemp
, fs_reg(7)));
1550 mlen
= 2 * dispatch_width
/ 8;
1551 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_xy
, src
,
1558 unreachable("Invalid intrinsic");
1562 /* 2 floats per slot returned */
1563 inst
->regs_written
= 2 * dispatch_width
/ 8;
1564 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1565 INTERP_QUALIFIER_NOPERSPECTIVE
;
1567 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1568 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1569 src
.type
= dest
.type
;
1571 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1572 dest
= offset(dest
, bld
, 1);
1577 case nir_intrinsic_store_output_indirect
:
1578 has_indirect
= true;
1580 case nir_intrinsic_store_output
: {
1581 fs_reg src
= get_nir_src(instr
->src
[0]);
1583 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1584 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
1585 instr
->const_index
[0] + index
);
1587 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1589 bld
.MOV(new_dest
, src
);
1590 src
= offset(src
, bld
, 1);
1595 case nir_intrinsic_barrier
:
1600 unreachable("unknown intrinsic");
1605 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1607 unsigned sampler
= instr
->sampler_index
;
1608 fs_reg
sampler_reg(sampler
);
1610 /* FINISHME: We're failing to recompile our programs when the sampler is
1611 * updated. This only matters for the texture rectangle scale parameters
1612 * (pre-gen6, or gen6+ with GL_CLAMP).
1614 int texunit
= prog
->SamplerUnits
[sampler
];
1616 int gather_component
= instr
->component
;
1618 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1620 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1623 int lod_components
= 0;
1624 int UNUSED offset_components
= 0;
1626 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1628 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1629 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1630 switch (instr
->src
[i
].src_type
) {
1631 case nir_tex_src_bias
:
1632 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1634 case nir_tex_src_comparitor
:
1635 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1637 case nir_tex_src_coord
:
1638 switch (instr
->op
) {
1640 case nir_texop_txf_ms
:
1641 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1644 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1648 case nir_tex_src_ddx
:
1649 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1650 lod_components
= nir_tex_instr_src_size(instr
, i
);
1652 case nir_tex_src_ddy
:
1653 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1655 case nir_tex_src_lod
:
1656 switch (instr
->op
) {
1658 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1661 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1664 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1668 case nir_tex_src_ms_index
:
1669 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1671 case nir_tex_src_offset
:
1672 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1673 if (instr
->is_array
)
1674 offset_components
= instr
->coord_components
- 1;
1676 offset_components
= instr
->coord_components
;
1678 case nir_tex_src_projector
:
1679 unreachable("should be lowered");
1681 case nir_tex_src_sampler_offset
: {
1682 /* Figure out the highest possible sampler index and mark it as used */
1683 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1684 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
1685 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1687 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1689 brw_mark_surface_used(prog_data
, max_used
);
1691 /* Emit code to evaluate the actual indexing expression */
1692 sampler_reg
= vgrf(glsl_type::uint_type
);
1693 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
1694 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
1699 unreachable("unknown texture source");
1703 if (instr
->op
== nir_texop_txf_ms
) {
1704 if (devinfo
->gen
>= 7 &&
1705 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1706 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1712 for (unsigned i
= 0; i
< 3; i
++) {
1713 if (instr
->const_offset
[i
] != 0) {
1714 assert(offset_components
== 0);
1715 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
1720 enum glsl_base_type dest_base_type
;
1721 switch (instr
->dest_type
) {
1722 case nir_type_float
:
1723 dest_base_type
= GLSL_TYPE_FLOAT
;
1726 dest_base_type
= GLSL_TYPE_INT
;
1728 case nir_type_unsigned
:
1729 dest_base_type
= GLSL_TYPE_UINT
;
1732 unreachable("bad type");
1735 const glsl_type
*dest_type
=
1736 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1739 ir_texture_opcode op
;
1740 switch (instr
->op
) {
1741 case nir_texop_lod
: op
= ir_lod
; break;
1742 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1743 case nir_texop_tex
: op
= ir_tex
; break;
1744 case nir_texop_tg4
: op
= ir_tg4
; break;
1745 case nir_texop_txb
: op
= ir_txb
; break;
1746 case nir_texop_txd
: op
= ir_txd
; break;
1747 case nir_texop_txf
: op
= ir_txf
; break;
1748 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1749 case nir_texop_txl
: op
= ir_txl
; break;
1750 case nir_texop_txs
: op
= ir_txs
; break;
1752 unreachable("unknown texture opcode");
1755 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1756 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1757 tex_offset
, mcs
, gather_component
,
1758 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1760 fs_reg dest
= get_nir_dest(instr
->dest
);
1761 dest
.type
= this->result
.type
;
1762 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1763 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
1764 dest
, this->result
),
1765 (1 << num_components
) - 1);
1769 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
1771 switch (instr
->type
) {
1772 case nir_jump_break
:
1773 bld
.emit(BRW_OPCODE_BREAK
);
1775 case nir_jump_continue
:
1776 bld
.emit(BRW_OPCODE_CONTINUE
);
1778 case nir_jump_return
:
1780 unreachable("unknown jump");